Z9104 Variable Delay Motherboard Clock Buffer Features Table 1. Feedback Scale Select Codes Mode • Output phase relationship is precisely controllable with respect to input clock via a dedicated external feedback path • Two-kV ESD protected • Six low-skew clocks generated • One 2.5V output clock • Outputs are individually enabled • Output frequencies from 30 to 120 MHz • 3.3V power supply • Synchronous output enable and disable control • 45–55% output duty cycle • ±100 ps cycle-to-cycle jitter • 32-lead TQFP package • Pin-compatible with MPC932P FBS1 FBS0 Pcounter Ncounter MF[1] 0 0 0 ³4 ³8 2.0 0 0 1 ³4 ³ 10 2.5 0 1 0 ³4 ³ 12 3.0 0 1 1 ³8 ³ 12 1.5 1 0 0 ³4 ³4 1.0 1 0 1 ³4 ³5 1.25 1 1 0 ³4 ³6 1.5 1 1 1 ³8 ³8 1.0 Note: 1. Multiplication Factor – The multiplication factor for these configurations is the output frequency with respect to REFIN (FOUT = FIN × multiplication factor). Block Diagram Pin Configuration VDDA MODE SC25 SC2,3 VSS CLK25 VDD25 CLK2 MODE FBS0 FBS1 VDDF FBIN REFIN Ncounter PLL FBOUT 1 32 31 30 29 28 27 26 25 0 Pcounter PLLEN Stop Logic SC25 VDDI REFIN PLLEN FBS0 FBS1 OEALL STOPCLK VSSI CLK25 VDD25 CLK2 SC2,3 Stop Logic Stop Logic CLK4 SC4 Stop Logic CLK5 SC5 Stop Logic CLK6 SC6 24 23 22 21 20 19 18 17 Z9104 VSS CLK3 VDD CLK4 VSS CLK5 VDD CLK6 VSSA SC6 SC5 SC4 FBIN VDDF FBOUT VSSF 9 10 11 12 13 14 15 16 CLK3 1 2 3 4 5 6 7 8 VDD STOPCLK OEALL Cypress Semiconductor Corporation Document #: 38-07083 Rev. *C • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised May 6, 2002 Z9104 Pin Description Pin Name PWR I/O[2] 2 REFIN VDDI I 3 PLLEN VDD I PU When LOW, Ref input bypass PLL. It is intended for static testing at the part’s internal logic. 4, 5 FBS(0:1) VDD I PU Feedback selection pins. These input pins control the internal routing of the feedback output clock that produce the multiplier values listed in the “Feedback Scale Select Code” table on page 1. 31 MODE VDD I PD Combined with the FBS pins, this pin determines the output clocks frequency with respect to the REFIN pin. See table on page 1 for functionality. 6 OEALL VDD I PU Output Enable for all CLK output clocks. When at a logic LOW level, all outputs are driven to a three-state. 7 STOPCLK VDD I PU Stop Clock for all CLK output clocks. When at a logic LOW CLK (2:6) and CLK25 are driven to a logic LOW level synchronously with their next occurring HIGH to LOW transition. This signal does NOT effect the FBOUT clock. 15 FBOUT VDDF O Clock source that is used in the device’s external feedback loop. This pin is connected to the device’s FBIN pin either directly or through an external delay circuit. 27 CLK25 VDD25 O 2.5V output clock copy of CLK(2:6). 25, 23, 21, 19, 17 CLK(2:6) VDD O These output clocks are the synthesized product of the REFIN clock and the selections programmed on the FB0, FB1 and MODE pins. 20, 24, 28 VSS P Ground pins for the device. 18, 22 VDD P 3.3V power supply pins for clock buffer circuit. 14 VDDF P 3.3V power supply pins for the FBOUT clock output buffers. 30 SC25 VDD I PU Synchronous output enable control pin for CLK25.[3] 29 SC2:3 VDD I PU Synchronous output enable control pin for CLK2 and CLK3 pins.[3] 12 SC4 VDD I PU Synchronous output enable control pin for CLK4 pins.[3] 11 SC5 VDD I PU Synchronous output enable control pin for CLK5 pins.[3] 10 SC6 VDD I PU Synchronous output enable control pin for CLK6 pins.[3] 26 VDD25 P 2.5V power supply pin for the CLK25 clock output buffers. 32 VDDA P Analog power. See recommended circuitry later in this data sheet. 16 VSSF P Ground supply for pin 15 (FBOUT) buffer. 9 VSSA P Ground power connection for analog circuitry. 8 VSSI P Ground power connection for input clock circuitry. 1 VDDI P 3.3V power connection for input clock circuitry. Description External reference clock input pin. Notes: 2. Pins with “PU” or “PD” listed in the Type column indicate that these pins have internal pull-up or pull down resistors. These resistors ensure that the device will sense a logic 1 (HIGH) or logic 0 (LOW) condition respectively when the device is powered up and no electrical connection is made to these pins. 3. All synchronous output enables, when driven to a logic LOW level, will cause their associated output clocks to transition to a logic LOW level and remain there. Likewise, they will cause their associated output clocks to begin running when driven to a logic HIGH level. This enabling and disabling action will produce no runt (short or long) clock output cycles. Document #: 38-07083 Rev. *C Page 2 of 7 Z9104 Output Clock Disable and Enable Timing When each clock enable pin (SC25 through SC6) is brought to a logic low level, its related output clock (CLK25 through CLK6) will be forced to a logic low level after one complete cycle. The enable pins are synchronized to the internal clock such that upon assertion, these signals will hold the clocks low until the beginning of a new clock period and thus avoid a runt pulse generation on the outputs. Figure 2 shows the recommended power supply decoupling circuitry to obtain minimum device clock noise (jitter). Designs shown implements this decoupling scheme in noisy VDD environments to protect the device’s internal analog circuitry from digital noise generated on the main 3.3V supply. A range of 2.2 to 15 Ohms is recommended for Rs. Rs should be adjusted to the minimum value required to produce acceptable performances from the device. The ultimate limitation on the Rs maximum value is the device’s minimum VDD spec. CLK SCx Stop on next falling edge CLKx Start on next rising edge Figure Fig. 2 1. Rs 3.3V VDDA .01 µF 22 µF + Z9104 Device Figure 2. Applications Examples Table 2. Z9104 Input Reference Frequency Ranges Mode FBS1 FBS0 REFIN Frequency Min. (MHz) REFIN Frequency Max. (MHz) CLK(25:6), Output Frequency (MHz) 1 0 0 50 120 1 x REFIN REFIN = 66.7 MHz CLK* = 66.7 MHz 1 0 1 40 96 1.25 x REFIN REFIN = 66.7 MHz CLK* = 83.3 MHz 1 1 0 33.3 80 1.5 x REFIN REFIN = 66.7 MHz CLK* = 100 MHz 1 1 1 25 60 1 x REFIN REFIN = 33.3 MHz CLK* = 33.3 MHz 0 0 0 25 60 2 x REFIN REFIN = 33.3 MHz CLK* = 66.7 MHz 0 0 1 20 48 2.5 x REFIN REFIN = 33.3 MHz CLK* = 83.3 MHz 0 1 0 16.7 40 3 X REFIN REFIN = 33.3 MHz CLK* = 100 MHz 0 1 1 16.7 40 1.5 X REFIN REFIN = 33.3 MHz CLK* = 50 MHz Document #: 38-07083 Rev. *C Example Page 3 of 7 Z9104 Maximum Ratings Voltage Relative to VSS:................................................–0.3V Voltage Relative to VDD: .................................................0.3V Storage Temperature: ................................–65°C to + 150°C Operating Temperature: ................................ –40°C to +85°C Maximum Power Supply: ...................................................7V Maximum ESD protection ............................................... 2KV This device contains circuitry to protect the inputs against damage due to up to 2,000 volt static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS < (Vin or Vout) < VDD Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). DC Parameters: VDD = VDDF = 3.3V±5%, VDD25 = 2.5V±5%, TA = –40°C to +85°C Parameter Description VIL Input Low Voltage VIH Input High Voltage IIL IIH VOH VOHC25 VOL Input Low Current Conditions [5] Input High Current [5] [4] Output Voltage High for CLK(2:6) Output Voltage for High CLK25 Output Low Voltage for [4,6] CLK(2:6)[4] VOLC25 Output Low Voltage for CLK25 Ioz Three-State Leakage Current [4,6] Min. Typ. Max. Unit VSS 0.8 V 2.0 VDD V VIN = VSS –100 mA VIN = VDD +100 mA @IOH = –20 mA 2.4 V @IOH = –13 mA 1.8 V @IOL = 20mA 0.5 V @IOL = 13 mA 0.5 V 10 mA Cpd Power Dissipation Capacitance ICCQ Quiescent Supply Current 15 mA Maximum Core Supply Current 130 mA Maximum PLL Supply Current 20 mA ICC ICCPLL Per Output 20 pF Notes: 4. Z9104D outputs can drive series or parallel terminated 50W (or 50W to VDD/2) transmission lines. 5. Inputs have pull-up and pull-down resistors, which affect the input current 6. Varies 1:1 with VDD25. Document #: 38-07083 Rev. *C Page 4 of 7 Z9104 AC Parameters[7]: VDD = VDDF = 3.3V±5%, VDD25 = 2.5V±5%, TA = –40°C to +85°C Parameter Description Conditions Tr,Tf REFIN Rise/Fall Time FVCO VCO lock range Fmax Maximum output frequency Pcounter = 4 REFIN Input Reference Frequency See Table 2 Min. Typ. 0.4 to 2.4 Volts 200 FrefDC Reference Input Duty Cycle Measured @ 1.5V TSkewO Output to Output clock skew (CLK(2:6])[8] Measured at 1.5 Volts TSkewO25 Output to Output clock skew (CLK25 Measured at 1.5 V on CLK(2:6) and at to Q(2:6))[8] 1.25V on CLK25 Tpd REFIN to FBIN Average Delay[9,10] Fin = 66.6 MHz DC Output Duty Cycle Tr,Tf Output Rise/Fall Time Ten Output Enable Time Tdis Output Disable Time Tjitter Cycle-to-cycle jitter Tlock Maximum PLL Lock Time Tpr Power Up Ramp Time Max. Unit 3.0 ns 480 MHz 120 MHz Controlled by VCO lock range 25 MHz 75 % 300 ps 600 ps –150 0 +150 ps Measured at 1.5 V on CLK(2:6) and at 1.25V on CLK25 45 50 55 % Measured from 0.8V to 2.0V on CLK(2:6) and from 0.8V to 1.8V on CLK25 0.1 1.2 ns 2.0 10 ns 2.0 8.0 ns Short term jitter (adjacent cycle) Select Code 100 50 MHz in/out Measured between 0.3V and 3.0V +100 250 ps 10 ms 20 ms ns Notes: 7. Parameters are guaranteed by design and characterization. Not 100% tested in production. 8. Outputs are loaded with 33 pF each. 9. REFIN rise time = FBIN rise time. 10. Tpd measurement uses the averaging feature of the scope to filter out the jitter component. Document #: 38-07083 Rev. *C Page 5 of 7 Z9104 Ordering Information Part Number Package Type Production Flow IMIZ9104DAB 32-lead TQFP Industrial, –40°C to +85°C IMIZ9104DABT 32-lead TQFP–Tape and Reel Industrial, –40°C to +85°C Package Drawing and Dimension 32-lead Thin Plastic Quad Flatpack 7 × 7 × 1.0 mm A32 51-85063-B All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07083 Rev. *C Page 6 of 7 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Z9104 Document Title: Z9104 Variable Delay Motherboard Clock Buffer Document Number: 38-07083 REV. ECN No. Issue Date Orig. of Change Description of Change ** 107119 06/05/01 IKA Convert from IMI to Cypress *A 108351 6/29/01 NDP Change Production flow from “Commercial” to “Industrial.” Change Part Number Revision from “C” to “D.” *B 109808 02/01/02 DSG Convert from Word Doc to Adobe Framemaker Cypress Format Changed the Output Frequency (30 to 10 MHz) to (30 to 120 MHz) *C 113686 05/13/02 CTK Corrected ordering information to indicate “Industrial” range Document #: 38-07083 Rev. *C Page 7 of 7