CY24233 MediaClock™ Clock Generator for DVD Players Product Features • • • • • • • Product Description Two reference outputs (27.00 MHz) Two 33.8688-MHz outputs Two 512fs outputs (22.5792 MHz or 24.576 MHz) 27.00-MHz clock or crystal input 3.3V or 3.0V operation (2.5V functional) High-drive outputs 16-pin TSSOP package The CY24233 is a clock generator solution that supports DVD digital disk players. It produces a complete set of clocks needed to support the entire system. All output clocks are synthesized from a single 27.00-MHz fundamental cut crystal or input reference clock. The output clocks are precisely synthesized to meet the systems low PPM error requirements. Table 1. Test FSEL 27-1Out 27-2Out 33-1Out 33-1Out 512-1Out 512-2Out 0 0 27.00 MHz 2.700 MHz 1.800 MHz 0 1 27.00 MHz 2.700 MHz 3.000 MHz 1 0 27.00 MHz 33.8688 MHz 22.5792 MHz 1 1 27.00 MHz 33.8688 MHz 24.576 MHz Pin Configuration Block Diagram XTI XT0 2 OS OSC C VDD 27-1Out, 27-2Out VSS 27-1Out or N/C1 PLL 1 2 27-2Out or 33-1Out, 33-2Out N/C1 VDD VSS XT1 PLL 2 2 XT0 512-1Out, 512-2Out 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 TEST 33-1Out or N/C1 FSEL 33-2Out or N/C1 VDD VSS 512-1Out 512-2Out FSEL Cypress Semiconductor Corporation Document #: 38-07132 Rev. *B • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 14, 2002 CY24233 Pin Description[1,2] Pin Number Pin Name I/O 3,4 27-1Out 27-2Out O 3.3V fixed-frequency 27.00-MHz clock outputs. See Table 1 on page 1 for frequency selection for test mode functionality. 9,10 512-1Out 512-2Out O 3.3V or 3.0V fixed frequency clock outputs. See Table 1 on page 1 for frequency selection. 13,15 33-1Out 33-2Out O 3.3V fixed frequency 33.8688-MHz clock outputs. See Table 1 on page 1 for frequency selection for test mode functionality. 14* FSEL I Frequency selection input. This pin controls the frequency that is present on two 512 output clock pins. 8 XTO O On-chip reference oscillator pin. Drives an external crystal. When an externally generated reference signal is used at XTI, this pin remains unconnected. Bypass with a proper capacitance to ground to match the external crystal’s load capacitance. 7 XTI I On-chip reference oscillator input pin. Requires either an external crystal (nominally 27 MHz) or externally generated reference signal. Bypass with a proper capacitance to ground to match the external crystal’s load capacitance. 1, 5, 12 VDD PWR 3.3V or 3.0V power supply. 2,6,11 VSS PWR Device ground for all circuitry. 16 TEST I Pin Description Internal pull up. If this input pin is asserted low, it will set this device into a test mode. See Table 1 on page 1. Table 2. Maximum Lumped Capacitative Output Loads Clock Max Load Units 27-1Out 40 pF 27-2Out 25 pF 33-1Out,33-2Out, 512-1Out,512-2Out 15 pF FSEL Switching Synchronization The FSEL input is used to select the frequency of the clocks on the 512-1Out and 512-2Out pins. The device contains internal clock edge synchronization to insure that when the state of this pin is changed while the clocks are running no short (runt) or long (stretched) clocks will occur in the output streams. This is to say that the transitions will be made at a naturally occurring clock edge of the former clocks period and the cycle immediately after the change will be of a full newly selected clocks period and duty cycle. FSEL Switching Synchronization Finish Cycle Start at Full Cycle Wait Notes: 1. Part may be operated with Pins 3,4,13,15 soldered to pads on PCB with no PCB trace connected to these pads, i.e., floating. 2. Table Nomenclature: All pin numbers with an asterisks (*) immediately after them indicates that they have an internal pull-up resistor to ensure that they will be sensed as a logic HIGH even if no external circuitry is attached to them. I = Input pins, O = Output pins and PWR = Power connection pins. Document #: 38-07132 Rev. *B Page 2 of 5 CY24233 Maximum Ratings[3] Storage Temperature: .................................–65°C to +150°C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: Operating Temperature: ................................ –20°C to +85°C VSS < (VIN or VOUT) < VDD. Maximum ESD protection ............................................... 2KV Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). Maximum Input Voltage Relative to VSS: ............. VSS – 0.3V Maximum Input Voltage Relative to VDD: ............. VDD + 0.3V Maximum Power Supply: ................................................5.5V Operating Voltage: ...................................................2.5–3.6V DC Parameters (VDD = 3.3V ± 10%, TA = –10°C to +75°C or VDD = 3.0V ± 10%, TA = –20°C to +85°C) Parameter Description Conditions Min. [3] VIL Input Low Voltage VIH Input High Voltage IIL Input Low Current IIH Input High Current For internal Pull-up resistors[3,5] IIL measured at VIN = GND, IIH measured at VIN = VDD Hysteriss[3] Typ. Max. Unit – – 0.8 Vdc 2.0 – – Vdc –18 –8 –3.5 µA – – 5 µA 250 410 750 mV – 48 60 mA VHYS Input Idd3.3V Dynamic Supply Current Test = 1, FSEL=1[6] Idd3.0V Dynamic Supply Current Test = 1, FSEL=1 [6] – 40 50 mA VOL Output Low Voltage IOL = 4.0 mA – – 0.4 V VOH Output High Voltage IOH = 4.0 mA 2.4 – – V Cin Input Pin Capacitance – – 5 pF Cout Output Pin Capacitance – – 6 pF Lpin Pin Inductance – – 7 nH Cxtal Crystal Pin Capacitance – 5 – pF AC Parameters (VDD = 3.3V ± 10%, TA = –10°C to +75°C) Parameter [7] Description Conditions Min. Typ. Max. Unit [8] – 2 5 ns – 2 5 ns TR Rise Time All clocks at rated load TF Fall Time All clocks at rated load[8] TPU Power up to Stable Output All Output Clocks – š 3 ms TDC1 Clock Duty Cycle (all output clocks) All clocks at rated load[9] 45 50 55 % Cycle to cycle jitter (Peak–Peak, 10,000 cycles ) All clocks at rated load[9] – 150 200 ps – 150 200 ps – – 350 ps – – 40 µs Tj2 Clock Jitter (33-1Out,33-2Out) Tj2 Clock Jitter (512-1Out,512-2Out) Tj3 Clock Jitter (27-1Out,27-2Out) TXS Crystal Oscillator Start-up Time AC Parameters (VDD = 3.0V ± 10%, TA = –20°C to +85°C, only 512-1Out and 512-2out Loaded) Parameter Description Conditions Min. Typ. Max. Units load[8] TR Rise Time All clocks at rated – 2.5 5 ns TF Fall Time All clocks at rated load[8] – 2.5 5 ns TPU Power-up to Stable Output All output clocks – – 3 ms Notes: 3. Multiple Supplies:The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 4. Applicable to input signal: FSEL and Test pins. 5. Although internal pull-up resistors have a typical value of 400K, this value may vary between 200K and 800K. 6. All outputs loaded as perTable 2 on page 2. 7. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with fully loaded outputs. 8. Measured between 0.2* VDD and 0.8*VDDV. 9. Triggering is done at 1.5V. Document #: 38-07132 Rev. *B Page 3 of 5 CY24233 AC Parameters (VDD = 3.0V ± 10%, TA = –20°C to +85°C, only 512-1Out and 512-2out Loaded) (continued) Parameter Description Conditions All clocks at rated load9 Min. Typ. Max. Units 40 50 60 % TDC1 Clock Duty Cycle (all output clocks) Tj2 Clock Jitter (512-1Out,512-2Out) Cycle to cycle jitter (Peak-to-Peak, 10,000 cycles) All clocks at rated load9 – 200 250 ps TXS Crystal Oscillator Start-up Time – – 40 µs Ordering Information Part Number Package Type CY24233ZC CY24233ZCT Product Flow 16-pin TSSOP Commercial, –20° to 85°C 16-pin TSSOP–Tape and Reel Commercial, –20° to 85°C Package Diagram 16-lead Thin Shrunk Small Outline Package (4.40 MM Body) Z16 51-85091 MediaClock is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07132 Rev. *B Page 4 of 5 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY24233 Document Title: CY24233 MediaClock™ Clock Generator for DVD Players Document Number: 38-07132 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 110596 11/29/01 DMG New Data Sheet *A 116543 08/22/02 CKN Changed values in DC and AC parameters for operation at 3.0V ±10%, and ambient temp. range from –20°C to 85°C: jitter, rise time, fall time Explictly allow use with only 512 outputs loaded. *B 122795 12/14/02 RBI Power up Requirements to Operating Conditions Information Document #: 38-07132 Rev. *B Page 5 of 5