ETC LMC555CH

LMC555
CMOS Timer
General Description
Features
The LMC555 is a CMOS version of the industry standard
555 series general purpose timers. It offers the same capability of generating accurate time delays and frequencies but
with much lower power dissipation and supply current
spikes. When operated as a one-shot, the time delay is precisely controlled by a single external resistor and capacitor.
In the astable mode the oscillation frequency and duty cycle
are accurately set by two external resistors and one capacitor. The use of National Semiconductor’s LMCMOS™ process extends both the frequency range and low supply capability.
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Less than 1 mW typical power dissipation at 5V supply
3 MHz astable frequency capability
1.5V supply operating voltage guaranteed
Output fully compatible with TTL and CMOS logic at 5V
supply
Tested to −10 mA, +50 mA output current levels
Reduced supply current spikes during output transitions
Extremely low reset, trigger, and threshold currents
Excellent temperature stability
Pin-for-pin compatible with 555 series of timers
Available in 8 pin MSOP Package
Block and Connection Diagrams
DS008669-1
(Pinouts for Molded and Metal Can Packages are identical)
Order Number LMC555CH, LMC555CM, LMC555CMM or LMC555CN
See NS Package Number H08C, M08A, MUA08A, or N08E
LMCMOS™ is a trademark of National Semiconductor Corp.
© 1997 National Semiconductor Corporation
DS008669
www.national.com
LMC555 CMOS Timer
May 1997
Absolute Maximum Ratings
(Note 2)
Soldering Information
Dual-In-Line Package
Soldering (10 seconds)
260˚C
Small Outline Package
(SOIC and MSOP)
Vapor Phase (60 seconds)
215˚C
Infrared (15 seconds)
220˚C
See AN-450 “Surface Mounting Methods and Their Effect on
Product Reliability” for other methods of soldering surface
mount devices.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage, V8
Input Voltages, V2, V4, V5, V6
Output Voltages, V3, V7
Output Current I3, I7
Operating Temperature Range
(Note 4)
Storage Temperature Range
15V
−0.3V to VS + 0.3V
15V
100 mA
−40˚C to +85˚C
−65˚C to +150˚C
Electrical Characteristics (Notes 1, 2)
Test Circuit, T = 25˚C, all switches open, RESET to VS unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Limits)
I8
V5
V7
Supply Current
Control Voltage
Discharge Saturation
Voltage
V3L
Output Voltage
(Low)
V3H
V2
VS = 1.5V
VS = 5V
VS = 12V
VS = 1.5V
VS = 5V
VS = 12V
(High)
Trigger Voltage
I2
Trigger Current
V4
Reset Voltage
I4
Reset Current
I6
Threshold Current
I7
Discharge Leakage
t
Timing Accuracy
150
250
150
400
0.8
1.0
1.2
2.9
3.3
3.8
7.4
8.0
8.6
VS = 1.5V, I7 = 1 mA
VS = 5V, I7 = 10 mA
VS = 1.5V, I3 = 1 mA
VS = 5V, I3 = 8 mA
VS = 12V, I3 = 50 mA
VS = 1.5V, I3 = −0.25 mA
VS = 5V, I3 = −2 mA
Output Voltage
50
100
1.0
75
150
150
300
0.2
0.4
0.3
0.6
1.0
2.0
4.7
VS = 12V, I3 = −10 mA
VS = 1.5V
10.5
11.3
0.4
0.5
0.6
VS = 12V
VS = 5V
VS = 1.5V (Note 5)
VS = 12V
3.7
4.0
4.3
0.4
0.7
1.0
0.4
0.75
1.1
∆t/∆Vs
Timing Shift with Supply
VS = 5V
VS = 12V
VS = 5V ± 1V
∆t/∆T
Timing Shift with
VS = 5V
mV
V
V
10
V
pA
10
V
pA
10
SW 2, 4 Closed
VS = 1.5V
V
1.25
4.4
VS = 5V
VS = 5V
VS = 12V
µA
pA
1.0
100
nA
0.9
1.1
1.25
ms
1.0
1.1
1.20
1.0
1.1
1.25
0.3
%/V
75
ppm/˚C
Temperature
−40˚C ≤ T ≤ +85˚C
fA
Astable Frequency
SW 1, 3 Closed
VS = 12V
fMAX
Maximum Frequency
Max. Freq. Test
Circuit, VS = 5V
3.0
MHz
tR, tF
Output Rise and
Max. Freq. Test Circuit
VS = 5V, CL = 10 pF
15
ns
Fall Times
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4.0
2
4.8
5.6
kHz
Electrical Characteristics (Notes 1, 2)
Test Circuit, T = 25˚C, all switches open, RESET to VS unless otherwise noted (Continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Limits)
tPD
Trigger Propagation Delay
VS = 5V, Measure Delay
from Trigger to Output
100
ns
Note 1: All voltages are measured with respect to the ground pin, unless otherwise specified.
Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit is
given, however, the typical value is a good indication of device performance.
Note 3: Refer to RETSC555X drawing for specifications of military LMC555H version.
Note 4: For operation at elevated temperatures, the device must be derated based on a 150˚C maximum junction temperature and a thermal resistance of 111˚C/W
for the LMC555CN, 167˚C/W for the LMC555CH, 169˚C/W for the LMC555CM, and 225˚C/W for the LMC555MM. Maximum allowable dissipation at 25˚C is 1126
mW for the LMC555CN, 755 mW for the LMC555CH, 740 mW for the LMC555CM and 555 mW for the LMC555MM.
Note 5: If the RESET pin is to be used at temperatures of −20˚C and below VS is required to be 2.0V or greater.
Test Circuit
Maximum Frequency Test Circuit
DS008669-3
DS008669-2
Typical Applications
Monostable (One-Shot)
DS008669-4
tH = 1.1 RAC (Gives time that output is high following trigger)
RESET overrides TRIGGER, which can override THRESHOLD. Therefore, the trigger pulse must be shorter than the desired tH.
The minimum trigger pulse width is 20 ns.
The minimum reset pulse width is 400 ns.
3
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Typical Applications
(Continued)
Variable Duty Cycle Oscillator
DS008669-5
(Gives fraction of total period that output is low)
50% Duty Cycle Oscillator
DS008669-6
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Physical Dimensions
inches (millimeters)
8-Lead TO-5 Metal Can Package (H)
Order Number LMC555CH
NS Package Number H08C
Molded Small Outline (SO) Package (M)
Order Number LMC555CM
NS Package Number M08A
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6
Physical Dimensions
inches (millimeters) (Continued)
8-Lead (0.118” Wide) Molded Mini Small Outline Package
Order Number LMC555CMM
NS Package Number MUA08A
7
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LMC555 CMOS Timer
Physical Dimensions
inches (millimeters) (Continued)
Molded Dual-in-line Package (N)
Order Number LMC555CN
NS Package Number N08E
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2. A critical component in any component of a life support
1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into
sonably expected to cause the failure of the life support
the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness.
ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
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