ETC LSI53C141

TECHNICAL
MANUAL
LSI53C141
SCSI Bus Expander
Version 2.1
November 2000
®
S14013.A
This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.
LSI Logic products are not intended for use in life-support appliances, devices,
or systems. Use of any LSI Logic product in such applications without written
consent of the appropriate LSI Logic officer is prohibited.
Document DB14-000082-01, Third Edition (November 2000)
This document describes the LSI Logic LSI53C141 SCSI Bus Expander and will
remain the official reference source for all revisions/releases of this product until
rescinded by an update.
To receive product literature, visit us at http://www.lsilogic.com.
LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of
LSI Logic or third parties.
Copyright © 1998–2000 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT
The LSI Logic logo, LVD Link, and TolerANT are registered trademarks or
trademarks of LSI Logic Corporation. All other brand and product names may be
trademarks of their respective companies.
ii
Preface
This book is the primary reference and technical manual for the
LSI53C141 SCSI Bus Expander chip which supports single-ended to
single-ended SCSI bus expansion (Repeater) or single-ended to low
voltage differential SCSI bus conversion (Converter). It contains a
functional description for the LSI53C141 and includes complete physical
and electrical specifications.
Audience
This document was prepared for logic designers and applications
engineers.
This document assumes that you have some familiarity with current and
proposed SCSI standards. For background information please contact:
ANSI
11 West 42nd Street
New York, NY 10036
(212) 642-4900
Ask for document number X3.131-1994 (SCSI-2) or X3.253-1995 (SPI)
Global Engineering Documents
15 Inverness Way East
Englewood, CO 80112
(800) 854-7179 or (303) 397-7956 (outside U.S.) FAX (303) 397-2740
Ask for document number X3.131-1994 (SCSI-2) or X3.253 (SCSI-3
Parallel Interface)
Preface
iii
ENDL Publications
14426 Black Walnut Court
Saratoga, CA 95070
(408) 867-6642
Document names: SCSI Bench Reference, SCSI Encyclopedia or SCSI
Tutor
Prentice Hall
113 Sylvan Avenue
Englewood Cliffs, NJ 07632
(800) 947-7700
Ask for document number ISBN 0-13-796855-8, SCSI: Understanding
the Small Computer System Interface
LSI Logic World Wide Web Home Page
www.lsilogic.com
Organization
This document has the following chapters and appendix:
iv
•
Chapter 1, Introduction, includes a general description of the
LSI53C141, its benefits and features.
•
Chapter 2, Functional Description, describes the LSI53C141
functions.
•
Chapter 3, Signal Descriptions, describes the signals of the
LSI53C141.
•
Chapter 4, Specifications, includes the electrical requirements for
DC characteristics, TolerANT Technology Electrical Characteristics,
and the AC timing characteristics. Also contains the outline drawing
of the 128-pin PQFP package.
•
Appendix A, Glossary of Terms and Abbreviations, provides
definitions of various terminology that is referenced throughout this
user’s guide.
Preface
Conventions Used in This Manual
The first time a word or phrase is defined in this manual, it is italicized.
The word assert means to drive a signal true or active. The word
deassert means to drive a signal false or inactive.
Hexadecimal numbers are indicated by the prefix “0x”—for example,
0x32CF. Binary numbers are indicated by the prefix “0b”—for example,
0b0011.0010.1100.1111.
The following is a list of notational conventions used throughout
this manual:
Notation
Example
Meaning and Use
courier typeface
.nwk file
Names of commands, files, signals, symbols, pins, parts,
directories, modules, and macrocells are shown in
courier typeface.
bold typeface
fd1sp
In a command line, keywords are shown in bold, nonitalic
typeface. Enter them exactly as shown.
italics
module
In command lines and names italics indicate user
variables. Italicized text must be replaced with
appropriate user-specified items. Enter items of the type
called for, using lower case.
italic underscore
full_pathname
When an underscore appears in an italicized string, enter
a user-supplied item of the type called for with no
spaces.
Preface
v
Revision Record
Page No.
Date
Version
All
7/97
1.0
11/97
1.1
Draft of the Data Manual
3-4
RBIAS description changed
3-6
VDD and VSS type changes
5VBIAS description change
NC with pullups and pulldown description changes
4-1
IDD Supply Current change
5/99
2.0
Final version, Preliminary removed, LSI53C141 has
reached GCA (General Customer Availability)
4-2
New table 4-6, Input Signal - Clock, input leakage
change from 10 µA to 20 µA.
4-4
Table 4-11 (was 4-10) Control Signals - RESET/,
WS_ENABLE, changed 3-state leakage from 10 µA to
20 µA.
4-7
Added new Figure 4.3 and renamed Figure 4.4
All
vi
Remarks
11/00
Preface
2.1
All product names changed from SYM to LSI.
Contents
Chapter 1
Chapter 2
Introduction
1.1
General Description
1.1.1
Applications
1.1.2
Features
1.1.3
Specifications
1.2
Benefits of LVD Link
1.2.1
LVD Link Benefits
1.3
Application Examples
1.3.1
LVD to SE Example
1.3.2
SE to SE and SE to LVD Example
1.3.3
Clustering Example
1.3.4
SCSI Bus Electrical Isolation
Functional Description
2.1
SCSI A-Side and B-Side SE Control Blocks
2.1.1
TolerANT Technology
2.1.2
LVD Link Technology
2.2
Retiming Logic
2.3
Precision Delay Control
2.4
State Machine Control
2.5
Dynamic Mode Switching
2.6
DIFFSENS Receiver
2.7
Signal Descriptions
2.7.1
Data and Parity
2.7.2
Busy (BSY) Control
2.7.3
Request (REQ)/Acknowledge (ACK) Control
2.7.4
Reset (RST) Control
2.7.5
Control/Data (C/D), Input/Output (I/O),
Message (MSG) and Attention (ATN) Controls
Contents
1-1
1-2
1-2
1-3
1-4
1-4
1-4
1-4
1-5
1-6
1-8
2-2
2-3
2-3
2-4
2-4
2-4
2-5
2-5
2-6
2-6
2-7
2-8
2-9
2-9
vii
2.7.6
2.7.7
2.7.8
2.7.9
2.8
Chapter 3
Chapter 4
Appendix A
Select (SEL) Control
Clock (CLOCK)
Chip Reset (RESET/)
Warm SWAP Enable and Transfer Active
(WS_ENABLE and XFER_ACTIVE)
SCSI Termination
Signal Descriptions
3.1
LSI53C141 Pin Diagram
3.2
LSI53C141 Signal Grouping
3.3
SCSI A Interface Pins
3.4
SCSI B SE and LVD Interface Pins
3.5
Interface Control Pins
3.6
SCSI Control Pins
3.7
Power and Ground Pins
3.8
No Connection Pins
Specifications
4.1
DC Characteristics
4.2
TolerANT Technology Electrical Characteristics
4.3
AC Characteristics
4.3.1
SCSI Interface Timings
4.4
LSI53C141 Mechanical Drawing
2-9
2-10
2-10
2-10
2-11
3-2
3-3
3-4
3-5
3-6
3-6
3-7
3-8
4-1
4-6
4-9
4-9
4-11
Glossary of Terms and Abbreviations
Customer Feedback
Figures
1.1
1.2
1.3
1.4
1.5
2.1
viii
LSI53C141 SCSI Bus Device
SCSI Extender Application (SE to SE Mode of Operation)
SCSI Extender or Converter Application (SE to LVD Mode
of Operation)
SCSI Bus Expanders in Clustering Environment
SCSI Bus Electrical Isolation
LSI53C141 Block Diagram
Contents
1-3
1-5
1-6
1-7
1-8
2-2
2.2
3.1
3.2
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
LSI53C141 Signal Grouping
LSI53C141 Pin Diagram
LSI53C141 Functional Signal Grouping
LVD Transmitter
LVD Receiver
Rise and Fall Time Test Conditions
SCSI Input Filtering
Hysteresis of SCSI Receiver
Input Current as a Function of Input Voltage
Output Current as a Function of Output Voltage
Clock Timing
Input/Output Timings
LSI53C141 Mechanical Drawing
2-6
3-2
3-3
4-4
4-5
4-7
4-7
4-8
4-8
4-8
4-9
4-10
4-11
1.1
2.1
2.2
2.3
2.4
3.1
3.2
3.3
3.4
3.5
3.6
3.7
4.1
4.2
4.3
Mode of Operation
DIFFSENS Voltage Levels
RESET/ Control Signal Polarity
WS_ENABLE Signal Polarity
XFER_ACTIVE Signal Polarity
SCSI A Signal Description
SCSI B Signal Description
Chip Control Signal Description
SCSI Control Signal Description
Power and Ground Signal Description
No Connect Pins
Internal Test Pins
Absolute Maximum Stress Ratings
Operating Conditions
SCSI Signals—A_SD[15:0]/, A_SDP[1:0]/, A_SREQ/,
A_SACK/, B_SD[15:0] ,B_SDP[1:0], B_SREQ ,
B_SACK
SCSI Signals—A_SCD/, A_SIO/, A_SMSG/, A_SBSY/,
A_SATN/, A_SSEL/, A_SRST/, B_SCD ,B_SIO ,
B_SMSG ,B_SBSY ,B_SATN ,B_SSEL ,B_SRST
Input Signal—CLOCK
Input Signal—DIFFSENS
Capacitance
1-1
2-5
2-10
2-11
2-11
3-4
3-5
3-6
3-6
3-7
3-8
3-8
4-1
4-2
Tables
4.4
4.5
4.6
4.7
Contents
4-2
4-3
4-3
4-3
4-3
ix
4.8
4.9
4.10
4.11
4.12
4.13
4.14
4.15
4.16
x
SCSI Signals, LVD Drivers—B_SD[15:0], B_SDP[1:0] ,
B_SCD ,B_SIO ,B_SMSG ,B_SREQ ,B_SACK ,
B_SBSY ,B_SATN ,B_SSEL ,B_SRST *
SCSI Signals, LVD Receivers—B_SD[15:0] ,
B_SDP[1:0] ,B_SCD ,B_SIO ,B_SMSG ,
B_SREQ ,B_SACK ,B_SBSY ,B_SATN ,
B_SSEL ,B_SRST
SCSI Signal—DIFFSENS
Control Signals—RESET/, WS_ENABLE
Control Signals—XFER_ACTIVE
TolerANT Technology Electrical Characteristics
Clock Timing
Input Timings
Output Timings
Contents
4-4
4-4
4-5
4-5
4-5
4-6
4-9
4-9
4-10
Chapter 1
Introduction
1.1 General Description
The LSI53C141 SCSI Bus Expander is a single chip solution allowing the
extension of device connectivity and/or cable length limits of the SCSI
bus. A SCSI bus expander couples bus segments together without any
impact to the SCSI protocol, software, or firmware. The LSI53C141
attaches Single-Ended (SE) SCSI peripherals to the Low Voltage
Differential (LVD) signaling a bus used by Ultra2 SCSI.
The LSI53C141 does not boost the transfer rates of SE devices to Ultra2
SCSI rates, but instead enables system architects to take advantage of
the inherent cable distance, device connectivity, and data reliability
benefits of LVD with Ultra SCSI peripherals.
The LSI53C141 operates in one of two modes:
•
SE to SE (Extender Mode)
•
SE to LVD (Converter mode)
For applications requiring SE to High-Voltage Differential (HVD), use the
LSI53C120 Bus Expander. Table 1.1 shows all modes of operation.
Table 1.1
Mode of Operation
LSI Logic Product
Extender
Converter
LSI53C120
SE to SE
SE to HVD
LSI53C141
SE to SE
SE to LVD
In both SCSI Bus Extender and Converter modes, cable segments are
electrically isolated from each other. This feature maintains the signal
integrity of each cable segment. For bus isolation applications, the
LSI53C141 is ideally suited for the LSI53C895 Ultra2 SCSI controller.
LSI53C141 SCSI Bus Expander
1-1
The LSI53C141 provides additional control capability through the pin
level electrical isolation mode. This feature permits logical disconnection
of both the A-side bus and the B-side bus without disrupting SCSI
transfers currently in progress. For example, devices on the logically
disconnected B-side can be swapped out while the A-side bus remains
active.
The LSI53C141 is based upon bus expander technology resulting in
some signal filtering and retiming to maintain signal skew budgets. In
addition, the LSI53C141 has no programmable registers, therefore, it
does not require any software.
1.1.1 Applications
Use the LSI53C141 for the following:
•
Server clustering environments
•
Expanders create distinct SCSI cable segments which are
electrically isolated from each other
•
Attaches SE SCSI devices to an LVD SCSI bus
•
Operates as a SCSI Bus Converter or Extender
•
Provides SCSI Bus electrical isolation for high availability and
scalable server clustering technologies
•
Allows targets and initiators to be located on either the A-side or
B-side of the device
•
Allows each side of the device to be logically disconnected from the
other by using the pin level electrical isolation mode
•
Accepts any asynchronous or synchronous transfer speed up to Ultra
SCSI
•
Does not consume a SCSI ID
•
Provides on-chip LVD Link™ transceivers
•
Supports TolerANT® transceiver technology
•
Can cascade up to three LSI53C141s
•
Provides complete support for SCSI-1, SCSI-2, and SCSI-3
1.1.2 Features
1-2
Introduction
•
Does not require software
The LSI53C141 works with the LSI Logic extensive LSI53C7XX and
LSI53C8XX family of SCSI products. It also works with other industry
SCSI controllers, disk drives, and SCSI peripherals. Use the LSI53C141
for those difficult SCSI subsystem designs.
Figure 1.1 illustrates the signal grouping of the LSI53C141. A SCSI SE
bus connects directly to the SCSI A-side. The interface signals are SCSI
bus compatible driver and receiver signals with no internal termination.
The SCSI B-side connects directly to a SCSI SE bus or to a SCSI LVD
bus. The interface signals utilize LVD Link technology.
Figure 1.1
LSI53C141 SCSI Bus Device
A-Side
SE Only
Wide Ultra SCSI Bus
(Data and Control)
B-Side
LSI53C141
SCSI Bus
Expander
LVD or SE
Wide Ultra SCSI Bus
(Data and Control)
Control
Signals
40 MHz
Oscillator
1.1.3 Specifications
The LSI53C141 is designed with the following specifications:
•
40 MHz Input Clock
•
128-Pin Plastic Quad Flat Pack (PQFP)
•
Compliant with these reference specifications:
–
SCSI Parallel Interface-2 (SPI-2) (Ultra2)
–
SCSI Enhanced Parallel Interface (EPI)
General Description
1-3
1.2 Benefits of LVD Link
The LSI53C141 supports LVD for SCSI, a signaling technology that
increases the reliability of SCSI data transfers over longer distances than
supported by SE SCSI. The low current output of LVD allows the I/O
transceivers to be integrated directly onto the chip. LVD provides the
reliability of High Voltage Differential (HVD) SCSI without the added cost
of external differential transceivers. LVD allows a longer SCSI cable and
more devices on the bus, with the same cables defined in the SCSI-3
Parallel Interface standard for Ultra SCSI. LVD provides a long-term
migration path to even faster SCSI transfer rates without compromising
signal integrity, cable length, or connectivity.
For backward compatibility to existing SE devices, the LSI53C141
features universal LVD Link transceivers that can switch between LVD
SCSI and SE modes.
1.2.1 LVD Link Benefits
Integrated LVD Link universal transceivers provide these benefits:
•
Supports LVD
•
Allows greater device connectivity and longer cable length
•
Saves cost of external differential transceivers by using LVD Link
transceivers
•
Supports a long-term performance migration path
1.3 Application Examples
The following examples represent typical applications for the LSI53C141.
Many other configurations are possible and are only limited by the
imagination of the system architect.
1.3.1 LVD to SE Example
Figure 1.2 illustrates how to use the LSI53C141 to attach SE devices to
an LVD bus. This application permits system architects to take advantage
1-4
Introduction
of the longer cable lengths associated with LVD using today’s SE
devices.
SCSI Extender Application (SE to SE Mode of Operation)
(LVD 12 meters,
4 loads, 40 Mbits/s)
Disk Subsystem
LSI53C141
LSI53C141
Device 1
Device 6
Device 10
Device 5
Ultra SCSI Drive Box
Ultra SCSI Drive Box
Device 11
Single-Ended
(1.5 meters)
LSI53C895
Ultra2 SCSI Controller
Device 0
Single-Ended
(1.5 meters)
Ultra2 SCSI
Host Adapter
LSI53C141
Terminator
Single-Ended
(1.5 meters)
Figure 1.2
Device 15
Ultra SCSI Drive Box
1.3.2 SE to SE and SE to LVD Example
Figure 1.3 illustrates both SE to SE and SE to LVD modes of the
LSI53C141 to create a remote storage configuration.
Application Examples
1-5
SCSI Extender or Converter Application (SE to LVD Mode of Operation)
LSI53C141
Figure 1.3
LVD (12 meters, 2 loads, 40 Mbits/s)
Terminator
Single-Ended (3 meters)
Dual Channel Ultra SCSI Host Adapter
LSI53C141
Device 11
LSI53C141
or
LSI53C120
Device 2
Single-Ended
(1.5 meters)
Single-Ended
(1.5 meters)
Device 7
Single-Ended
(1.5 meters)
LSI53C141
or
LSI53C120
Device 12
Device 14
LSI53C876
Dual Channel
Ultra SCSI
Controller
Device 0 & 1
Device 6
Ultra SCSI Remote
Storage Box
Ultra SCSI Drive Box
Ultra SCSI Drive Box
1.3.3 Clustering Example
Figure 1.4 illustrates how servers share the same storage within a
cluster. When a server fails, the other server ensures data availability to
client workstations (often transparently to client applications). The
LSI53C141s create distinct SCSI segments that are electrically isolated
from each other. The LSI53C141 logical disconnection feature aids in the
failure recovery process. Cluster configuration improves data availability,
fault tolerance, and performance.
1-6
Introduction
Figure 1.4
SCSI Bus Expanders in Clustering Environment
Workstation
Workstation
Workstation
Shared Disk Cluster
LVD
SCSI Bus
Expander
SE
SE
SCSI Bus
Expander
Primary
Server
SE
SCSI Bus
Expander
LVD
Secondary
Server
SE
Application Examples
1-7
1.3.4 SCSI Bus Electrical Isolation
Figure 1.5 illustrates how to use the LSI53C141 to electrically isolate an
external SCSI bus from an internal SCSI bus. This configuration ensures
externally attached peripherals will not affect the operation of internal
peripherals.
Figure 1.5
SCSI Bus Electrical Isolation
External
Ultra SCSI Bus
(Legacy Devices)
H. D. 68 Pin
H. D. 68 Pin
Terminator
Terminator
LSI53C141
Flash
ROM
LSI53C895
Ultra2 SCSI
Controller
PCI Bus
1-8
Introduction
Chapter 2
Functional Description
The LSI53C141 has no programmable registers, therefore, no software
requirements. SCSI control signals control all LSI53C141 functions. This
chapter describes all signals, their groupings, and functions. Figure 2.1
shows a block diagram of the LSI53C141, which is divided into these
specific areas:
•
A-side SCSI Control Block
–
•
TolerANT Drivers and Receivers
B-side SCSI Control Block
–
LVD Link Technology
•
Retiming Circuit
•
Precision Delay Control
•
State Machine Control
•
LVD Control
LSI53C141 SCSI Bus Expander
2-1
Figure 2.1
LSI53C141 Block Diagram
Control
SCSI Control Block
Control
Precision
Delay
Control
LVD Link
Retiming Circuit
SCSI Control Block
SE Only
Wide Ultra SCSI Bus
Data and Control
B-Side
TolerANT Drivers and Receivers
A-Side
LVD and SE
Wide Ultra SCSI Bus
Data and Control
State
Machine
Control
Control
Signals
LVD DIFFSENS
Receiver
Chip Boundary
40 MHz Clock Input
In its simplest form, the LSI53C141 passes data and parity from a source
bus to a load bus. The side asserting, deasserting, or releasing the SCSI
signals is the source side. The simplest model is that the LSI53C141 is
just pieces of wire that allow corresponding SCSI signals to flow from
side to side. In reality, the LSI53C141 needs to know which side is driving
the signals so it can enable the proper drivers to pass the signals along.
In addition, the LSI53C141 does some signal retiming to maintain the
signal skew budget from source bus to load bus as if the source was a
local bus member.
2.1 SCSI A-Side and B-Side SE Control Blocks
In the SE to SE mode, the SCSI A-side pins are connected internally to
the corresponding SCSI B-side pins, forming bidirectional connections to
the SCSI bus.
The SCSI A-side and B-side SE control blocks connect to both targets
and initiators and accept any asynchronous or synchronous data transfer
2-2
Functional Description
rates up to the 40 Mbytes/s rate of Wide Ultra SCSI. LVD Link technology
is part of the SCSI B-side SE control block. TolerANT technology is part
of the SCSI A-side SE control block.
2.1.1 TolerANT Technology
The LSI53C141 features TolerANT technology, which includes active
negation on the SCSI drivers and input signal filtering on the SCSI
receivers. Active negation causes the SCSI Request, Acknowledge,
Data, and Parity signals to be actively driven HIGH rather than passively
pulled up by terminators.
TolerANT receiver technology improves data integrity in unreliable
cabling environments, where other devices would be subject to data
corruption. TolerANT receivers filter the SCSI bus signals to eliminate
unwanted transitions, without the long signal delay associated with
RC-type input filters. This improved driver and receiver technology helps
eliminate double clocking of data, which is the single biggest reliability
issue with SCSI operations.
The benefits of TolerANT include increased immunity to noise on the
deasserting signal edge, better performance due to balanced duty
cycles, and improved SCSI transfer rates. In addition, TolerANT SCSI
devices prevent glitches on the SCSI bus at power up or power down, so
other devices on the bus are also protected from data corruption.
2.1.2 LVD Link Technology
To support greater device connectivity and a longer SCSI cable, the
LSI53C141 features LVD Link technology, the LSI Logic implementation
of universal LVD SCSI. LVD Link transceivers provide the inherent
reliability of differential SCSI, and a long-term migration path of faster
SCSI transfer rates.
LVD Link technology is based on current drive. Since its low output
current reduces the power needed to drive the SCSI bus, the I/O drivers
can be integrated directly onto the chip. This reduces the cost and
complexity compared to traditional (high power) differential designs.
LVD Link lowers the amplitude of noise reflections and allows higher
transmission frequencies.
SCSI A-Side and B-Side SE Control Blocks
2-3
The LVD Link transceivers operate in LVD and SE modes. The
LSI53C141 automatically detects which type of signal is connected,
based on voltage detected by DIFFSENS, pin 46.
2.2 Retiming Logic
The SCSI signals, as they propagate from one side of the LSI53C141 to
the other side, are processed by logic that retimes the bus signals as
needed to guarantee or improve required SCSI timings. This logic is
governed by the state machine controls that keep track of SCSI phases,
the location of initiator and target devices, and various timing functions.
In addition, this logic contains numerous precision delay elements that
are periodically calibrated by the precision delay control block. The
purpose of this calibration is to guarantee specified timings, such as
output pulse widths, setup and hold times, and other timings.
2.3 Precision Delay Control
The precision delay control block provides calibration information to the
precision delay elements in the retiming logic block. The purpose of this
information is to maintain precise timings as signals propagate through
the device. The operating conditions for the LSI53C141, such as voltage
and temperature, vary over time. The precision delay control block
periodically updates the delay settings in the retiming logic to maintain
constant and precise control over bus timings.
2.4 State Machine Control
The state machine controls keep track of the SCSI bus phase protocol
and other internal operating conditions. This block provides signals to the
retiming logic that identifies how to properly handle SCSI bus signal
retiming and protocol, based on observed bus conditions.
2-4
Functional Description
2.5 Dynamic Mode Switching
The LSI53C141 supports dynamic transmission mode changes on the
bus segment that supports both LVD and SE (B-side SCSI bus). The
DIFFSENS circuitry detects a valid mode switch on the bus segment.
The new DIFFSENS state must be present for 100 ms before the
LSI53C141 declares a valid shift in transmission mode. The LSI53C141
then generates a SCSI reset on the opposite bus (A-side SCSI bus). This
reset informs any initiators residing on this opposing segment of the
change in transmission mode. These initiators may then analyze the
integrity of this mode change versus performance capabilities and
conduct any necessary renegotiations.
2.6 DIFFSENS Receiver
The LSI53C141 contains an LVD DIFFSENS receiver that detects the
voltage level on the DIFFSENS line for purposes of informing the
LSI53C141 of the transmission mode being used by the B-side SCSI
bus. The LVD DIFFSENS receiver is capable of detecting the voltage
level of an incoming SCSI signal to determine whether it is from a
SE or LVD device. A device does not change its present signal driver or
receiver mode based on the DIFFSENS voltage level unless a new mode
is sensed continuously for at least 100 ms.
Transmission mode detection for SE or LVD is accomplished through the
use of the DIFFSENS line. Table 2.1 shows the corresponding voltages
and what mode they indicate.
Table 2.1
DIFFSENS Voltage Levels
Mode
SE
LVD
Voltage
− 0.35 to + 0.5
0.7 to 1.9
Note: The maximum voltage allowed to this pin is 3.3 volts.
Dynamic Mode Switching
2-5
2.7 Signal Descriptions
Figure 2.2 illustrates the LSI53C141 signal groupings. A description of
the signals follows. For specific signal timings, see Section 4.3, “AC
Characteristics,” in Chapter 4.
Figure 2.2
A-Side
SE
Only
Data and
Control
LSI53C141 Signal Grouping
A_SD[15:0]/
A_SDP[1:0]/
A_SCD/
A_SIO/
A_SMSG/
A_SREQ/
A_SACK/
A_SBSY/
A_SATN/
A_SSEL/
A_SRST/
Control
Signals
RESET/
WS_ENABLE
XFER_ACTIVE
Clock
Input
CLOCK
LSI53C141
SE-to-LVD SCSI
Expander
128 PQFP
B_SD[15:0]−
B_SD[15:0]+
B_SDP[1:0]−
B_SDP[1:0]+
B_SCDB_SCD+
B_SIOB_SIO+
B_SMSGB_SMSG+
B_SREQB_SREQ+
B_SACKB_SACK+
B_SBSYB_SBSY+
B_SATNB_SATN+
B_SSELB_SSEL+
B_SRSTB_SRST+
RBIASRBIAS+
DIFFSENS
B-Side
SE
Data and Control
or
LVD
Data and Control
LVD Control
2.7.1 Data and Parity
The signals named A_SD[15:0]/ and A_SDP[1:0]/ are the data and parity
signals from the A-side; the signals named B_SD[15:0] and B_SDP[1:0]±
are the data and parity signals from the B-side of the LSI53C141. These
signals are sent and received from the LSI53C141 through a SCSI
compatible driver and receiver logic designed into the LSI53C141
interfaces. This logic provides the necessary drive, sense thresholds, and
input hysteresis to function correctly in a SCSI bus environment as
defined in ANSI Standard for SCSI-1, SCSI-2, and SCSI-3.
2-6
Functional Description
The LSI53C141 receives data and parity signals and passes them from
the source bus to the load bus and provides any necessary edge shifting
to guarantee the skew budget for the load bus. Either side of the
LSI53C141 can be the source bus or the load bus. The side asserting,
deasserting, or releasing the SCSI signals is the source side. The
following steps are a part of the LSI53C141 data path:
1. Asserted data is accepted from the receiver logic as soon as it is
received. Once the clock signal has been received, data is gated
from the receiver latch.
2. The path is tested to ensure the signal, if being driven by the
LSI53C141, is not misinterpreted as an incoming signal.
3. The data is then leading edge filtered. The assertion edge is held for
a specified time to prevent any signal bounce. The duration is then
controlled by the input signal.
4. The next stage is a latch that samples the signal. This provides a
stable data window for the load bus.
5. The final stage develops pull-up and pull-down controls for the SCSI
I/O logic, including 3-state controls for the pull-up.
6. A parallel function ensures that bus (transmission line) recovery is
ensured for a specified time after the last signal deassertion on each
signal line.
2.7.2 Busy (BSY) Control
A_SBSY/ and B_SBSY± signals are propagated from the source bus to
the load bus. These signals go through the following processing steps:
1. The path is tested to ensure the signal, if being driven by the
LSI53C141, is not misinterpreted as an incoming signal.
2. The data is then leading edge filtered. The assertion edge is held for
a specified time to prevent any signal bounce. The duration is then
controlled by the input signal.
3. The next stage has two modes. One mode simply passes data
through. The other mode behaves like a large filter. The current state
in the LSI53C141 state machine that tracks SCSI phases selects the
mode. The large filter mode is used where the Busy (BSY) and
Select (SEL) sources may switch from side to side. This output is
then fed to the output driver which is a pull-down open collector only.
Signal Descriptions
2-7
A parallel function ensures that bus (transmission line) recovery is
ensured for a specified time after the last signal deassertion on each
signal line.
2.7.3 Request (REQ)/Acknowledge (ACK) Control
A_SACK/, B_SACK±, A_SREQ/ and B_SREQ± are clock and control
signals. Their signal paths contain controls to guarantee minimum pulse
width, filter edges, and does some retiming when used as data transfer
clocks. Each signal, REQ and ACK, has paths from A to B and B to A.
The received signal goes through the following processing steps before
being sent to the opposite bus.
1. The asserted input signal is sensed and forwarded to the next stage
if the direction control permits it. The direction controls are developed
from state machines that are driven by the sequence of bus control
signals.
2. The signal must then pass the test of not being generated by the
LSI53C141.
3. In the A to B bus direction, the next stage is a leading edge filter.
This ensures that the output does not switch during the specified
hold time after the leading edge. The duration of the input signal
determines the duration of the output after the hold time. In the B to
A direction, the circuit guarantees a minimum pulse.
4. The next stage passes the signal if it is not a data clock. If REQ or
ACK is a data clock, it delays the leading edge to improve data
output setup times. The duration is again controlled by the input
signal.
5. The following stage is a trailing edge signal filter. When the signal
deasserts, the filter does not permit any signal bounce. The output
signal deasserts at the first deasserted edge of the input signal.
6. The last stage develops pull-up and pull-down signals with drive and
3-state control.
7. A parallel function ensures that bus (transmission line) recovery is
ensured for a specified time after the last signal deassertion on each
signal line.
2-8
Functional Description
2.7.4 Reset (RST) Control
A_SRST/ and B_SRST± are also passed from the source to the load
bus. These reset signals are processed in the following steps.
1. The input signal is blocked if it is already being driven by the
LSI53C141.
2. The next stage is a leading edge filter. This ensures that the output
does not switch for a specified time after the leading edge. The
duration of the input signal then determines the duration of the
output.
3. A parallel function ensures that bus (transmission line) recovery is
ensured for a specified time after the last signal deassertion on each
signal line.
2.7.5 Control/Data (C/D), Input/Output (I/O), Message (MSG) and
Attention (ATN) Controls
A_SCD/, A_SIO/, A_SMSG/, A_SATN/, B_SCD±, B_SIO±, B_SMSG±,
and B_SATN± are control signals that have the following processing
steps:
1. The input signal is blocked if it is being driven by the LSI53C141.
2. The next stage is a leading edge filter. This ensures that the output
does not switch for a specified time after the leading edge. The
duration of the input signal determines the duration of the output.
3. The final stage develops pull-up and pull-down controls for the SCSI
I/O logic, including 3-state controls for the pull-up.
4. A parallel function ensures that bus (transmission line) recovery is for
a specified time after the last signal deassertion on each signal line.
2.7.6 Select (SEL) Control
A_SSEL/ and B_SSEL± are control signals used during bus arbitration
and selection. Whichever bus asserts SEL propagates it to the other
side. If both signals are asserted at the same time, the A-side receives
SEL and sends it to the B-side. The signal goes through the following
processing steps.
1. The input signal is blocked if it is being driven by the LSI53C141.
Signal Descriptions
2-9
2. The next stage is a leading edge filter. This ensures that the output
does not switch for a specified time after the leading edge. The
duration of the input signal then determines the duration of the
output.
3. A parallel function ensures that bus (transmission line) recovery is
ensured for a specified time after the last signal deassertion on each
signal line.
2.7.7 Clock (CLOCK)
This is the 40 MHz oscillator input to the LSI53C141. This is the clock
source for protocol control state machines and timing generation logic.
This clock is not used in any bus signal transfer paths.
2.7.8 Chip Reset (RESET/)
This general chip reset is intended to force all the internal elements of
the LSI53C141 into a known state. This brings all state machines to an
idle state and force all controls to a passive state. The minimum RESET
input asserted pulse width is 100 nanoseconds.
The LSI53C141 also contains an internal Power On Reset (POR)
function that is wire ORed with the chip reset pin. This function eliminates
the need for an external chip reset.
Table 2.2
RESET/ Control Signal Polarity
Signal Level
State
Effect
LOW = 0
Asserted
Reset is forced to all internal LSI53C141
elements.
HIGH = 1
Deasserted
LSI53C141 is not in a forced reset state.
2.7.9 Warm SWAP Enable and Transfer Active (WS_ENABLE and
XFER_ACTIVE)
These two pins provide additional control capability for the LSI53C141.
They allow both the SCSI A-side bus and the SCSI B-side bus to be
logically disconnected. The XFER_ACTIVE output changes state only
with the detection of a SCSI bus free state; this guarantees that transfers
2-10
Functional Description
currently in progress are not disrupted by the assertion or deassertion of
the WS_ENABLE pin.
Assertion or deassertion of the WS_ENABLE pin may not be effective
immediately since it may take several milliseconds for a bus free state to
be detected and then indicated by a change in state of the
XFER_ACTIVE output signal.
Table 2.3
WS_ENABLE Signal Polarity
Signal
Level
State
Effect
LOW = 0
Asserted
The LSI53C141 discontinues transfers through the
device (off-line) upon detection of a SCSI bus free
state.
HIGH = 1
Deasserted
The LSI53C141 performs normal transfers through
the device.
Table 2.4
Signal
Level
XFER_ACTIVE Signal Polarity
State
Effect
HIGH = 1 Asserted
Indicates normal operation, transfers through the
LSI53C141 are enabled.
LOW = 0
The LSI53C141 has detected a bus free state due
to WS_ENABLE being LOW, disabling transfers
through the device.
Deasserted
2.8 SCSI Termination
The terminator networks provide the biasing needed to pull signals to an
inactive voltage level, and to match the impedance seen at the end of
the cable with the characteristic impedance of the cable. Terminators
must be installed at the extreme ends of the SCSI chain, and only at the
ends. No system should ever have more or less than two terminators
installed and active. SCSI host adapters should provide a means of
accommodating terminators. The terminators should be socketed so that,
SCSI Termination
2-11
if they are not needed, they may be removed. Otherwise, there should
be a means of disabling them with software.
The use of active termination is highly recommended. For information on
terminators that support LVD, refer to the SPI-2 Draft standard.
Important:
2-12
If the LSI53C141 is to be used in a design with only an
8-bit SCSI bus, all 16 data lines must still be terminated or
pulled HIGH.
Functional Description
Chapter 3
Signal Descriptions
The LSI53C141 is packaged in a 128-pin PQFP. Figure 3.1 shows the
decoupling capacitor arrangement recommended to maximize the
benefits of the internal split ground system. Capacitor values should be
between 0.01 µF and 0.1 µF. Figure 3.2 shows the signals, their
grouping, and their I/O direction. A slash (/) at the end of a signal name
indicates that it is an active LOW signal.
LSI53C141 SCSI Bus Expander
3-1
WS_ENABLE
127
VSS_SCSI
VDD_CORE
41
126
XFER_ACTIVE
NC
42
125
NC
NC
43
124
VDD_CORE
VSS_CORE
44
123
PROBE (NC)
RESET/
45
122
TESTIN (NC)
DIFFSENS
46
121
CLOCK
VDD_SCSI
47
120
HV-MODE(NC)
B_SD11-
48
119
VSS_CORE
B_SD11+
49
118
B_SD12+
B_SD10-
50
117
B_SD12B_SD10+
51
116
VSS_SCSI
VSS_SCSI
52
115
B_SD!3+
B_SD9-
53
114
B_SD13B_SD9+
54
113
B_SD14+
B_SD8-
55
112
B_SD14B_SD8+
56
111
VDD_SCSI
VDD_SCSI
57
110
B_SD15+
B_SIO-
58
109
B_SD15B_SIO+
59
108
B_SDP1+
B_SREQ-
60
107
B_SDP1B_SREQ+
61
106
VSS_SCSI
VSS_SCSI
62
105
B_SD0+
B_SCD-
63
104
B_SD0B_SCD+
64
103
B_SD1+
Top View
128
40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
NC
LSI53C141 Pin Diagram
3.1 LSI53C141 Pin Diagram
NC
NC
VDD_SCSI
A_SD12/
A_SD13/
A_SD14/
VSS_SCSI
A_SD15/
A_SDP1/
A_SD0/
A_SD1/
VSS_SCSI
A_SD2/
A_SD3/
A_SD4/
A_SD5/
VSS_SCSI
A_SD6/
A_SD7/
A_SDP0/
A_SATN/
VSS_SCSI
A_SBSY/
A_SACK/
A_SRST/
A_SMSG
A_SSEL
VSS_SCSI
A_SCD/
A_SREQ/
A_SIO
A_SDB8/
VSS_SCSI
A_SD9/
A_SD10/
A_SD11/
VDD_SCSI
NC
5VBIAS
Signal Descriptions
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
B_SD1VDD_SCSI
VSS_SCSI
B_SD2+
B_SD2B_SD3+
B_SD3B_SD4+
B_SD4B_SD5+
B_SD5VDD_SCSI
B_SD6+
B_SD6B_SD7+
B_SD7NC
B_SDP0+
B_SDP0VSS_SCSI
RBIAS+
RBIASVSS_SCSI
B_SATN+
B_SATNVDD_SCSI
B_SBSY+
B_SBSYB_SACK+
B_SACKB_SRST+
B_SRSTB_SMSG+
B_SMSGVSS_SCSI
VDD_SCSI
B_SSEL+
B_SSEL-
SCSI B-Side (Low Voltage Differential or Single-Ended)
Figure 3.1
3-2
SCSI A-Side (Single-Ended Only)
3.2 LSI53C141 Signal Grouping
Figure 3.2
A-Side
SE Only
Data and
Control
LSI53C141 Functional Signal Grouping
A_SD[15:0]/
A_SDP[1:0]/
A_SCD/
A_SIO/
A_SMSG/
A_SREQ/
A_SACK/
A_SBSYU/
A_SATN/
A_SSEL/
A_SRST/
Control
Signals
RESET/
WS_ENABLE
XFER_ACTIVE
Clock
Input
CLOCK
LSI53C141
SE-to-LVD SCSI
Expander
128 PQFP
LSI53C141 Signal Grouping
B_SD[15:0]−
B_SD[15:0]+
B_SDP[1:0]−
B_SDP[1:0]+
B_SCDB_SCD+
B_SIOB_SIO+
B_SMSGB_SMSG+
B_SREQB_SREQ+
B_SACKB_SACK+
B_SBSYB_SBSY+
B_SATNB_SATN+
B_SSELB_SSEL+
B_SRSTB_SRST+
RBIASRBIAS+
DIFFSENS
B-Side
SE
Data and Control
or LVD
Data and Control
LVD Control
3-3
3.3 SCSI A Interface Pins
Table 3.1
SCSI A
SCSI A Signal Description
Pin
Type
A_SD[15:0]/
8, 6, 5, 4, 36, 35, 34,
32, 19, 18, 16, 15, 14,
13, 11, 10
I/O
Data (16-bit SCSI bus)
A_SDP[1:0]/
9, 20
I/O
Data parity bits
A_SCD/
29
I/O
Phase line, command/data
A_SIO/
31
I/O
Phase line, input/output
A_SMSG/
26
I/O
Phase line, message
A_SREQ/
30
I/O
Data handshake signal from target device
A_SACK/
24
I/O
Data handshake signal from initiator device
A_SBSY/
23
I/O
Bus arbitration signal, busy
A_SATN/
21
I/O
Attention, the initiator is requesting a message out
phase
A_SSEL/
27
I/O
Bus arbitration signal, select device
A_SRST/
25
I/O
Bus reset
3-4
Signal Descriptions
Description
3.4 SCSI B SE and LVD Interface Pins
Table 3.2
SCSI B
SCSI B Signal Description
Pin
Type
Description
B_SD[15:0]+
110, 113, 115,
118, 49, 51, 54,
56, 88, 90, 93, 95,
97, 99, 103, 105
I/O
Differential+ Signal Data (16-bit SCSI bus)
B_SD[15:0]−
109, 112, 114,
117, 48, 50, 53,
55, 87, 89, 92, 94,
96, 98, 102, 104
I/O
Differential− Signal Data (16-bit SCSI bus)
B_SDP[1:0]+
108, 85
I/O
Differential+ Signal Data parity bits
B_SDP[1:0]−
107, 84
I/O
Differential− Signal Data parity bits
B_SCD±
63, 64
I/O
Differential Signal Phase line, command/data
B_SIO±
58, 59
I/O
Differential Signal Phase line, input/output
B_SMSG±
69, 70
I/O
Differential Signal Phase line, message
B_SREQ±
60, 61
I/O
Differential Signal Data handshake signal from target
device
B_SACK±
73, 74
I/O
Differential Signal Data handshake signal from initiator
device
B_SBSY±
75, 76
I/O
Differential Signal Bus arbitration signal, busy
B_SATN±
78, 79
I/O
Differential Signal Attention, the initiator is requesting a
message out phase
B_SSEL±
65, 66
I/O
Differential Signal Bus arbitration signal, select device
B_SRST±
71, 72
I/O
Differential Signal Bus Reset
RBIAS±
81, 82
I
The RBIAS± pins need to have a 2.0 kΩ, 1% resistor
between them to provide the correct bias current to the
LVD pads. Additionally, +3.3 V needs to be connected
to the RBIAS−, pin 81
Note: An SE interface uses only the − (minus) signals. LVD interface uses both
the + and − signals.
SCSI B SE and LVD Interface Pins
3-5
3.5 Interface Control Pins
Table 3.3
Chip Control Signal Description
Control
Pin
Type
Description
RESET/
45
I
Master reset, active LOW
WS_ENABLE
128
I
Enable/disable SCSI transfers through LSI53C141
XFER_ACTIVE
126
O
Transfers through the LSI53C141 are enabled/disabled
3.6 SCSI Control Pins
Table 3.4
SCSI Control Signal Description
SCSI Control
Pin
Type
CLOCK
121
I
40 MHz input clock
DIFFSENS
46
I
The Differential Sense pin detects the voltage level of an incoming
SCSI signal to determine whether it originates from an SE, LVD, or
high-power source.
This pin should be connected to the DIFFSENS signal on the SCSI
cable.
Note: The maximum voltage allowed to this pin is 3.3 V
3-6
Description
Signal Descriptions
3.7 Power and Ground Pins
Table 3.5
Power and Ground Signal Description
Power and Ground
Pin
Type Description
VDD_SCSI
3, 37, 47,
57, 67, 77,
91, 101,
111
I
Power supplies to the SCSI bus I/O pins
VSS_SCSI
7, 12, 17,
22, 28,
33,52, 62,
68, 80, 83,
100, 106,
116, 127
I
Ground for the SCSI bus I/O pins
VDD_CORE
41, 124
I
Power supplies to the CORE logic
VSS_CORE
44, 119
I
Ground for the CORE logic
39
I
5 V biasing pin. This pin must be supplied with 5 V in a
5 V environment
Connecting 5VBIAS pin to 5 V allows for 5 V inputs on the
CLK, WS_ENABLE, and RESET/
Connecting 5VBIAS pin to 3.3 V allows for 3.3 V inputs on
the CLK, WS_ENABLE, and RESET/ pins
5VBIAS
Note: All VDD pins must be supplied 3.3 volts. The LSI53C141 output signals
drive 3.3 volts.
Note: If you separate the power supplies to VDD_IO and VDD_CORE pins in a
chip testing environment, either power up the pins simultaneously or power
up VDD_CORE before VDD_IO. The VDD_IO pin must always power down
before the VDD_CORE pin.
Power and Ground Pins
3-7
3.8 No Connection Pins
Table 3.6
No Connect Pins
No Connects
Pin
Type
NC
2, 38, 40, 43,
86, 123, 125
NC
Table 3.7
Description
Make no external connection
Internal Test Pins
Internal Test
Pin
Type
Reserved
1, 42, 122
Reserved
Pull-ups should be connected to the following pins:
1, 42, and 122. (4.5K resistor to +5 V or 3.3 V)
Reserved
120
Reserved
A pull-down should be connected to pin 120
(100 Ω resistor to ground)
3-8
Signal Descriptions
Description
Chapter 4
Specifications
4.1 DC Characteristics
Table 4.1
Symbol
Absolute Maximum Stress Ratings
Parameter
Min
Max
Unit
Test Conditions
TSTG
Storage temperature
−55
150
°C
–
VDD
Supply voltage
−0.5
5.0
V
–
VIN
Input Voltage
VSS −0.3
VDD +0.3
V
–
ILP1
Latch-up current
±150
–
mA
–
–
2K
V
MIL-STD 883C,
Method 3015.7
ESD2
Electrostatic discharge
1. − 2 V < VPIN < 8 V.
2. SCSI pins only.
Note:
Stresses beyond those listed above may cause permanent damage to the device. These
are stress ratings only; functional operation of the device at these or any other conditions
beyond those indicated in the Operating Conditions section of the manual is not implied.
LSI53C141 SCSI Bus Expander
4-1
Table 4.2
Symbol
Parameter
Min
Max
Unit
Test Conditions
VDD
Supply voltage
3.1
3.45
V
–
IDD
Supply current (dynamic SE)
Supply current (dynamic LVD)
–
–
130
600
mA
mA
Supply current (static)
–
1
mA
–
RBIAS = 2.0 kΩ, 1%
VDD = 3.3 V
–
TA
Operating free air
0
70
°C
–
θJA
Thermal resistance
(junction to ambient air)
–
67
°C/W
–
Note:
Table 4.3
Symbol
Conditions that exceed the operating limits may cause the device to function incorrectly.
SCSI Signals—A_SD[15:0]/, A_SDP[1:0]/, A_SREQ/, A_SACK/,
B_SD[15:0], B_SDP[1:0], B_SREQ, B_SACK
Parameter
Min
Max
Unit
Test Conditions
VIH
Input high voltage
1.9
VDD +0.5
V
–
VIL
Input low voltage
VSS −0.5
1.0
V
–
VOH*
Output high voltage
2.4
3.5
V
2.5 mA
VOL
Output low voltage
VSS
0.4
V
48 mA
IOZ
3-state leakage
−10
10
µA
–
Note:
4-2
Operating Conditions
TolerANT active negation enabled.
Specifications
Table 4.4
Symbol
SCSI Signals—A_SCD/, A_SIO/, A_SMSG/, A_SBSY/, A_SATN/, A_SSEL/,
A_SRST/, B_SCD, B_SIO, B_SMSG, B_SBSY, B_SATN, B_SSEL, B_SRST
Parameter
Min
Max
Unit
Test Conditions
VIH
Input high voltage
1.9
VDD +0.5
V
–
VIL
Input low voltage
VSS −0.5
1.0
V
–
VOL
Output low voltage
VSS
0.5
V
48 mA
IOZ
3-state leakage
(SRST/ only)
−10
−500
10
−50
µA
–
Table 4.5
Symbol
Input Signal—CLOCK
Parameter
Min
Max
Unit
Test Conditions
VIH
Input high voltage
2.0
VDD +0.5
V
–
VIL
Input low voltage
VSS −0.5
0.8
V
–
IIN
Input leakage
−20
20
µA
–
Table 4.6
Symbol
Input Signal—DIFFSENS
Parameter
Min
Max
Unit
Test Conditions
VIH
Input high voltage
2.0
VDD +0.5
V
–
VIL
Input low voltage
VSS −0.5
0.8
V
–
IIN
Input leakage
−10
10
µA
–
Min
Max
Unit
Test Conditions
Table 4.7
Symbol
Capacitance
Parameter
CI
Input capacitance of
input pads
–
7
pF
–
CIO
Input capacitance of
I/O pads
–
10
pF
–
DC Characteristics
4-3
Table 4.8
Symbol
SCSI Signals, LVD Drivers—B_SD[15:0], B_SDP[1:0], B_SCD, B_SIO,
B_SMSG, B_SREQ, B_SACK, B_SBSY, B_SATN, B_SSEL,
B_SRST*
Parameter
Min
Max
Units
Test Conditions
IO+
Source (+) current
7
11
mA
Asserted state
IO−
Sink (−) current
−7
−11
mA
Asserted state
IO+
Source (+) current
−3.5
−5.5
mA
Negated state
IO−
Sink (−) current
3.5
5.5
mA
Negated state
IOZ
3-state leakage
−20
20
µA
–
*IOZ (SRST-
3-state leakage
−500
−50
µA
–
only)
VCM = 0.7–1.8 V.
RL = 0–110 Ω.
Rbias = 2.0 kΩ.
Figure 4.1
LVD Transmitter
I O+
RL/2
+
VCM
+
−
Table 4.9
Symbol
IO−
SCSI Signals, LVD Receivers—B_SD[15:0], B_SDP[1:0] ,B_SCD,
B_SIO, B_SMSG, B_SREQ, B_SACK, B_SBSY, B_SATN, B_SSEL,
B_SRST
Parameter
Min
Max
Units
VI
LVD receiver voltage asserting
60
–
mV
VI
LVD receiver voltage negating
–
−60
mV
VCM = 0.7–1.8 V
4-4
−
RL/2
Specifications
Figure 4.2
LVD Receiver
+
+
VCM
−
Table 4.10
Symbol
VI/2
−
+
+
−
VI/2
−
SCSI Signal—DIFFSENS
Parameter
Min
Max
Unit
Test Conditions
VIH
HVD sense voltage
2.4
VDD +0.3
V
–
VS
LVD sense voltage
.7
1.9
V
–
VIL
SE sense voltage
VSS −0.3
0.5
V
–
IOZ
3-state leakage
−10
10
µA
–
Table 4.11
Symbol
Control Signals—RESET/, WS_ENABLE
Parameter
Min
Max
Unit
Test Conditions
VIH
Input high voltage
2.0
VDD +0.5
V
–
VIL
Input low voltage
VSS −0.5
0.8
V
–
IOZ
3-state leakage
−20
20
µA
–
Table 4.12
Symbol
Control Signals—XFER_ACTIVE
Parameter
Min
Max
Unit
Test Conditions
VOH
Output high voltage
2.4
VDD
V
16 mA
VOL
Output low voltage
VSS
0.4
V
16 mA
IOZ
3-state leakage
−10
10
µA
–
DC Characteristics
4-5
4.2 TolerANT Technology Electrical Characteristics
Table 4.13
Symbol
Parameter
Min
Max
Units
Test Conditions
VOH1
Output high voltage
2.5
3.5
V
IOH = 2.5 mA
VOL
Output low voltage
0.1
0.5
V
IOL = 48 mA
VIH
Input high voltage
1.9
7.0
V
–
VIL
Input low voltage
−0.5
1.0
V
Referenced to VSS
VIK
Input clamp voltage
−0.66
−0.77
V
VDD = 4.75;
II = − 20 mA
VTH
Threshold, high to low
1.1
1.3
V
–
VTL
Threshold, low to high
1.5
1.7
V
–
Hysteresis
200
400
mV
–
IOH1
Output high current
2.5
24
mA
VOH = 2.5 V
IOL
Output low current
100
200
mA
VOL = 0.5 V
VTH-VTL
IOSH1
Short-circuit output high
current
–
625
mA
Output driving low,
pin shorted to VDD
supply2
IOSL
Short-circuit output low
current
–
95
mA
Output driving high,
pin shorted to VSS
supply
ILH
Input high leakage
–
10
µA
−0.5 < VDD < 5.25
VPIN = 2.7 V
ILL
Input low leakage
–
− 10
µA
−0.5 < VDD < 5.25
VPIN = 0.5 V
RI
Input resistance
20
–
MΩ
SCSI pins3
CP
Capacitance per pin
–
10
pF
PQFP
tR1
Rise time, 10% to 90%
9.7
18.5
ns
Figure 4.3
Note:
4-6
TolerANT Technology Electrical Characteristics
These values are guaranteed by periodic characterization; they are not 100% tested
on every device.
Specifications
Table 4.13
Symbol
TolerANT Technology Electrical Characteristics (Cont.)
Parameter
Min
Max
Units
Test Conditions
Fall time, 90% to 10%
5.2
14.7
ns
Figure 4.3
dVH/dt
Slew rate, LOW to HIGH
0.15
0.49
V/ns
Figure 4.3
dVL/dt
Slew rate, HIGH to LOW
0.19
0.67
V/ns
Figure 4.3
2
–
kV
MIL-STD-883C;
3015-7
Latch-up
100
–
mA
–
Filter delay
10
15
ns
Figure 4.4
tF
ESD
Note:
Electrostatic discharge
These values are guaranteed by periodic characterization; they are not 100% tested
on every device.
1. Active negation outputs only: Data, Parity, SREQ/, SACK/.
2. Single pin only; irreversible damage may occur if sustained for one second.
3. SCSI RESET pin has 10 kΩ pull-up resistor.
Figure 4.3
Rise and Fall Time Test Conditions
47 Ω
+
20 pF
Figure 4.4
−
2.5 V
SCSI Input Filtering
t1
REQn or ACKn Input
VTL
TolerANT Technology Electrical Characteristics
4-7
Figure 4.5
Hysteresis of SCSI Receiver
1.1
1.3
Receiving Logic Level
1
0
1.5
1.7
Input Voltage (Volts)
Input Current (milliamperes)
Figure 4.6
+ 40
+ 20
0
− 0.7 V
Output
Active
− 40
-4
0
4
8
12
16
Output Current as a Function of Output Voltage
−200
−400
−600
−800
1
2
3
4
Output Voltage (Volts)
4-8
HIGH-Z
− 20
0
0
14.4 V
8.2 V
Specifications
5
Output Source Current (milliamperes)
Output Sink Current (milliamperes)
Figure 4.7
Input Current as a Function of Input Voltage
100
80
60
40
20
0
0
1
2
3
4
Output Voltage (Volts)
5
4.3 AC Characteristics
The AC characteristics described in this section apply over the entire
range of operating conditions (refer to Section 4.1, “DC Characteristics”).
Chip timings are based on simulation at worst case voltage, temperature,
and processing. The LSI53C141 requires a 40 MHz clock input.
Table 4.14
Symbol
Clock Timing
Parameter
Min
Max
Units
t1
Clock period
24.5
25.5
ns
t2
Clock LOW time
10
15
ns
t3
Clock HIGH time
10
15
ns
t4
Clock rise time
1
–
V/ns
Figure 4.8
Clock Timing
t1
t3
CLOCK
t4
t2
4.3.1 SCSI Interface Timings
Table 4.15
Symbol
Input Timings
Parameter
Min
Max
Units
t1
Input data setup
2
–
ns
t2
Input data hold
6
–
ns
t3
Input REQ/ACK assertion pulse
width
11
–
ns
t4
Input REQ/ACK deassertion pulse
width
16
–
ns
AC Characteristics
4-9
Table 4.16
Output Timings
Symbol Parameter
Min
Max
Units
t5
Output data setup
min [t1 + 18ns, t4 + 5]
–
ns
t6
Output data hold
max [18, (t2 −20), t3]
–
ns
t7
Output REQ/ACK pulse
width
max [20 ns, t3 −5]
max [30 ns, t3 +5]
ns
t8
REQ/ACK transport
delay
25 ns if REQ/ACK is clock
for input data,10 ns if not
50 ns if REQ/ACK is clock
for input data, 30 ns if not
ns
t9
Data transport delay
6
[t3 +35]
ns
Figure 4.9
Input/Output Timings
t3
Input Timings
t4
REQ or ACK
t1
t2
Valid Data
DATA
t8
Output Timings
t7
REQ or ACK
t9
t6
Valid Data
DATA
4-10
t5
Specifications
4.4 LSI53C141 Mechanical Drawing
The LSI53C141 comes in a 128-pin metric PQFP with a 3.9 mm footprint.
Figure 4.10 LSI53C141 Mechanical Drawing
23.9 mm
20.0 mm
0.50 mm
17.9 mm
128-Pin
PQFP
14.0 mm
Pin 1
Detail A
Detail A
0 ˚ Min
2.80 ± 0.25
3.40 Max
0˚−7˚
Seating Plane
0.13 mm
0.40 Min
0.80 ± 0.15
0.22 ± 0.05
1.95
Note: All dimensions are in millimeters.
Important:
This drawing may not be the latest version. For board layout and manufacturing,
obtain the most recent engineering drawings from your LSI Logic marketing representative by
requesting the outline drawing.
LSI53C141 Mechanical Drawing
4-11
4-12
Specifications
Appendix A
Glossary of Terms and
Abbreviations
ACK/
Acknowledge
Driven by an initiator, ACK/ indicates an acknowledgment for a SCSI data
transfer. In the target mode, ACK/ is received as a response to the
REQ/ signal.
ANSI
American National Standards Institute.
Arbitration
The process of selecting one respondent from a collection of several
candidates that request service concurrently.
Asserted
A signal is asserted when it is in the state which is indicated by the name
of the signal. Opposite of negated or deasserted.
Assertion
The act of driving a signal to the true state.
Asynchronous
Transmission
Transmission in which each byte of the information is synchronized
individually, through the use of Request (REQ/) and Acknowledge (ACK/)
signals.
ATN/
Attention
Driven by an initiator, indicates an attention condition. In the target role,
ATN/ is received and is responded to by entering the Message Out
Phase.
Block
A block is the basic 512 byte region of storage into which the storage
media is divided. The Logical Block Address protocol uses sequential
block addresses to access the media.
BSY/
Busy
Indicates that the SCSI Bus is being used. BSY/ can be driven by both
the initiator and the target device.
Bus
A collection of unbroken signal lines that interconnect computer modules.
The connections are made by taps on the lines.
Bus Expander
Bus expander technology permits the extension of a bus by providing
some signal filtering and retiming to maintain signal skew budgets.
LSI53C141 SCSI Bus Expander
A-1
Cable Skew
Delay
Cable skew delay is the minimum difference in propagation time allowed
between any two SCSI bus signals measured between any two SCSI
devices.
C_D/
Control/Data
Driven by a target, indicates Control or Data Information is on the SCSI
Bus. This signal is received by the initiator.
Connect
The function that occurs when an initiator selects a target to start an
operation, or a target reselects an initiator to continue an operation.
Control Signals
The set of nine lines used to put the SCSI bus into its different phases.
The combinations of asserted and negated control signals define the
phases.
Controller
A computer module that interprets signals between a host and a
peripheral device. Often, the controller is a part of the peripheral device,
such as circuitry on a disk drive.
DB0/-DB7/
SCSI Data Bits and Parity Bit
These eight Data Bits (DB0/–DB7/), plus a Parity Bit (DBP/), form the
SCSI bus. DB7/ is the most significant bit and has the highest priority ID
during the Arbitration Phase. Data parity is odd. Parity is always
generated and optionally checked. Parity is not valid during arbitration.
Deasserted
The act of driving a signal to the false state or allowing the cable
terminators to bias the signal to the false state (by placing the driver in
the high impedance condition). A signal is deasserted or negated when
it is in the state opposite to that which is indicated by the name of the
signal. Opposite of asserted.
Device
A single unit on the SCSI bus, identifiable by an SCSI address. It can be
a processor unit, a storage unit (such as a disk or tape controller or
drive), an output unit (such as a controller or printer), or a
communications unit.
Differential
A signaling alternative that employs differential drivers and receivers to
improve signal-to-noise ratios and increase maximum cable lengths.
Disconnect
The function that occurs when a target releases control of the SCSI bus,
allowing the bus to go to the bus free phase.
Driver
When used in the context of electrical configuration, “driver” is the
circuitry that creates a signal on a line.
A-2
Glossary of Terms and Abbreviations
External
Configuration
All SCSI peripheral devices are external to the host enclosure.
External
Terminator
The terminator that exists on the last peripheral subsystem that
terminates the external end of the SCSI bus.
Free
In the context of bus free phase, “free” means that no SCSI device is
actively using the SCSI bus and, therefore, the bus is available for use.
Host
A processor, usually consisting of the central processing unit and main
memory. Typically, a host communicates with other devices, such as
peripherals and other hosts. On the SCSI bus, a host has an SCSI
address.
Host Adapter
Circuitry that translates between a processor's internal bus and a
different bus, such as SCSI. On the SCSI bus, a host adapter usually
acts as an initiator.
Initiator
A SCSI device that requests another SCSI device (a target) to perform
an operation. Usually, a host acts as an initiator and a peripheral device
acts as a target.
Internal
Configuration
All SCSI peripheral devices are internal to the host enclosure.
Internal
Terminator
The terminator that exists within the host that terminates the internal end
of the SCSI bus.
I/O
Input/Output
Driven by a target, controls the direction of data transfer on the SCSI bus.
When active, this signal indicates input to the initiator. When inactive, this
signal indicates output from the initiator. This signal is also used to
distinguish between the Selection and Reselection Phases.
I/O Cycle
An I/O cycle is an Input (I/O Read) operation or Output (I/O Write)
operation that accesses the PC Card’s I/O address space.
Logical Unit
The logical representation of a physical or virtual device, addressable
through a target. A physical device can have more than one logical unit.
LOW
(logical level)
A signal is in the LOW logic level when it is below approximately
0.5 volts.
Glossary of Terms and Abbreviations
A-3
LSB
Least Significant Bit or Least Significant Byte
That portion of a number, address, or field that occurs right-most when
its value is written as a single number in conventional hexadecimal or
binary notation. The portion of the number having the least weight in a
mathematical calculation using the value.
LUN
Logical Unit Number
Used to identify a logical unit.
Mandatory
A characteristic or feature that must be present in every implementation
of the standard.
MHz
MegaHertz
Measurement in thousands of cycles per second. Used as a
measurement of data transfer rate.
µs
Microsecond
One millionth of a second.
MSB
Most Significant Bit and Most Significant Byte
That portion of a number, address or field that occurs left-most when its
value is written as a single number in conventional hexadecimal or binary
notation. The portion of the number having the most weight in a
mathematical calculation using the value.
MSG/
Message
Driven active by a target during the Message Phase. This signal is
received by the initiator.
Negated
A signal is negated or deasserted when it is in the state opposite to that
which is indicated by the name of the signal. Opposite of asserted.
Negation
The act of driving a signal to the false state or allowing the cable
terminators to bias the signal to the false state (by placing the driver in
the high impedance condition).
ns
Nanosecond
One billionth of a second.
Parity
A method of checking the accuracy of binary numbers. An extra bit,
called a parity bit, is added to a number. If even parity is used, the sum
of all ones in the number and its corresponding parity is always even. If
odd parity is used, the sum of the ones and the parity bit is always odd.
A-4
Glossary of Terms and Abbreviations
Peripheral
Device
A device that can be attached to an SCSI bus. Typical peripheral devices
are disk drives, tape drives, printers, CD ROMs, or communications units.
Phase
One of the eight states to which the SCSI bus can be set. During each
phase, different communication tasks can be performed.
Port
A connection into a bus. The SCSI bus allows eight ports.
Priority
The ranking of the devices on the bus during arbitration.
Protocol
A convention for data transmission that encompasses timing control,
formatting, and data representation.
Receiver
The circuitry that receives electrical signals on a line.
Reconnect
The function that occurs when a target reselects an initiator to continue
an operation after a disconnect.
Release
The act of allowing the cable terminators to bias the signal to the false
state (by placing the driver in the high impedance condition).
REQ/
Request
Driven by a target, indicates a request for an SCSI data-transfer
handshake. This signal is received by the initiator.
Reselect
A target can disconnect from an initiator in order to perform a
time-consuming function, such as a disk seek. After performing the
operation, the target can “reselect” the initiator.
RESET
Reset
Clears all internal registers when active. It does not assert the SCSI
RST/ signal and therefore does not reset the SCSI bus.
RST
Reset
Indicates an SCSI Bus reset condition.
SCSI Address
The octal representation of the unique address (0–7) assigned to an
SCSI device. This address is normally assigned and set in the SCSI
device during system installation.
SCSI ID
(Identification) or SCSI Device ID
The bit-significant representation of the SCSI address referring to one of
the signal lines DB0/ through DB7/.
SCSI
Small Computer System Interface.
Glossary of Terms and Abbreviations
A-5
SCAM
SCSI Configured Automatically
SCAM is the new automatic ID assignment protocol for SCSI. SCAM
frees SCSI users from locating and setting SCSI ID switches and
jumpers. SCAM is the key part of Plug and Play SCSI.
SEL/
Select
Used by an initiator to select a target or by a target to reselect an initiator.
Single-Ended
Configuration
An electrical signal configuration that uses a single line for each signal
referenced to a ground path common to the other signal lines. The
advantage of a single-ended configuration is that it uses half the pins,
chips, and board area that differential/low voltage differential
configurations require. The main disadvantage of single-ended
configurations is that they are vulnerable to common mode noise. Also,
cable lengths are limited.
Synchronous
Transmission
Transmission in which the sending and receiving devices operate
continuously at the same frequency and are held in a desired phase
relationship by correction devices. For buses, synchronous transmission
is a timing protocol that uses a master clock and has a clock period.
Target
An SCSI device that performs an operation requested by an initiator.
Termination
The electrical connection at each end of the SCSI bus, composed of a
set of resistors.
µs
Microsecond
One millionth of a second.
A-6
Glossary of Terms and Abbreviations
Index
Symbols
asynchronous transmission A-1
attention 3-4, 3-5
ATN A-1
(A_SACK/) 2-8, 3-4
(A_SATN/) 2-9, 3-4
(A_SBSY/) 2-7, 3-4
(A_SCD/) 2-9, 3-4
(A_SD[15:0]) 3-4
(A_SD[15:0], P0, P1) 2-6
(A_SDP[1:0]) 3-4
(A_SIO/) 3-4
(A_SMSG/) 2-9, 3-4
(A_SREQ/) 2-8, 3-4
(A_SRST/) 2-9, 3-4
(A_SSEL/) 2-9, 3-4
(ACK) 2-8
(ATN) 2-9
(B_SACK/) 2-8, 3-5
(B_SATN/) 2-9, 3-5
(B_SBSY/) 2-7, 3-5
(B_SCD/) 2-9, 3-5
(B_SD[15:0], P0, P1) ) 2-6
(B_SIO/) 2-9, 3-5
(B_SMSG/) 2-9, 3-5
(B_SREQ/) 2-8, 3-5
(B_SRST/) 2-9, 3-5
(B_SSEL/) 2-9, 3-5
(BSY) 2-7
(CLOCK) 2-10
(REQ) 2-8
(RST) 2-9
B
B 3-5
backward compatibility 1-4
balanced duty cycles 2-3
bidirectional connections 2-2
block A-1
BSY A-1
bus A-1
arbitration 3-4, 3-5
reset 3-5
timings 2-4
C
Numerics
128-pin plastic quad flat pack 1-3
3-state 2-7
leakage 4-2
A
absolute maximum stress ratings 4-1
AC characteristics 4-9
ACK 2-8, A-1
acknowledge 2-3
active negation 2-3
ANSI A-1
standard X3.131 2-6
application examples 1-4
applications 1-2
arbitration A-1
asserted A-1
assertion A-1
calibration 2-4
capacitance 4-3
chip reset (RESET/) 2-10
CLOCK 3-6
clock
signal 2-7
timing 4-9
cluster configuration 1-6
clustering example 1-6
configuration 1-4, 1-5, 1-8
connect A-2
control signals 4-5, A-2
control/data (C/D) 2-9
controller A-2
converter mode 1-1
D
data 2-3, 2-6, 3-5
handshake 3-4, 3-5
parity bits 3-5
DB0–DB7 A-2
deasserted A-2
decoupling capacitor 3-1
delay settings 2-4
device A-2
DIFF_SENSE 2-4, 2-5, 3-6
receiver 2-5
differential transceivers 1-4
disconnect A-2
double clocking of data 2-3
driver A-2
LSI53C141 SCSI Bus Expander
IX-1
E
EEPROM A-3
electrically isolated 1-6
electrostatic discharge 4-1
enable/disable SCSI transfers 3-6
ESD 4-1
external SCSI bus 1-8
F
filter edges 2-8
free A-3
G
glitches 2-3
H
high voltage differential SCSI 1-4
host A-3
host adapter A-3
HVD 1-1
hysteresis 2-6
I
I/O A-3
I/O cycle A-3
identification A-5
initiator A-3
input
capacitance of I/O pads 4-3
capacitance of input pads 4-3
high voltage 4-2
low voltage 4-2
signals 4-3
timings 4-9
voltage 4-1
input/output (I/O) 2-9
internal
SCSI bus 1-8
split ground system 3-1
L
latch-up current 4-1
leading edge filter 2-9
leading edge filtered 2-7
load bus 2-7
logical unit A-3
low (logical level) A-3
LSB A-4
LSI53C120 bus expander 1-1
LSI53C141 pin diagram 3-2
LSI53C141 SCSI bus expander 1-1
LSI53C7XX 1-3
LSI53C895 Ultra2 SCSI controller 1-1
LSI53C8XX 1-3
LUN A-4
LVD 1-2
control 2-1
DIFF_SENSE 2-5
to SE example 1-4
IX-2
LVD Link 1-4
benefits 1-4
DC characteristics 4-4
technology 2-3
transceivers 1-2, 1-4, 2-4
M
mandatory A-4
master reset 3-6
message (MSG) 2-9
MHz A-4
microsecond A-4
migration path 1-4
MSB A-4
MSG A-4
N
nanosecond A-4
negated A-4
negation A-4
O
operating conditions 4-2
operating free air 4-2
output
high voltage 4-2
low voltage 4-2
timings 4-10
P
parallel function 2-8, 2-9
parity 2-3, 2-6, A-4
peripheral device A-5
phase A-5
Phase line 3-5
phase line 3-4, 3-5
plastic quad flat pack (PQFP) 3-1
port A-5
power down 2-3
power on reset (POR) 2-10
power up 2-3
PQFP 1-3
precision delay
control 2-1
control block 2-4
elements 2-4
priority A-5
protocol A-5
pull-down 2-7, 2-9
pull-up 2-7, 2-9
pulse width 2-8
R
RC-type input filters 2-3
receiver A-5
receiver latch 2-7
reconnect A-5
recovery 2-8
release A-5
reliability issue 2-3
REQ 2-8, A-5
request 2-3
reselect A-5
reserved A-5
RESET/ 2-10, 3-6, A-5
control signal polarity 2-10
retiming 2-8
circuit 2-1
logic block 2-4
RST A-5
S
SCSI A-5
address A-5
A-side 1-3
B-side 1-3
B-side signal description 3-5
bus electrical isolation 1-8
bus free state 2-10
bus protocol 2-4
device ID A-5
I/O logic 2-9
ID A-5
interface timings 4-9
parallel interconnect 1-3
phases 2-4
signals 4-3
TolerANT technology 2-3
SCSI A-side signal description 3-4
SEL 2-9, A-6
select (SEL) 2-9
server clustering 1-2
signal groupings 2-6
signal skew 2-2
single-ended
configuration A-6
control blocks 2-2
SE to SE and SE to LVD example 1-5
to differential 1-5
to single-ended 1-5, 2-2
software 2-1
source bus 2-2, 2-7
state machine 2-8
control 2-1, 2-4
storage temperature 4-1
supply voltage 4-1
synchronous transmission A-6
U
Ultra SCSI 1-4
peripherals 1-1
Ultra2 SCSI 1-1
V
VDD_CORE 3-7
VDD_SCSI 3-7
voltage 2-4
VSS_CORE 3-7
VSS_SCSI 3-7
W
warm start enable and transfer active 2-10
wide Ultra SCSI 2-3
WS_ENABLE 2-11, 3-6
WS_ENABLE signal polarity 2-11
X
XFER_ACTIVE 2-10, 3-6
XFER_ACTIVE signal polarity 2-11
T
target A-6
temperature 2-4
termination A-6
thermal resistance 4-2
TolerANT
drivers and receivers 2-3
electrical characteristics 4-6
receiver technology 2-3
SCSI 2-3
technology 2-3
transceiver 1-2
typical applications 1-4
IX-3
IX-4
Customer Feedback
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LSI53C141 SCSI Bus Expander
Reader’s Comments
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Name
Telephone
Title
Department
Company Name
Street
City, State, Zip
Customer Feedback
Date
Fax
Mail Stop
U.S. Distributors
by State
A. E.
Avnet Electronics
http://www.hh.avnet.com
B. M.
Bell Microproducts,
Inc. (for HAB’s)
http://www.bellmicro.com
I. E.
Insight Electronics
http://www.insight-electronics.com
W. E.
Wyle Electronics
http://www.wyle.com
Alabama
Daphne
I. E.
Tel: 334.626.6190
Huntsville
A. E.
Tel: 256.837.8700
B. M.
Tel: 256.705.3559
I. E.
Tel: 256.830.1222
W. E. Tel: 800.964.9953
Alaska
A. E.
Tel: 800.332.8638
Arizona
Phoenix
A. E.
Tel: 480.736.7000
B. M.
Tel: 602.267.9551
W. E. Tel: 800.528.4040
Tempe
I. E.
Tel: 480.829.1800
Tucson
A. E.
Tel: 520.742.0515
Arkansas
W. E. Tel: 972.235.9953
California
Agoura Hills
B. M.
Tel: 818.865.0266
Granite Bay
B. M.
Tel: 916.523.7047
Irvine
A. E.
Tel: 949.789.4100
B. M.
Tel: 949.470.2900
I. E.
Tel: 949.727.3291
W. E. Tel: 800.626.9953
Los Angeles
A. E.
Tel: 818.594.0404
W. E. Tel: 800.288.9953
Sacramento
A. E.
Tel: 916.632.4500
W. E. Tel: 800.627.9953
San Diego
A. E.
Tel: 858.385.7500
B. M.
Tel: 858.597.3010
I. E.
Tel: 800.677.6011
W. E. Tel: 800.829.9953
San Jose
A. E.
Tel: 408.435.3500
B. M.
Tel: 408.436.0881
I. E.
Tel: 408.952.7000
Santa Clara
W. E. Tel: 800.866.9953
Woodland Hills
A. E.
Tel: 818.594.0404
Westlake Village
I. E.
Tel: 818.707.2101
Colorado
Denver
A. E.
Tel: 303.790.1662
B. M.
Tel: 303.846.3065
W. E. Tel: 800.933.9953
Englewood
I. E.
Tel: 303.649.1800
Idaho Springs
B. M.
Tel: 303.567.0703
Illinois
North/South
A. E.
Tel: 847.797.7300
Tel: 314.291.5350
Chicago
B. M.
Tel: 847.413.8530
W. E. Tel: 800.853.9953
Schaumburg
I. E.
Tel: 847.885.9700
Connecticut
Cheshire
A. E.
Tel: 203.271.5700
I. E.
Tel: 203.272.5843
Wallingford
W. E. Tel: 800.605.9953
Indiana
Fort Wayne
I. E.
Tel: 219.436.4250
W. E. Tel: 888.358.9953
Indianapolis
A. E.
Tel: 317.575.3500
Delaware
North/South
A. E.
Tel: 800.526.4812
Tel: 800.638.5988
B. M.
Tel: 302.328.8968
W. E. Tel: 856.439.9110
Iowa
W. E. Tel: 612.853.2280
Cedar Rapids
A. E.
Tel: 319.393.0033
Florida
Altamonte Springs
B. M.
Tel: 407.682.1199
I. E.
Tel: 407.834.6310
Boca Raton
I. E.
Tel: 561.997.2540
Bonita Springs
B. M.
Tel: 941.498.6011
Clearwater
I. E.
Tel: 727.524.8850
Fort Lauderdale
A. E.
Tel: 954.484.5482
W. E. Tel: 800.568.9953
Miami
B. M.
Tel: 305.477.6406
Orlando
A. E.
Tel: 407.657.3300
W. E. Tel: 407.740.7450
Tampa
W. E. Tel: 800.395.9953
St. Petersburg
A. E.
Tel: 727.507.5000
Georgia
Atlanta
A. E.
Tel: 770.623.4400
B. M.
Tel: 770.980.4922
W. E. Tel: 800.876.9953
Duluth
I. E.
Tel: 678.584.0812
Hawaii
A. E.
Tel: 800.851.2282
Idaho
A. E.
W. E.
Tel: 801.365.3800
Tel: 801.974.9953
Kansas
W. E. Tel: 303.457.9953
Kansas City
A. E.
Tel: 913.663.7900
Lenexa
I. E.
Tel: 913.492.0408
Kentucky
W. E. Tel: 937.436.9953
Central/Northern/ Western
A. E.
Tel: 800.984.9503
Tel: 800.767.0329
Tel: 800.829.0146
Louisiana
W. E. Tel: 713.854.9953
North/South
A. E.
Tel: 800.231.0253
Tel: 800.231.5775
Maine
A. E.
W. E.
Tel: 800.272.9255
Tel: 781.271.9953
Maryland
Baltimore
A. E.
Tel: 410.720.3400
W. E. Tel: 800.863.9953
Columbia
B. M.
Tel: 800.673.7461
I. E.
Tel: 410.381.3131
Massachusetts
Boston
A. E.
Tel: 978.532.9808
W. E. Tel: 800.444.9953
Burlington
I. E.
Tel: 781.270.9400
Marlborough
B. M.
Tel: 800.673.7459
Woburn
B. M.
Tel: 800.552.4305
Michigan
Brighton
I. E.
Tel: 810.229.7710
Detroit
A. E.
Tel: 734.416.5800
W. E. Tel: 888.318.9953
Clarkston
B. M.
Tel: 877.922.9363
Minnesota
Champlin
B. M.
Tel: 800.557.2566
Eden Prairie
B. M.
Tel: 800.255.1469
Minneapolis
A. E.
Tel: 612.346.3000
W. E. Tel: 800.860.9953
St. Louis Park
I. E.
Tel: 612.525.9999
Mississippi
A. E.
Tel: 800.633.2918
W. E. Tel: 256.830.1119
Missouri
W. E. Tel: 630.620.0969
St. Louis
A. E.
Tel: 314.291.5350
I. E.
Tel: 314.872.2182
Montana
A. E.
Tel: 800.526.1741
W. E. Tel: 801.974.9953
Nebraska
A. E.
Tel: 800.332.4375
W. E. Tel: 303.457.9953
Nevada
Las Vegas
A. E.
Tel: 800.528.8471
W. E. Tel: 702.765.7117
New Hampshire
A. E.
Tel: 800.272.9255
W. E. Tel: 781.271.9953
New Jersey
North/South
A. E.
Tel: 201.515.1641
Tel: 609.222.6400
Mt. Laurel
I. E.
Tel: 856.222.9566
Pine Brook
B. M.
Tel: 973.244.9668
W. E. Tel: 800.862.9953
Parsippany
I. E.
Tel: 973.299.4425
Wayne
W. E. Tel: 973.237.9010
New Mexico
W. E. Tel: 480.804.7000
Albuquerque
A. E.
Tel: 505.293.5119
U.S. Distributors
by State
(Continued)
New York
Hauppauge
I. E.
Tel: 516.761.0960
Long Island
A. E.
Tel: 516.434.7400
W. E. Tel: 800.861.9953
Rochester
A. E.
Tel: 716.475.9130
I. E.
Tel: 716.242.7790
W. E. Tel: 800.319.9953
Smithtown
B. M.
Tel: 800.543.2008
Syracuse
A. E.
Tel: 315.449.4927
North Carolina
Raleigh
A. E.
Tel: 919.859.9159
I. E.
Tel: 919.873.9922
W. E. Tel: 800.560.9953
North Dakota
A. E.
Tel: 800.829.0116
W. E. Tel: 612.853.2280
Ohio
Cleveland
A. E.
Tel: 216.498.1100
W. E. Tel: 800.763.9953
Dayton
A. E.
Tel: 614.888.3313
I. E.
Tel: 937.253.7501
W. E. Tel: 800.575.9953
Strongsville
B. M.
Tel: 440.238.0404
Valley View
I. E.
Tel: 216.520.4333
Oklahoma
W. E. Tel: 972.235.9953
Tulsa
A. E.
Tel: 918.459.6000
I. E.
Tel: 918.665.4664
Oregon
Beaverton
B. M.
Tel: 503.524.1075
I. E.
Tel: 503.644.3300
Portland
A. E.
Tel: 503.526.6200
W. E. Tel: 800.879.9953
Pennsylvania
Mercer
I. E.
Tel: 412.662.2707
Philadelphia
A. E.
Tel: 800.526.4812
B. M.
Tel: 877.351.2355
W. E. Tel: 800.871.9953
Pittsburgh
A. E.
Tel: 412.281.4150
W. E. Tel: 440.248.9996
Rhode Island
A. E.
800.272.9255
W. E. Tel: 781.271.9953
South Carolina
A. E.
Tel: 919.872.0712
W. E. Tel: 919.469.1502
South Dakota
A. E.
Tel: 800.829.0116
W. E. Tel: 612.853.2280
Tennessee
W. E. Tel: 256.830.1119
East/West
A. E.
Tel: 800.241.8182
Tel: 800.633.2918
Texas
Arlington
B. M.
Tel: 817.417.5993
Austin
A. E.
Tel: 512.219.3700
B. M.
Tel: 512.258.0725
I. E.
Tel: 512.719.3090
W. E. Tel: 800.365.9953
Dallas
A. E.
Tel: 214.553.4300
B. M.
Tel: 972.783.4191
W. E. Tel: 800.955.9953
El Paso
A. E.
Tel: 800.526.9238
Houston
A. E.
Tel: 713.781.6100
B. M.
Tel: 713.917.0663
W. E. Tel: 800.888.9953
Richardson
I. E.
Tel: 972.783.0800
Rio Grande Valley
A. E.
Tel: 210.412.2047
Stafford
I. E.
Tel: 281.277.8200
Utah
Centerville
B. M.
Tel: 801.295.3900
Murray
I. E.
Tel: 801.288.9001
Salt Lake City
A. E.
Tel: 801.365.3800
W. E. Tel: 800.477.9953
Vermont
A. E.
Tel: 800.272.9255
W. E. Tel: 716.334.5970
Virginia
A. E.
Tel: 800.638.5988
W. E. Tel: 301.604.8488
Haymarket
B. M.
Tel: 703.754.3399
Springfield
B. M.
Tel: 703.644.9045
Washington
Kirkland
I. E.
Tel: 425.820.8100
Maple Valley
B. M.
Tel: 206.223.0080
Seattle
A. E.
Tel: 425.882.7000
W. E. Tel: 800.248.9953
West Virginia
A. E.
Tel: 800.638.5988
Wisconsin
Milwaukee
A. E.
Tel: 414.513.1500
W. E. Tel: 800.867.9953
Wauwatosa
I. E.
Tel: 414.258.5338
Wyoming
A. E.
Tel: 800.332.9326
W. E. Tel: 801.974.9953
Direct Sales
Representatives by State
(Components and Boards)
E. A.
E. L.
GRP
I. S.
ION
R. A.
SGY
Earle Associates
Electrodyne - UT
Group 2000
Infinity Sales, Inc.
ION Associates, Inc.
Rathsburg Associates, Inc.
Synergy Associates,
Inc.
Arizona
Tempe
E. A.
Tel: 480.921.3305
California
Calabasas
I. S.
Tel: 818.880.6480
Irvine
I. S.
Tel: 714.833.0300
San Diego
E. A.
Tel: 619.278.5441
Illinois
Elmhurst
R. A.
Tel: 630.516.8400
Indiana
Cicero
R. A.
Tel: 317.984.8608
Ligonier
R. A.
Tel: 219.894.3184
Plainfield
R. A.
Tel: 317.838.0360
Massachusetts
Burlington
SGY
Tel: 781.238.0870
Michigan
Byron Center
R. A.
Tel: 616.554.1460
Good Rich
R. A.
Tel: 810.636.6060
Novi
R. A.
Tel: 810.615.4000
North Carolina
Cary
GRP
Tel: 919.481.1530
Ohio
Columbus
R. A.
Tel: 614.457.2242
Dayton
R. A.
Tel: 513.291.4001
Independence
R. A.
Tel: 216.447.8825
Pennsylvania
Somerset
R. A.
Tel: 814.445.6976
Texas
Austin
ION
Tel: 512.794.9006
Arlington
ION
Tel: 817.695.8000
Houston
ION
Tel: 281.376.2000
Utah
Salt Lake City
E. L.
Tel: 801.264.8050
Wisconsin
Muskego
R. A.
Tel: 414.679.8250
Saukville
R. A.
Tel: 414.268.1152
Sales Offices and Design
Resource Centers
LSI Logic Corporation
Corporate Headquarters
1551 McCarthy Blvd
Milpitas CA 95035
Tel: 408.433.8000
Fax: 408.433.8989
Fort Collins
2001 Danfield Court
Fort Collins, CO 80525
Tel: 970.223.5100
Fax: 970.206.5549
New Jersey
Red Bank
125 Half Mile Road
Suite 200
Red Bank, NJ 07701
Tel: 732.933.2656
Fax: 732.933.2643
NORTH AMERICA
Florida
Boca Raton
Cherry Hill - Mint Technology
California
Irvine
2255 Glades Road
Suite 324A
Boca Raton, FL 33431
Tel: 561.989.3236
Fax: 561.989.3237
Tel: 856.489.5530
Fax: 856.489.5531
Georgia
Alpharetta
New York
Fairport
2475 North Winds Parkway
Suite 200
Alpharetta, GA 30004
550 Willowbrook Office Park
Fairport, NY 14450
18301 Von Karman Ave
Suite 900
Irvine, CA 92612
♦ Tel: 949.809.4600
Fax: 949.809.4444
Pleasanton Design Center
5050 Hopyard Road, 3rd Floor
Suite 300
Pleasanton, CA 94588
Tel: 925.730.8800
Fax: 925.730.8700
Tel: 770.753.6146
Fax: 770.753.6147
Illinois
Oakbrook Terrace
215 Longstone Drive
Cherry Hill, NJ 08003
Tel: 716.218.0020
Fax: 716.218.9010
North Carolina
Raleigh
Phase II
4601 Six Forks Road
Suite 528
Raleigh, NC 27609
Tel: 630.954.2234
Fax: 630.954.2235
Tel: 919.785.4520
Fax: 919.783.8909
Kentucky
Bowling Green
Oregon
Beaverton
1551 McCarthy Blvd
Sales Office
M/S C-500
Milpitas, CA 95035
1262 Chestnut Street
Bowling Green, KY 42101
15455 NW Greenbrier Parkway
Suite 235
Beaverton, OR 97006
Fax: 408.954.3353
Maryland
Bethesda
7585 Ronson Road
Suite 100
San Diego, CA 92111
Tel: 858.467.6981
Fax: 858.496.0548
Silicon Valley
♦ Tel: 408.433.8000
Design Center
M/S C-410
Tel: 408.433.8000
Fax: 408.433.7695
Wireless Design Center
11452 El Camino Real
Suite 210
San Diego, CA 92130
Tel: 858.350.5560
Fax: 858.350.0171
Colorado
Boulder
4940 Pearl East Circle
Suite 201
Boulder, CO 80301
♦ Tel: 303.447.3800
Fax: 303.541.0641
Colorado Springs
Tel: 270.793.0010
Fax: 270.793.0040
6903 Rockledge Drive
Suite 230
Bethesda, MD 20817
Tel: 301.897.5800
Fax: 301.897.8389
Massachusetts
Waltham
200 West Street
Waltham, MA 02451
♦ Tel: 781.890.0180
Fax: 781.890.6158
Tel: 503.645.0589
Fax: 503.645.6612
Texas
Austin
9020 Capital of TX Highway North
Building 1
Suite 150
Austin, TX 78759
Tel: 512.388.7294
Fax: 512.388.4171
Plano
500 North Central Expressway
Suite 440
Plano, TX 75074
♦ Tel: 972.244.5000
Burlington - Mint Technology
Fax: 972.244.5001
77 South Bedford Street
Burlington, MA 01803
Houston
Tel: 781.685.3800
Fax: 781.685.3801
20405 State Highway 249
Suite 450
Houston, TX 77070
4420 Arrowswest Drive
Colorado Springs, CO 80907
Minnesota
Minneapolis
Tel: 719.533.7000
Fax: 719.533.7020
8300 Norman Center Drive
Suite 730
Minneapolis, MN 55437
♦ Tel: 612.921.8300
Fax: 612.921.8399
260 Hearst Way
Suite 400
Kanata, ON K2L 3H1
♦ Tel: 613.592.1263
Fax: 613.592.3253
Two Mid American Plaza
Suite 800
Oakbrook Terrace, IL 60181
San Diego
Canada
Ontario
Ottawa
Tel: 281.379.7800
Fax: 281.379.7818
INTERNATIONAL
France
Paris
LSI Logic S.A.
Immeuble Europa
53 bis Avenue de l'Europe
B.P. 139
78148 Velizy-Villacoublay
Cedex, Paris
♦ Tel: 33.1.34.63.13.13
Fax: 33.1.34.63.13.19
Germany
Munich
LSI Logic GmbH
Orleansstrasse 4
81669 Munich
♦ Tel: 49.89.4.58.33.0
Fax: 49.89.4.58.33.108
Stuttgart
Mittlerer Pfad 4
D-70499 Stuttgart
♦ Tel: 49.711.13.96.90
Fax: 49.711.86.61.428
Italy
Milan
LSI Logic S.P.A.
Centro Direzionale Colleoni
Palazzo Orione Ingresso 1
20041 Agrate Brianza, Milano
♦ Tel: 39.039.687371
Fax: 39.039.6057867
Japan
Tokyo
LSI Logic K.K.
Rivage-Shinagawa Bldg. 14F
4-1-8 Kounan
Minato-ku, Tokyo 108-0075
♦ Tel: 81.3.5463.7821
Fax: 81.3.5463.7820
Osaka
Crystal Tower 14F
1-2-27 Shiromi
Chuo-ku, Osaka 540-6014
♦ Tel: 81.6.947.5281
Fax: 81.6.947.5287
Sales Offices and Design
Resource Centers
(Continued)
Korea
Seoul
LSI Logic Corporation of
Korea Ltd
10th Fl., Haesung 1 Bldg.
942, Daechi-dong,
Kangnam-ku, Seoul, 135-283
Tel: 82.2.528.3400
Fax: 82.2.528.2250
The Netherlands
Eindhoven
LSI Logic Europe Ltd
World Trade Center Eindhoven
Building ‘Rijder’
Bogert 26
5612 LZ Eindhoven
Tel: 31.40.265.3580
Fax: 31.40.296.2109
Singapore
Singapore
LSI Logic Pte Ltd
7 Temasek Boulevard
#28-02 Suntec Tower One
Singapore 038987
Tel: 65.334.9061
Fax: 65.334.4749
Sweden
Stockholm
LSI Logic AB
Finlandsgatan 14
164 74 Kista
♦ Tel: 46.8.444.15.00
Fax: 46.8.750.66.47
Taiwan
Taipei
LSI Logic Asia, Inc.
Taiwan Branch
10/F 156 Min Sheng E. Road
Section 3
Taipei, Taiwan R.O.C.
Tel: 886.2.2718.7828
Fax: 886.2.2718.8869
United Kingdom
Bracknell
LSI Logic Europe Ltd
Greenwood House
London Road
Bracknell, Berkshire RG12 2UB
♦ Tel: 44.1344.426544
Fax: 44.1344.481039
♦ Sales Offices with
Design Resource Centers
International Distributors
Australia
New South Wales
Reptechnic Pty Ltd
Hong Kong
Hong Kong
AVT Industrial Ltd
3/36 Bydown Street
Neutral Bay, NSW 2089
Unit 608 Tower 1
Cheung Sha Wan Plaza
833 Cheung Sha Wan Road
Kowloon, Hong Kong
♦ Tel: 612.9953.9844
Fax: 612.9953.9683
Belgium
Acal nv/sa
Lozenberg 4
1932 Zaventem
Tel: 32.2.7205983
Fax: 32.2.7251014
China
Beijing
LSI Logic International
Services Inc.
Beijing Representative
Office
Room 708
Canway Building
66 Nan Li Shi Lu
Xicheng District
Beijing 100045, China
Tel: 86.10.6804.2534 to 38
Fax: 86.10.6804.2521
France
Rungis Cedex
Azzurri Technology France
22 Rue Saarinen
Sillic 274
94578 Rungis Cedex
Tel: 33.1.41806310
Fax: 33.1.41730340
Germany
Haar
EBV Elektronik
Tel: 852.2428.0008
Fax: 852.2401.2105
Serial System (HK) Ltd
2301 Nanyang Plaza
57 Hung To Road, Kwun Tong
Kowloon, Hong Kong
Tel: 852.2995.7538
Fax: 852.2950.0386
India
Bangalore
Spike Technologies India
Private Ltd
951, Vijayalakshmi Complex,
2nd Floor, 24th Main,
J P Nagar II Phase,
Bangalore, India 560078
♦ Tel: 91.80.664.5530
Fax: 91.80.664.9748
Macnica Corporation
Tel: 44.1628.826826
Fax: 44.1628.829730
Hakusan High-Tech Park
1-22-2 Hadusan, Midori-Ku,
Yokohama-City, 226-8505
Milton Keynes
Ingram Micro (UK) Ltd
Tel: 81.45.939.6140
Fax: 81.45.939.6141
The Netherlands
Eindhoven
Acal Nederland b.v.
Japan
Tokyo
Daito Electron
Tel: 49.89.4600980
Fax: 49.89.46009840
Munich
Avnet Emg GmbH
Global Electronics
Corporation
Stahlgruberring 12
81829 Munich
Nichibei Time24 Bldg. 35 Tansu-cho
Shinjuku-ku, Tokyo 162-0833
Tel: 49.89.45110102
Fax: 49.89.42.27.75
Tel: 81.3.3260.1411
Fax: 81.3.3260.7100
Technical Center
Tel: 81.471.43.8200
Tel: 81.3.5778.8662
Fax: 81.3.5778.8669
Shinki Electronics
Myuru Daikanyama 3F
3-7-3 Ebisu Minami
Shibuya-ku, Tokyo 150-0022
Tel: 81.3.3760.3110
Fax: 81.3.3760.3101
Tel: 44.1908.260422
Swindon
EBV Elektronik
Tel: 31.40.2.502602
Fax: 31.40.2.510255
12 Interface Business Park
Bincknoll Lane
Wootton Bassett,
Swindon, Wiltshire SN4 8SY
Switzerland
Brugg
LSI Logic Sulzer AG
Mattenstrasse 6a
CH 2555 Brugg
14F, No. 145,
Sec. 2, Chien Kuo N. Road
Taipei, Taiwan, R.O.C.
Tel: 886.2.2516.7303
Fax: 886.2.2505.7391
Lumax International
Corporation, Ltd
7th Fl., 52, Sec. 3
Nan-Kang Road
Taipei, Taiwan, R.O.C.
Tel: 886.2.2788.3656
Fax: 886.2.2788.3568
Prospect Technology
Corporation, Ltd
4Fl., No. 34, Chu Luen Street
Taipei, Taiwan, R.O.C.
Tel: 886.2.2721.9533
Fax: 886.2.2773.3756
Marubeni Solutions
1-26-20 Higashi
Shibuya-ku, Tokyo 150-0001
Garamonde Drive
Wymbush
Milton Keynes
Buckinghamshire MK8 8DF
Beatrix de Rijkweg 8
5657 EG Eindhoven
Taiwan
Taipei
Avnet-Mercuries
Corporation, Ltd
Tel: 81.3.3264.0326
Fax: 81.3.3261.3984
Tel: 49.2957.79.1692
Fax: 49.2957.79.9341
16 Grove Park Business Estate
Waltham Road
White Waltham
Maidenhead, Berkshire SL6 3LW
11 Rozanis Street
P.O. Box 39300
Tel Aviv 61392
Tel: 972.3.6458777
Fax: 972.3.6458666
United Kingdom
Maidenhead
Azzurri Technology Ltd
Tel: 81.45.474.9037
Fax: 81.45.474.9065
Tel: 41.32.3743232
Fax: 41.32.3743233
Sogo Kojimachi No.3 Bldg
1-6 Kojimachi
Chiyoda-ku, Tokyo 102-8730
Graf-Zepplin-Str 14
D-33181 Wuennenberg-Haaren
2-15-10 Shin Yokohama
Kohoku-ku
Yokohama-City, 222-8580
Israel
Tel Aviv
Eastronics Ltd
Hans-Pinsel Str. 4
D-85540 Haar
Wuennenberg-Haaren
Peacock AG
Yokohama-City
Innotech
Wintech Microeletronics
Co., Ltd
7F., No. 34, Sec. 3, Pateh Road
Taipei, Taiwan, R.O.C.
Tel: 886.2.2579.5858
Fax: 886.2.2570.3123
Tel: 44.1793.849933
Fax: 44.1793.859555
♦ Sales Offices with
Design Resource Centers