ETC LU6X14FT

Product Brief
August 2000
LU6X14FT
1.0—1.25/2.0—2.5/3.125 Gbits/s SERDES
Description
Features
The LU6X14FT is a quad transceiver for serial data
transmission over fiber or coaxial media from
1.0 Gbits/s—3.125 Gbits/s. The device is available in
a 208-pin PBGAM package. The block diagram of the
chip is shown in Figure 1 on page 2. The transmitter
section accepts either 8-bit unencoded data or 10-bit
encoded data at the parallel input port. It also
accepts the low-speed system clock at the REFCLK
input and uses this clock to synthesize the internal
high-speed serial bit clock. In the 1.0 Gbits/s—
1.25 Gbits/s mode, the parallel input data is latched
on the falling edge of the low-speed TBC clock. In the
2.0 Gbits/s to 3.125 Gbits/s mode, the parallel input
data is framed by the rising and falling edges of the
low-speed TBC clock. REFCLK and TBC clock are
required to be the same frequency, but the phase
relationship is arbitrary. The serialized data is available at the differential CML output, terminated by
50 Ω or 75 Ω, to drive either an optical transmitter or
coaxial media.
■
Designed to operate in Ethernet, fibre channel,
FireWire *, or backplane applications.
■
Operationally compliant with the fibre channel
X3T11. Provides FC-0 services at 1.0 Gbits/s—
1.25 Gbits/s, 2.0 Gbits/s—2.5 Gbits/s, and
3.125 Gbits/s.
■
Selectable data rate (1.0 Gbits/s—1.25 Gbits/s,
2.0 Gbits/s—2.5 Gbits/s, and 3.125 Gbits/s).
■
100 MHz—156 MHz differential CML or singleended CMOS reference clock.
■
8-bit/10-bit parallel I/O interface.
■
Programmable control and configuration interface
to define the various device configurations.
■
Automatic lock to reference in absence of receive
data.
■
CML high-speed interface I/O for use with optical
transceiver, coaxial copper media, or shielded
twisted pairs.
■
Programmable transmit pre-emphasis optimized
for backplanes.
■
Requires one external resistor for bias current generation.
■
Requires no external components for clock recovery and frequency synthesis.
■
Under 250 mW per transceiver.
■
Low powerdown dissipation.
■
1.5 V ± 5% power supply.
■
1.8 V ± 5% power supply option for differential high
speed I/O circuits.
■
–40 °C—70 °C ambient temperature.
The receive section receives high-speed serial data
at its differential CML input port. This data is fed to
the clock recovery section which generates a recovered clock and retimes the data. The retimed data is
deserialized and presented as a 10-bit encoded or a
8-bit unencoded parallel data on the output port.
Two-phase receive byte clocks are available synchronous with the parallel words. The receiver also recognizes the comma characters and aligns the bit
stream to the proper word boundary.
The quad transceiver is controlled and configured
with an 8-bit microprocessor interface. Each channel
has dedicated registers that are readable and writable. The quad device also contains global registers
for control of common circuitry and functions.
Potential Applications
■
Stand-alone transceiver product.
■
Transceiver macrocell template.
* FireWire is a registered trademark of Apple Computer, Inc.
LU6X14FT
1.0—1.25/2.0—2.5/3.125 Gbits/s SERDES
Product Brief
August 2000
Block Diagrams
INT
LOOPENB
CONTROLLER
REFCLK
MICROPROCESSOR INTERFACE
WDSYNC
BYTSYNC
RECEIVER
RBC0
RBC1
LCKREFN
ENBSYNC
LDOUT[0—9]
10
TBC
XCK
LDIN[0—9]
TRANSMITTER
10
CLOCK
MANAGEMENT
0611 (F)
Figure 1. LU6X14FT Block Diagram
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Lucent Technologies Inc.
LU6X14FT
1.0—1.25/2.0—2.5/3.125 Gbits/s SERDES
Product Brief
August 2000
Block Diagrams (continued)
PARALLEL
TRANSMIT
CLOCK
HIGH-SPEED
TRANSMIT
CLOCK
RX TO TX
LOOPBACK
10
REGISTER
8B110B
ENCODER
TBC
PARALLEL
TO
SERIAL
MUX
LDIN[0—9]
8B10BT
LOOPEN
PRBS
GLOBAL PRBS
HDOUTP
OUTPUT
DRIVER
HDOUTN
PE0
PE1
HAMP
PRBS
CONTROLLER
8B10BR
GLOBAL PRBS
0610 (F)
Figure 2. LU6X14FT Transmit Detail
Lucent Technologies Inc.
3
LU6X14FT
1.0—1.25/2.0—2.5/3.125 Gbits/s SERDES
Product Brief
August 2000
Block Diagrams (continued)
HDINP
LCKREFN
WDSYNC
LINK
STATE
BYTSYNC
SERIAL-TOPARALLEL
CONVERTER
RBC0
ACTIVITY
DETECTOR
MUX
GLOBAL
PRBS
RX TO TX
LOOPBACK
LINKSM
10B18B
DECODER
SDON
PBRS
CHECK
RXHR
ENBYSYNC
PRBSCHK
BYTE
ALIGNER
RBC1
LDOUT
[0—9]
HDINN
RX
PLL
CONTROLLER
8B10BR
0609 (F)
Figure 3. LU6X14FT Receive Detail
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Lucent Technologies Inc.
LU6X14FT
1.0—1.25/2.0—2.5/3.125 Gbits/s SERDES
Product Brief
August 2000
Block Diagrams (continued)
TBC ÷ 2
÷2
TBC
TBC
PARALLEL
TRANSMIT
CLOCK
XCK
REFCLK
TX
PLL
RBC[0—1]
XCK
TBCKSEL
TXHR
LOOPENB
RBC[0—1]
HIGH-SPEED
TRANSMIT
CLOCK
TXHR
RECEIVER
RXHR
CONTROLLER
0608 (F)
Figure 4. Clock Management
Functional Description
Bias Section
A fractional band-gap voltage generator is included on the chip. A precision external resistor connected between
the pins RESIN and RESRT is used to generate the bias currents within the chip. The value of this resistor should
be 3.32 kΩ ± 1%. The current handling capability of this resistor should be at least 300 µA.
Transmit/Receive Data Rate Selection
The high-speed transmit and receive serial data can operate at 1.0 Gbits/s—1.25 Gbits/s or 2.0 Gbits/s—
3.125 Gbits/s, depending on the state of the TXHR and RXHR control bits from the microprocessor interface. The
REFCLK and TBC clock are always frequency synchronous. Table 1 shows the relationship between the data rates
and the input and recovered clocks.
Table 1. Input and Recovered Clock Rates for Different Data Rates
Data Rate
TBC/Reference Clock
RBC[0:1]
1.0 Gbits/s
1.25 Gbits/s
2.0 Gbits/s
2.5 Gbits/s
3.125 Gbits/s
100 MHz
125 MHz
100 MHz
125 MHz
156 MHz
50 MHz
62.5 MHz
100 MHz
125 MHz
156 MHz
Lucent Technologies Inc.
5
LU6X14FT
1.0—1.25/2.0—2.5/3.125 Gbits/s SERDES
Product Brief
August 2000
Functional Description (continued)
Reference Clock
The differential clock is distributed to all of the four channels. Each channel has a differential buffer to isolate the
clock from the other channels. The input clock is preferably a differential signal; however, the device can operate
with a single-ended input. The input reference clock directly impacts the transmit data eye, so the clock should have
low jitter. In particular, jitter components in the dc—5 MHz range should be minimized.
Transmitter Section
The block diagram of the transmitter is shown in Figure 2 on page 3. The 8-bit unencoded or 10-bit encoded
parallel input data word is latched into an on-chip register with the externally supplied TBC clock and serialized at
ten times the incoming parallel data rate. When the transmitter is operating in the half rate mode (1.0 Gbits/s—
1.25 Gbits/s), the falling edge of the TBC clock is used to latch the data. When the transmitter is operating in the full
rate mode (2.0 Gbits/s—3.125 Gbits/s), the TBC clock frames the input data so that when TBC is high a bit is
latched by an internal clock and again when TBC is low. The full rate data makes transitions on both edges of the
clock as shown in Figure 6 on page 7. Table 2 shows the timing margins.
TBC is the same frequency as REFCLK; however, it is assumed to be of arbitrary phase w.r.t. REFCLK. During a
powerup reset sequence, the phase relationship between REFCLK, TBC, and the PLL generated high-speed clock
is established. The relative phase of the input clocks, TBC and REFCLK, must remain fixed after the powerup
sequence is completed.
A 256-state PRBS generator is included on the chip to enable testability in loopback mode.
t1
TBC CLK
t2
t1
tVALID
tVALID
LDIN<7:0>
0612 (F)
Figure 5. Transmit Timing Diagram
Table 2. Timing Relationship of LDIN and TBC Clock at Full Rate (3.125 Gbits/s)
Parameter
Minimum
Typical
Maximum
Unit
t1
t2
—
—
2.5
—
—
—
1.0
0.5
—
ns
ns
ns
tvalid
In the half-rate mode, the incoming data transitions only on the rising edge of the clock, as shown in Figure 6 on
page 7. Table 3 on page 7 shows the timing relationships in this case.
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Lucent Technologies Inc.
LU6X14FT
1.0—1.25/2.0—2.5/3.125 Gbits/s SERDES
Product Brief
August 2000
Functional Description (continued)
t1
t1
TBC CLK
t2
t2
LDIN<7:0>
0613 (F)
Figure 6. Transmit Timing Waveform
Table 3. Timing Relationship of LDIN and TBC Clock at Half Rate (1.25 Gbits/s)
Parameter
Minimum
Typical
Maximum
Unit
t1
t2
—
—
—
—
3.2
3.2
ns
ns
The maximum latency of the transmitter, counting from the corresponding edge of the data transition at the input to
the instance when the first high speed serial bit is transmitted, is 5 byte periods when the 8B/10B encoder is not
used. With the encoder, the maximum latency is 6 byte periods.
Lucent Technologies Inc.
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For additional information, contact your Microelectronics Group Account Manager or the following:
http://www.lucent.com/micro
INTERNET:
[email protected]
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Tel. (65) 778 8833, FAX (65) 777 7495
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Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No
rights under any patent accompany the sale of any such product(s) or information. This device is manufactured in qualified Lucent facilities—Lucent reserves the right to change qualified locations
of manufacture.
Copyright © 2000 Lucent Technologies Inc.
All Rights Reserved
August 2000
PB00-124CMPR-1