DS92LV090AEP DS92LV090AEP 9 Channel Bus LVDS Transceiver Literature Number: SNLS184A June 15, 2009 DS92LV090AEP 9 Channel Bus LVDS Transceiver General Description Features The DS92LV090AEP is one in a series of Bus LVDS transceivers designed specifically for the high speed, low power proprietary backplane or cable interfaces. The device operates from a single 3.3V power supply and includes nine differential line drivers and nine receivers. To minimize bus loading, the driver outputs and receiver inputs are internally connected. The separate I/O of the logic side allows for loop back support. The device also features a flow through pin out which allows easy PCB routing for short stubs between its pins and the connector. The driver translates 3V TTL levels (single-ended) to differential Bus LVDS (BLVDS) output levels. This allows for high speed operation, while consuming minimal power with reduced EMI. In addition, the differential signaling provides common mode noise rejection of ±1V. The receiver threshold is less than ±100 mV over a ±1V common mode range and translates the differential Bus LVDS to standard (TTL/CMOS) levels. (See Applications Information Section for more details.) ENHANCED PLASTIC • Extended Temperature Performance of −40°C to +85°C • Baseline Control - Single Fab & Assembly Site • Process Change Notification (PCN) • Qualification & Reliability Data • Solder (PbSn) Lead Finish is standard • Enhanced Diminishing Manufacturing Sources (DMS) Support ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Bus LVDS Signaling 3.2 nanosecond propagation delay max Chip to Chip skew ±800ps Low power CMOS design High Signaling Rate Capability (above 100 Mbps) 0.1V to 2.3V Common Mode Range for VID = 200mV ±100 mV Receiver Sensitivity Supports open and terminated failsafe on port pins 3.3V operation Glitch free power up/down (Driver & Receiver disabled) Light Bus Loading (5 pF typical) per Bus LVDS load Designed for Double Termination Applications Balanced Output Impedance Product offered in 64 pin TQFP package High impedance Bus pins on power off (VCC = 0V) Driver Channel to Channel skew (same device) 230ps typical ■ Receiver Channel to Channel skew (same device) 370ps typical Application ■ Selected Military Applications ■ Selected Avionics Applications Ordering Infromation PART NUMBER VID PART NUMBER NS PACKAGE NUMBER (Note 3) DS92LV090ATVEP V62/04741-01 VEH64A (Notes 1, 2) TBD TBD Note 1: For the following (Enhanced Plastic) version, check for availability: DS92LV090TVHXEP. Parts listed with an "X" are provided in Tape & Reel and parts without an "X" are in Rails. Note 2: FOR ADDITIONAL ORDERING AND PRODUCT INFORMATION, PLEASE VISIT THE ENHANCED PLASTIC WEB SITE AT: www.national.com/ mil Note 3: Refer to package details under Physical Dimensions TRI-STATE® is a registered trademark of National Semiconductor Corporation. © 2009 National Semiconductor Corporation 201195 201195 Version 2 Revision 1 www.national.com Print Date/Time: 2009/06/15 11:43:19 DS92LV090AEP 9 Channel Bus LVDS Transceiver OBSOLETE DS92LV090AEP Simplified Functional Diagram 20119501 Connection Diagram 20119502 Top View See NS Package Number VEH064DB www.national.com 2 201195 Version 2 Revision 1 Print Date/Time: 2009/06/15 11:43:19 Pin Name Pin # Input/Output DO+/RI+ 27, 31, 35, 37, 41, 45, 47, 51, 55 I/O True Bus LVDS Driver Outputs and Receiver Inputs. Descriptions DO−/RI− 26, 30, 34, 36, 40, 44, 46, 50, 54 I/O Complimentary Bus LVDS Driver Outputs and Receiver Inputs. DIN 2, 6, 12, 18, 20, 22, 58, 60, 62 I TTL Driver Input. RO 3, 7, 13, 19, 21, 23, 59, 61, 63 O TTL Receiver Output. RE 17 I Receiver Enable TTL Input (Active Low). DE 16 I Driver Enable TTL Input (Active High). GND 4, 5, 9, 14, 25, 56 Power Ground for digital circuitry (must connect to GND on PC board). These pins connected internally. VCC 10, 15, 24, 57, 64 Power VCC for digital circuitry (must connect to VCC on PC board). These pins connected internally. AGND 28, 33, 43, 49, 53 Power Ground for analog circuitry (must connect to GND on PC board). These pins connected internally. AVCC 29, 32, 42, 48, 52 Power Analog VCC (must connect to VCC on PC board). These pins connected internally. NC 1, 8, 11, 38, 39 N/A Leave open circuit, do not connect. 3 201195 Version 2 Revision 1 Print Date/Time: 2009/06/15 11:43:19 www.national.com DS92LV090AEP Pin Descriptions DS92LV090AEP θja Absolute Maximum Ratings (Notes 4, 5) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) Enable Input Voltage (DE, RE) Driver Input Voltage (DIN) Receiver Output Voltage (ROUT) Bus Pin Voltage (DO/RI±) 71.7°C/W θjc Storage Temperature Range Lead Temperature (Soldering, 4 sec.) 4.0V 10.9°C/W −65°C to +150°C 260°C Recommended Operating Conditions −0.3V to (VCC +0.3V) −0.3V to (VCC +0.3V) −0.3V to (VCC +0.3V) −0.3V to +3.9V Supply Voltage (VCC) Receiver Input Voltage Operating Free Air Temperature Maximum Input Edge Rate ESD (HBM 1.5 kΩ, 100 pF) >4.5 kV Driver Short Circuit Duration momentary Receiver Short Circuit Duration momentary Maximum Package Power Dissipation at 25°C TQFP 1.74 W Derate TQFP Package 13.9 mW/°C Min 3.0 0.0 −40 (Note 9)(20% to 80%) Data Control Max 3.6 2.4 +85 Units V V °C 1.0 3.0 Δt/ΔV ns/V ns/V DC Electrical Characteristics Over recommended operating supply voltage and temperature ranges unless otherwise specified (Notes 5, 6, 17) Symbol Parameter Conditions Pin RL = 27Ω, Figure 1 VOD Output Differential Voltage ΔVOD VOD Magnitude Change DO+/RI+, DO−/RI− VOS Offset Voltage ΔVOS Offset Magnitude Change VOH Driver Output High Voltage RL = 27Ω VOL Driver Output Low Voltage RL = 27Ω IOSD Output Short Circuit Current VOD = 0V, DE = VCC, Driver outputs (Note 13) shorted together VOH Voltage Output High (Note 14) Min Typ Max Units 240 300 460 mV 27 mV 1.5 V 5 10 mV 1.4 1.65 V 1.1 VID = +300 mV 0.95 IOH = −400 µA 1.3 1.1 |36| |65| mA VCC−0.2 V Inputs Open VCC−0.2 V Inputs Terminated, RL = 27Ω VCC−0.2 V VOL Voltage Output Low IOL = 2.0 mA, VID = −300 mV IOD Receiver Output Dynamic Current (Note 13) VID = 300mV, VOUT = VCC−1.0V VTH Input Threshold High DE = 0V, VCM = 1.5V VTL Input Threshold Low VCMR Receiver Common Mode Range IIN Input Current VIH Minimum Input High Voltage VIL Maximum Input Low Voltage IIH Input High Current VIN = VCC or 2.4V IIL Input Low Current VIN = GND or 0.4V VCL Input Diode Clamp Voltage ICLAMP = −18 mA ROUT V 0.05 −110 VID = −300mV, VOUT = 1.0V |75| DO+/RI+, DO−/RI− VCC = 0V, VIN = +2.4V or 0V ±1 −20 ±1 2.0 GND www.national.com mA mV 2.4 − | VID|/2 V +20 µA +20 µA VCC V 0.8 V ±10 +20 µA −20 ±10 +20 µA −1.5 −0.8 −20 4 201195 Version 2 Revision 1 110 +100 mV −20 DIN, DE, RE V mA −100 |VID|/2 DE = 0V, RE = 2.4V, VIN = +2.4V or 0V 0.075 |75| Print Date/Time: 2009/06/15 11:43:19 V ICCD ICCR ICCZ ICC IOFF Parameter Conditions Typ Max Units 55 80 mA Power Supply Current DE = RE = 0V, VID = ±300mV Drivers Disabled, Receivers Enabled 73 80 mA Power Supply Current, Drivers and Receivers TRISTATE® DE = 0V; RE = VCC, DIN = VCC or GND 35 80 mA Power Supply Current, Drivers and Receivers Enabled DE = VCC; RE = 0V, DIN = VCC or GND, 170 210 mA Power Off Leakage Current VCC = 0V or OPEN, DIN, DE, RE = 0V or OPEN, VAPPLIED = 3.6V (Port Pins) +20 µA Power Supply Current Drivers Enabled, Receivers Disabled Pin No Load, DE = RE = VCC, DIN = VCC or GND Min VCC RL = 27Ω DO+/RI+, DO−/RI− −20 COUTPUT Capacitance @ Bus Pins DO+/RI+, DO−/RI− 5 pF cOUTPUT ROUT 7 pF Capacitance @ ROUT 5 201195 Version 2 Revision 1 Print Date/Time: 2009/06/15 11:43:19 www.national.com DS92LV090AEP Symbol DS92LV090AEP AC Electrical Characteristics Over recommended operating supply voltage and temperature ranges unless otherwise specified (Notes 9, 17) Symbol Parameter Conditions Min Typ Max Unit s 0.6 1.4 2.2 ns 0.6 1.4 2.2 ns DIFFERENTIAL DRIVER TIMING REQUIREMENTS RL = 27Ω, Figures 2, 3, CL = 10 pF tPHLD Differential Prop. Delay High to Low (Note 11) tPLHD Differential Prop. Delay Low to High (Note 11) tSKD1 Differential Skew |tPHLD–tPLHD| (Note 12) tSKD2 Chip to Chip Skew (Note 15) 1.6 ns tSKD3 Channel to Channel Skew (Note 16) 0.25 0.45 ns tTLH Transition Time Low to High 0.6 1.2 ns tTHL Transition Time High to Low 0.5 1.2 ns tPHZ Disable Time High to Z 3 8 ns tPLZ Disable Time Low to Z 3 8 ns tPZH Enable Time Z to High 3 8 ns tPZL Enable Time Z to Low 3 8 ns 1.6 2.4 3.2 ns 1.6 2.4 3.2 ns 80 RL = 27Ω, Figures 4, 5, CL = 10 pF ps DIFFERENTIAL RECEIVER TIMING REQUIREMENTS tPHLD Differential Prop. Delay High to Low (Note 11) Figures 6, 7, CL = 35 pF tPLHD Differential Prop Delay Low to High (Note 11) tSDK1 Differential Skew |tPHLD–tPLHD| (Note 12) tSDK2 Chip to Chip Skew (Note 15) 1.6 ns tSDK3 Channel to Channel Skew (Note 16) 0.35 0.60 ns tTLH Transition Time Low to High 1.5 2.5 ns tTHL Transition Time High to Low 1.5 2.5 ns tPHZ Disable Time High to Z 4.5 10 ns tPLZ Disable Time Low to Z 3.5 8 ns tPZH Enable Time Z to High 3.5 8 ns tPZL Enable Time Z to Low 3.5 8 ns 80 RL = 500Ω, Figures 8, 9, CL = 35 pF ps Note 4: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. Note 5: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified except VOD, ΔVOD and VID. Note 6: All typicals are given for VCC = +3.3V and TA = +25°C, unless otherwise stated. Note 7: ESD Rating: HBM (1.5 kΩ, 100 pF) > 4.5 kV EIAJ (0Ω, 200 pF) > 300V. Note 8: CL includes probe and fixture capacitance. Note 9: Generator waveforms for all tests unless otherwise specified: f = 25 MHz, ZO = 50Ω, tr, tf = <1.0 ns (0%–100%). To ensure fastest propagation delay and minimum skew, data input edge rates should be equal to or faster than 1ns/V; control signals equal to or faster than 3ns/V. In general, the faster the input edge rate, the better the AC performance. Note 10: The DS92LV090AEP functions within datasheet specification when a resistive load is applied to the driver outputs. Note 11: Propagation delays are guaranteed by design and characterization. Note 12: tSKD1 |tPHLD–tPLHD| is the worse case skew between any channel and any device over recommended operation conditions. Note 13: Only one output at a time should be shorted, do not exceed maximum package power dissipation capacity. Note 14: VOH failsafe terminated test performed with 27Ω connected between RI+ and RI− inputs. No external voltage is applied. Note 15: Chip to Chip skew is the difference in differential propagation delay between any channels of any devices, either edge. Note 16: Channel to Channel skew is the difference in driver output or receiver output propagation delay between any channels within a device, either edge. Note 17: "Testing and other quality control techniques are used to the extent deemed necessary to ensure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific PARAMETRIC testing, product performance is assured by characterization and/or design." www.national.com 6 201195 Version 2 Revision 1 Print Date/Time: 2009/06/15 11:43:19 General application guidelines and hints may be found in the following application notes: AN-808, AN-903, AN-971, AN-977, and AN-1108. There are a few common practices which should be implied when designing PCB for Bus LVDS signaling. Recommended practices are: • Use at least 4 PCB board layer (Bus LVDS signals, ground, power and TTL signals). • Keep drivers and receivers as close to the (Bus LVDS port side) connector as possible. • Bypass each Bus LVDS device and also use distributed bulk capacitance between power planes. Surface mount capacitors placed close to power and ground pins work best. Two or three high frequency, multi-layer ceramic (MLC) surface mount (0.1 µF, 0.01 µF, 0.001 µF) in parallel should be used between each VCC and ground. The capacitors should be as close as possible to the VCC pin. Multiple vias should be used to connect VCC and Ground planes to the pads of the by-pass capacitors. In addition, randomly distributed by-pass capacitors should be used. • Use the termination resistor which best matches the differential impedance of your transmission line. • Leave unused Bus LVDS receiver inputs open (floating). Limit traces on unused inputs to <0.5 inches. • Isolate TTL signals from Bus LVDS signals MEDIA (CONNECTOR or BACKPLANE) SELECTION: • Use controlled impedance media. The backplane and connectors should have a matched differential impedance. MODE SELECTED DE RE H DRIVER MODE H RECEIVER MODE L L TRI-STATE MODE L H LOOP BACK MODE H L TABLE 2. Transmitter Mode INPUTS DE OUTPUTS DIN DO+ DO− H H L L H H H L H 0.8V< DIN <2.0V X X L X Z Z TABLE 3. Receiver Mode INPUTS OUTPUT RE (RI+) – (RI−) L L (< −100 mV) L L H (> +100 mV) H L −100 mV < VID < +100 mV X H X Z X = High or Low logic state L = Low state Z = High impedance state H = High state Test Circuits and Timing Waveforms 20119503 FIGURE 1. Differential Driver DC Test Circuit 20119504 FIGURE 2. Differential Driver Propagation Delay and Transition Time Test Circuit 7 201195 Version 2 Revision 1 Print Date/Time: 2009/06/15 11:43:19 www.national.com DS92LV090AEP TABLE 1. Functional Table Applications Information DS92LV090AEP 20119505 FIGURE 3. Differential Driver Propagation Delay and Transition Time Waveforms 20119506 FIGURE 4. Driver TRI-STATE Delay Test Circuit 20119507 FIGURE 5. Driver TRI-STATE Delay Waveforms www.national.com 8 201195 Version 2 Revision 1 Print Date/Time: 2009/06/15 11:43:19 DS92LV090AEP 20119508 FIGURE 6. Receiver Propagation Delay and Transition Time Test Circuit 20119509 FIGURE 7. Receiver Propagation Delay and Transition Time Waveforms 20119510 FIGURE 8. Receiver TRI-STATE Delay Test Circuit 20119511 FIGURE 9. Receiver TRI-STATE Delay Waveforms Typical Bus Application Configurations 9 201195 Version 2 Revision 1 Print Date/Time: 2009/06/15 11:43:19 www.national.com DS92LV090AEP 20119512 Bi-Directional Half-Duplex Point-to-Point Applications 20119513 Multi-Point Bus Applications Physical Dimensions www.national.com 10 201195 Version 2 Revision 1 Print Date/Time: 2009/06/15 11:43:19 DS92LV090AEP Physical Dimensions inches (millimeters) unless otherwise noted 64-Lead Molded TQFP Package NS Package Number VEH064DBAll 11 201195 Version 2 Revision 1 Print Date/Time: 2009/06/15 11:43:19 www.national.com DS92LV090AEP 9 Channel Bus LVDS Transceiver Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Design Support Amplifiers www.national.com/amplifiers WEBENCH® Tools www.national.com/webench Audio www.national.com/audio App Notes www.national.com/appnotes Clock and Timing www.national.com/timing Reference Designs www.national.com/refdesigns Data Converters www.national.com/adc Samples www.national.com/samples Interface www.national.com/interface Eval Boards www.national.com/evalboards LVDS www.national.com/lvds Packaging www.national.com/packaging Power Management www.national.com/power Green Compliance www.national.com/quality/green Switching Regulators www.national.com/switchers Distributors www.national.com/contacts LDOs www.national.com/ldo Quality and Reliability www.national.com/quality LED Lighting www.national.com/led Feedback/Support www.national.com/feedback Voltage Reference www.national.com/vref Design Made Easy www.national.com/easy www.national.com/powerwise Solutions www.national.com/solutions Mil/Aero www.national.com/milaero PowerWise® Solutions Serial Digital Interface (SDI) www.national.com/sdi Temperature Sensors www.national.com/tempsensors SolarMagic™ www.national.com/solarmagic Wireless (PLL/VCO) www.national.com/wireless www.national.com/training PowerWise® Design University THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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