NM93C86AL 16,384-Bit Serial Interface, Low Voltage CMOS EEPROM (MICROWIRE TM Synchronous Bus) General Description Features The NM93C86AL is 16,384 bits of CMOS nonvolatile, electrically erasable memory available user organized as either 1024 16-bit registers or 2048 8-bit registers. The user organization is determined by the status of the ORG input. The memory device is fabricated using National Semiconductor’s floating gate CMOS process for high reliability, high endurance, and low power consumption. The NM93C86AL is available in an 8-pin SO package for space considerations. The EEPROM is MICROWIRE compatible for simple interfacing to a wide variety of microcontrollers and microprocessors. There are 7 instructions that operate the NM93C86AL: Read, Erase/Write Enable, Erase, Write, Erase/Write Disable, Write All, and Erase All. The NM93C86AL defaults to the 1024 x 16 configuration if the ORG pin (Pin 6) is left floating, as it is internally pulled up to VCC. Y Y Y Y Y Y Y Y Y Y 2.7V to 5.5V operation in all modes Typical active current of 100 mA; Typical standby current of 1 mA Device status indication during programming mode No erase required before write Reliable CMOS floating gate technology MICROWIRE compatible serial I/O Self-timed programming cycle 40 years data retention Endurance: 106 data changes Packages available: 8-pin SO, 8-pin DIP Block Diagram TL/D/12511 – 1 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. MICROWIRETM is a trademark of National Semiconductor Corporation. C1996 National Semiconductor Corporation TL/D/12511 RRD-B30M96/Printed in U. S. A. http://www.national.com NM93C86AL 16,384-Bit Serial Interface, Low Voltage CMOS EEPROM (MICROWIRE Synchronous Bus) September 1996 Connection Diagram Dual-In-Line Package (N) and 8-Pin SO Package (M8) TL/D/12511 – 3 Top View See NS Package Number N08E and M08A Pin Names CS Chip Select SK Serial Data Clock DI Serial Data Input DO Serial Data Output VSS Ground ORG Memory Organizational Select NC No Connect VCC Positive Power Supply Ordering Information Commercial Temp. Range (0§ C to a 70§ C) Order Number NM93C86ALN NM93C86ALM8 Extended Temp. Range (b40§ C to a 85§ C) Order Number NM93C86ALEN NM93C86ALEM8 Automotive Temp. Range (b40§ C to a 125§ C) Order Number NM93C86ALVN NM93C86ALVM8 http://www.national.com 2 Absolute Maximum Ratings (Note 1) Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Ambient Operating Temperature NM93C86AL NM93C86ALE NM93C86ALV Ambient Storage Temperature All Input or Output Voltage with Respect to Ground Lead Temperature (Soldering, 10 sec.) ESD Rating b 65§ C to a 150§ C 0§ C to a 70§ C b 40§ C to a 85§ C b 40§ C to a 125§ C Power Supply (VCC) Range 2.7V to 5.5V VCC a 1 to b0.3V a 300§ C 2000V DC and AC Electrical Characteristics 2.7V s VCC k 4.5V Symbol ICCA Parameter Part Number Condition Min Operating Current CS e VIH, fSK e 250 kHz ICCS Standby Current CS e 0V, ORG e VCC or NC IIL Input Leakage VIN e 0V to VCC (Note 2) IILO Input Leakage ORG pin ORG tied to VCC ORG tied to VSS (Note 3) IOL Output Leakage VIN e 0V to VCC VIL Input Low Voltage VIH Input High Voltage 0.8 VCC VOL Output Low Voltage IOL e 10 mA VOH Output High Voltage IOH e b10 mA fSK SK Clock Frequency (Note 4) tSKH SK High Time tSKL SK Low Time tCS Minimum CS Low Time tCSS Max Units 1 mA 50 mA b1 1 mA b1 b 2.5 1 2.5 mA b1 1 mA b 0.1 0.15 VCC V VCC a 1 V 0.2 0.9 VCC 0 V V 250 kHz 1 ms 1 ms 1 ms CS Set-up Time 0.2 ms tDH DO Hold Time 70 ns tDIS DI Set-up Time 0.4 ms tCSH CS Hold Time 0 ms tDIH DI Hold Time 0.4 tPD1 Output Delay to ‘‘1’’ 2 ms tPD0 Output Delay to ‘‘0’’ 2 ms tSV CS to Status Valid 1 ms tDF CS to DO in TRI-STATEÉ 0.4 ms tWP Write Cycle Time 15 ms (Note 5) 3 ms http://www.national.com DC and AC Electrical Characteristics 4.5V s VCC k 5.5V Max Units ICCA Symbol Operating Current CS e VIH, fSK e 250 kHz 1 mA ICCS Standby Current CS e 0V, ORG e VCC or NC 50 mA IIL Input Leakage VIN e 0V to VCC (Note 2) b1 1 mA IILO Input Leakage ORG pin ORG tied to VCC ORG tied to VSS (Note 3) b1 b 2.5 1 2.5 mA Output Leakage VIN e 0V to VCC b1 IOL Parameter Part Number Condition Min VIL Input Low Voltage b 0.1 VIH Input High Voltage 2 VOL1 Output Low Voltage IOL e 2.1 mA VOH1 Output High Voltage IOH e b400 mA VOL2 Output Low Voltage IOL e 10 mA VOH2 Output High Voltage IOH e b10 mA fSK SK Clock Frequency (Note 4) tSKH SK High Time tSKL SK Low Time tCS Minimum CS Low Time tCSS CS Set-up Time tDH tDIS NM93C86AL NM93C86ALE/V mA 0.8 V VCC a 1 V 0.4 2.4 0.2 V 1 MHz VCC b 0.2 0 V V V 250 300 ns 250 ns 250 ns 50 ns DO Hold Time 70 ns DI Set-up Time 100 ns tCSH CS Hold Time 0 ns tDIH DI Hold Time 20 ns tPD1 Output Delay to ‘‘1’’ 500 ns tPD0 Output Delay to ‘‘0’’ 500 ns tSV CS to Status Valid 500 ns tDF CS to DO in TRI-STATE 100 ns tWP Write Cycle Time 10 ms http://www.national.com (Note 5) 1 4 Capacitance TA e a 25§ C, f e 1 MHz Test Max Units COUT Symbol Output Capacitance 5 pF CIN Input Capacitance 5 pF AC Test Conditions Output Load 1 TTL Gate and CL e 100 pF Input Pulse Levels 0.4V and 2.4V Timing Measurement Reference Level Input 1V and 2V Output 0.8V and 2.0V Note 1: Stress ratings above those listed under ‘‘Absolute Maximum Ratings’’ may cause permanent damage to the device. This is a stress rating only and operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2: Typical leakage values are in the 20 nA range. Note 3: The ORG pin may draw l 1 mA when in the x8 mode due to an internal pull-up transistor. Note 4: The shortest allowable SK clock period e 1/fSK (as shown under the fSK parameter). Maximum SK clock speed (minimum SK period) is determined by the interaction of several AC parameters stated in the datasheet. Within this SK period, both tSKH and tSKL limits must be observed. Therefore, it is not allowable to set 1/tSK e tSKH(minimum) a tSKL(minimum) for shorter SK cycle time operation. Note 5: CS (Chip Select) must be brought low (to VIL) for an interval of tCS in order to reset all internal device registers (device reset) prior to beginning another opcode cycle. (This is shown in the opcode diagrams in the following pages.) 5 http://www.national.com Interface Pin Description Chip Select (CS): Data-Out (DO): Chip Select performs several functions. It is used to differentiate between various devices on the same MICROWIRE bus. The rising edge resets the internal circuitry of the device, a function necessary prior to initiating a new cycle. Chip Select (as shown on Block Diagram) also gates the Data Input (DI) and Serial Clock (SK) Input, to disable these functions. In the case of these EEPROMs, Chip Select cannot be tied HIGH even if it is the only device on the bus. Chip Select must be held HIGH continuously during the course of clocking in the start bit, op-code address, and data-in or data-out. Otherwise the internal circuits will reset and the cycle will have to be started again with a new start bit. Chip Select initiates the internal programming cycle. The falling edge of Chip Select will start the internal asynchronous programming cycle after a programming op-code has been entered (Erase, Write, Erase All, or Write All). In conjunction with Chip Select, Data-Out (DO) will indicate when programming is complete. If the internal programming is incomplete, then Data-Out pin will be LOW. Then when the internal programming is complete, the Data-Out pin will be HIGH (see Timing Diagrams). The Data-Out pin sends Read data onto the MICROWIRE bus and it is clocked out on the rising edge of the Serial Clock. During the Read cycle, the DO output begins to drive actively after the last address bit (A0) is clocked in. Data-Out also carries the device’s status during the asynchronous programming cycle. The Data-Out pin drives LOW while the device is still in its internal programming cycle. After the EEPROM has completed this internal programming, Data-Out will drive HIGH. This is accomplished while Chip Select is held HIGH. Finally, if Chip Select is pulsed LOW to HIGH, Data-Out pin will again produce a pulse HIGH. Thus indicating the completion of the programming cycle. To clear the Ready/Busy polling, it is necessary to raise Chip Select and clock in another start bit. Once the start bit is clocked in, Data-Out will return to the HIGH impedance state. It is not necessary to continue with a cycle after this start bit has been clocked in, although it is permissible to start a new cycle with this start bit. This clearing of Ready/ Busy status may be necessary if a bidirectional data bus is used (Data-In tied to Data-Out) as the Data-Out output will interfere with the new data being presented on the Data-In pin. This connecting of the two Data pins is used for threewire interface schemes. Serial Clock (SK): The Serial Clock input is used to clock all start bits, opcodes, data, addresses, and data bits into or out of the EEPROMs. The clock’s rising edge controls the input and output of bits. The falling edge has no effect on the device. The Serial Clock is not necessary for the asynchronous Ready/Busy polling function. The Serial Clock is in a ‘‘Don’t Care’’ at any time Chip Select is LOW. It is also in a ‘‘Don’t Care’’ state prior to clocking in a start bit, or during Ready/Busy polling. During either of these last two conditions, Data-In (DI) must be held at a LOW level, otherwise a new start bit will be interpreted. Organization (ORG): The Organization input (ORG) is available on the NM93C86AL device and it is used to control the internal organization of the memory. The two selectable organizations are 16-bit words and 8-bit words. By connecting the ORG pin to VCC, 16-bit words are selected. In contrast, by connecting the ORG pin to GND, 8-bit words are selected. If the ORG pin is left floating, then default setting is the 16-bit word. When in the 8-bit mode, one additional address bit is required in the instruction sequence since the depth of the memory is doubled. Data-In (DI): The Data-In pin receives the start bit, address, and input data synchronously. Each bit is clocked in on the rising edge of SK. DI is gated by Chip Select to provide a high degree of noise immunity. Data-In is routed to both the instruction shift register and the data shift register. After the start bit is clocked into the last bit of the instruction register, the clock is switched to the data register to receive input data. To avoid false reading of a start bit, it is safer to keep the DataIn pin at LOW level when not in use. http://www.national.com 6 Instruction Set for the NM93C86AL The NM93C86AL has 7 instructions as described below. Note that the MSB of any instruction is a ‘‘1’’ and is viewed as a start bit in the interface sequence. The next 2 bits carry the op code, the next 10 (or 11) bits carry the address for selection of 1 of 1024 16-bit registers or 1 of 2048 8-bit registers, depending on memory array organization. 1024 by 16-Bit Organization (NM93C86AL when ORG e VCC or NC) SB OP-Code 2 Bits READ 1 10 A9–A0 EWEN 1 00 11XXXXXXXX EWDS 1 00 00XXXXXXXX ERASE 1 11 A9–A0 WRITE 1 01 A9–A0 ERAL 1 00 10XXXXXXXX WRAL 1 00 01XXXXXXXX Instruction Address 10 Bits Data 16 Bits Function Read data stored in selected register. Enables programming modes. Disables all programming modes. Erases selected register. D15 – D0 Writes data pattern D15 – D0 into selected register. Erases all registers. D15 – D0 Writes data pattern D15 – D0 into all registers. 2048 by 8-Bit Organization (NM93C86AL when ORG e GND) SB OP-Code 2 Bits READ 1 10 A10 – A0 EWEN 1 00 11XXXXXXXXX Enables programming modes. EWDS 1 00 00XXXXXXXXX Disables all programming modes. ERASE 1 11 A10– A0 WRITE 1 01 A10– A0 ERAL 1 00 10XXXXXXXXX WRAL 1 00 01XXXXXXXXX Instruction Address 11 Bits Data 18 Bits Function Read data stored in selected register. Erases selected register. D7 – D0 Writes data pattern D7 – D0 into selected register. Erases all registers. D7 – D0 Writes data pattern D7 – D0 into all registers. Functional Description Device NM93C86AL CS held ‘‘high’’, the DO pin will exit the high impedance state and indicate the READY/BUSY status of the device. DO e logical ‘‘0’’ indicates that programming is still in progress and no other instruction can be executed. DO e logical ‘‘1’’ indicates that the device is READY for another instruction. If CS is forced ‘‘low’’ the DO pin will return to the high impedance state. After the programming cycle has been completed and DO e logical ‘‘1’’, the DO pin can be reset back to the high impedance state by clocking a logical ‘‘1’’ into the DI pin. (This is also performed with the start bit on all op codes, thus clocking an instruction has the same effect.) ORG Pin Memory Logic Configuration Ý of Address Bits 0 2048 x 8 11 Bits 1 1024 x 16 10 Bits Programming The programming cycle for both devices is automatically started after entering the D0 data bit; independent of the status of the CS input pin. This feature allows a programming instruction (ERASE/WRITE/ERAL/WRAL) to be cancelled at any time before entering the last data bit (D0). This is accomplished by forcing the CS input pin low (for tCS) at any time before the DO data bit is clocked in. Note that the CS input pin can be brought low after the D0 bit is clocked in, to maintain compatibility with the other family members, but is not necessary to start a programming cycle. In all programming modes the READY/BUSY status of the device can be determined by polling the DO pin. After clocking in the last bit of the instruction sequence and with the Read (READ) The READ instruction outputs serial data on the DO pin. After a READ instruction is received, the instruction and address are decoded, followed by data transfer from the selected memory register into a serial-out shift register. A dummy bit (logical 0) precedes the serial data output string. Output data changes are initiated by a low to high transition of the SK clock after the last address bit (A0) is clocked in. 7 http://www.national.com Functional Description (Continued) Write (WRITE) The WRITE instruction is followed by 16 bits of data (or 8 bits of data when using the NM93C86AL in the x8 organization) to be written into the specified address. Note that if the CS is brought ‘‘low’’ before clocking in all of the data bits, then the WRITE instruction will be aborted. The selftimed programming cycle is initiated on the rising edge of the SK clock as the last data bit (D0) is clocked in. At this point, CS, SK and DI become don’t care states. No separate ERASE cycle is required before a WRITE instruction. As in the ERASE instruction, after starting a WRITE cycle, the DO pin indicates the READY/BUSY status of the chip if CS is held ‘‘high’’. DO e logical ‘‘0’’ indicates that programming is still in progress. DO e logical ‘‘1’’ indicates that the register, at the address specified in the instruction, has been written and that the part is ready for another instruction. Erase/Write Enable (EWEN) When VCC is applied to the part, it ‘‘powers up’’ in the Erase/Write Disable (EWDS) state. Therefore, all programming modes must be preceded by an Erase/Write Enable (EWEN) instruction. Once an Erase/Write Enable instruction is executed, programming remains enabled until an Erase/Write Disable (EWDS) instruction is executed or VCC is removed from the part. Erase/Write Disable (EWDS) To protect against accidental data overwrites, the Erase/ Write Disable (EWDS) instruction disables all programming modes and should follow all programming operations. Execution of a READ instruction is independent of both the EWEN and EWDS instructions. Erase (ERASE) The ERASE instruction will program all bits in the specified register to the logical ‘‘1’’ state. The self-timed programming cycle is initiated on the rising edge of the SK clock as the last address bit (A0) is clocked in. At this point CS, SK, and DI become don’t care states. After starting an ERASE cycle the DO pin indicates the READY/BUSY status of the chip if CS is held ‘‘high’’. DO e logical ‘‘0’’ indicates that programming is still in progress. DO e logical ‘‘1’’ indicates that the register, at the address specified in the instruction, has been erased. Erase All (ERAL) The ERAL instruction will simultaneously program all registers in the memory array to the logical ‘‘1’’ state. Write All (WRAL) The WRAL instruction will simultaneously program all registers with the data pattern specified in the instruction. Timing Diagrams for the NM93C86AL Synchronous Data Timing TL/D/12511 – 4 http://www.national.com 8 Timing Diagrams (Continued) Organization of Address and Data Fields for the NM93C86AL Organization AN DN VCC or NC Org 1024 x 16 A9 D15 VSS 2048 x 8 A10 D7 READ TL/D/12511 – 5 EWEN DO e TRI-STATE TL/D/12511 – 6 EWDS DO e TRI-STATE TL/D/12511 – 7 ERASE TL/D/12511 – 8 9 http://www.national.com Timing Diagrams (Continued) WRITE TL/D/12511 – 9 ERAL TL/D/12511 – 10 WRAL TL/D/12511 – 11 http://www.national.com 10 Physical Dimensions inches (millimeters) unless otherwise noted Molded Small Out-Line Package (M8) NS Package Number M08A 11 http://www.national.com NM93C86AL 16,384-Bit Serial Interface, Low Voltage CMOS EEPROM (MICROWIRE Synchronous Bus) Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Molded Dual-In-Line Package (N) NS Package Number N08E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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