ETC NTMD6N02R2/D

NTMD6N02R2
Product Preview
Power MOSFET
6.0 Amps, 20 Volts
N–Channel Enhancement Mode
Dual SO–8 Package
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Features
•
•
•
•
•
•
•
Ultra Low RDS(on)
Higher Efficiency Extending Battery Life
Logic Level Gate Drive
Miniature Dual SO–8 Surface Mount Package
Diode Exhibits High Speed, Soft Recovery
Avalanche Energy Specified
SO–8 Mounting Information Provided
6.0 AMPERES
20 VOLTS
35 m @ VGS = 4.5 V
N–Channel
Applications
D
• DC–DC Converters
• Low Voltage Motor Control
• Power Management in Portable and Battery–Powered Products, i.e.:
Computers, Printers, Cellular and Cordless Telephones and PCMCIA
Cards
G
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
S
Symbol
Value
Unit
Drain–to–Source Voltage
VDSS
20
V
Drain–to–Gate Voltage (RGS = 1.0 M)
VDGR
20
V
Gate–to–Source Voltage – Continuous
VGS
12
V
Thermal Resistance –
Junction–to–Ambient (Note 1.)
Total Power Dissipation @ TA = 25°C
Continuous Drain Current @ TA = 25°C
Continuous Drain Current @ TA = 70°C
Pulsed Drain Current (Note 4.)
RθJA
PD
ID
ID
IDM
62.5
2.0
6.5
5.5
20
°C/W
W
A
A
A
Thermal Resistance –
Junction–to–Ambient (Note 2.)
Total Power Dissipation @ TA = 25°C
Continuous Drain Current @ TA = 25°C
Continuous Drain Current @ TA = 70°C
Pulsed Drain Current (Note 4.)
RθJA
PD
ID
ID
IDM
102
1.22
5.07
4.07
16
°C/W
W
A
A
A
Thermal Resistance –
Junction–to–Ambient (Note 3.)
Total Power Dissipation @ TA = 25°C
Continuous Drain Current @ TA = 25°C
Continuous Drain Current @ TA = 70°C
Pulsed Drain Current (Note 4.)
RθJA
PD
ID
ID
IDM
172
0.73
3.92
3.14
12
°C/W
W
A
A
A
1
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
November, 2000 – Rev. 0
SO–8
CASE 751
STYLE 11
MARKING DIAGRAM
& PIN ASSIGNMENT
Source 1
Gate 1
Source 2
Gate 2
1. Mounted onto a 2″ square FR–4 Board (1″ sq. 2 oz. Cu 0.06″ thick single
sided), t < 10 seconds.
2. Mounted onto a 2″ square FR–4 Board (1″ sq. 2 oz. Cu 0.06″ thick single
sided), t = steady state.
3. Minimum FR–4 or G–10 PCB, t = steady state.
4. Pulse Test: Pulse Width = 300 s, Duty Cycle = 2%.
 Semiconductor Components Industries, LLC, 2000
8
1
1
8
2
7
3
E6N02
LYWW
4
6
5
Drain 1
Drain 1
Drain 2
Drain 2
(Top View)
E6N02
L
Y
WW
= Device Code
= Assembly Location
= Year
= Work Week
ORDERING INFORMATION
Device
NTMD6N02R2
Package
Shipping
SO–8
2500/Tape & Reel
Publication Order Number:
NTMD6N02R2/D
NTMD6N02R2
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) (continued)
Rating
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy – Starting TJ = 25°C
(VDD = 20 Vdc, VGS = 5.0 Vdc, Peak IL = 6.0 Apk, L = 20 mH, RG = 25 Ω)
Maximum Lead Temperature for Soldering Purposes for 10 seconds
Symbol
Value
Unit
TJ, Tstg
–55 to +150
°C
EAS
360
mJ
TL
260
°C
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) *
Characteristic
Symbol
Min
Typ
Max
20
–
–
19.2
–
–
–
–
–
–
1.0
10
Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 µAdc)
Temperature Coefficient (Positive)
V(BR)DSS
Vdc
mV/°C
µAdc
Zero Gate Voltage Drain Current
(VDS = 20 Vdc, VGS = 0 Vdc, TJ = 25°C)
(VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125°C)
IDSS
Gate–Body Leakage Current (VGS = +12 Vdc, VDS = 0 Vdc)
IGSS
–
–
100
nAdc
Gate–Body Leakage Current (VGS = –12 Vdc, VDS = 0 Vdc)
IGSS
–
–
–100
nAdc
0.6
–
0.9
–3.0
1.2
–
–
–
–
–
0.028
0.028
0.033
0.035
0.035
0.043
0.048
0.049
gFS
–
10
–
Mhos
Ciss
–
785
1100
pF
Coss
–
260
450
Crss
–
75
180
td(on)
–
12
20
tr
–
50
90
td(off)
–
45
75
tf
–
80
130
td(on)
–
11
18
tr
–
35
65
td(off)
–
45
75
tf
–
60
110
Qtot
–
12
20
Qgs
–
1.5
–
Qgd
–
4.0
–
ON CHARACTERISTICS
Gate Threshold Voltage
(VDS = VGS, ID = –250 µAdc)
Temperature Coefficient (Negative)
VGS(th)
Static Drain–to–Source On–State Resistance
(VGS = 4.5 Vdc, ID = 6.0 Adc)
(VGS = 4.5 Vdc, ID = 4.0 Adc)
(VGS = 2.7 Vdc, ID = 2.0 Adc)
(VGS = 2.5 Vdc, ID = 3.0 Adc)
RDS(on)
Forward Transconductance (VDS = 12 Vdc, ID = 3.0 Adc)
Vdc
mV/°C
Ω
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 16 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (Notes 5. and 6.)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
(VDD = 16 Vdc, ID = 6.0 Adc,
VGS = 4.5
4 5 Vdc,
Vdc
RG = 6.0 Ω)
Fall Time
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
(VDD = 16 Vdc, ID = 4.0 Adc,
4 5 Vdc,
Vdc
VGS = 4.5
RG = 6.0 Ω)
Fall Time
Total Gate Charge
Gate–Source Charge
Gate–Drain Charge
(VDS = 16 Vdc,
VGS = 4.5 Vdc,
ID = 6.0
6 0 Adc)
Ad )
5. Indicates Pulse Test: Pulse Width = 300 µs max, Duty Cycle = 2%.
6. Switching characteristics are independent of operating junction temperature.
* Handling precautions to protect against electrostatic discharge is mandatory.
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2
ns
ns
nC
NTMD6N02R2
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) (continued) *
Characteristic
Symbol
Min
Typ
Max
Unit
VSD
–
–
–
0.83
0.88
0.75
1.1
1.2
–
Vdc
trr
–
30
–
ns
ta
–
15
–
tb
–
15
–
QRR
–
0.02
–
BODY–DRAIN DIODE RATINGS (Note 7.)
(IS = 4.0 Adc, VGS = 0 Vdc)
(IS = 6.0 Adc, VGS = 0 Vdc)
(IS = 6.0 Adc, VGS = 0 Vdc, TJ = 125°C)
Diode Forward On–Voltage
Reverse Recovery Time
(IS = 6.0
6 0 Adc,
Ad VGS = 0 Vdc,
Vd
dIS/dt = 100 A/µs)
Reverse Recovery Stored Charge
µC
7. Indicates Pulse Test: Pulse Width = 300 µs max, Duty Cycle = 2%.
* Handling precautions to protect against electrostatic discharge is mandatory.
2.5 V
12
2.0 V
4.5 V
3.2 V
ID, DRAIN CURRENT (AMPS)
10
TJ = 25°C
8
1.8 V
6
4
VGS = 1.5 V
2
0
R DS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
10 V
0
0.25
0.5
0.75
1
1.25
1.5
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 1. On–Region Characteristics
0.07
ID = 6.0 A
TJ = 25°C
0.06
0.05
0.04
0.03
0.02
0.01
0
0
2
4
6
8
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
VDS ≥ 10 V
10
8
6
4
10
25°C
100°C
TJ = –55°C
2
0
1.75
R DS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
I D, DRAIN CURRENT (AMPS)
12
0.5
1
1.5
2
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
2.5
Figure 2. Transfer Characteristics
0.05
TJ = 25°C
0.04
VGS = 2.5 V
0.03
4.5 V
0.02
0.01
1
Figure 3. On–Resistance versus
Gate–To–Source Voltage
3
5
7
9
ID, DRAIN CURRENT (AMPS)
11
13
Figure 4. On-Resistance versus Drain Current
and Gate Voltage
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3
1.6
1000
ID = 6.0 A
VGS = 4.5 V
1.4
I DSS , LEAKAGE (nA)
1.2
1
VGS = 0 V
TJ = 125°C
100
100°C
10
1
25°C
0.1
0.8
0.6
–50
0.01
–25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
150
4
VDS = 0 V
2000
VGS = 0 V
TJ = 25°C
Ciss
1500
Crss
1000
Ciss
500
Coss
Crss
0
10
5
0
5
10
15
VGS VDS
20
5
20
QT
16
4
VDS
VGS
3
12
Q1
2
ID = 6 A
VDS = 16 V
VGS = 4.5 V
TJ = 25°C
Q2
8
4
1
0
0
0
4
8
12
16
Qg, TOTAL GATE CHARGE (nC)
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
Figure 7. Capacitance Variation
1000
VDS = 16 V
ID = 6.0 A
VGS = 4.5 V
t, TIME (ns)
C, CAPACITANCE (pF)
2500
100
tf
tr
td(off)
td(on)
10
1
20
Figure 6. Drain–To–Source Leakage Current
versus Voltage
VGS , GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 5. On–Resistance Variation with
Temperature
8
12
16
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
10
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
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4
100
V DS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
RDS(on) , DRAIN–TO–SOURCE RESISTANC
(NORMALIZED)
NTMD6N02R2
NTMD6N02R2
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
100
VGS = 0 V
TJ = 25°C
4
3
2
1
0
VGS = 12 V
SINGLE PULSE
TC = 25°C
I D , DRAIN CURRENT (AMPS)
I S, SOURCE CURRENT (AMPS)
5
10
10 ms
1
0.1
0
0.2
0.4
0.6
0.8
1.2
1.0
1 ms
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1
0.1
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
dc
10
100
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 12. Diode Reverse Recovery Waveform
TYPICAL ELECTRICAL CHARACTERISTICS
Rthja(t), EFFECTIVE TRANSIENT
THERMAL RESISTANCE
1
D = 0.5
0.2
0.1
0.1
0.05
P(pk)
0.02
0.01
0.01
t1
t2
DUTY CYCLE, D = t1/t2
SINGLE PULSE
RθJC(t) = r(t) RθJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) - TC = P(pk) RθJC(t)
0.001
1.0E–05
1.0E–04
1.0E–03
1.0E–02
1.0E–01
1.0E+00
t, TIME (s)
Figure 13. Thermal Response
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5
1.0E+01
1.0E+02
1.0E+03
NTMD6N02R2
INFORMATION FOR USING THE SO–8 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to ensure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self–align when
subjected to a solder reflow process.
0.060
1.52
0.275
7.0
0.155
4.0
0.024
0.6
0.050
1.270
inches
mm
SOLDERING PRECAUTIONS
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
• When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied
during cooling.
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
• Always preheat the device.
• The delta temperature between the preheat and
soldering should be 100°C or less.*
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10°C.
* Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.
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6
NTMD6N02R2
TYPICAL SOLDER HEATING PROFILE
temperature versus time. The line on the graph shows the
actual temperature that might be experienced on the surface
of a test board at or near a central solder joint. The two
profiles are based on a high density and a low density
board. The Vitronics SMD310 convection/infrared reflow
soldering system was used to generate this profile. The type
of solder used was 62/36/2 Tin Lead Silver with a melting
point between 177–189°C. When this type of furnace is
used for solder reflow work, the circuit boards and solder
joints tend to heat first. The components on the board are
then heated by conduction. The circuit board, because it has
a large surface area, absorbs the thermal energy more
efficiently, then distributes this energy to the components.
Because of this effect, the main body of a component may
be up to 30 degrees cooler than the adjacent solder joints.
For any given circuit board, there will be a group of
control settings that will give the desired heat pattern. The
operator must set temperatures for several heating zones
and a figure for belt speed. Taken together, these control
settings make up a heating “profile” for that particular
circuit board. On machines controlled by a computer, the
computer remembers these profiles from one operating
session to the next. Figure 14 shows a typical heating
profile for use when soldering a surface mount device to a
printed circuit board. This profile will vary among
soldering systems, but it is a good starting point. Factors
that can affect the profile include the type of soldering
system in use, density and types of components on the
board, type of solder used, and the type of board or
substrate material being used. This profile shows
STEP 1
PREHEAT
ZONE 1
“RAMP”
200°C
STEP 2
STEP 3
VENT
HEATING
“SOAK” ZONES 2 & 5
“RAMP”
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
STEP 4
HEATING
ZONES 3 & 6
“SOAK”
160°C
STEP 5
STEP 6
STEP 7
HEATING
VENT
COOLING
ZONES 4 & 7
205° TO 219°C
“SPIKE”
PEAK AT
170°C
SOLDER
JOINT
150°C
150°C
100°C
140°C
100°C
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
MASS OF ASSEMBLY)
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
5°C
TIME (3 TO 7 MINUTES TOTAL)
TMAX
Figure 14. Typical Solder Heating Profile
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7
NTMD6N02R2
PACKAGE DIMENSIONS
SO–8
CASE 751–06
PLASTIC
ISSUE T
D
A
8
E
5
0.25
H
1
M
B
M
4
h
B
X 45 e
A
C
SEATING
PLANE
L
0.10
A1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS ARE IN MILLIMETER.
3. DIMENSION D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
C
B
0.25
M
C B
S
A
S
DIM
A
A1
B
C
D
E
e
H
h
L
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.35
0.49
0.19
0.25
4.80
5.00
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0
7
STYLE 11:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
SOURCE 1
GATE 1
SOURCE 2
GATE 2
DRAIN 2
DRAIN 2
DRAIN 1
DRAIN 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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NTMD6N02R2/D