NTQD6866R2 Power MOSFET 6.9 Amps, 20 Volts N–Channel TSSOP–8 Features • • • • • • • New Low Profile TSSOP–8 Package Ultra Low RDS(on) Higher Efficiency Extending Battery Life Logic Level Gate Drive Diode Exhibits High Speed, Soft Recovery Avalanche Energy Specified IDSS and VDS(on) Specified at Elevated Temperatures http://onsemi.com 6.9 AMPERES 20 VOLTS 30 mΩ @ VGS = 4.5 V Applications • Power Management in Portable and Battery–Powered Products, i.e.: • • N–Channel Computers, Printers, PCMCIA Cards, Cellular and Cordless Telephones Battery Applications NoteBook PC MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Value Unit 20 Vdc Drain–to–Gate Voltage (RGS = 1.0 MΩ) VDSS VDGR 20 Vdc Gate–to–Source Voltage – Continuous VGS 12 Vdc Thermal Resistance – Single Die Junction–to–Ambient (Note 1) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Pulsed Drain Current (Note 4) RJA PD ID IDM 62.5 2.0 6.9 24 °C/W W Adc Adc Thermal Resistance – Single Die Junction–to–Ambient (Note 2) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C Pulsed Drain Current (Note 4) RJA PD ID ID IDM 88 1.42 5.8 4.6 20 °C/W W Adc Adc Adc Thermal Resistance – Single Die Junction–to–Ambient (Note 3) RJA 132 °C/W PD 0.94 W Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C ID 4.7 Adc ID 3.8 Adc Continuous Drain Current @ TA = 70C IDM 14 Adc Pulsed Drain Current (Note 4) 1. Mounted onto a 2″ square FR–4 board (1″ sq. 2 oz Cu 0.06″ thick single sided), t < 10 seconds. 2. Mounted onto a 2″ square FR–4 board (1″ sq. 2 oz Cu 0.06″ thick single sided), t = 10 seconds. 3. Minimum FR–4 or G–10 PCB, t = steady state. 4. Pulse Test: Pulse Width = 300 µs, Duty Cycle = 2%. G2 S1 September, 2001 – Rev. 1 1 S2 TSSOP–8 CASE 948S PLASTIC 8 1 MARKING DIAGRAM & PIN ASSIGNMENT 1 S1 G1 S2 2 3 G2 4 866 YWW 8 7 6 5 D D D D Top View 866 YWW = Device Code = Date Code ORDERING INFORMATION Device NTQD6866R2 Semiconductor Components Industries, LLC, 2001 D G1 Symbol Drain–to–Source Voltage N–Channel D Package Shipping TSSOP–8 4000/Tape & Reel Publication Order Number: NTQD6866R2/D NTQD6866R2 MAXIMUM RATINGS (continued) Rating Thermal Resistance – Both Die Junction–to–Ambient (Note 5) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Pulsed Drain Current (Note 5) Operating and Storage Temperature Range Symbol Value Unit RJA PD ID IDM TJ, Tstg 160 0.78 4.3 14 °C/W W Adc Adc Single Pulse Drain–to–Source Avalanche Energy – Starting TJ = 25°C (VDD = 20 Vdc, VGS = 5.0 Vdc, Peak IL = 5.5 Apk, L = 10 mH, RG = 25 Ω) Maximum Lead Temperature for Soldering Purposes for 10 seconds –55 to +150 EAS °C mJ 150 TL 260 °C ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 20 – – 18.5 – – – – – – 1.0 10 – – ±100 0.6 – 0.9 –2.7 1.2 – – – – – 0.026 0.025 0.030 0.030 0.032 0.030 0.038 0.038 gFS – 14 – Mhos pF OFF CHARACTERISTICS V(BR)DSS Drain–to–Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 µAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VGS = 0 Vdc, VDS = 20 Vdc, TJ = 25°C) (VGS = 0 Vdc, VDS = 20 Vdc, TJ = 100°C) Gate–Body Leakage Current Vdc µAdc IDSS (VGS = ±12 Vdc, VDS = 0 Vdc) IGSS mV/°C nAdc ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = 250 µAdc) Temperature Coefficient (Negative) VGS(th) Static Drain–to–Source On–State Resistance (VGS = 4.5 Vdc, ID = 6.9 Adc) (VGS = 4.5 Vdc, ID = 5.8 Adc) (VGS = 2.5 Vdc, ID = 3.5 Adc) (VGS = 2.5 Vdc, ID = 2.9 Adc) RDS(on) Forward Transconductance (VDS = 10 Vdc, ID = 5.8 Adc) Vdc mV/°C Ω DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 16 Vdc, Vd VGS = 0 Vd Vdc, f = 1.0 MHz) Reverse Transfer Capacitance 5. Pulse Test: Pulse Width = 300 µs, Duty Cycle = 2%. http://onsemi.com 2 Ciss – 875 1400 Coss – 325 550 Crss – 100 175 NTQD6866R2 ELECTRICAL CHARACTERISTICS (continued) Characteristic Symbol Min Typ Max Unit td(on) – 10 18 ns tr – 45 80 td(off) – 40 75 tf – 90 150 td(on) – 8.0 – tr – 45 – td(off) – 35 – tf – 75 – Qtot – 13 22 SWITCHING CHARACTERISTICS (Notes 6 & 7) Turn–On Delay Time Rise Time (VDD = 16 Vdc, ID = 5.8 Adc, VGS = 4.5 Vdc, RG = 6.0 Ω) Turn–Off Delay Time Fall Time Turn–On Delay Time Rise Time (VDD = 16 Vdc, ID = 5.8 Adc, VGS = 4.5 Vdc, RG = 3.0 Ω) Turn–Off Delay Time Fall Time Gate Charge (VDS = 16 Vdc, Vd VGS = 4 4.5 5 Vd Vdc, ID = 5.8 Adc) ns nC Qgs – 1.8 – Qgd – 4.5 – VSD – – 0.85 0.75 1.0 – Vdc trr – 23 – ns ta – 12 – tb – 11 – QRR – 0.013 – BODY–DRAIN DIODE RATINGS (Note 6) Forward On–Voltage Reverse Recovery Time (IS = 5.8 Adc, VGS = 0 Vdc) (IS = 5.8 Adc, VGS = 0 Vdc, TJ = 100°C) (IS = 5.8 Adc, VGS = 0 Vdc, VDS = 20 Vdc dIS/dt = 100 A/ A/µs)) Reverse Recovery Stored Charge 6. Pulse Test: Pulse Width = 300 µs, Duty Cycle = 2%. 7. Switching characteristics are independent of operating junction temperature. http://onsemi.com 3 µC NTQD6866R2 16 18 VDS ≥ 10 V ID, DRAIN CURRENT (AMPS) 14 5 V VGS = 10 V ID, DRAIN CURRENT (AMPS) 2V TJ = 25°C 12 1.8 V 3V 10 8 2.2 V 6 1.6 V 4 1.4 V 2 16 14 12 10 8 6 TJ = 25°C 4 TJ = 100°C 2 1.2 V 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) 0 0.5 2 TJ = –55°C 1 1.5 2 VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) RDS(on), DRAIN–TO–SOURCE RESISTANCE (Ω) Figure 2. Transfer Characteristics 0.045 ID = 5.8 A TJ = 25°C 0.04 0.035 0.03 0.025 0.02 0.015 0.01 0 2 4 6 8 0.04 TJ = 25°C 0.03 VGS = 2.5 V 0.02 VGS = 4.5 V 0.01 0 4 6 8 10 12 14 VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS) Figure 3. On–Resistance versus Gate–to–Source Voltage Figure 4. On–Resistance versus Drain Current and Gate Voltage 16 10000 2 VGS = 0 V ID = 2.9 A VGS = 4.5 V IDSS, LEAKAGE (nA) RDS(on), DRAIN–TO–SOURCE RESISTANCE (NORMALIZED) RDS(on), DRAIN–TO–SOURCE RESISTANCE (Ω) Figure 1. On–Region Characteristics 2.5 1.5 1 TJ = 150°C 1000 100 TJ = 100°C 0.5 –50 10 –25 0 25 50 75 100 125 150 0 8 12 16 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) Figure 5. On–Resistance Variation with Temperature Figure 6. Drain–to–Source Leakage Current versus Voltage http://onsemi.com 4 20 2500 VDS = 0 V VGS = 0 V Ciss TJ = 25°C C, CAPACITANCE (pF) 2000 Crss 1500 1000 Ciss 500 Coss Crss 0 10 VGS 0 VDS 5 5 10 20 15 VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) NTQD6866R2 5 QT 4 VGS 3 Q1 2 Q2 1 ID = 5.8 A TJ = 25°C 0 0 2 4 GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS) 10 12 Figure 8. Gate–to–Source Voltage versus Total Charge 1000 10 100 IS, SOURCE CURRENT (AMPS) VDD = 16 V ID = 5.8 A VGS = 4.5 V t, TIME (ns) 8 Qg, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation tf tr td(off) 10 1 6 td(on) 1 10 VGS = 0 V TJ = 25°C 8 6 4 2 0 0.4 100 0.5 RG, GATE RESISTANCE (Ω) 0.6 0.7 0.8 VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS) Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure 10. Diode Forward Voltage versus Current ID, DRAIN CURRENT (AMPS) 100 VGS = 20 V SINGLE PULSE TC = 25°C 100 µs 10 di/dt 1 ms IS 10 ms 1 trr ta 0.1 0.01 0.1 tb TIME RDS(on) Limit Thermal Limit Package Limit dc 0.25 IS tp IS 1 10 100 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Diode Reverse Recovery Waveform http://onsemi.com 5 NTQD6866R2 r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) 10 1 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 0.001 Single Pulse 0.0001 0.000001 0.00001 0.0001 0.001 0.01 0.1 t, TIME (s) Figure 13. Thermal Response http://onsemi.com 6 1 10 100 NTQD6866R2 INFORMATION FOR USING THE TSSOP–8 SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 0.038 0.95 0.252 6.4 0.177 4.5 0.018 0.45 0.026 0.65 inches mm SOLDERING PRECAUTIONS • When shifting from preheating to soldering, the maximum temperature gradient shall be 5°C or less. • After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. • Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. • Always preheat the device. • The delta temperature between the preheat and soldering should be 100°C or less.* • When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10°C. • The soldering temperature and time shall not exceed 260°C for more than 10 seconds. * * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering. http://onsemi.com 7 NTQD6866R2 TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating “profile” for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 14 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the STEP 1 PREHEAT ZONE 1 “RAMP” 200°C STEP 2 STEP 3 VENT HEATING “SOAK” ZONES 2 & 5 “RAMP” DESIRED CURVE FOR HIGH MASS ASSEMBLIES actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177–189°C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joint. STEP 4 HEATING ZONES 3 & 6 “SOAK” 160°C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205° TO 219°C “SPIKE” PEAK AT 170°C SOLDER JOINT 150°C 150°C 100°C 140°C 100°C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5°C TMAX TIME (3 TO 7 MINUTES TOTAL) Figure 14. Typical Solder Heating Profile http://onsemi.com 8 NTQD6866R2 PACKAGE DIMENSIONS TSSOP–8 CASE 948S–01 PLASTIC ISSUE O 8x 0.20 (0.008) T U K REF 0.10 (0.004) S 2X L/2 8 B –U– 1 V S J J1 4 PIN 1 IDENT S T U 5 L 0.20 (0.008) T U M ÎÎÎ ÏÏÏ ÏÏÏ ÎÎÎ K1 K A –V– SECTION N–N –W– C 0.076 (0.003) –T– SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. S D DETAIL E G P 0.25 (0.010) N M N P1 F DETAIL E http://onsemi.com 9 DIM A B C D F G J J1 K K1 L M P P1 MILLIMETERS MIN MAX 2.90 3.10 4.30 4.50 --1.10 0.05 0.15 0.50 0.70 0.65 BSC 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0 8 --2.20 --3.20 INCHES MIN MAX 0.114 0.122 0.169 0.177 --0.043 0.002 0.006 0.020 0.028 0.026 BSC 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0 8 --0.087 --0.126 NTQD6866R2 Notes http://onsemi.com 10 NTQD6866R2 Notes http://onsemi.com 11 NTQD6866R2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada Email: [email protected] JAPAN: ON Semiconductor, Japan Customer Focus Center 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031 Phone: 81–3–5740–2700 Email: [email protected] ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. N. American Technical Support: 800–282–9855 Toll Free USA/Canada http://onsemi.com 12 NTQD6866R2/D