Low Cost, Low Power, True RMS-to-DC Converter AD8436 FEATURES FUNCTIONAL BLOCK DIAGRAM CAVG CCF VCC 100kΩ SUM RMS IGND 8kΩ 100kΩ RMS CORE VEE 16kΩ OUT 10pF IBUFGN 10kΩ 10kΩ IBUFIN– – IBUFIN+ + OBUFIN+ OBUFIN– FET OP AMP + 16kΩ OGND DC BUFFER – IBUFOUT OBUFOUT 10033-001 Computes true rms value instantly Accuracy: ±10 μV ± 0.5% of reading Wide dynamic input range 100 μV rms to 3 V rms (8.5 V p-p) full-scale input range Larger inputs with external scaling Wide bandwidth: 1 MHz for −3 dB (300 mV) 65 kHz for additional 1% error Zero converter dc output offset No residual switching products Specified at 300 mV rms input Accurate conversion with crest factors up to 10 Low power: 300 µA typical at ±2.4 V Fast settling at all input levels High-Z FET separately powered input buffer RIN ≥ 1012 Ω, CIN ≤ 2 pF Precision dc output buffer Wide supply range Dual: ±2.4 V to ±18 V Single: 4.8 V to 36 V Small size: 4 mm × 4 mm package ESD protected AD8436 Figure 1. GENERAL DESCRIPTION meters and other battery-powered applications. The precision dc output buffer offers extremely low offset voltages, thanks to bias current cancellation. Unlike digital solutions, the AD8436 has no switching circuitry limiting performance at high or low amplitudes (see Figure 2). A usable response of <100 μV and >3 V extends the dynamic range with no external scaling, accommodating the most demanding low signal conditions. GREATER INPUT DYNAMIC RANGE The AD8436 delivers instant true rms results at less cost than misleading peak, averaging, or digital solutions. There is no programming expense or processor overhead to consider, and the 4 mm × 4 mm package easily fits into those tight applications. On-board buffer amplifiers enable the widest range of options for any rms-to-dc converter available, regardless of cost. For minimal applications, only a single external averaging capacitor is required. The built-in high impedance FET buffer provides an interface for external attenuators, frequency compensation, or driving low impedance loads. A matched pair of internal resistors enables an easily configurable gain-of-two or more, extending the usable input range even lower. The low power, precision input buffer makes the AD8436 attractive for use in portable multi- AD8436 ∆Σ SOLUTION 100µV 1mV 10mV 100mV 1V 3V 10033-002 The AD8436 is a new generation, translinear precision, low power, true rms-to-dc converter that is loaded with options. It computes a precise dc equivalent of the rms value of ac waveforms, including complex patterns such as those generated by switchmode power supplies and triacs. Its accuracy spans a wide range of input levels (see Figure 2) and temperatures. The ensured accuracy of ≤±0.5% and ≤10 μV output offset result from the latest Analog Devices, Inc., technology. The crest factor error is <0.5% for CF values between 1 and 10. Figure 2. Usable Dynamic Range of the AD8436 vs. ΔΣ The AD8436 operates from single or dual supplies of ±2.4 V (4.8 V) to ±18 V (36 V). A and J grades are available in a compact 4 mm × 4 mm, 20-lead chip-scale package. The operating temperature ranges are −40°C to 125°C and 0°C to 70°C. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. AD8436 TABLE OF CONTENTS Features .............................................................................................. 1 Test Circuits........................................................................................9 Functional Block Diagram .............................................................. 1 Theory of Operation ...................................................................... 10 General Description ......................................................................... 1 Overview ..................................................................................... 10 Revision History ............................................................................... 2 Applications Information .............................................................. 12 Specifications..................................................................................... 3 Using the AD8436....................................................................... 12 Absolute Maximum Ratings............................................................ 4 AD8436 Evaluation Board......................................................... 16 Thermal Resistance ...................................................................... 4 Outline Dimensions ....................................................................... 18 ESD Caution.................................................................................. 4 Ordering Guide .......................................................................... 18 Pin Configuration and Function Descriptions............................. 5 Typical Performance Characteristics ............................................. 6 REVISION HISTORY 7/11—Revision 0: Initial Version Rev. 0 | Page 2 of 20 AD8436 SPECIFICATIONS eIN = 300 mV ac (rms), frequency = 1 kHz sinusoidal, ac-coupled, ±VS = ±5 V, TA = 25°C, CAVG = 10 μF, unless otherwise specified. Table 1. Parameter RMS CORE Conversion Error Vs. Temperature Vs. Rail Voltage Input Offset Voltage Output Offset Voltage Vs. Temperature DC Reversal Error Nonlinearity Crest Factor Error 1 < CF < 10 Peak Input Voltage Input Resistance Frequency Response 1% Additional Error 3 dB Bandwidth Settling Time 0.1% 0.01% Output Resistance Supply Current INPUT BUFFER Signal Voltage Swing Input Output Offset Voltage Input Bias Current Input Resistance Frequency Response 0.1 dB 3 dB Bandwidth Supply Current Optional Gain Resistor Gain Error OUTPUT BUFFER Offset Voltage Input Current Output Voltage Swing Gain Error Supply Current SUPPLY VOLTAGE Dual Single Test Conditions/Comments Min Typ Max Unit Default conditions −40°C < T < 125 C ±2.4 V to ±18 V DC-coupled Default conditions, ac-coupled input −40 C < T < 125°C DC-coupled, VIN = ±300 mV eIN = 10 mV to 300 mV ac (rms) Additional error CCF = 0.1 μF ±10 − 0.5 ±0 ± 0 0.006 ±0.013 0 0 0.3 ±0.5 0.05 ±10 + 0.5 μV/% rdg %/°C ±%/V μV V μV/°C % % −500 −0.5 −VS − 0.7 7.92 8 +500 ±2 +0.5 +VS + 0.7 8.08 % V kΩ VIN = 300 mV rms Rising/falling Rising/falling 15.68 No input G=1 AC- or dc-coupled AC-coupled to Pin RMS −VS −VS + 0.2 −1 65 1 kHz MHz 148/341 158/350 16 325 ms ms kΩ μA 0 16.32 400 +VS +VS − 0.2 +1 50 1012 100 −9.9 950 2.1 160 +10 −200 0 G = ×1 Connected to Pin OUT −VS + 0.0005 0.003 40 ±2.4 4.8 Rev. 0 | Page 3 of 20 V mV mV pA Ω 200 +10.1 0.05 kHz MHz μA kΩ % +200 3 +VS − 1 0.01 70 μV nA V % μA ±18 36 V V AD8436 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage Internal Power Dissipation Input Voltage Output Short-Circuit Duration Differential Input Voltage Temperature Operating Range Storage Range Lead Soldering (60 sec) ESD Rating THERMAL RESISTANCE Rating ±18 V 18 mW ±VS Indefinite +VS and −VS θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance −40°C to +125°C −65°C to +125°C 300°C 2 kV Package Type CP-20-10 LFCSP Without Thermal Pad CP-20-10 LFCSP With Thermal Pad ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 4 of 20 θJA 86 48 Unit °C/W °C/W AD8436 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SUM CAVG CCF VCC 20 IBUFV+ 16 1 15 DNC OBUFV+ PIN 1 INDICATOR RMS OBUFOUT AD8436 TOP VIEW (Not to Scale) IBUFOUT OBUFIN– IBUFIN– OBUFIN+ IBUFIN+ IGND 5 11 6 10 DNC OGND OUT VEE NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED PAD SHOULD NOT BE CONNECTED. 10033-003 IBUFGN Figure 3. Pin Configuration, Top View Table 4. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 Mnemonic DNC RMS IBUFOUT IBUFIN– IBUFIN+ IBUFGN DNC OGND 9 10 11 12 13 14 15 16 17 18 19 20 EP OUT VEE IGND OBUFIN+ OBUFIN− OBUFOUT OBUFV+ IBUFV+ VCC CCF CAVG SUM DNC Description Do Not Connect. Used for factory test. AC Input to the RMS Core. Output Connection for the FET Input Buffer Amplifier. Inverting Input to the FET Input Buffer Amplifier. Noninverting Input to the FET Input Buffer Amplifier. Optional 10 kΩ Precision Gain Resistor. Do Not Connect. Used for factory test. Internal 16 kΩ Current-to-Voltage Resistor. Connect to ground for voltage output at Pin 9; leave unconnected for current output at Pin 9. Voltage or Current Output of the RMS Core. Negative Supply Rail. Half Supply Node. Leave open for single-supply operation. Noninverting Input of the Optional Precision Output Buffer. OBUFIN+ is typically connected to OUT. Inverting Input of the Optional Precision Output Buffer. OBUFIN− is typically connected to OBUFOUT. Low Impedance Output for ADC or Other Loads. Power Pin for the Output Buffer. Power Pin for the Input Buffer. Positive Supply Rail for the RMS Core. Connection for Crest Factor Capacitor. Connection for Averaging Capacitor. Summing Amplifier Input Node. An external resistor can be connected for custom scaling. Exposed Pad. The exposed pad should not be connected. Rev. 0 | Page 5 of 20 AD8436 TYPICAL PERFORMANCE CHARACTERISTICS 5V 5V 1V 1V INPUT LEVEL (V rms) 100mV 10mV −3dB BW 100mV 10mV −3dB BW 1mV 1mV 50 100 1k 10k 100k FREQUENCY (Hz) 1M 5M 50µV 10033-004 50µV VS = 4.8V 100µV 100µV 50 100 1k 10k 100k FREQUENCY (Hz) 1M 10033-007 INPUT LEVEL (V rms) TA = 25°C, ±VS = ±5 V, CAVG = 10 μF, 1 kHz sine wave, unless otherwise indicated. 5M Figure 7. RMS Core Frequency Response with VS = +4.8 V (See Figure 21) Figure 4. RMS Core Frequency Response (See Figure 20) 5V 15 12 1V eIN = 3.5mV rms 6 100mV GAIN (dB) INPUT LEVEL (V rms) 9 10mV −3dB BW 3 0 –3 –6 1mV –9 50 100 1k 10k 100k FREQUENCY (Hz) 1M 5M –15 100 10k 100k 1M 5M FREQUENCY (Hz) Figure 5. RMS Core Frequency Response with VS = ±2.4 V (See Figure 20) Figure 8. Input Buffer, Small Signal Bandwidth at 0 dB and 6 dB Gain 15 5V 12 1V eIN = 300mV rms 9 6 100mV GAIN (dB) INPUT LEVEL (V rms) 1k 10033-008 VS = ±2.4V 10033-005 100µV 50µV –12 10mV 3 0 –3 −3dB BW –6 1mV –9 50µV 50 100 1k 10k 100k FREQUENCY (Hz) 1M 5M 10033-006 VS = ±15V 100µV Figure 6. RMS Core Frequency Response with VS = ±15 V (See Figure 20) Rev. 0 | Page 6 of 20 –15 100 1k 10k 100k FREQUENCY (Hz) 1M 5M 10033-009 –12 Figure 9. Input Buffer, Large Signal Bandwidth at 0 dB and 6 dB Gain AD8436 10 eIN = 3.5mV rms PW = 100µs ADDITIONAL ERROR (% OF READING) 12 9 3 0 –3 –6 –9 –15 100 1k 10k 1M 100k 5M FREQUENCY (Hz) Figure 10. Output Buffer, Small Signal Bandwidth CAVG = 10µF −5 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 4 6 CREST FACTOR RATIO 8 10 2 4 6 8 10 12 14 SUPPLY VOLTAGE (±V) 16 18 20 0.50 0.25 0 −0.25 −0.50 −0.75 −1.00 –50 10033-011 0 0.75 –25 0 50 25 TEMPERATURE (°C) 75 100 125 Figure 14. Additional Conversion Error vs. Temperature Figure 11. Additional Error vs. Supply Voltage 2.5 1.6 2.0 SUPPLY CURRENT (mA) 2.0 1.2 0.8 VS = ±15V 1.5 VS = ±5V VS = ±2.4V 1.0 0.5 0.4 0 2 4 12 6 8 10 SUPPLY VOLTAGE (±V) 14 16 18 Figure 12. Core Input Voltage for 1% Error vs. Supply Voltage 0 10033-012 INPUT LEVEL (V rms) 2 10033-014 ADDITIONAL ERROR (% OF READING) 0.3 0 0 1.00 CAVG = 10µF 8 SAMPLES 0.4 NORMALIZED ERROR (%) 0 Figure 13. Crest Factor Error vs. Crest Factor for CAVG and CAVG and CCF Capacitor Combinations 0.5 –0.5 CAVG = 10µF CCF = 0.1µF −10 10033-010 –12 5 0 0.5 1.0 1.5 INPUT VOLTAGE (V rms) 2.0 10033-015 GAIN (dB) 6 10033-013 15 Figure 15. RMS Core Supply Current vs. Input for VS = ±2.4 V, ±5 V, and ±15 V Rev. 0 | Page 7 of 20 90 250 80 200 70 150 INPUT OFFSET VOLTAGE (µV) 60 50 40 30 20 10 100 50 0 −50 −100 −150 −200 −10 −50 −25 0 25 50 TEMPERATURE (°C) 75 100 125 10033-016 0 Figure 16. FET Input Buffer Bias Current vs. Temperature −250 −50 −25 0 25 50 TEMPERATURE (°C) 75 100 125 10033-019 BIAS CURRENT (pA) AD8436 Figure 18. Output Buffer VOS vs. Temperature 1000 CAVG = 10µF 1kHz 300mV rms BURST INPUT 0V 500 250 0 300mV DC OUT −250 0V −500 1kHz 1mV rms BURST INPUT 0V −750 −25 0 25 50 75 TEMPERATURE (°C) 100 125 1mV DC OUT 0V TIME (50ms/DIV) Figure 19. Transition Times with 1 kHz Burst at Two Input Levels (See Theory of Operation Section) Figure 17. Input Offset Voltage of FET Buffer vs. Temperature Rev. 0 | Page 8 of 20 10033-020 −1000 −50 10033-018 INPUT OFFSET VOLTAGE (µV) 750 AD8436 TEST CIRCUITS SIGNAL SOURCE 10µF CAV RMS +5V VCC 4.7µF 100kΩ RMS CORE IGND AC-IN MONITOR 100kΩ 16kΩ PRECISION DMM OUT OGND VEE 10033-021 –5V PRECISION DMM Figure 20. Core Response Test Circuit Using Dual Supplies SIGNAL SOURCE 10µF CAV RMS 4.80V VCC 4.7µF 100kΩ RMS CORE IGND AC-IN MONITOR 4.7µF 100kΩ 16kΩ PRECISION DMM OGND VEE 10033-022 OUT PRECISION DMM Figure 21. Core Response Test Circuit Using a Single Supply 10µF +5V FUNCTION GENERATOR CAV RMS VCC 4.7µF RMS CORE 100kΩ IGND AC-IN MONITOR 100kΩ 16kΩ PRECISION DMM OGND VEE –5V PRECISION DMM Figure 22. Crest Factor Test Circuit Rev. 0 | Page 9 of 20 10033-023 OUT AD8436 THEORY OF OPERATION OVERVIEW The rms value of an ac voltage waveform is equal to the dc voltage providing the same heating power to a load. A common measurement technique for ac waveforms is to rectify the signal in a straightforward way using a diode array of some sort, resulting in the average value. The average value of various waveforms (sine, square, and triangular, for example) varies widely; true rms is the only metric that achieves equivalency for all ac waveforms. See Table 5 for non-rms-responding circuit errors. RMS Core The core consists of a voltage-to-current converter (precision resistor), absolute value, and translinear sections. The translinear section exploits the properties of the bipolar transistor junctions for squaring and root extraction (see Figure 23). The external capacitor (CAVG) provides for averaging the product. Figure 19 shows that there is no effect of signal input on the transition times, as seen in the dc output. Although the rms core responds to input voltages, the conversion process is current sensitive. If the rms input is ac-coupled, as recommended, there is no output offset voltage, as reflected in Table 1. If the rms input is dc-coupled, the input offset voltage is reflected in the output and can be calibrated as with any fixed error. V+ + 5kΩ CAVG AC IN ABSOLUTE VALUE CIRCUIT V-TO-I The acronym “rms” means root-mean-square and reads as follows: “the square root of the average of the sum of the squares” of the peak values of any waveform. RMS is shown in the following equation: OUT V+ 16kΩ 10033-024 Why RMS? For additional information, select Section I of the 2nd edition of the Analog Devices RMS-to-DC Applications Guide. – The AD8436 is an implicit function rms-to-dc converter that renders a dc voltage dependent on the rms (heating value) of an ac voltage. In addition to the basic converter, this highly integrated functional circuit block includes two fully independent, optional amplifiers, a standalone FET input buffer amplifier and a precision dc output buffer amplifier (see Figure 1). The rms core includes a precision current responding full-wave rectifier and a log-antilog transistor array for current squaring and square rooting to implement the classic expression for rms (see Equation 1). For basic applications, the converter requires only an external capacitor, for averaging (see Figure 30). The optional on-board amplifiers offer utility and flexibility in a variety of applications without incurring additional circuit board footprint. For lowest power, the amplifier supply pins are left unconnected. V– Figure 23. RMS Core Block Diagram (1) Table 5. General AC Parameters Waveform Type (1 V p-p) Sine Square Triangle Noise Rectangular Pulse SCR DC = 50% DC = 25% Crest Factor 1.414 1.00 1.73 3 2 10 RMS Value 0.707 1.00 0.577 0.333 0.5 0.1 Reading of an Average Value Circuit Calibrated to an RMS Sine Wave 0.707 1.11 0.555 0.295 0.278 0.011 2 4.7 0.495 0.212 0.354 0.150 Rev. 0 | Page 10 of 20 Error (%) 0 11.0 −3.8 −11.4 −44 −89 −28 −30 AD8436 Referring to Figure 1, the input resistance of the AD8436 is 8 kΩ, and a voltage source input is preferred. The optional input buffer is a wideband JFET input amplifier that minimally loads non-0 Ω sources, such as a tapped resistor attenuator or voltage sensor. Although the input buffer consumes only 150 μA, the supply is pinned out and left unconnected to reduce power where needed. Optional matched 10 kΩ input and feedback resistors are provided on chip. Consult the Applications Information section to learn how these resistors can be used. The 3 dB bandwidth of the input buffer is 2.7 MHz at 10 mV rms input and approximately 1.5 MHz at 1 V rms. The amplifier gain and bandwidth are sufficient for applications requiring modest gain or response enhancement to a few hundred kilohertz (kHz), if desired. Configurations of the input buffer are discussed in the Applications Information section. Precision Output Buffer The precision output buffer is a bipolar input amplifier, laser trimmed to cancel input offset voltage errors. As with the input buffer, the supply current is very low (<50 μA, typically), and the power can be disconnected for power savings if the buffer is not needed. Be sure that the noninverting input is also disconnected from the core output (OUT) if the buffer supply pin is disconnected. Although the input current of the buffer is very low, a laser-trimmed 16 kΩ resistor, connected in series with the inverting input, offsets any self-bias offset voltage. Dynamic Range The AD8436 is a translinear rms-to-dc converter with exceptional dynamic range. Although accuracy varies slightly more at the extreme input values, the device still converts with no spurious noise or dropout. Figure 24 is a plot of the rms/dc transfer function near zero voltage. Unlike processor or other solutions, residual errors at very low input levels can be disregarded for most applications. 30 ∆Σ OR OTHER DIGITAL SOLUTIONS CANNOT WORK AT ZERO VOLTS 20 10 AD8436 SOLUTION 0 –30 Rev. 0 | Page 11 of 20 –20 –10 0 10 INPUT VOLTAGE (mV DC) Figure 24. DC Transfer Function near Zero 20 30 10033-025 FET Input Buffer The output buffer can be configured as a single or two-pole lowpass filter using circuits shown in the Applications Information section. Residual output ripple is reduced, without affecting the converted dc output. As the response approaches the low frequency end of the bandwidth, the ripple rises, dependent on the value of the averaging capacitor. Figure 26 shows the effects of four combinations of averaging and filter capacitors. Although the filter capacitor reduces the ripple for any given frequency, the dc error is unaffected. Of course, a larger value averaging capacitor can be selected, at a larger cost. The advantage of using a low-pass filter is that a small value of filter capacitor, in conjunction with the 16 kΩ output resistor, reduces ripple and permits a smaller averaging capacitor, effecting a cost savings. The recommended capacitor values for operation to 40 Hz are 10 μF for averaging and 3.3 μF for filter. OUTPUT VOLTAGE (mV DC) The 16 kΩ resistor in the output converts the output current to a dc voltage that can be connected to the output buffer or to the circuit that follows. The output appears as a voltage source in series with 16 kΩ. If a current output is desired, the resistor connection to ground is left open and the output current is applied to a subsequent circuit, such as the summing node of a current summing amplifier. Thus, the core has both current and voltage outputs, depending on the configuration. For a voltage output with 0 Ω source impedance, use the output buffer. The offset voltage of the buffer is 25 μV or 50 μV, depending on the grade. AD8436 APPLICATIONS INFORMATION Ripple is reduced by increasing the value of the averaging capacitor, or by postconversion filtering. Ripple reduction following conversion is far more efficient because the ripple average value has been converted to its rms value. Capacitor values for postconversion filtering are significantly less than the equivalent averaging capacitor value for the same level of ripple reduction. This approach requires only a single capacitor connected to the OUT pin (see Figure 25). The capacitor value correlates to the simple frequency relation of ½ π R-C, where R is fixed at 16 kΩ. USING THE AD8436 This section describes the power supply and feature options, as well as the function and selection of averaging and filter capacitor values. Averaging and filtering options are shown graphically and apply to all circuit configurations. Averaging Capacitor Considerations—RMS Accuracy Typical AD8436 applications require only a single external capacitor (CAVG) connected to the CAVG pin (see Figure 30). The function of the averaging capacitor is to compute the mean (that is, average value) of the sum of the squares. Averaging (that is, integration) follows the absolute value circuit, where the polarity of negative input current components is reversed (rectified) prior to squaring. The mean value is the average value of the squared input voltage over several input waveform periods. The rms error is directly affected by the number of periods averaged, as is the resultant peak-to-peak ripple. DC OUTPUT 9 16kΩ CLPF 8 10033-026 OGND Figure 25. Simple One-Pole Post Conversion Filter As seen in Figure 26, CAVG alone determines the rms error, and CLPF serves purely to reduce ripple. Figure 26 shows a constant rms error for CLPF values of 0.33 μF and 3.3 μF; only the ripple is affected. 1 CAVG = 10µF CLPF = 0.33µF OR 3.3µF 0 –1 –2 –3 –4 –5 –6 CAVG = 1µF CLPF = 0.33µF OR 3.3µF –7 Post Conversion Ripple Reduction Filter –8 Input rectification included in the AD8436 introduces a residual ripple component that is dependent on the value of CAVG and twice the input signal frequency. For sampling applications such as a high resolution ADC, the ripple component may cause one or more LSBs to cycle, and low value display numerals to flash. –9 –10 10 100 FREQUENCY (Hz) 1k Figure 26. RMS Error vs. Frequency for Two Values of CAVG and CLPF (Compare the effects of CAVG and CLPF, and note that CLPF does not affect rms error result.) 0 22µF 47µF –0.5 –1.0 4.7µF 0.47µF CAVG = 0.22µF 2.2µF –1.5 –2.0 10 1µF 100 FREQUENCY (Hz) Figure 27. Conversion Error vs. Frequency for Various Values of CAVG Rev. 0 | Page 12 of 20 1k 10033-028 CONVERSION ERROR (%) 10µF 10033-027 RMS ERROR (%) The result of the conversion process is a dc component and a ripple component whose frequency is twice that of the input. The rms conversion accuracy depends on the value of CAVG, so the value selected need only be large enough to average enough periods at the lowest frequency of interest to yield the required rms accuracy. Figure 27 is a plot of rms error vs. frequency for various averaging capacitor values. For Figure 27, the additional error was 0.001% at 40 Hz using a 10 μF metalized polyester capacitor. Larger values yield diminished returns because the settling time increases with negligible improvement in rms accuracy. To use Figure 27, determine the minimum operating frequency and accuracy of the application and then find the suggested capacitor value on the chart. For example, for –0.5% rms at 100 Hz, the capacitor value is 1 μF. OUT CORE AD8436 For simplicity, Figure 28 shows ripple vs. frequency for four combinations of CAVG and CLPF The signal source sees the input 8 kΩ voltage-to-current conversion resistor at Pin 2 (RMS); thus, the ideal source impedance is a voltage source (0 Ω source impedance). If a non-zero signal source impedance cannot be avoided, be sure to account for any series connected voltage drop. An input coupling capacitor must be used to realize the near-zero output offset voltage feature of the AD8436. Select a coupling capacitor value that is appropriate for the lowest expected operating frequency of interest. As a rule of thumb, the input coupling capacitor can be the same as or half the value of the averaging capacitor because the time constants are similar. For a 10 μF averaging capacitor, a 4.7 μF or 10 μF tantalum capacitor is a good choice (see Figure 30). AC INPUT = 300mV rms CAVG = 1µF, CLPF = 0.33µF CAVG = 1µF, CLPF = 3.3µF CAVG = 10µF, CLPF = 0.33µF CAVG = 10µF, CLPF = 3.3µF 0.1 0.01 0.0001 10 100 INPUT FREQUENCY (Hz) 1k CAVG 10033-029 0.001 Figure 28. Residual Ripple Voltage for Various Filter Configurations Figure 29 shows the effects of averaging and post-rms filter capacitors on transition and settling times using a 10-cycle, 50 Hz, 1 second period burst signal input to demonstrate timedomain behavior. In this instance, the averaging capacitor value was 10 μF, yielding a ripple value of 6 mV rms. A postconversion capacitor (CLPF) of .068 μF reduced the ripple to 1 mV rms. An averaging capacitor value of 82 μF reduced the ripple to 1 mV but extended the transition time (and cost) significantly. +5V 10µF 4.7µF OR 10µF 19 17 CAVG VCC RMS OUT 9 AD8436 2 IGND 11 VEE OGND 10 8 10033-031 RIPPLE ERROR (V p-p) 1 –5V Figure 30. Basic Applications Circuit Using a Capacitor for High Crest Factor Applications The AD8436 contains a unique crest factor feature. Crest factor is often overlooked when considering the requirements of rmsto-dc converters, but it is very important when working with signals with spikes or high peaks. The crest factor is defined as the ratio of peak voltage to rms. See Table 5 for crest factors for some common waveforms. INPUT 50Hz 10 CYCLE BURST 400mV/DIV CAVG = 10µF FOR BOTH PLOTS, BUT RED PLOT HAS NO LOW-PASS FILTER, GREEN PLOT HAS CLPF = 68nF 100mV/DIV CAVG +5V 10µF CCF CAVG = 82µF 0.1µF 19 CAVG CCF 11 Although tolerant of most capacitor styles, rms conversion accuracy can be affected by the type of capacitor that is selected. Capacitors with low dc leakage yield best all around performance, and many sources are available. Metalized polyester or similar film styles are best, as long as the temperature range is appropriate. For practical applications such as the rms-to-dc function in DMMs or power monitoring circuits, surface mount tantalums are the best over-all choice. Basic Core Connections Many applications require only a single external capacitor for averaging. A 10 μF capacitor is more than adequate for acceptable rms errors at line frequencies and below. OUT 9 RMS IGND Capacitor Construction 17 VCC AD8436 2 Figure 29. Effects of Various Filter Options on Transition Times 18 VEE OGND 10 –5V 8 10033-032 10033-030 TIME (100ms/DIV) 4.7µF OR 10µF Figure 31. Connection for Additional Crest Factor Performance Crest factor performance is mostly applicable for unexpected waveforms such as switching transients in switchmode power supplies. In such applications, most of the energy is in these peaks and can be destructive to the circuitry involved, although the average ac value can be quite low. Figure 13 shows the effects of an additional crest factor capacitor of 0.1 μF and an averaging capacitor of 10 μF. The larger capacitor serves to average the energy over long spaces between pulses, while the CCF capacitor charges and holds the energy within the relatively narrow pulse. Rev. 0 | Page 13 of 20 AD8436 The on-chip FET input buffer is an uncommitted FET input op amp used for driving the 8 kΩ I-to-V input resistor of the rms core. Pin 3, Pin 4, and Pin 5 are the I/O, Pin 6 is an optional connection for gain in the input buffer, and and Pin 16 connects power to the buffer (see Figure 3 and Table 4 for location and description). Connecting Pin 16 to the positive rail is the only power connection required because the negative rail is internally connected. Because the input stage is a FET and the input impedance must be very high to prevent loading of the source, a large value (10 MΩ) resistor must be connected from midsupply at Pin 11 (IGND) to Pin 5 (IBUFIN+) to prevent the input gate from floating high. For unity gain, connect Pin 3 (IBUFOUT) to Pin 4 (IBUFIN−). For a gain of 2×, connect Pin 6 (IBUFGN) to ground. See Figure 8 and Figure 9 for large and small signal responses at the two built-in gain options. The offset voltage of the input buffer is ≤500 μV, depending on grade. A capacitor connected between the Buffer Output Pin 3 (IBUFOUT) and Pin 2 (RMS) is recommended so that the input buffer offset voltage does not contribute to the overall error. Select the capacitor value for least minimum error at the lowest operating frequency. Figure 32 is a schematic showing internal components and pin connections. The bandwidth diminishes at the typical rate of a decade per 20 dB of gain, and the output voltage range is constrained. The small signal response, as shown in Figure 8, serves as a guide. As an example, suppose one wanted to detect small input signals at power line frequencies? An external 10 Ω resistor connected from Pin 4 to ground sets the gain to 101 and the 3 dB bandwidth to ~30 kHz, which is more than adequate for amplifying power line frequencies. Using the Output Buffer The AD8436 output is a precision op amp that is optimized for dc operation. Figure 33 shows a block diagram of the basic amplifier and I/O pins. The amplifier is intended for noninverting operation only; note that the 16 kΩ resistor, in series with the inverting input of the amplifier, is used to balance the bias current of the noninverting amplifier. As with the input FET buffer, the amplifier positive supply is pinned out separately for power sensitive applications. In normal circumstances, the buffers are connected to the same supply as the core. Figure 34 shows the signal connections to the output buffer. Note that the input offset voltage contribution by the bias currents are balanced by equal value series resistors, resulting in near zero offset voltage. OUTPUT BUFFER OBUFIN+ + OBUFOUT 16kΩ OBUFIN– 10033-034 Using the FET Input Buffer – 16 2 RMS Figure 33. Output Buffer Block Diagram IBUFV+ 10µF 4 5 IBUFIN– – IBUFIN+ + OUT CORE 10kΩ 16kΩ 10MΩ 10pF IGND OGND 12 13 OBUFIN+ OBUFOUT + 16kΩ 14 – OBUFIN– 8 10033-035 11 IBIAS 9 6 IBUFGN 10033-033 10kΩ Figure 34. Basic Output Buffer Connections Figure 32. Connecting the FET Input Buffer Capacitor coupling at the input and output of the FET buffer is recommended to avoid transferring the buffer offset voltage to the output. Although the FET input impedance is extremely high, the 10 MΩ centering resistor connected to IGND must be taken into account when selecting an input capacitor value. This is simply an impedance calculation using the lowest desired frequency, and finding a capacitor value based on the least attenuation desired. Because the 10 kΩ resistors are closely matched and trimmed to a high tolerance, the input buffer gain can be increased to several hundred with an external resistor connected to Pin 4 (IBUFIN−). For applications requiring ripple suppression in addition to the single-pole output filter described previously, the output buffer is configurable as a two-pole Sallen-Key filter using two external resistors and two capacitors. At just over 100 kHz, the amplifier has enough bandwidth to function as an active filter for low frequencies such as power line ripple. For a modest savings in cost and complexity, the external 16 kΩ feedback resistor can be omitted, resulting in slightly higher VOS (80 μV). 2C OUT CORE 16kΩ OGND 9 16kΩ 12 C 13 OBUFIN+ 16kΩ + – OBUFIN– 14 OBUFOUT 8 16kΩ Figure 35. Output Buffer Amplifier Configured as a Two-Pole, Sallen-Key Low-Pass Filter Rev. 0 | Page 14 of 20 10033-036 0.47µF IBUFOUT IBIAS 3 AD8436 10µF 9 13 16kΩ OGND 12 32.4kΩ 8 OBUFIN– OBUFIN+ – OBUFOUT 0.47µF 3 IBUFOUT 4 IBUFIN– 5 IBUFIN+ 10MΩ If a current output is required, connect the current output, OUT (Pin 9), to the destination load. To maximize precision, provide a means for external calibration to replace the internal trimmed resistor, which is bypassed. This configuration is useful for convenient summing of the AD8436 result with another voltage, or for polarity inversion. C AVG CCF 19 RMS 2 18 DIRECTION OF DC OUTPUT CURRENT 8kΩ CORE OUT 9 AD8436 RMS Figure 36. Inverting Output Configuration Current Output Option 17 VCC 2 4.7µF 14 + 19 CAV IGND 11 OGND VEE 8 10 Recommended Application Figure 39 shows a circuit for a typical application for frequencies as low as power line, and above. The recommended averaging, crest factor and LPF capacitor values are 10 μF, 0.1 μF and 3.3 μF. Refer to the Using the Output Buffer section if additional low-pass filtering is required. VCC 2kΩ 15kΩ (OPTIONAL) 10µF + 20 0.1µF 19 18 SUM CAVG + 16kΩ INVERTED DC VOLTAGE OUTPUT 2 8 DO NOT CONNECT FOR CURRENT OUTPUT 17 CCF 10µF Figure 37. Connections for Current Output Showing Voltage Inversion 4 Single Supply Connections for single supply operation are shown in Figure 38 and are similar to those for dual power supply when the device is ac-coupled. The analog inputs are all biased to half the supply voltage, but the output remains referred to ground because the output of the AD8436 is a current source. An additional bypass connection is required at Pin 11 (IGND) to suppress ambient noise. 3 0.47µF AC IN 10MΩ 5 16 VCC IBUFV+ 1 DNC 10033-038 OGND 4.7µF Figure 38. Connections for Single Supply Operation – 16kΩ OUT 9 OBUFV+ AD8436 OBUFOUT RMS IBUFOUT OBUFIN– IBUFIN– OBUFIN+ IBUFIN+ IGND IBUFGN DNC OGND OUT 6 7 8 9 14 DC OUT 13 12 11 VEE 10 VEE 3.3µF Figure 39. Typical Application Circuit Rev. 0 | Page 15 of 20 15 10033-040 CORE 16kΩ 10033-037 OUT 10033-039 Configure the output buffer as shown in Figure 36 to invert the dc output. AD8436 The AD8436-EVALZ provides a platform to evaluate AD8436 performance. The board is fully assembled, tested and ready to use after the power and signal sources are connected. Figure 45 is a photograph of the board. Signal connections are located on the primary and secondary sides, with power and ground on the inner layers. Figure 40, Figure 41, Figure 42, Figure 43, and Figure 44 illustrate the various design details of the board, including a basic layout and copper patterns. These figures are useful for reference for application designs. 10033-042 AD8436 EVALUATION BOARD Figure 41. AD8436-EVALZ Primary Side Copper A Word About Using the AD8436 Evaluation Board The AD8436-EVALZ offers many options, without sacrificing simplicity. The board is tested and shipped with a 10 μF averaging capacitor (CAVG), 3.3 μF low-pass filter capacitor (C8) and a 0.1 μF (COPT) capacitor to optimize crest factor performance. To evaluate minimum cost applications, remove C8 and COPT. 10033-043 The functions of the five switches are listed in Table 6. Table 6. IBUF_VCC OBUF_VCC Function Selects core or input for the input signal Selects ac or dc coupling to the core Selects the output buffer or the core output at the DCOUT BNC. Enable or disables the input buffer Enable or disables the output buffer All the I/Os are provided with test points for easy monitoring with test equipment. The input buffer gain default is unity; for 2× gain, install a 0603 0 Ω resistor at Position R5. For higher IBUF gains, remove the 0 Ω resistor at Position RFBH (there is an internal 10 kΩ resistor from the OBUF_OUT to IBUFIN−) and install a smaller value resistor in Position RFBL. A 100 Ω resistor establishes a gain of 100×. Figure 42. AD8436-EVALZ Secondary Side Copper 10033-044 Switch CORE_BUFFER INCOUP SDCOUT Figure 43. AD8436-EVALZ Power Plane 10033-045 Single supply operation requires removal of Resistor R6 and installing a 0.1 μF capacitor in the same position for noise decoupling. 10033-041 Figure 44. AD8436-EVALZ Ground Plane Figure 40. Assembly of the AD8436-EVALZ Rev. 0 | Page 16 of 20 10033-046 AD8436 Figure 45. Photograph of the AD8436-EVALZ +V (RED) CAVE 10µF GND1 GND2 GND3 GND4 GND5 GND6 + TSUM TCAVE TOPT 19 18 20 INCOUP DC CORE BUF CIN 10µF RFBH 0Ω C5 0.47µF RFBL DNI DIS IBUF_VCC 16 IBUF TOBUFV+ EN V+ OBUF 15 V+ C1 10µF + 50V –40°C TO +125°C VCC DIS OBUF_VCC TRMSIN 2 TIBUFOUT TACIN VCC 1 DNC CORE_BUF AC IN 17 DNC CAVG C2 + 10µF 50V –40°C TO +125°C VEE 3 TIBFIN– 4 TIBFIN+ 5 TOBFOUT OBUF 14 OUT RMS AD8436 IBUFOUT OBUF IN– IBUFIN+ IBUFGN 6 TBUFGN IGND DNC 7 OGND OUT 8 9 TOGND R5 0Ω C6 0.47µF TDCOUT BUF DC OUT TOBUFIN+ OBUF 12 IN+ IBUFIN– R1 1MΩ R8 TOBUFIN– 0Ω 13 R2 0Ω TIOUT 11 TIGND VEE R7 0Ω 10 C3 0.1µF R6 0Ω CORE C7 0.22µF SDCOUT R3 4.99kΩ R4 4.99kΩ VEE C38 3.3µF *COMPONENTS IN GRAY ARE NOT FACTORY INSTALLED. Figure 46. Evaluation Board Schematic Rev. 0 | Page 17 of 20 10033-047 AC SUM C4 TIBUFV+ 0.1µF EN COPT 0.1µF –V (GRN) AD8436 OUTLINE DIMENSIONS PIN 1 INDICATOR 4.10 4.00 SQ 3.90 0.30 0.25 0.20 0.50 BSC 20 16 15 1 EXPOSED PAD 5 PIN 1 INDICATOR 2.65 2.50 SQ 2.35 11 0.80 0.75 0.70 0.50 0.40 0.30 10 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 6 BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WGGD. 061609-B TOP VIEW Figure 47. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] (CP-20-10) Dimensions shown in inches ORDERING GUIDE Model 1 AD8436ACPZ-R7 AD8436ACPZ-RL AD8436ACPZ-WP AD8436JCPZ-R7 AD8436JCPZ-RL AD8436JCPZ-WP AD8436-EVALZ 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C 0°C to +70°C 0°C to +70°C 0°C to +70°C Package Description 20-Lead Lead Frame Chip Scale [LFCSP_WQ] 20-Lead Lead Frame Chip Scale [LFCSP_WQ] 20-Lead Lead Frame Chip Scale [LFCSP_WQ] 20-Lead Lead Frame Chip Scale [LFCSP_WQ] 20-Lead Lead Frame Chip Scale [LFCSP_WQ] 20-Lead Lead Frame Chip Scale [LFCSP_WQ] Evaluation Board Z = RoHS Compliant Part. Rev. 0 | Page 18 of 20 Package Option CP-20-10 CP-20-10 CP-20-10 CP-20-10 CP-20-10 CP-20-10 AD8436 NOTES Rev. 0 | Page 19 of 20 AD8436 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 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