TOSHIBA TMP93CS45

TOSHIBA Original CMOS 16-Bit Microcontroller
TLCS-900/L Series
TMP93CS44/S45
Semiconductor Company
Preface
Thank you very much for making use of Toshiba microcomputer LSIs.
Before use this LSI, refer the section, “Points of Note and Restrictions”.
Especially, take care below cautions.
**CAUTION**
How to release the HALT mode
Usually, interrupts can release all halts status. However, the interrupts = ( NMI ,
INT0), which can release the HALT mode may not be able to do so if they are
input during the period CPU is shifting to the HALT mode (for about 3 clocks of
fFPH) with IDLE1 or STOP mode (RUN and IDLE2 are not applicable to this case).
(In this case, an interrupt request is kept on hold internally.)
If another interrupt is generated after it has shifted to HALT mode completely,
halt status can be released without difficultly. The priority of this interrupt is
compare with that of the interrupt kept on hold internally, and the interrupt with
higher priority is handled first followed by the other interrupt.
TMP93CS44/S45
Low Voltage/Low Power
CMOS 16-bit Microcontrollers
TMP93CS44F/TMP93CS45F
1.
Outline and Device Characteristics
The TMP93CS44/TMP93CS45 are high-speed, advanced 16-bit microcontrollers developed for
controlling medium to large-scale equipment. The TMP93CS45 does not have a ROM, the
TMP93CS44 has a built-in ROM. Otherwise, the devices function in the same way.
The TMP93CS44F/TMP93CS45F are housed in 80-pin flat package (P-LQFP80-1212-0.50E).
The device characteristics are as follows:
(1) Original 16-bit CPU (900/L CPU)
•
TLCS-90 instruction mnemonic upward compatible
•
16-Mbyte linear address space
•
General-purpose registers and register bank system
•
16-bit multiplication/division and bit transfer/arithmetic instructions
•
Micro DMA: 4 channels (1.6 µs per 2 bytes at 20 MHz)
(2) Minimum instruction execution time: 200 ns at 20 MHz
(3) Internal RAM: 2 Kbytes
Internal ROM: TMP93CS44
TMP93CS45
64-Kbyte ROM
None
(4) External memory expansion
•
Can be expanded up to 16 Mbytes (for both programs and data)
•
AM8/ ΑΜ16 pin (Select the external data bus width)
•
Can mix 8- and 16-bit external data buses (Dynamic bus sizing)
(5) 8-bit timer: 4 channels
(6) 16-bit timer: 2 channels
030619EBP1
• The information contained herein is subject to change without notice.
• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of TOSHIBA or others.
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general
can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid
situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to
property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most
recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for
Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..
• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal
equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are
neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or
failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made
at the customer’s own risk.
• The products described in this document are subject to the foreign exchange and foreign trade laws.
• TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law
and regulations.
• For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality
and Reliability Assurance/Handling Precautions.
Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use
these components in an I2C system, provided that the system conforms to the I2C Standard
Specification as defined by Philips.
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TMP93CS44/S45
(7) Serial interface: 2 channels
(8) Serial bus interface: 1 channel
•
I2C bus mode
•
Clocked-synchronous 8-bit serial interface mode
(9) 10-bit AD converter: 8 channels
(10) High current output: 8 ports
(11) Watchdog timer
(12) Bus width/wait controller: 3 blocks
(13) Interrupt functions: 33
•
9 CPU interrupts
•
17 internal interrupts
•
7 external interrupts
7-level priority can be set (except NMI and INTWD)
(14) I/O ports
TMP93CS44
62 pins
TMP93CS45
44 pins
(15) Standby function: 4 HALT modes (RUN, IDLE2, IDLE1, STOP)
(16) Clock gear function
•
Dual clock operation
•
High-frequency clock can be changed from fc to fc/16
(17) Wide range of operating voltage
•
VCC = 2.7 to 5.5 V
(18) Package
Type Number
TMP93CS44F
TMP93CS45F
Package
P-LQFP80-1212-0.50E
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TMP93CS44/S45
AN0 to AN2 (P50 to P52)
AN3/ ADTRG (P53)
AN4 to AN7 (P54 to P57)
AVCC
AVSS
VREFH
VREFL
10-bit 8-ch
AD converter
TXD0 (P60)
RXD0 (P61)
SCLK0/ CTS0 (P62)
Serial I/O
(Channel 0)
TXD1 (P63)
RXD1 (P64)
SCLK1/ CTS1 (P65)
Serial I/O
(Channel 1)
XWA
XBC
XDE
XHL
XIX
XIY
XIZ
XSP
W A
B C
D E
H L
IX
IY
IZ
SP
32-bits
F
SR
INT1/TI0 (P40)
Highfrequency
OSC
Lowfrequency
OSC
XT1 (P66)
XT2 (P67)
AM8/ AM16
EA
RESET
ALE
TEST1/TEST2
Interrupt
controller
Port 7
INT0 (P35)
NMI
Watchdog
timer
2-Kbyte RAM
8-bit timer
(Timer 0)
Port 0
AD0 to AD7*
(P00 to P07)
Port 1
AD8 to AD15/A8 to A15*
(P10 to P17)
Port 2
A0 to A7/A16 to A23*
(P20 to P27)
8-bit timer
(Timer 1)
8-bit timer
(Timer 2)
TO3 (P41)
X1
X2
CLK
PC
WAIT (P70)
P71
P72
P73
P74
P75
P76
P77
VCC [2]
VSS [2]
900/L CPU
Port 3
8-bit timer
(Timer 3)
64-Kbyte ROM
INT4/TI4 (P42)
INT5/TI5 (P43)
TO4 (P44)
16-bit timer
(Timer 4)
INT6/TI6 (P45)
INT7/TI7 (P46)
TO6 (P47)
16-bit timer
(Timer 5)
Not included in the
TMP93CS45
RD (P30) *
WR (P31) *
HWR /SCK (P32)
Wait
controller
(3 blocks)
Serial bus
interface
controller
SO/SDA (P33)
SI/SCL (P34)
Note: The pin state after reset.
Product
AM8/ AM16
TMP93CS44
“H” level
Item in parentheses ( ) are the initial setting after reset.
“H” level
Except for “*” pins, item in parentheses ( ) are the initial
setting after reset.
“L” level
Except for “*” pins, item in parentheses ( ) are the initial
setting after reset. However, port 1 is initialized item of out
parentheses.
TMP93CS45
Pin Function after Reset
Figure 1.1 TMP93CS44/TMP93CS45 Block Diagram
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TMP93CS44/S45
2.
Pin Assignment and Functions
The assignment of input and output pins for the TMP93CS44/TMP93CS45, their names and
functions are described below.
Pin Assignment
41
45
50
40
61
65
35
TMP93CS44F/45F
QFP80
70
30
Top view
75
25
P07 (AD7)
P06 (AD6)
P05 (AD5)
P04 (AD4)
P03 (AD3)
P02 (AD2)
P01 (AD1)
P00 (AD0)
ALE
VSS
VCC
TEST2
TEST1
P67 (XT2)
P66 (XT1)
RESET
EA
21
X2
X1
AM8/ AM16
20
15
5
NMI
(TXD0) P60
(RXD0) P61
(SCLK0/CTS0) P62
(TXD1) P63
(RXD1) P64
(SCLK1/CTS1) P65
(WAIT) P70
P71
VSS
P72
P73
P74
P75
P76
P77
CLK
10
80
1
(SO/SDA) P33
(SI/SCL) P34
(INT0) P35
(TI0/INT1) P40
(TO3) P41
(TI4/INT4) P42
(TI5/INT5) P43
(TO4) P44
(TI6/INT6) P45
(TI7/INT7) P46
(TO6) P47
VREFH
VREFL
AVSS
AVCC
(AN0) P50
(AN1) P51
(AN2) P52
(AN3/ ADTRG ) P53
(AN4) P54
55
60
P32 (HWR /SCK)
P31(WR)
P30 (RD)
VCC
P27 (A23/A7)
P26 (A22/A6)
P25 (A21/A5)
P24 (A20/A4)
P23 (A19/A3)
P22 (A18/A2)
P21 (A17/A1)
P20 (A16/A0)
P17 (AD15/A15)
P16 (AD14/A14)
P15 (AD13/A13)
P14 (AD12/A12)
P13 (AD11/A11)
P12 (AD10/A10)
P11 (AD9/A9)
P10 (AD8/A8)
Figure 2.1.1 shows pin assignment of the TMP93CS44F/TMP93CS45F.
(AN5) P55
(AN6) P56
(AN7) P57
2.1
Figure 2.1.1 Pin Assignment (P-LQFP80-1212-0.50E)
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TMP93CS44/S45
2.2
Pin Names and Functions
The names of input/output pins and their functions are described below.
Table 2.2.1 to Table 2.2.3 show “Pin Names and Functions”.
Table 2.2.1 Pin Names and Functions (1/3)
Pin Names
Number
of Pins
P00 to P07
AD0 to AD7
8
P10 to P17
AD8 to AD15
A8 to A15
8
P20 to P27
8
I/O Port 1: I/O port that allows selection of I/O on a bit basis
Output Address: Bits 8 to 15 for address bus
I/O Port 2: I/O port that allows selection of I/O on a bit basis
(with pull-up resistor)
Output Address: Bits 0 to 7 for address bus
Output Address: Bits 16 to 23 for address bus
1
Output Port 30: Output port
Output Read: Strobe signal for reading external memory
1
WR
P32
I/O Port 0: I/O port that allows selection of I/O on a bit basis
3 states Address/data (Upper): Bits 8 to 15 for address/data bus
RD
P31
Functions
3 states Address/data (Lower): Bits 0 to 7 for address/data bus
A0 to A7
A16 to A23
P30
I/O
Output Port 31: Output port
Output Write: Strobe signal for writing data on pins AD0 to AD7
1
I/O Port 32: I/O port (with pull-up resistor)
Output High write: Strobe signal for writing data on pins AD8 to AD15
HWR
SCK
I/O Mode clock SBI SIO mode clock
P33
SO
SDA
1
P34
SI
SCL
1
P35
INT0
1
P40
TI0
INT1
1
P41
TO3
1
P42
TI4
INT4
1
I/O Port 33: I/O port
Output Serial send data
I/O SBI I2C bus mode channel data
I/O Port 34: I/O port
Input Serial receive data
I/O SBI I2C bus mode clock
I/O Port 35: I/O port
Input Interrupt request pin 0: Interrupt request pin with programmable level/rising edge
I/O Port 40: I/O port
Input Timer input 0: Timer 0 input
Input Interrupt request pin 1: Interrupt request pin with rising edge
I/O Port 41: I/O port
Output Timer output 3: 8-bit timer 3 output
I/O Port 42: I/O port
Input Timer input 4: Timer 4 input
Input Interrupt request pin 4: Interrupt request pin with
programmable rising/falling edge
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TMP93CS44/S45
Table 2.2.2 Pin Names and Functions (2/3)
Number
Pin Names
of Pins
P43
TI5
INT5
1
P44
TO4
1
P45
TI6
INT6
1
P46
TI7
INT7
1
P47
TO6
1
P50 to P52,
P54 to P57
AN0 to AN2,
AN4 to AN7
7
P53
AN3
1
I/O
Functions
I/O Port 43: I/O port
Input Timer input 5: Timer 4 input
Input Interrupt request pin 5: Interrupt request pin with rising edge
I/O Port 44: I/O port
Output Timer output 4: Timer 4 output pin
I/O Port 45: I/O port
Input Timer input 6: Timer 5 input
Input Interrupt request pin 6: Interrupt request pin with
programmable rising/falling edge
I/O Port 46: I/O port
Input Timer input 7: Timer 5 input
Input
Interrupt request pin 7: Interrupt request pin with rising edge
I/O Port 47: I/O port
Output Timer output 6: Timer 5 output pin
Input Port 50 to Port 52, Port 54 to Port 57: Input port
Input Analog input: Analog signal input for AD converter
Input Port53: Input port
Input Analog input: Analog signal input for AD converter
ADTRG
Input AD converter external start trigger input
P60
TXD0
1
P61
RXD0
1
P62
SCLK0
1
I/O Port 60: I/O port (with pull-up resistor)
Output Serial send data 0
I/O Port 61: I/O port (with pull-up resistor)
Input Serial receive data 0
I/O Port 62: I/O port (with pull-up resistor)
I/O Serial clock I/O 0
CTS0
Input Serial data send enable 0 (Clear to send)
P63
TXD1
1
P64
RXD1
1
P65
SCLK1
1
I/O Port 63: I/O port (with pull-up resistor)
Output Serial send data 1
I/O Port 64: I/O port (with pull-up resistor)
Input Serial receive data 1
I/O Port 65: I/O port (with pull-up resistor)
I/O Serial clock I/O 1
CTS1
Input Serial data send enable 1 (Clear to send)
P66
XT1
1
P67
XT2
1
I/O Port 66: I/O port (Open-drain output)
Input Low-frequency oscillator connecting pin
I/O Port 67: I/O port (Open-drain output)
Output Low-frequency oscillator connecting pin
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TMP93CS44/S45
Table 2.2.3 Pin Names and Functions (3/3)
Pin Names
P70
Number
of Pins
1
I/O
Functions
I/O Port 70: I/O port (High current output available)
Input WAIT: Pin used to request CPU bus wait (It is active in (1 + N) WAIT mode. Set by the
bus-width/wait control register)
WAIT
P71 to P77
7
AVCC
1
Input Power supply pin for AD converter
I/O Port 71 to Port 77: I/O port (High current output available)
AVSS
1
Input GND pin for AD converter (0 V)
VREFH
1
Input Pin for high-level reference voltage input to AD converter
VREFL
1
Input Pin for low-level reference voltage input to AD converter
NMI
1
Input Non-maskable interrupt request pin: Interrupt request pin with falling edge. Can also be
operated at falling and rising edges by program.
X1
1
Input High-frequency oscillator connecting pin
X2
1
Output High-frequency oscillator connecting pin
RESET
1
Input Reset: Initializes TMP93CS44/S45. (with pull-up resistor)
ALE
1
Output Address latch enable. Can be disabled for reducing noise.
CLK
1
Output Clock output: Outputs “fSYS ÷ 2” clock.
Pulled-up during reset.
Can be disabled for reducing noise.
EA
1
Input External access:
“0” should be inputted with TMP93CS45.
“1” should be inputted with TMP93CS44.
AM8/ AM16
1
Input Address mode: Selects external data bus width.
(The case of TMP93CS44)
“1” should be inputted. The data bus width for external access is set by chip
select/WAIT control register, port 1 control register.
(The case of TMP93CS45)
“0” should be inputted with fixed 16-bit bus width or 16-bit bus interlarded with 8-bit
bus. “1” should be inputted with fixed 8-bit bus width.
VCC
2
Input Power supply pin (All VCC pins should be connected with GND (0 V).)
VSS
2
TEST1/TEST2
2
Note:
Input GND pin (0 V) (All VSS pins should be connected with GND (0 V).)
Output/Input TEST1 should be connected with TEST2 pin. Do not connect to any other pins.
Built-in pull-up resistors can be released from the pins other than the RESET pin by software.
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TMP93CS44/S45
3.
Operation
This section describes the functions and basic operational blocks of TMP93CS44/S45 devices.
See the 7. “Points of Note and Restriction” for the using notice and restrictions for each block.
3.1
CPU
TMP93CS44/S45 devices have a built-in high-performance 16-bit CPU (900/L CPU). (For
CPU operation, see TLCS-900/L CPU in the previous section.)
This section describes CPU functions unique to the TMP93CS44/S45 that are not described in
the previous section.
3.1.1
Reset
When resetting the TMP93CS44/S45 microcontroller, ensure that the power supply
voltage is within the operating voltage range, and that the internal high-frequency
oscillator has stabilized. Then set the RESET input to low level at least for 10 system
clocks (16 µs at 20 MHz). Thus, when turn on the switch, be set to the power supply voltage
is within the operating voltage range, and that the internal high-frequency oscillator has
stabilized. Then hold the RESET input to low level at least for 10 system clocks.
Clock gear is initialized 1/16 mode by reset operation. It means that the system clock
mode fSYS is set to fc/32 (= fc/16 × 1/2).
When reset is accepted, the CPU sets as follows:
•
Program counter (PC) according to reset vector that is stored FFFF00H to FFFF02H.
PC<7:0>
← Stored data in location FFFF00H
PC<15:8>
← Stored data in location FFFF01H
PC<23:16>
← Stored data in location FFFF02H
•
Stack pointer (XSP) for system mode to 100H.
•
Bits IFF2 to IFF0 of status register to 111. (Sets mask register to interrupt level 7.)
•
MAX bit of status register to 1. (Sets to maximum mode.)
•
Bits RFP2 to RFP0 of status register to 000. (Sets register banks to 0.)
When reset is released, instruction execution starts from PC (Reset vector). CPU internal
registers other than the above are not changed.
When reset is accepted, processing for built-in I/Os, ports, and other pins is as follows.
•
Initializes built-in I/O registers as per specifications.
•
Sets port pins (including pins also used as built-in I/Os) to general-purpose
input/output port mode.
•
Pulls up the CLK pin to “H” level.
•
Sets the ALE pin to “L” level (the case of TMP93CS45), to High-impedance (High-Z)
(the case of TMP93CS44).
Note 1: By resetting, register in the CPU except program counter (PC), status register (SR) and
stack pointer (XSP) and the data in internal RAM are not changed.
Note 2: The CLK pin is pulled up to “H” level during reset. When the voltage is put down
externally, there is possible to cause malfunctions.
Figure 3.1.1 and Figure 3.1.2 show the reset timing chart of TMP93CS44 and
TMP93CS45.
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93CS44-9
P66, P67
P33 to P35, P40 to P47,
P50 to P57, P70 to P77
P20 to P27, P32,
P60 to P65
HWR
WR
AD0 to AD15
RD
AD0 to AD15
ALE
A16 to A23
RESET
CLK
X1
Data output
Internal pull up
High-Z
Address
Address
Address
Address
Sampling
(Output mode: Open-drain output)
(Input mode)
(Input mode)
(P32 input mode)
(P20 to P27 input mode)
Sampling
45 × 1 cycles omitted
Total of 220 × 1 cycles omitted
Write
Read
TMP93CS44/S45
Figure 3.1.1 TMP93CS44 Reset Timing Chart
2004-02-10
93CS44-10
P66, P67
P33 to P35, P40 to P47,
P50 to P57, P70 to P77
P20 to P27, P32,
P60 to P65
HWR
WR
AD0 to AD15
RD
AD0 to AD15
ALE
A16 to A23
RESET
CLK
X1
Date output
Internal pull up
High-Z
Address
Address
Address
Address
Sampling
(Output mode: Open-drain output)
(Input mode)
(Input mode)
(P32 input mode)
(P20 to P27 input mode)
Sampling
45 × 1 cycles omitted
Address
Data input
Total of 220 × 1 cycles omitted
Write
Read
TMP93CS44/S45
Figure 3.1.2 TMP93CS45 Reset Timing Chart
2004-02-10
TMP93CS44/S45
3.1.2
AM8/ AM16 pin
(1) TMP93CS44
Set this pin to “H”. After reset, the CPU accesses the internal ROM with 16-bit bus
width. The bus width when the CPU accesses an external area is set by bus width/wait
control registers and the registers of port 1, which are described in section 3.6.3. (The
value of this pin is ignored and the value set by register is active.)
(2) TMP93CS45
1.
With fixed 16-bit data bus external 16-bit data bus or 8-bit data bus is selectable
Set this pm to “L”. Port 1, AD8 to AD15 and A8 to A15 pins are fixed to AD8 to
AD15 functions. The values set in port 1 control register and port 1 function
register are invalid.
The external data bus width is set by the bus width/wait control register which
is described in section 3.6.3.
It is necessary to set the program memory to be accessed to 16-bit data bus after
reset.
2.
With fixed external 8-bit data bus
Set this pin to “H”. Port l, AD8 to AD15 and A8 to A15 pins are fixed to A8 to
A15 functions. The values set in port 1 control register and port 1 function register
are invalid.
The values of bit4 <B0BUS>, <B1BUS> and <B2BUS> in the bus width/wait
control register described in section 3.6.3 are invalid. The external 8-bit data bus
is fixed.
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TMP93CS44/S45
3.2
Memory Map
Figure 3.2.1 is a memory map of the TMP93CS44/S45.
000000H
000080H
Internal I/O
(128 bytes)
256-byte direct
area (n)
000100H
Internal RAM
(2 Kbytes)
000880H
64-Kbyte area
(nn)
External memory
010000H
16-Mbyte area
(r32)
(−r32)
(r32+)
(r32 + d8/16)
(r32 + r8/16)
(nnn)
FF0000H
64-Kbyte internal ROM
(TMP93CS44)
FFFF00H
FFFFFFH
External area
for TMP93CS45
Vector table (256 bytes)
(
= Internal area)
Figure 3.2.1 Memory Map
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TMP93CS44/S45
3.3
Dual Clock, Standby Function
Dual clock, standby control circuits consist of (1) System clock controller, (2) Prescaler clock
controller and (3) Standby controller.
The oscillator operating mode is classified to (a) Single clock mode (Only X1 and X2 pin), and
(b) Dual clock mode (X1, X2, XT1 and XT2 pin).
Figure 3.3.1 shows a transition figure. Figure 3.3.2 shows the block diagram. Figure 3.3.3
shows I/O registers. Table 3.3.1 shows the internal operation and system clock.
Reset
RUN mode
(Stops only CPU)
Interrupt
IDLE2 mode
Interrupt
(Stops CPU and AD)
Instruction
Instruction
Instruction
IDLE1 mode
Release reset
NORMAL mode
(fc/gear value/2)
Instruction
Interrupt
STOP mode
(Stops all circuits)
Interrupt
(Operates only osciIIator)
(a) Single clock mode transition figure
Reset
RUN mode
(Stops only CPU)
IDLE2 mode
(Stops CPU and AD)
IDLE1 mode
Release reset
Instruction
Interrupt
Instruction
Interrupt
Instruction
NORMAL mode
(fc/gear value/2)
Interrupt
(Operates only oscillator)
Instruction
RUN mode
(Stops only CPU)
IDLE2 mode
(Stops CPU and AD)
IDLE1 mode
(Operates only oscillator)
Instruction
Interrupt
STOP mode
(Stops all circuits)
Instruction
Interrupt
Instruction
Interrupt
Instruction
SLOW mode
Instruction
(fs/2)
Interrupt
(b) Dual clock mode transition figure
Figure 3.3.1 Transition Figure
The clock frequency input from X1, X2 pin is called fc and the clock frequency input from
XT1, XT2 pin is called fs. The clock frequency selected by SYSCR1<SYSCK> is called
system clock fFPH. The devided clock of fFPH is called system clock fSYS, and the 1 cycle of
fSYS, is called 1 state.
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TMP93CS44/S45
Table 3.3.1 Internal Operation and System Clock
Oscillator
Operating Mode High Frequency Low Frequency
(fc)
NORMAL
RUN
Oscillation
NORMAL
Dual
clock
SLOW
RUN
IDLE2
IDLE1
STOP
Reset
Reset
fc/32
Stop
Stop
IDLE1
RESET
System Clock
fSYS
Operate
IDLE2
STOP
Internal l/O
(fs)
RESET
Single
clock
CPU
Operate
Stop only AD
Stop
Stop
Stop
Oscillation
Reset
Programmable
Programmable
Operate
Oscillation
Oscillator being used as system
clock: Oscillation
Other oscillator: Programmable
Stop
Reset
93CS44-14
Stop
fc/32
Programmable
(fc/2, fc/4, fc/8, fc/16, fc/32)
Operate
Stop only AD
Stop
Stop
Programmable
(fc/2, fc/4, fc/8,
fc/16, fc/32)
fs/2
Programmable
(fc/2, fc/4, fc/8,
fc/16, fc/32, fs/2)
Stop
2004-02-10
93CS44-15
Lowfrequency
oscillator
X1
X2
Highfrequency
oscillator
WDMOD<HALTM1:0>
SYSCR0<XEN><RXEN>
XT1
XT2
fc
SYSCR0<XTEN><RXTEN>
fc
÷2
÷4
÷8
÷16
fc/2 fc/4 fc/8 fc/16
fs
fs
• Watchdog timer... fSYS
SYSCR0
<PRCK1:0>
Selector
SYSCR1<SYSCK>
SYSCR0<RSYSCK>
SYSCR1<GEAR2:0>
Selector
Selector
fFPH
fs
fc/16
• Warm up (Releasing STOP mode) ... fFPH
• Warm up (Changing clocks)... fc or fs
÷2
System
clock
fSYS
÷4
CPU
÷2
Internal I/O
ROM, RAM
9-bit prescaler
Run and
stop
TRUN
<PRRUN>
Watchdog timer/
warm-up timer
SYSCR0<WUEF>
CLK
8-bit timers 0, 1, 2 and 3
16-bit timers 4 and 5
Serial interfaces 0 and 1
TMP93CS44/S45
Figure 3.3.2 Block Diagram of Dual Clock, Standby Circuits
2004-02-10
TMP93CS44/S45
System Clock Control Register 0
SYSCR0
(006EH)
Bit symbol
7
6
5
4
3
2
1
0
XEN
XTEN
RXEN
RXTEN
RSYSCK
WUEF
PRCK1
PRCK0
1
0
1
0
0
0
Highfrequency
oscillator
(fc) after
released
STOP mode
Lowfrequency
oscillator
(fs) after
released
STOP mode
Read/Write
R/W
After reset
Function
Highfrequency
oscillator
(fc)
Lowfrequency
oscillator
(fs)
0: Stop
0: Stop
1: Oscillation 1: Oscillation
0
0
Select clock Warm-up
timer
after
released
(Write)
STOP mode
0: Don’t care
1: Start timer
0: fc
1: fs
Select prescaler clock
00: fFPH
01: fs
10: fc/16
11: (Reserved)
(Read)
0: End
warm up
0: Stop
0: Stop
1: Oscillation 1: Oscillation
1: Not end
warm up
System Clock Control Register 1
7
SYSCR1
(006FH)
6
5
4
Bit symbol
3
2
1
0
SYSCK
GEAR2
GEAR1
GEAR0
0
1
0
0
Read/Write
R/W
After reset
Function
Select
system
clock
0: fc
1: fs
Select gear value of high frequency (fc)
000: fc
001: fc/2
010: fc/4
011: fc/8
100: fc/16
101: (Reserved)
110: (Reserved)
111: (Reserved)
Clock Output Control Register
7
CKOCR
(006DH)
6
−
Bit symbol
Read/Write
After reset
4
3
2
−
1
0
ALEEN
R/W
CLKEN
R/W
0
Function
5
0/1 (Note 2)
0
Always write to “0”.
0/1 (Note 2)
ALE pin
CLK pin
output control
output control
0: High-Z
output
0: High-Z
output
1: ALE output
1: CLK output
Watchdog Timer Mode Control Register
WDMOD
(005CH)
Bit symbol
7
6
5
4
WDTE
WDTP1
WDTP0
WARM
Read/Write
After reset
Function
3
2
1
0
HALTM1
HALTM0
RESCR
DRVE
R/W
1
WDT control
0
WDT detection time
0
0
Warm-up
0
0
HALT mode
timer
15
0: Disable
1: Enable
00: 2 /fSYS
01: 217/fSYS
19
10: 2 /fSYS
11: 221/fSYS
0: 214/
frequency
inputted
1: 216/
Note 3:
0
Pin state
1: Connects
control in
STOP mode
00: RUN mode
01: STOP mode
WDT
output to
10: IDLE1 mode
11: IDLE2 mode
RESET
pin
frequency
inputted
Note 1:
Note 2:
0
0: Don’t care
internally.
0: I/O off
1: Remains
the state
before
halt
SYSCR1<bit7:4> and CKOCR<bit5:2> are read as “1”.
In the TMP93CS44, resetting sets <ALEEN>, <CLKEN> bit to “0” (High-impedance ALE and CLK). In the
TMP93CS45, resetting sets <ALEEN>, <CLKEN> bit to “1” (output ALE and CLK). The CLK pin is internally
pulled up during reset regardless of the product types.
Writing “0” to SYSCR1<SYSCK> enables the high-frequency oscillator regardless of the value of
SYSCR0<XEN>. Additionally, writing “1” to <SYSCK> register enebles the low-frequency oscillator
regardless of th value of SYSCR0<XTEN>.
Figure 3.3.3 I/O Registers about Dual Clock, Standby
93CS44-16
2004-02-10
TMP93CS44/S45
3.3.1
System Clock Controller
The system clock controller generates system clock (fSYS) for CPU core and internal I/O.
It contains two oscillation circuits and clock gear circuit for high frequency (fc). The register
SYSCR1<SYSCK> changes system clock to either fc or fs, SYSCR0<XEN>, <XTEN>
controls enable/disable each oscillator, SYSCR1<GEAR2:0> changes high-frequency clock
gear to either 1, 2, 4, 8 or 16 (fc, fc/2, fc/4, fc/8 or fc/16), and these functions can reduce the
power consumption of the equipment in which the device is installed.
The system clock (fSYS) is set to fc/32 (fc/16 × 1/2) because of <XEN> = “1”, <XTEN> = “0”,
<SYSCK> = “0”, <GEAR2:0> = “100” by resetting. For example, fSYS is set to 0.625 MHz by
resetting the case of 20 MHz oscillator is connected to X1, X2 pins.
The high-frequency (fc) and low-frequency (fs) clocks can be easily obtained by connecting
a resonator to the X1/X2, XT1/XT2 pins, respectively. Clock input from an external
oscillator is also possible.
The XT1, XT2 pins have also port 66, 67 function. Therefore the case of single clock mode,
the XT1, XT2 pins can be used as I/O port pins.
Low-frequency clock
High-frequency clock
X1
X2
X1
X2
XT1
XT2
XT1
XT2
(Open)
74HCU04
Refer to chapter
5 “Application
Circuit.”
(a) Crystal/ceramic
resonator
(b) External oscillator
(c) Crystal resonator
(d) External oscillator
Figure 3.3.4 Examples of Resonator Connection
Note 1: Note on using the low-frequency oscillation circuit.
In connecting the low-frequency resonator to ports 66 and 67, it is necessary to make the
following settings to reduce the power consumption.
(Connecting with resonators)
P6CR<P66C:67C> = “11”, P6<P66:67> = “00”
(Connecting with oscillators)
P6CR<P66C:67C> = “11”, P6<P66:67> = “10”
Note 2: Accurate adjustment of the oscillation frequency.
The CLK pin outputs at 1/2 the system clock frequency (fSYS/2) is used to monitor the oscillation
clock. With a system requiring adjustment of the oscillation frequency, an adjusting program
must be written.
93CS44-17
2004-02-10
TMP93CS44/S45
(1) Switching from NORMAL to SLOW mode
When the resonator is connected to X1, X2, or XT1, XT2 pin, the warm-up timer is
used to change the operation frequency after getting stabilized oscillation.
The warm-up time can be selected by WDMOD<WARM>.
This starting and ending of warm-up timer are performed like the following example
1, 2 by program.
Note 1: The warm-up timer is also used as a watchdog timer. So, when it is used as a
warm-up timer, the watchdog timer must be disabled.
Note 2: The case of using oscillator (Not resonator) with stabilized oscillation, a warm-up
timer is not need.
Note 3: The warm-up timer is operated by a oscillation clock. Therefore, warm-up time has
an error.
Table 3.3.2 Warm-up Time
Warm-up Time
WDMOD<WARM>
Change to NORMAL
0 (214/frequency)
0.8192 (ms)
500 (ms)
1 (216/frequency)
3.2768 (ms)
2000 (ms)
Change to SLOW
at fc = 20 MHz, fs = 32.768 kHz
93CS44-18
2004-02-10
TMP93CS44/S45
Clock setting example 1:
Changing from the high frequency (fc) to the low frequency (fs).
SYSCR0
SYSCR1
WDCR
WDMOD
WUP:
EQU
EQU
EQU
EQU
RES
LD
SET
SET
SET
BIT
JR
SET
RES
SET
006EH
006FH
005DH
005CH
7, (WDMOD)
(WDCR), B1H
4, (WDMOD)
6, (SYSCR0)
2, (SYSCR0)
2, (SYSCR0)
NZ, WUP
3, (SYSCR1)
7, (SYSCR0)
7, (WDMOD)
;
;
;
;
;
;
;
;
;
;
Disables watchdog timer.
Sets warm-up time to 216/fs.
Enables low-frequency oscillation
Clears and starts warm-up timer.
Detects end of warm-up timer.
Changes fSYS from fc to fs.
Disables high-frequency oscillation.
Enables watchdog timer.
<XEN>
X1, X2 pins
<XTEN>
XT1, XT2 pins
Warm-up timer
Counts up by fSYS
Counts up by fs
End of warm-up timer
fc
<SYSCK>
fs
System clock fSYS
Enables
low frequency
Clears and starts
warm-up timer
Changes fSYS Disables
from fc to fs
high frequency
End of warm-up timer
93CS44-19
2004-02-10
TMP93CS44/S45
Clock setting example 2:
Changing from the low frequency (fs) to the high frequency (fc).
SYSCR0
SYSCR1
WDCR
WDMOD
WUP:
EQU
EQU
EQU
EQU
RES
LD
SET
SET
SET
BIT
JR
SET
RES
SET
006EH
006FH
005DH
005CH
7, (WDMOD)
(WDCR), B1H
4, (WDMOD)
7, (SYSCR0)
2, (SYSCR0)
2, (SYSCR0)
NZ, WUP
3, (SYSCR1)
6, (SYSCR0)
7, (WDMOD)
;
;
;
;
;
;
;
;
;
;
Disables watchdog timer.
Sets warm-up time to 214/fc.
Enables high-frequency (fc).
Clears and starts warm-up timer.
Detects end of warm-up timer.
Changes fSYS from fs to fc.
Disables low-frequency oscillation.
Enable watchdog timer.
<XEN>
X1, X2 pins
<XTEN>
XT1, XT2 pins
Warm-up timer
Counts up by fSYS
Counts up
by fc
End of warm-up timer
fc
fs
<SYSCK>
System clock fSYS
Enables
high frequency
Clears and starts
warm-up timer
Change fSYS
from fs to fc
End of warm-up
timer
93CS44-20
Disables
low frequency
2004-02-10
TMP93CS44/S45
(2) Clock gear controller
When the high-frequency clock fc is selected at SYSCR1<SYSCK> = “0”, the clock
gear select register SYSCR1<GEAR2:0> sets fFPH to either fc, fc/2, fc/4, fc/8, fc/16.
Switching fFPH with the clock gear reduces the power consumption.
Clock setting example 3:
Changing gear value of the high-frequency clock
SYSCR1
EQU
006FH
LD
LD
(SYSCR1), XXXX0000B
(SYSCR1), XXXX0100B
; Changes fSYS to fc/2.
; Changes fSYS to fc/32.
X: Don’t care
(High-frequency clock gear changing)
To change the frequency of the clock gear, write the value to SYSCR1<GEAR2:0>
register. It is necessary to continue the warm-up time until changing after writing
the register value.
There is a possibility that the instruction next to the clock gear changing
instruction is executed by the clock gear before changing. To execute the
instruction next to the clock gear changing instruction by the clock gear after
changing, input the dummy instruction (Instruction to execute the write cycle) as
follows.
Example: SYSCR1
EQU
LD
LD
006FH
(SYSCR1), XXXX0001B
(DUMMY), 00H
; Changes fSYS to fc/4.
; Dummy instruction.
Instruction to be executed by the clock gear after changing
X: Don’t care
93CS44-21
2004-02-10
TMP93CS44/S45
3.3.2
Prescaler Clock Controller
The 9-bit prescaler provides a clock to 8-bit timer 0, 1, 2, 3, 16-bit timer 4, 5, and serial
interface 0, 1.
The clock input to the 9-bit prescaler is selected either fFPH, fc/16, or fs by
SYSCR0<PRCK1:0> register.
<PRCK1:0> register is initialized to “00” by resetting.
When the IDLE 1 mode (Operates only oscillator) is used, set TRUN<PRRUN> to “0” to
stop 9 bit prescaler before “HALT” instruction is executed.
3.3.3
Internal Clock Pin Output Function
CLK pin outputs fSYS divided by 2 internal clock.
Outputs are specified by the clock output control register CKOCR<CLKEN>. Writing “1”
sets clock output, and writing “0” sets high impedance.
After reset, CKOCR<CLKEN> is depended on each product types. It is necessary to set
for each usage. Table 3.3.3 shows the value and operation after reset.
During reset, CLK pin is internally pulled up regardless of the value of <CLKEN>
register. See “TMP93CS44/S45 Reset Timing Chart” in Figure 3.1.1 and Figure 3.1.2.
Table 3.3.3 <CLKEN> and CLK Pin Operation after Reset
Type Number
CKOCR<CLKEN>
TMP93CS44
0
CLK Pin Operation
High impedance
TMP93CS45
1
fSYS/2 clock output
Note: To set <CLKEN> = “0” and set CLK pin to high impedance, pull up externally to prevent
through current which follows to the input buffer of CLK pin.
93CS44-22
2004-02-10
TMP93CS44/S45
3.3.4
Standby Controller
(1) HALT mode
When the HALT instruction is executed, the operating mode changes RUN, IDLE2,
IDLE1 or STOP mode depending on the contents of the HALT mode setting register
WDMOD<HALTM1:0>. Figure 3.3.5 shows the alternative states of watchdog timer
mode registers.
Watchdog Timer Mode Register
WDMOD
(005CH)
Bit symbol
7
6
5
4
3
2
1
0
WDTE
WDTP1
WDTP0
WARM
HALTM1
HALTM0
RESCR
DRVE
1
0
0
0
Read/Write
After reset
Function
R/W
Watchdog
timer
control
0: Disable
1: Enable
Watchdog timer detect
time selection
Warm-up
0
0: 2 /clock
frequency
selection
16
1: 2 /clock
frequency
0
Runaway
detection
00:
01:
10:
11:
internal reset
control
timer
14
00: 215/fSYS
01: 217/fSYS
10: 219/fSYS
11: 221/fSYS
0
HALT mode selection
RUN mode
STOP mode
IDLE1 mode
IDLE2 mode
1: Executes
0
STOP
mode pin
control
1: Drive
pins in
internal reset
by runaway
STOP
mode
detection
selection
Pin state control in STOP mode
0
I/O off
1
Retains the state before halt
HALT mode setting
00
RUN mode (Only CPU stop)
01
STOP mode (All circuits stop)
10
IDLE1 mode (Only oscillator operating)
11
IDLE2 mode (Partial I/O operating)
Warm-up time selection at returning from the stop
mode (see Table 3.3.6)
0
214/select clock frequency
1
216/select clock frequency
Figure 3.3.5 Watchdog Timer Mode Register
The futures of RUN, IDLE2, IDLE1 and STOP modes are as follows.
1. RUN:
Only the CPU halts; power consumption remains unchanged.
2. IDLE2: The built-in oscillator and the specified I/O operates.
The power consumption is reduced to 1/2 than that during NORMAL
operation.
3. IDLE1: Only the built-in oscillator operates, while all other built-in circuits stop.
Consumption is reduced to 1/5 or less than that during NORMAL
operation.
4. STOP:
All internal circuits including the built-in oscillator stop.
This greatly reduces power consumption.
93CS44-23
2004-02-10
TMP93CS44/S45
The operations in the halt state is described in Table 3.3.4.
Table 3.3.4 I/O Operation during HALT Mode
HALT mode
RUN
IDLE2
IDLE1
STOP
WDMOD<HALTM1:0>
00
11
10
01
CPU
Stop
I/O Port
Keep the state when the “HALT” instruction was executed. See Table 3.3.7
8-bit timer
16-bit timer
BLOCK
Serial channel
Serial bus interface
Operate
AD converter
Stop
Watchdog timer
Interrupt controller
(2) How to release the HALT mode
These halt states can be released by resetting or requesting an interrupt. The halt
release sources are determined by the combinations between the states of interrupt
mask register <IFF2:0> and the HALT modes. The details for releasing the halt status
are shown in Table 3.3.5.
•
Released by requesting an interrupt
The operating released from the HALT mode depends on the interrupt enabled
status. When the interrupt request level set before executing the HALT instruction
exceeds the value of the interrupt mask register, the interrupt due to the source is
processed after releasing the HALT mode, and CPU starts executing an instruction
that follows the HALT instruction. When the interrupt request level set before
executing the HALT instruction is less than the value of the interrupt mask
register, releasing the HALT mode is not executed (in non-maskable interrupts,
interrupt processing is processed after releasing the HALT mode regardless of the
value of the mask register.)
However only for INT0 interrupts, even if the interrupt request level set before
executing the HALT instruction is less than the value of the interrupt mask
register, releasing the HALT mode is executed. In this case, interrupt processing is
not processed, and CPU starts executing the instruction next to the HALT
instruction, but the interrupt request flag is held at “1”.
•
Note: Usually, interrupts can release all halts status. However, the interrupts = ( NMI ,
INT0) which can release the HALT mode may not be able to do so if they are
input during the period CPU is shifting to the HALT mode (for about 3 clocks of
fFPH) with IDLE1 or STOP mode (RUN and IDLE2 are not applicable to this
case). (In this case, an interrupt request is kept on hold internally.)
If another interrupt is generated after it has shifted to HALT mode completely,
halt status can be released without difficultly. The priority of this interrupt is
compare with that of the interrupt kept on hold internally, and the interrupt with
higher priority is handled first followed by the other interrupt.
Release by resetting
Releasing all halt status is executed by resetting.
When the STOP mode is released by RESET, it is necessary enough resetting
time (3 ms or more) to set the operation of the oscillator to be stable.
When releasing the HALT mode by resetting, the internal RAM data keeps the
state before the “HALT” instruction is executed. However the other setting
contents are initialized. (Releasing due to interrupts keep the state before the
“HALT” instruction is executed.)
93CS44-24
2004-02-10
TMP93CS44/S45
Table 3.3.5 Halt Releasing Source and Halt Releasing Operation
Interrupt Receiving Status
HALT mode
NMI
INTWDT
INT0
INT1, INT4 to INT7
Halt
releasing Interrupt
source
INTT0 to INTT3
INTTR4 to INTTR7
INTTO4, INTTO5
INTRX0, INTTX0
INTRX1, INTTX1
INTS2
INTAD
RESET
♦:
○:
Interrupt Enable
Interrupt Disable
(Interrupt level) ≥ (Interrupt mask)
(Interrupt level) < (Interrupt mask)
RUN
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
IDLE2
♦
IDLE1
♦
STOP
♦*1
RUN
IDLE2
IDLE1
STOP
−
−
−
−
×
×
×
−
−
−
−
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦*1
○
○
○
○*1
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
♦
♦
♦
♦
♦
♦
♦
After releasing the HALT mode, CPU starts interrupt processing. (RESET initializes LSI.)
After releasing the HALT mode, CPU starts executing an instruction that follows the HALT
instruction.
×:
−:
It can not be used to release the HALT mode.
This combination type does not exist because the priority level (Interrupt request level) of
non-maskable interrupts is fixed to highest priority level “7”.
*1:
Releasing the HALT mode is executed after passing the warm-up time.
Note:
When releasing the HALT mode is executed by INT0 interrupt of the level mode in the interrupt
enabled status, hold level “H” until starting interrupt processing. If level “L” is set before holding level
“L”, interrupt processing is correctly started.
(Example releasing “RUN” mode)
INT0 interrupt releases halt state when the RUN mode is on.
Address
8203H
8206H
8209H
820BH
820EH
LD
LD
EI
LD
HALT
(IIMC), 00H
(INTE0AD), 06H
5
(WDMOD), 00H
INT0
820FH
; Selects interrupt rising edge for INT0.
; Sets interrupt level to “6” for INT0.
; Sets interrupt level to “5” for CPU.
; Sets HALT mode to “RUN”.
; Halts CPU.
INT0 interrupt routine
LD
XX, XX
RETI
When halt is released by reset, the states (Including those of the internal RAM)
before halt state was entered can be maintained. However, if the HALT instruction is
executed within the internal RAM, the contents of the RAM may not be maintained. In
this case, we recommend releasing the halt state using INT0.
93CS44-25
2004-02-10
TMP93CS44/S45
(3) Operation
1.
RUN mode
In the RUN mode, the system clock continues to operate even after a HALT
instruction is executed.
Only the CPU stops executing the instruction. In the halt state, an interrupt
request is sampled with the falling edge of the “CLK” signal.
Releasing the RUN mode is executed by the external/internal interrupts. (See
Table 3.3.5 “Halt Releasing Source and Halt Releasing Operation”.)
Figure 3.3.6 shows the interrupt timing for releasing the halt state by
interrupts in the RUN/IDLE2 mode.
X1
CLK
A0 to A23
Address + 2
Address
ALE
AD0 to AD15
Address
Data
Address
Address
Data
RD
WR
NMI
INT0
(Level)
INT1, INT4 to INT7
(Rising edge)
INT4, INT6
(Falling edge)
Internal INT
RUN/IDLE2
mode
Figure 3.3.6 Timing Chart for Releasing the Halt State by Interrupt in RUN/IDLE2
Modes
2.
IDLE2 mode
In the IDLE2 mode, the system clock is supplied to only specific internal I/O
devices, and the CPU stops executing the current instruction.
In the IDLE2 mode, the halt state is released by an interrupt with the same
timing as in the RUN mode. The IDLE2 mode is released by external/internal
interrupt, except INTWDT/INTAD interrupts. (See Table 3.3.5 “Halt Releasing
Source and Halt Releasing Operation”.)
In the IDLE2 mode, the watchdog timer should be disabled before entering the
halt status to prevent the watchdog timer interrupt occurring just after releasing
the HALT mode.
93CS44-26
2004-02-10
TMP93CS44/S45
3.
IDLE1 mode
In the IDLE1 mode, only the internal oscillator operates. The system clock in
the MCU stops, the CLK pin is fixed at the level “H” in the output enable
(CKOCR<CLKEN> = “1”).
In the halt state, and interrupt request is sampled asynchronously with the
system clock, however the halt release (Restart of operation) is performed
synchronously with it.
IDLE1 mode is released by external interrupts (NMI, INT0). (See Table 3.3.5
“Halt Releasing Source and Halt Releasing Operation”.)
When the IDLE1 mode is used, setting TRUN<PRRUN> to “0” to stop 9-bit
prescaler before “HALT” instruction reduces the power consumption.
Figure 3.3.7 illustrates the timing for releasing the halt state by interrupts in
the IDLE1 mode.
X1
CLK
A0 to A23
Address + 2
Address
ALE
AD0 to AD15
Address
Data
Address
Data
RD
WR
NMI
INT0
(Level)
INT0
(Rising edge)
IDLE1 mode
Figure 3.3.7 Timing Chart of Halt Released by Interrupts in IDLE1 Mode
93CS44-27
2004-02-10
TMP93CS44/S45
4.
STOP mode
The STOP mode is selected to stop all internal circuits including the internal
oscillator. The pin status in the STOP mode depends on setting of a bit in the
watchdog timer mode register WDMOD<DRVE>. (See Figure 3.3.5 for setting of
WDMOD<DRVE>.) Table 3.3.7 summarizes the state of these pins in the STOP
mode.
The STOP mode is released by external interrupts (NMI, INT0). When the
STOP mode is released, the system clock output starts after warm-up time
required to attain stable oscillation. The warm-up time can be set using
WDMOD<WARM>. See the example of warm-up time (Table 3.3.6).
In a system which supplies stable clock generated by an external oscillator, the
warm-up time can be reduced by using the setting of T45CR<QCU>.
Figure 3.3.8 illustrates the timing for releasing the halt state by interrupts
during the STOP mode.
Warm-up
time
X1
CLK
A0 to A23
Address + 2
Address
ALE
AD0 to AD15
Address
Data
Address
Data
RD
WR
NMI
INT0
(Level)
INT0
(Rising edge)
STOP
mode
Figure 3.3.8 Timing Chart of Halt State Release by Interrupts in STOP Mode
93CS44-28
2004-02-10
TMP93CS44/S45
Table 3.3.6 The Example of Warm-up Time after Releasing the STOP Mode
Warm-up Time [ms]
Clock Operation Frequency
after the STOP Mode
WDMOD<WARM> = 0 WDMOD<WARM> = 1
fc
0.8192
fc/2
1.6384
6.5536
fc/4
3.2768
13.1072
3.2768
fc/8
6.5536
26.2144
fc/16
13.1072
52.4288
fs
500
Clock Frequency
2000
fc = 20 MHz
fs = 32.768 kHz
How to calculate the warm-up time
14
WDMOD<WARM> = 0:
Clock operation frequency after the 2 /STOP mode.
16
WDMOD<WARM> = 1:
Clock operation frequency after the 2 /STOP mode.
The NORMAL/SLOW mode selection is possible after released STOP mode. This is
selected by SYSCR0<RSYSCK>. Therefore, Setting to <RSYSCK>, <RXEN>,
<RXTEN> is necessary before “HALT” instruction is executed.
Setting example: The STOP mode is entered when the low-frequency (fs) operates, and after that
high-frequency operates after releasing by NMI .
Address
SYSCR0
SYSCR1
WDMOD
8FFDH
EQU
EQU
EQU
LD
006EH
006FH
005CH
(SYSCR1), 08H
9000H
9002H
RES
LD
4, (WDMOD)
(SYSCR0), −11000 − − B
9005H
HALT
; fSYS = fs/2.
; Sets warm-up time to 214/fc.
; Operates high frequency after released.
Clears and starts warm-up timer.
(High frequency)
NMI
End
NMI Interrupt routine.
9006H
LD
XX, XX
RETI
−: No change
Note:
When different modes are used before and after STOP mode as the above mentioned, there is
possible to release the HALT mode without changing the operation mode by acceptance of the
halt release interrupt request during execution of “HALT” instruction (during 8 states). In the
system which accepts the interrupts during execution “HALT” instruction, set the same
operation mode before and after the STOP mode.
93CS44-29
2004-02-10
TMP93CS44/S45
Table 3.3.7 Pin States in STOP Mode
Pin Name
P00 to P07
P10 to P17
P20 to P27
I/O
<DRVE> = 1
<DRVE> = 0
<DRVE> = 1
▲
▲
×
×
Output mode
High-Z
Output
×
×
AD0 to AD7
High-Z
High-Z
High-Z
High-Z
×
▲
▲
×
Output mode/A8 to A15
High-Z
Output
×
×
AD8 to AD15
High-Z
High-Z
High-Z
High-Z
Input mode
Input mode
▲
▲
▲
▲
Output mode A0 to A7/A16 to
A23
▲
Output
▲
Output
High-Z
Output
High-Z
“H” level output
PU*
PU
PU*
Output
Output
P32 (HWR/SCK)
Input mode
Output mode
P40 to P47
Input mode
Invalid
Invalid
Output mode
High-Z
Output
Input mode
Invalid
Invalid
Output mode
High-Z
Output
P50 to P57
Input
P60 to P65
Input mode
Output mode
P70 to P77
TMP93CS45
<DRVE> = 0
Input mode
P30 (RD), P31 (WR)
P33 to P35
TMP93CS44
▲
▲
PU*
PU
PU*
Output
Input mode
Invalid
Invalid
Output mode
High-Z
Output
The same as for
TMP93CS44
NMI
Input
Input
Input
ALE
Output (<ALEEN> = 1)
“L” level output
“L” level output
CLK
Output (<CLKEN> = 1)
High-Z
“H” level output
RESET
Input
Input
Input
EA
Input
“H” level fix
“H” level fix
“L” level fix
“L” level fix
AM8/ AM16
Input
“H” level fix
“H” level fix
Input
Input
X1
Input
Invalid
Invalid
X2
Output
“H” level output
“H” level output
P66
Input mode
Invalid
Invalid
Output mode
High-Z
Output*
■
■
XT1
P67
Input mode
Invalid
Invalid
Output mode
High-Z
Output*
■
■
XT2
The same as for
TMP93CS44
Input:
Input gate in operation. Fix input voltage to 0 or 1 so that the input pin stays constant.
Output: Output state.
Output*: Open-drain output state. Input gate in operation. Set output to “L” or attach pull up on pin so that the input gate stays
constant.
Invalid: Input is not accepted.
High-Z: Output is at high impedance.
PU:
Programmable pull-up pin in input gate in operation. Fix the pin to avoid through current since the input gate
operates when a pull-up pin resistor is not set.
PU*:
Programmable pull-up pin in input gate disable state. No through current even if the pin is set to high impedance.
▲:
When a HALT instruction is executed and the CPU stops at the address of the port register, an input gate operates.
Fix the pin to avoid through current, and change the program.
Cannot set.
×:
■:
To connect a low-frequency resonator to port 66 and port 67, it is necessary to set the following procedures to reduce
the consumption power supply.
(Connecting to a resonater)
Set P6CR<P66C:67C> = “11”, P6<P66:67> = “00”
(Connecting to an oscillator)
Set P6CR<P66C:67C> = “11”, P6<P66:67> = “10”
Note: Port registers are used for controlling programmable pull up. If a pin is also used for an output function (e.g., TO3) and
the output function is specified, whether pull up is selected depends on the output function data. If a pin is also used for
an input function, whether pull up is selected depends on the port register setting value only.
93CS44-30
2004-02-10
TMP93CS44/S45
3.4
Interrupts
TLCS-900 interrupts are controlled by the CPU interrupt mask flip-flop <IFF2:0> and the
built-in interrupt controller.
Altogether the TMP93CS44/S45 have the following 33 interrupt sources:
Internal interrupts ............................ 26
•
Software interrupts: 8
•
Illegal instruction execution: 1
•
Interrupts from built-in I/Os: 17
External interrupts ........................... 7
•
External pins ( NMI , INT0, INT1, INT4, to INT7)
A fixed individual interrupt vector number is assigned to each interrupt source; six levels of
priority can also be assigned to each maskable interrupt. Non-maskable interrupts have a fixed
priority of 7.
When an interrupt is generated, the interrupt controller sends the value of the priority of the
interupt source to the CPU. When more than one interrupt is generated simultaneously, the
interrupt controller sends the value of the highest priority (7 for non-maskable interrupts is the
highest) to the CPU.
The CPU compares the value of the priority sent with the value in the CPU interrupt mask
register <IFF2:0>. If the value is greater than that the CPU interrupt mask register, the
interrupt is accepted. The value in the CPU interrupt mask register <IFF2:0> can be changed
using the EI instruction (Executing EI n changes the contents of <IFF2:0> to n). For example,
programming EI 3 enables acceptance of maskable interrupts with a priority of 3 or greater, and
non-maskable interrupts which are set in the interrupt controller. The DI instruction (<IFF2:0>
= 7) operates in the same way as the EI 7 instruction. Since the priority values for maskable
interrupts are 0 to 6, the DI instruction is used to disable acceptance of maskable interrupts.
The EI instruction becomes effective immediately after execution (with the TLCS-90, the EI
instruction becomes effective after execution of the subsequent instruction).
In addition to the general-purpose interrupt processing mode described above, there is also a
micro DMA processing mode. Micro DMA is a mode used by the CPU to automatically transfer
byte or word data. It enables the CPU to process interrupts such as data saves to built-in I/Os at
high speed.
Figure 3.4.1 is a flowchart showing overall interrupt processing.
93CS44-31
2004-02-10
TMP93CS44/S45
Interrupt processing
Read interrupt vector V.
Clear interrupt request F/F.
Start vector
match of vector V and
micro DMA
Yes
No
General-purpose
interrupt processing
Data transfer by
micro DMA
PUSH
PC
PUSH
SR
SR<IFF2:0> ← Accepted
interruput
level +1
INTNEST ← INTNEST + 1
COUNT ← COUNT − 1
Yes
Micro DMA
processing
COUNT = 0
PC ← (FFFF00H + V)
No
Interrupt processing
program
RETI instruction
POP SR
POP PC
INTNEST ← INTNEST − 1
End
Figure 3.4.1 Interrupt Processing Flowchart
93CS44-32
2004-02-10
TMP93CS44/S45
3.4.1
General-purpose Interrupt Processing
When accepting an interrupt, the CPU operates as follows. In the cases of software
interrupts or interrupts generated by the CPU because of attempts to execute illegal
instructions, the following steps (1) and (3) are not executed.
(1) The CPU reads the interrupt vector from the interrupt controller. When more than one
interrupt with the same level is generated simultaneously, the interrupt controller
generates interrupt vectors in accordance with the default priority (which is fixed as
follows: The smaller the vector value, the higher the priority), then clears the interrupt
request.
(2) The CPU pushes the program counter and the status register to the system stack area
(Area indicated by the system mode stack pointer (XSP)).
(3) The CPU sets a value in the CPU interrupt mask register <IFF2:0> that is higher by 1
than the value of the accepted interrupt level. However, if the value is 7, 7 is set
without an increment.
(4) The CPU increments the INTNEST (Interrupt nesting counter).
(5) The CPU jumps to address stored at FFFF00H + interrupt vector, then starts the
interrupt processing routine.
The following diagram shows all the above processing state number.
Bus Width of Stack
Bus Width of
Area
Interrupt Vector Area
8 bits
16 bits
Interrupt Processing State
Number
8 bits
35
16 bits
31
8 bits
29
16 bits
25
To return to the main routine after completion of the interrupt processing, the RETI
instruction is usually used. Executing this instruction restores the contents of the program
counter and the status registers and decrements INTNEST (Interrupt nesting counter).
Though acceptance of non-maskable interrupts cannot be disabled by program,
acceptance of maskable interrupts can. A priority can be set for each source of maskable
interrupts. The CPU accepts an interrupt request with a priority higher than the value in
the CPU mask register <IFF2:0>. The CPU mask register <IFF2:0> is set to a value higher
by 1 than the priority of the accepted interrupt. Thus, if an interrupt with a level higher
than the interrupt being processed is generated, the CPU accepts the interrupt with the
higher level, causing interrupt processing to nest.
The interrupt request with a priority higher than the accepted now interrupt during the
CPU is processing above (1) to (5) is accepted before the 1’st instruction in the interrupt
processing routine, causing interrupt processing to nest. (This is the same case of over
lapped each non-maskable interrupt (level 7).) The CPU does not accept an interrupt
request of the same level as that of the interrupt being processed.
Resetting initializes the CPU mask registers <IFF2:0> to 7; therefore, maskable
interrupts are disabled.
93CS44-33
2004-02-10
TMP93CS44/S45
The following (1) to (5) show a flowchart of interrupt processing.
(1) Maskable interrupt
(Main)
EI 1
[1]
(INTT0 interrupt routine)
(Main)
D1
IFF ← 2
[2]
INTT0
(Level 1)
[5]
(2) Non-maskable interrupt
NMI
[4]
IFF ← 1
[3]
(Level 7)
RETI
[5]
INTT0
(Level 3)
[9]
[8]
IFF ← 3
[4]
IFF ← 7
RETI
(4) Software interrupt
(INTT0 interrupt routine) (INTT1 interrupt routine)
IFF ← 4
[2]
[3]
DI instruction is executed in the main program, so that
the interrupts of only level 7 are accepted. The CPU
does not increment the IFF even if the CPU accepts
an interrupt request of level 7.
(3) Interrupt nesting
[1]
IFF ← 7
[2]
[1]
During execution of the main program, the CPU
accepts an interrupt request. The CPU increments the
IFF so that the interrupts of level 1 are not accepted
during processing the interrupt routine.
(Main)
EI 3
(NMI interrupt routine)
IFF ← 5
[4]
[3]
(Main)
D1
[1]
INTT1
(Level 4)
[5]
[7]
RETI
(SWI3 routine)
[2]
SWI3
[3]
[6]
IFF ← 4
RETI
During processing the interrupts of level 3, the IFF is set to 4.
When an interrupt with a level higher than level 4 is generated,
the CPU accepts the interrupt with the higher level, causing
interrupt processing to nest.
[5]
[4]
RETI
The CPU accepts the software interrupt request
during DI status (IFF = 7) because of the level 7.
The IFF is not changed by the software interrupts.
(5) Interrupt sampling timing
(INTT0 interrupt routine)
(Main)
EI 3
[1]
[3]
INTT1
(Level 4)
[2]
INTT0
(Level 3)
[8]
Example:
XXX
[6]
[7]
RETI
[5]
(Underline): Instruction
[1], [2], …:
Execution flow
[4]
RETI
If an interrupt with a level higher than the interrupt being
processed is generated, the CPU accepts the interrupt with the
higher level. The program counter which returns at e is the start
address of INTT0 interrupt routine.
93CS44-34
2004-02-10
TMP93CS44/S45
The addresses FFFF00H to FFFFFFH (256 bytes) of the TMP93CS44/S45 are assigned
for interrupt vector area.
Table 3.4.1 TMP93CS44/S45 Interrupt Table
Default Priority
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
−
to
−
Type
Interrupt Source
Nonmaskable
Reset or SWI0 instruction
SWI 1 instruction
Illegal instruction, or SWI2
SWI 3 instruction
SWI 4 instruction
SWI 5 instruction
SWI 6 instruction
SWI 7 instruction
NMI:
NMI pin input
INTWD: Watchdog timer
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Maskable
INT0:
INT0 pin input
INT1:
INT1 pin input
INT4:
INT4 pin input
INT5:
INT5 pin input
INT6:
INT6 pin input
INT7:
INT7 pin input
INTT0: 8-bit timer 0
INTT1: 8-bit timer 1
INTT2: 8-bit timer 2
INTT3: 8-bit timer 3
INTTR4: 16-bit timer 4 (TREG4)
INTTR5: 16-bit timer 4 (TREG5)
INTTR6: 16-bit timer 5 (TREG6)
INTTR7: 16-bit timer 5 (TREG7)
INTTO4: 16-bit timer 4 (Overflow)
INTTO5: 16-bit timer 5 (Overflow)
INTRX0: Serial receive (Channel 0)
INTTX0: Serial send (Channel 0)
INTRX1: Serial receive (Channel 1)
INTTX1: Serial send (Channel 1)
INTAD: AD conversion completion
INTS2: Serial bus send and receive
(Reserved)
to
(Reserved)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
93CS44-35
Address
Refer to
Vector
Micro DMA
Start Vector
FFFF00H
FFFF04H
FFFF08H
FFFF0CH
FFFF10H
FFFF14H
FFFF18H
FFFF1CH
FFFF20H
FFFF24H
−
−
−
−
−
−
−
−
08H
09H
FFFF28H
FFFF2CH
FFFF30H
FFFF34H
FFFF38H
FFFF3CH
FFFF40H
FFFF44H
FFFF48H
FFFF4CH
FFFF50H
FFFF54H
FFFF58H
FFFF5CH
FFFF60H
FFFF64H
FFFF68H
FFFF6CH
FFFF70H
FFFF74H
FFFF78H
FFFF7CH
FFFF80H
to
H FFFFFCH
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
−
to
−
Vector Value
“V”
0
0
0
0
1
1
1
1
2
2
0
4
8
C
0
4
8
C
0
4
H
H
H
H
H
H
H
H
H
H
2 8
2 C
3 0
3 4
3 8
3 C
4 0
4 4
4 8
4 C
5 0
5 4
5 8
5 C
6 0
6 4
6 8
6 C
7 0
7 4
7 8
7 C
8 0
to
0 0 F C
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
2004-02-10
TMP93CS44/S45
Setting to reset/interrupt vector
1.
Reset vector
FFFF00H
FFFF01H
FFFF02H
FFFF03H
PC<7:0>
PC<15:8>
PC<23:16>
XX
The vector base addresses are depended on the products.
Type Number
Vector Base Address
TMP93CS45
TMP93PS44
TMP93CU44
PC Setting Sequence after Reset
PC<7:0> ← Address FFFF00H
PC<15:8> ← Address FFFF01H
PC<23:16> ← Address FFFF02H
TMP93CS44
FFFF00H
TMP93CW44
TMP93PW44A
2.
Notes
P27 to P20/A23 to A16 pins input
ports with pull-up due to reset. The
logic data is “FFH”. When port 2 is
used as A23 to A16 pins to access
the program ROM, set PC<23:16> to
“FFH” and the reset vector to
“FF0000H to FFFFFFH” (for mainly
products without ROM).
Interrupt vector (except reset vector)
Address refer to vector
+0
+1
+2
+3
PC<7:0>
PC<15:8>
PC<23:16>
XX
93CS44-36
XX: Don’t care
2004-02-10
TMP93CS44/S45
(Setting example)
Sets the reset vector: FF0000H, NMI vector: FF9ABCH, INTAD vector: 123456H.
ORG
DL
FFFF00H
FF0000H
; Reset = FF0000H.
ORG
DL
FFFF20H
FF9ABCH
; NMI = FF9ABCH.
ORG
DL
FFFF78H
123456H
; INTAD = 123456H.
ORG
LD
FF0000H
A, B
ORG
LD
FF9ABCH
B, C
ORG
LD
123456H
C, A
Note:
ORG, DL are assembler directives.
ORG: Control location counter.
DL: Defines long word (32 bits) data.
93CS44-37
2004-02-10
TMP93CS44/S45
3.4.2
Micro DMA
In addition to the conventional interrupt processing, the TLCS-900 also has a micro DMA
function. When an interrupt is accepted, in addition to an interrupt vector, the CPU
receives data indicating whether processing is micro DMA mode or general-purpose
interrupt. If micro DMA mode is requested, the CPU performs micro DMA processing.
The TLCS-900 can process at very high speed because it has transfer parameters in
dedicated registers in the CPU. Since those dedicated registers are assigned as CPU
control registers, they can only be accessed by the LDC instruction.
(1) Micro DMA operation
Micro DMA operation starts when the accepted interrupt vector value matches the
micro DMA start vector value. The micro DMA has four channels so that it can be set
for up to four types of interrupt source.
When a micro DMA interrupt is accepted, data is automatically transferred from the
transfer source address to the transfer destination address set in the control register,
and the transfer counter is decremented. If the value in the counter after decrementing
is other than 0, micro DMA processing is completed; if the value in the counter after
decrementing is 0, general-purpose interrupt processing is performed.
32-bit control registers are used for setting transfer source/destination addresses.
However, the TLCS-900 has only 24 address pins for output. A 16-Mbyte space is
available for the micro DMA.
There are two data transfer modes: one-byte mode and one-word mode. Incrementing,
decrementing, and fixing the transfer source/destination address after transfer can be
done in both modes. Therefore data can easily be transferred between I/O and memory
and between I/Os. For details of transfer modes, see the description of transfer mode
registers.
The transfer counter has 16 bits, so up to 65536 transfers (the maximum when the
initial value of the transfer counter is 0000H) can be performed for one interrupt
source by micro DMA processing.
When the transfer counter is decremented to “0” after data is transferred with micro
DMA, general-purpose interrupt processing is performed. After processing the
general-purpose interrupt, starting the interrupts of the same channel restarts the
transfer counter from 65536. If necessary, reset the transfer counter.
Interrupt sources processed by micro DMA processing are those with the micro DMA
start vectors listed in Table 3.4.1.
The following timing chart is a micro DMA cycle of the transfer address INC
(Increment) mode (Condition: MAX mode, 16-bit bus width for 16 MBytes, 0 waits).
93CS44-38
2004-02-10
D0 to D15
DM6
D0 to D15
DM8
Destination address
A0 to A15
DM7
DM9
Dummy
DM10
D0 to D15
DM12
Address
A0 to A15
DM11
DM13
Address + 2
D0 to D15
DM14
(Note 3)
A0 to A15
This may be a dummy cycle with an instruction queue buffer.
Source address
A0 to A15
DM5
These 2 states are added in the case that the bus width of the destination address area is 8 bits or the address starts from an odd number.
Dummy
DM4
Note 3:
DM3
(Note 3)
Note 2:
Dummy
DM2
(Note 2)
These 2 states are added in the case that the bus width of the source address area is 8 bits or the address starts from an odd number.
DM1
(Note 1)
Note 1:
WR, HWR
RD
A16 to A23
AD0 to AD15
ALE
X1
1 state
D0 to D15
DM16
Address + 4
A0 to A15
DM15
(Note 3)
TMP93CS44/S45
Figure 3.4.2 Micro DMA Cycle (COUNT ≠ 0)
93CS44-39
2004-02-10
93CS44-40
DM2
D0 to D15
DM6
DM37
DM21
D0 to D15
DM8
D0 to D15
DM14
DM29
DM31
Dummy
DM32
DM16
Dummy
DM15
FFFF02H + V
DM30
Address + 2
A0 to A15
DM13
(Note 3)
FFFF00H + V
DM28
This be a dummy cycle with an instruction queue buffer.
DM27
These 2 states are added in the case of the bus width of stack address area is 8 bits or stack pointer starts from an odd number.
Dummy
DM26
D0 to D15
DM12
Address
A0 to A15
DM11
Note 4:
DM25
Dummy
DM10
Note 3:
XSP-2
DM24
DM9
These 2 states are added in the case that the bus width of the destination address area is 8 bits or the address starts from an odd number.
DM23
(Note 4)
Destination address
A0 to A15
DM7
These 2 states are added in the case that the bus width of the source address area is 8 bits or the address starts from an odd number.
XSP-4
DM22
(Note 4)
Source address
A0 to A15
DM5
Address + 2
DM36
XSP-6
DM20
(Note 4)
DM35
Address
DM34
DM4
Dummy
DM19
DM3
(Note 3)
Note 2:
Dummy
DM33
Dummy
DM18
Dummy
DM17
DM1
(Note 2)
Note 1:
WR, HWR
RD
AD0 to AD15
ALE
X1
WR, HWR
RD
AD0 to AD15
ALE
X1
WR, HWR
RD
A16 to A23
AD0 to AD15
ALE
X1
(Note 1)
TMP93CS44/S45
Figure 3.4.3 Micro DMA Cycle (COUNT = 0)
2004-02-10
TMP93CS44/S45
(2) Register configuration (CPU control register)
Channel 0
DMAS0
Transfer source address register 0
DMAD0
Transfer destination address register 0
DMAC0
DMAM0
(Use only lower 24 bits.)
Transfer counter register 0 (1 to 65536)
Transfer mode register 0
Channel 1
DMAS1
Transfer source address register 1
DMAD1
Transfer destination address register 1
DMAC1
DMAM1
Transfer counter register 1
Transfer mode register 1
Channel 2
DMAS2
Transfer source address register 2
DMAD2
Transfer destination address register 2
DMAC2
DMAM2
Transfer counter register 2
Transfer mode register 2
Channel 3
DMAS3
Transfer source address register 3
DMAD3
Transfer destination address register 3
DMAC3
DMAM3
Transfer counter register 3
Transfer mode register 3
8 bits
16 bits
32 bits
These control register can not be set only “LDC cr, r” instruction.
Example:
LD
LDC
LD
LDC
LD
LDC
LD
LDC
XWA, 100H
DMAS0, XWA
XWA, 50H
DMAD0, XWA
WA, 40H
DMAC0, WA
A, 05H
DMAM0, A
93CS44-41
2004-02-10
TMP93CS44/S45
(3) Transfer mode register details
(DMAM0 to DMAM3)
0
0
0
0
Mode
Note: When setting values for
this register, set the upper 4 bits to 0.
Execution time
(Min) at 20 MHz
Z 0 = byte transfer, 1 = word transfer
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
Z
Z
Z
Z
Z
1
Transfer destination address INC mode............................ for I/O to memory
(DMADn+) ← (DMASn)
DMACn ← DMACn − 1
if DMACn = 0 then INT.
16 states
Transfer destination address DEC mode .......................... for I/O to memory
(DMADn−) ← (DMASn)
DMACn ← DMACn − 1
if DMACn = 0 then INT.
16 states
Transfer source address INC mode .................................. for memory to I/O
(DMADn) ← (DMASn+)
DMACn ← DMACn − 1
if DMACn = 0 then INT.
16 states
Transfer source address DEC mode................................. for memory to I/O
(DMADn) ← (DMASn−)
DMACn ← DMACn − 1
if DMACn = 0 then INT.
16 states
Fixed address mode ......................................................... I/O to I/O
(DMADn) ← (DMASn)
DMACn ← DMACn − 1
if DMACn = 0 then INT.
16 states
Counter mode................................................................... for interrupt counter
DMASn ← DMASn + 1
DMACn ← DMACn − 1
if DMACn = 0 then INT.
11 states
(1.6 µs)
(1.6 µs)
(1.6 µs)
(1.6 µs)
(1.6 µs)
(1.1 µs)
(1 states = 100 ns at 20 MHz, High-frequency mode)
Note 1: n: Corresponds to micro DMA channels 0 to 3.
DMADn+/DMASn+: Post-increment (Increments register value after transfer.)
DMADn−/DMASn−: Post-decrement (Decrement register value after transfer.)
Note 2: Execution time: When setting source address/destination address area to 16-bit bus, 0
waits.
Clock condition: fc = 20 MHz, clock gear: 1 (fc)
Note 3: Do not use the codes other than the above mentioned codes for transfer mode register.
93CS44-42
2004-02-10
TMP93CS44/S45
3.4.3
Interrupt Controller
Figure 3.4.4 is a block diagram of the interrupt circuits. The left half of the diagram
shows the interrupt controller; the right half includes the CPU interrupt request signal
circuit and the halt release signal circuit.
Each interrupt channel (Total of 24 channels) in the interrupt controller has an interrupt
request flip-flop, interrupt priority setting register, and a register for storing the micro
DMA start vector. The interrupt request fip-flop is used to latch interrupt requests from
peripheral devices. The flip-flop is cleared to 0 at reset, when the CPU reads the interrupt
channel vector after the acceptance of interrupt, or when the CPU executes an instruction
that clears the interrupt of that channel (Writes 0 in the clear bit of the interrupt priority
setting register).
For example, to clear the INT0 interrupt request, set the register after the DI instruction
as follows.
INTE0AD ← − − − − 0 − − − B
The status of the interrupt request flip-flop is detected by reading the clear bit. Detects
whether there is an interrupt request for an interrupt channel.
The interrupt priority can be set by writing the priority in the interrupt priority setting
register (e.g., INTE0AD, INTE45 etc.) provided for each interrupt source. Interrupt levels
to be set are from 1 to 6. Writing 0 or 7 as the interrupt priority disables the corresponding
interrupt request. The priority of the non-maskable interrupt ( NMI pin, watchdog timer
etc.) is fixed to 7. If interrupt requests with the same interrupt level are generated
simultaneously, interrupts are accepted in accordance with the default priority (the smaller
the vector value, the higher the priority).
The interrupt controller sends the interrupt request with the highest priority among the
simultaneous interrupts and its vector address to the CPU. The CPU compares the priority
value <IFF2:0> set in the status register by the interrupt request signal with the priority
value sent; if the latter is higher, the interrupt is accepted. Then the CPU sets a value
higher than the priority value by 1 in the CPU SR<IFF2:0>. Interrupt requests where the
priority value equals or is higher than the set value are accepted simultaneously during the
previous interrupt routine. When interrupt processing is completed (after execution of the
RETI instruction) , the CPU restores the priority value saved in the stack before the
interrupt was generated to the CPU SR<IFF2:0>.
The interrupt controller also has four registers used to store the micro DMA start vector.
These are I/O registers; unlike other micro DMA registers (DMAS, DMAD, DMAM, and
DMAC). Writing the start vector of the interrupt source for the micro DMA processing (See
Table 3.4.1), enables the corresponding interrupt to be processed by micro DMA processing.
The values must be set in the micro DMA parameter registers (e.g., DMAS and DMAD)
prior to the micro DMA processing.
93CS44-43
2004-02-10
INT1
INT4
INT5
INT6
INT7
INTT0
INTT1
INTT2
INTT3
INTTR4
INTTR5
INTTR6
INTTR7
INTTO4
INTTO5
INTRX0
INTTX0
INTRX1
INTTX1
INTAD
INTS2
INT0
INTWD
NMI
93CS44-44
R
Interrupt request flip-flop read
Dn + 3
V = 20H
V = 24H
Decoder
Y1
A
Y2
Y3
B
Y4
C
Y5
Y6
6
D4
D3
D
Q
D2
D1
CLR
D0
RESET
5
5
DMA0V
DMA1V
DMA2V
DMA3V
Match
detect
Interrupt request clear Dn + 3
Interrupt request V read
V = 28H
V = 2CH
V = 30H
V = 34H
V = 38H
V = 3CH
V = 40H
V = 44H
V = 48H
V = 4CH
V = 50H
V = 54H
V = 58H
V = 5CH
V = 60H
V = 64H
V = 68H
V = 6CH
V = 70H
V = 74H
V = 78H
V = 7CH
Micro DMA start vector setting register
RESET
Interrupt
request F/F
S
Q
Priority setting register
Dn
Dn + 1
D
Q
Dn + 2
CLR
RESET
R
Interrupt
vecror V read
Interrupt request flip-flop
S
Q
Interrupt controller
1
6
4
1
7
Interrupt
vector
generation
0
A
1
2
B
3
Micro DMA channel
priorty encoder
4 input OR
24
3
INTRQ2 to 0
5
2
D6
D5
D4
D3
D2
D1
D0
Interrupt
vector read
(Highese priority = 7)
Priority encoder
1
2
A
3 Highest B
priority C
4
interrupt
5 level
select
6
7
Interrupt request
signal to CPU
Interrupt
level detect
2
RESET
INT0
NMI
Micro DMA
channel specification
Micro DMA request
Halt release
During
IDLE1
During
STOP
Interrupt request
signal
EI 1 to EI 7
DI
RESET
If INTRQ2 to 0 ≥ IFF2
to 0 then 1.
3
3
IFF<2:0>
Interrupt enable
flag on CPU side
CPU
TMP93CS44/S45
Figure 3.4.4 Block Diagram of Interrupt Controller
2004-02-10
TMP93CS44/S45
(1) Interrupt priority setting register
Symbol
INTE0AD
INTE45
INTE67
INTET10
INTET32
INTET54
INTET76
INTEO54
INTES0
INTES1
INTE1S2
IxxM2
0
0
0
0
1
1
1
1
IxxC
0
1
Address
7
IADC
R/W
0
0070H
I5C
R/W
0
0071H
I7C
R/W
0
0072H
IT1C
R/W
0
0073H
IT3C
R/W
0
0074H
IT5C
R/W
0
0075H
IT7C
R/W
0
0076H
0077H
ITO5C
R/W
0
0078H
0079H
007AH
IxxM1
0
0
1
1
0
0
1
1
ITX0C
R/W
0
ITX1C
R/W
0
I1C
R/W
0
6
5
INTAD
IADM2
IADM1
W
0
0
INT5
I5M2
I5M1
W
0
0
INT7
I7M2
I7M1
W
0
0
INTT1 (Timer 1)
IT1M2
IT1M1
W
0
0
INTT3 (Timer 3)
IT3M2
IT3M1
W
0
0
INTTR5 (TREG5)
IT5M2
IT5M1
W
0
INTTR7 (TREG7)
IT7M2
IT7M1
W
0
0
INTTO5
ITO5M2 ITO5M1
W
0
0
INTTX0
ITX0M2
ITX0M1
W
0
0
INTTX1
ITX1M2
ITX1M1
W
0
0
INT1
I1M2
I1M1
W
0
0
IxxM0
0
1
0
1
0
1
0
1
4
(Prohibit read-modify-write)
3
2
1
0
I0M1
W
0
I0M0
I4M1
W
0
I4M0
INT0
IADM0
0
I0C
R/W
0
I0M2
0
0
← Interrupt source
← Bit symbol
← Read/Write
← After reset
INT4
I5M0
0
I4C
R/W
0
I4M2
0
0
INT6
I7M0
0
IT1M0
0
IT3M0
0
IT5M0
0
IT7M0
0
ITO5M0
0
ITX0M0
0
ITX1M0
0
I1M0
0
I6C
R/W
0
IT0C
R/W
0
IT2C
R/W
0
IT4C
R/W
0
IT6C
R/W
0
ITO4C
R/W
0
IRX0C
R/W
0
IRX1C
R/W
0
IS2C
R/W
0
I6M2
I6M1
W
0
0
INTT0 (Timer 0)
IT0M2
IT0M1
W
0
0
INTT2 (Timer 2)
IT2M2
IT2M1
W
0
0
INTTR4 (TREG4)
IT4M2
IT4M1
W
0
0
INTTR6 (TREG6)
IT6M2
IT6M1
W
0
0
INTTO4
ITO4M2 ITO4M1
W
0
0
INTRX0
IRX0M2 IRX0M1
W
0
0
INTRX1
IRX1M2 IRX1M1
W
0
0
INTS2
IS2M2
IS2M1
W
0
0
I6M0
0
IT0M0
0
IT2M0
0
IT4M0
0
IT6M0
0
ITO4M0
0
IRX0M0
0
IRX1M0
0
IS2M0
0
Function (Write)
Prohibits interrupt request.
Sets interrupt request level to 1.
Sets interrupt request level to 2.
Sets interrupt request level to 3.
Sets interrupt request level to 4.
Sets interrupt request level to 5.
Sets interrupt request level to 6.
Prohibits interrupt request.
Function (Read)
Indicates no interrupt request.
Indicates interrupt request.
Function (Write)
Clears interrupt request flag.
Don’t care
Note 1: Read-modify-write is prohibited.
Note 2: Note about clearing interrupt request flag
The interrupt request flag of INTRX0, INTRX1 are not cleared by writing “00” to IXXC because of they
are level interrupts. They can be cleared only by resetting or reading SCBUFn.
Figure 3.4.5 Interrupt Priority Setting Register
93CS44-45
2004-02-10
TMP93CS44/S45
(2) External interrupt control
Interrupt Input Mode Control Register
7
IIMC
(007BH)
6
5
Bit symbol
−
Read/Write
W
After reset
0
Always
write “0”.
Function
Prohibit
readmodifywrite
4
3
Note 1:
0
I0IE
I0LE
NMIREE
0
0
1: INT0
input
enable
Input enable
The INT0 pin can also be used for standby release as described
later. Even if the pin is not used for standby release, setting this
register to “0” maintains the port function during standby mode.
Note 2:
1
W
INT0 input enable (Note 1)
0
INT0 disable (P35 function only)
1
2
0: INT0
edge
mode
1: INT0
level
mode
0
1: Can be
accepted
in NMI
rising
edge.
NMI rising edge enable
0
Interrupt request generation at
falling edge
1
Interrupt request generation at
rising/falling edge
INT0 level enable (Note 2)
0
Rising edge detect interrupt
1
High level interrupt
Case of changing from level to edge for INT0 pin mode (<I0LE> “1” → “0” )
Execution example:
LD (INTE0AD)
LD (IIMC)
LD (INTE0AD)
, xxxx0000B
, xxxxx10xB
, xxxx0nnnB
; INT0 disable, clean the request flag.
; Change from level to edge.
; Set interrupt level “n” for INT0, clear the request flag.
Note 3:
IIMC<Bit7:3> is always read as “1”.
Note 4:
See electrical characteristics in section 4 for external interrupt input pulse.
Figure 3.4.6 Interrupt Input Mode Control Register
Table 3.4.2 Setting of External Interrupt Pin Functions
Interrupt
NMI
INT0
Shared Pin
NMI
(Dedicated pin)
Setting method
Falling edge
IIMC<NMIREE> = 0
Falling and rising
IIMC<NMIREE> = 1
edges
Rising edge
IIMC<I0LE> = 0, <I0IE> = 1
Level
IIMC<I0LE> = 1, <I0IE> = 1
P35
INT1
P40
INT4
P42
INT5
P43
INT6
P45
INT7
Mode
P46
−
Rising edge
Rising edge
T4MOD<CAP12M1:0> = 0, 0 or 0, 1 or 1, 1
Falling edge
T4MOD<CAP12M1:0> = 1, 0
Rising edge
−
Rising edge
T5MOD<CAP34M1:0> = 0, 0 or 0, 1 or 1, 1
Falling edge
T5MOD<CAP34M1:0> = 1, 0
Rising edge
−
93CS44-46
2004-02-10
TMP93CS44/S45
(3) Micro DMA start vector
When the CPU reads the interrupt vector after accepting an interrupt, it
simultaneously compares the interrupt vector (Bits 2 to 6 of the interrupt vector) with
each channel’s micro DMA start vector. When the two match, the interrupt from the
channel whose value matched is processed in micro DMA mode.
If the interrupt vector matches more than one channel, the channel with the lower
channel number has a higher priority.
Micro DMA0 Start Vector
7
DMA0V
(007CH)
Prohibit
readmodifywrite
6
5
Bit symbol
4
3
2
1
0
DMA0V4
DMA0V3
DMA0V2
DMA0V1
DMA0V0
0
0
Read/Write
W
After reset
Function
0
0
0
Micro DMA channel 0 processed by matching bits 2 to 6 of the interrupt vector.
Micro DMA1 Start Vector
7
DMA1V
(007DH)
Prohibit
readmodifywrite
6
5
Bit symbol
4
3
2
1
0
DMA1V4
DMA1V3
DMA1V2
DMA1V1
DMA1V0
0
0
Read/Write
W
After reset
Function
0
0
0
Micro DMA channel 1 processed by matching bits 2 to 6 of the interrupt vector.
Micro DMA2 Start Vector
7
DMA2V
(007EH)
Prohibit
readmodifywrite
6
5
Bit symbol
4
3
2
1
0
DMA2V4
DMA2V3
DMA2V2
DMA2V1
DMA2V0
0
0
Read/Write
W
After reset
Function
0
0
0
Micro DMA channel 2 processed by matching bits 2 to 6 of the interrupt vector.
Micro DMA3 Start Vector
7
DMA3V
(007FH)
Prohibit
readmodifywrite
Bit symbol
6
5
4
3
2
1
0
DMA3V4
DMA3V3
DMA3V2
DMA3V1
DMA3V0
0
0
Read/Write
After reset
Function
W
0
0
0
Micro DMA channel 3 processed by matching bits 2 to 6 of the interrupt vector.
Figure 3.4.7 Micro DMA Start Vector Register
93CS44-47
2004-02-10
TMP93CS44/S45
(4) Notes
The instruction execution unit and the bus interface unit of this CPU operate
independently of each other. Therefore, if the instruction used to clear an interrupt
request flag of an interrupt is fetched before the interrupt is generated, it is possible
that the CPU might execute the fetched instruction to clear the interrupt request flag
while reading the interrupt vector after accepting the interrupt.
To avoid the above occurring, clear the interrupt request flag by entering the
instruction to clear the flag after the DI instruction. In the case of setting an interrupt
enable again by EI instruction after the execution of clearing instruction, execute EI
instruction after clearing instruction and following more than one instruction are
executed. When EI instruction is placed immediately after clearing instruction, an
interrupt becomes enable before interrupt request flags are cleared.
In the case of changing the value of the interrupt mask register <IFF2:0> by
execution of POP SR instruction, disable an interrupt by DI instruction before
execution of POP SR instruction.
93CS44-48
2004-02-10
TMP93CS44/S45
3.5
Functions of Ports
The TMP93CS44 has 62 bits for I/O ports. The TMP93CS45 has 44 bits for I/O ports because
Port 0, Port 1, P30, and P31 are dedicated pins for AD0 to AD7, AD8 to AD15 (or A8 to A15), RD ,
and WR .
These port pins have I/O functions for the built-in CPU and internal I/Os as well as
general-purpose I/O port functions. Table 3.5.1 lists the function of each port pin. Table 3.5.2
lists I/O registers and specification.
Table 3.5.1 Functions of Ports
(PU = with programmable pull-up resistor)
Port Name
Pin Name
Pin
Number
Direction
R
Direction
Setting Unit
Pin Name for Built-in
Function
Port 0
P00 to P07
8
I/O
−
Bit
AD0 to AD7
Port 1
P10 to P17
8
I/O
−
Bit
AD8 to AD15/A8 to A15
Port 2
P20 to P27
8
I/O
PU
Bit
A0 to A7/A16 to A23
Port 3
P30
1
Output
−
(fixed)
P31
1
Output
−
(fixed)
P32
1
I/O
PU
Bit
P33
1
I/O
−
Bit
SO/SDA
P34
1
I/O
−
Bit
SI/SCL
P35
1
I/O
−
Bit
INT0
P40
1
I/O
−
Bit
TI0/INT1
P41
1
I/O
−
Bit
TO3
P42
1
I/O
−
Bit
TI4/INT4
P43
1
I/O
−
Bit
TI5/INT5
P44
1
I/O
−
Bit
TO4
P45
1
I/O
−
Bit
TI6/INT6
P46
1
I/O
−
Bit
TI7/INT7
P47
1
I/O
−
Bit
TO6
P50 to P52
3
Input
−
(fixed)
P53
1
Input
−
(fixed)
AN3/ ADTRG
P54 to P57
4
Input
−
(fixed)
AN4 to AN7
P60
1
I/O
PU
Bit
TXD0
P61
1
I/O
PU
Bit
RXD0
P62
1
I/O
PU
Bit
SCLK0/ CTS0
P63
1
I/O
PU
Bit
TXD1
P64
1
I/O
PU
Bit
RXD1
P65
1
I/O
PU
Bit
SCLK1/ CTS1
P66
1
I/O
−
Bit
XT1
P67
1
I/O
−
Bit
XT2
P70
1
I/O
−
Bit
WAIT (High current output)
P71 to P77
7
I/O
−
Bit
(High current output)
Port 4
Port 5
Port 6
Port 7
93CS44-49
RD
WR
HWR /SCK
AN0 to AN2
2004-02-10
TMP93CS44/S45
Table 3.5.2 I/O Registers and Specification (1/2)
Port
Port 0
Port 1
Port 2
Port 3
Name
P00 to P07
P10 to P17
P20 to P27
P30
P31
P32
P33
P34
P35
Port 4
P40
P41
P42
P43
Specification
I/O Register
Pn
PnCR
PnFC
Input port (Note 1)
×
0
Output port (Note 1)
×
1
AD0 to AD7 bus
×
×
Input port (Note 1)
×
0
0
Output port (Note1)
×
1
0
AD8 to AD15 bus (Note 2)
×
0
1
AD8 to AD15 output (Note 2)
×
1
1
None
Input port (without pull up)
0
0
0
Input port (with pull up)
1
0
0
Output port
×
1
0
A0 to A7 output (Note 1)
0
0
1
A16 to A23 output
0
1
1
Output port (Note 1)
×
Outputs RD only when accessing external space
1
None
1
0
Always outputs RD
0
Output port (Note 1)
×
Outputs WR only when accessing external
space
×
None
1
Input port SCK input (without pull up)
0
0
0
Input port SCK input (with pull up)
1
0
0
Output port
×
1
0
HWR output (<P32M> = 0)
×
1
1
SCK output (<P32M> = 1)
×
1
1
Input port
×
0
0
Output port
×
1
0
SDA I/O, SO output
×
1
1
Input port
×
0
0
SI input
×
0
×
1
0
Output port
×
1
0
SCL I/O
×
1
1
Input port/INT0 input (Note 3)
×
0
Output port
×
1
None
Input port/TI0/INT
×
0
Output port
×
1
Input port
×
0
Output port
×
1
0
TO3 output
×
1
1
Input port/TI4/INT4 input
×
0
Output port
×
1
Input port/TI5/INT5 input
×
0
Output port
×
1
None
0
None
X: Don’t care, n: Port number
Note 1: In the TMP93CS45, these functions are not available.
Note 2: In the TMP93CS45, these functions are fixed depending on the value of the
AM8/ AM16 pin.
Note 3: Using P35 pin as INT0, IIMC register has to be set enable interrupt.
93CS44-50
2004-02-10
TMP93CS44/S45
Table 3.5.2 I/O Registers and Specification (2/2)
Port
Port 4
Name
P44
P45
P46
P47
Port 5
Port 6
P50 to P57
P60
P61
P62
P63
P64
P65
P66, P67
Port 7
P70
P71 to P77
Specification
I/O Register
Pn
PnCR
PnFC
Input port
×
0
0
Output port
×
1
0
TO4 output
×
1
1
Input port/TI6/INT6 input
×
0
Output port
×
1
Input port/TI7/INT7 input
×
0
Output port
×
1
Input port
×
0
Output port
×
1
0
TO6 output
×
1
1
None
0
Input port
×
AN0 to AN7 input (Note 4)
×
Input port (without pull up)
0
0
0
Input port (with pull up)
1
0
0
Output port
×
1
0
TXD0 output
×
1
1
None
Input port/RXD0 input (without pull up)
0
0
Input port/RXD0 input (with pull up)
1
0
Output port
×
1
Input port/SCLK0/ CTS0 input (without pull up)
0
0
0
Input port/SCLK0/ CTS0 input (with pull up)
1
0
0
Output port
×
1
0
SCLK0 output
×
1
1
Input port (without pull up)
0
0
0
Input port (with pull up)
1
0
0
Output port
×
1
0
TXD1 output (Note 3)
×
1
1
None
Input port/RXD1 input (without pull up)
0
0
Input port/RXD1 input (with pull up)
1
0
Output port
×
1
Input port/SCLK1/ CTS1 input (without pull up)
0
0
0
Input port/SCLK1/ CTS1 input (with pull up)
1
0
0
Output port
×
1
0
SCLK1 output
×
1
1
Input port
×
0
Output port (Note 5)
×
1
XT1/2 (Note 6)
×
0
Input port/ WAIT input
×
0
Output port
×
1
Input port
×
0
Output port
×
1
None
None
None
X: Don’t care, n: Port number
Note 4: Using P50 to P57 pins as input channels for the AD converter, the channels are
selected by ADMOD1<ADCH2:0>.
Note 5: Using P66 and P67 pins as the output ports, output is through the open-drain buffer.
Note 6: Using P66 and P67 pins as the XT1 to XT2, oscillation is enabled by the SYSCR0
register.
93CS44-51
2004-02-10
TMP93CS44/S45
Resetting makes the port pins listed below function as general-purpose I/O ports.
I/O pins programmable for input or output are set to input ports except P66/XT1, P67/XT2.
To set port pins for built-in functions, a program is required.
Since the TMP93CS45 needs external ROMs, some ports are permanently assigned for
memory interface.
•
P00 to P07
→
AD0 to AD7
•
P30
→
RD
•
P10 to P17
→
AD8 to AD15 (or A8 to A15)
•
P31
→
WR
93CS44-52
2004-02-10
TMP93CS44/S45
3.5
Port 0 (P00 to P07)
Port 0 is an 8-bit general-purpose I/O port. I/O can be set on a bit basis using the control
register P0CR. Resetting sets all bits of P0CR to 0 and sets port 0 to input mode. Figure
3.5.3 shows the registers for port 0.
In addition to functioning as a general-purpose I/O port, port 0 also shares functions as
an address data bus (AD0 to AD7). To access external memory, port 0 functions as an
address data bus (AD0 to AD7) and all bits of the control register P0CR are set to 0.
With the TMP93CS45, which needs external ROMs, port 0 always functions as an
address data bus (AD0 to AD7) regardless of the value set in control register P0CR.
Reset
Direction control
(on bit basis)
P0CR write
Internal data bus
3.5.1
Output
latch
Port 0
P00 to P07
(AD0 to AD7)
Output buffer
P0 write
S
S
B
Selector
A
A
P0 read
B
Selector
Figure 3.5.1 Port 0
93CS44-53
2004-02-10
TMP93CS44/S45
Port 1 (P10 to P17)
Port 1 is an 8-bit general-purpose I/O port. I/O can be set on a bit basis using control
register P1CR and function register P1FC. Resetting sets all bits of output latch P1, control
register P1CR, and function register P1FC to 0 and sets port 1 to input mode.
Figure 3.5.3 shows the registers for port 1.
In addition to functioning as a general-purpose I/O port, port 1 also shares functions as
an address data bus (AD8 to AD15) or an address bus (A8 to A15).
With the TMP93CS45, which needs external ROMs, port 1 always functions as an
address data bus (AD8 to AD15) (the case of AM8/ AM16 = 0), as an address bus (A8 to A15)
(the case of AM8/ AM16 = 1) regardless of the value set in control register P1CR.
Reset
Direction control
(on bit basis)
P1CR write
Internal data bus
3.5.2
Function control
(on bit basis)
P1FC write
Output
latch
Output buffer
P1 write
Port 1
P10 to P17
(AD8 to AD15/A8 to A15)
S
B
Selector
A
P1 read
Figure 3.5.2 Port 1
93CS44-54
2004-02-10
TMP93CS44/S45
Port 0 Register
P0
(0000H)
Bit symbol
7
6
5
4
3
2
1
0
P07
P06
P05
P04
P03
P02
P01
P00
Read/Write
R/W
After reset
Input mode (Output latch register becomes undefined.)
Port 0 Control Register
P0CR
(0002H)
Prohibit
readmodifywrite
Bit symbol
7
6
5
4
3
2
1
0
P07C
P06C
P05C
P04C
P03C
P02C
P01C
P00C
0
0
0
0
0
0
0
0
Read/Write
After reset
Function
W
0: Input 1: Output (at external access, port 0 becomes AD7 to AD0 and P0CR is set to “0”.)
Port 0 I/O setting
0
Input
1
Output
Port 1 Register
P1
(0001H)
Bit symbol
7
6
5
4
P17
P16
P15
P14
3
2
1
0
P13
P12
P11
P10
Read/Write
R/W
After reset
Input mode (Output latch register is set to “0”.)
Port 1 Control Register
P1CR
(0004H)
Prohibit
readmodifywrite
Bit symbol
7
6
5
4
3
2
1
0
P17C
P16C
P15C
P14C
P13C
P12C
P11C
P10C
0
0
0
0
0
0
0
0
Read/Write
After reset
W
<<See P1FC below.>>
Function
Port 1 Function Register
P1FC
(0005H)
Bit symbol
Prohibit
readmodifywrite
After reset
7
6
5
4
3
2
1
0
P17F
P16F
P15F
P14F
P13F
P12F
P11F
P10F
0
0
0
0
0
0
0
0
Read/Write
Function
W
P1FC/P1CR = 00: Input
01: Output
10: AD15 to AD8
11: A15 to A8
Port 1 function setting
P1FC<P1XF>
P1CR
<P1XC>
0
1
0
Input port
Address data bus
(AD15 to AD8)
1
Output port
Address bus
(A15 to A8)
Note: <P1XF> is bit X in register P1FC; <P1XC>, in register P1CR.
Figure 3.5.3 Registers for Port 0 and Port 1
93CS44-55
2004-02-10
TMP93CS44/S45
Port 2 (P20 to P27)
Port 2 is an 8-bit general-purpose I/O port. I/O can be set on bit basis using the control
register P2CR and function register P2FC. All bits of the output latch P2 is set to 1 by reset,
and all bits of P2CR and P2FC are cleared to 0. Port 2 becomes the input mode with the
pull-up resistor.
In addition to functioning as a general-purpose I/O port, port 2 also shares functions as
an address data bus (A0 to A7) and an address bus (A16 to A23). Using port 2 as address
bus (A0 to A7 or A16 to A23), write 0 to output latches and be off the programmable pull-up
resistor.
A16 to A23
B
A0 to A7
Reset
A
Selector
S
Direction control
(on bit basis)
P2CR write
Internal data bus
3.5.3
Function control
(on bit basis)
P-ch
Programmable
pull up
S
B
P2FC write
Selector
Output
latch
P2 write
A
Output buffer
Port 2
P20 to P27
(A0 to A7/A16 to A23)
S
B
Selector
A
P2 read
Figure 3.5.4 Port 2
93CS44-56
2004-02-10
TMP93CS44/S45
Port 2 Register
P2
(0006H)
Bit symbol
7
6
5
4
3
2
1
0
P27
P26
P25
P24
P23
P22
P21
P20
Read/Write
R/W
After reset
Input mode (Output latch register is set to “1”.)
Note 1:
When port 2 is used in the input mode, P2 register controls the built-in pull-up resistor. Read-modify-write is
prohibited in the input mode or the I/O mode.
Setting the built-in pull-up resistor may be depended on the states of the input pin.
Port 2 Control Register
P2CR
(0008H)
Prohibit
readmodifywrite
Bit symbol
7
6
5
4
3
2
1
0
P27C
P26C
P25C
P24C
P23C
P22C
P21C
P20C
0
0
0
0
0
0
0
0
Read/Write
After reset
W
<<See P2FC below.>>
Function
Port 2 Function Register
P2FC
(0009H)
Bit symbol
Prohibit
readmodifywrite
After reset
7
6
5
4
3
2
1
0
P27F
P26F
P25F
P24F
P23F
P22F
P21F
P20F
0
0
0
0
0
0
0
0
Read/Write
Function
W
P2FC/P2CR = 00: Input
01: Output
10: A7 to A0
11: A23 to A16
Port 2 function setting
P2FC<P2XF>
P2CR<P2XC>
Note 2:
0
0
Input port
1
Output port
1
Address bus
(A7 to A0)
Address bus
(A23 to A16)
<P2XF> is bit X in register P2FC; <P2XC>, in register P2CR. To set as an address bus A23 to A16, set
P2FC after setting P2CR.
Figure 3.5.5 Registers for Port 2
93CS44-57
2004-02-10
TMP93CS44/S45
3.5.4
Port 3 (P30 to P35)
Port 3 is an 6-bit general-purpose I/O port.
I/O can be set on a bit basis, but note that P30 and P31 are used for output only. I/O is set
using control register P3CR and function register P3FC. Resetting sets all bits of output
latch P3 to 1. All bits of control register P3CR (bits 0 and 1 are unused), and function
register P3FC are set to 0. Resetting also outputs 1 from P30 and P31.
In addition to functioning as a general-purpose I/O port, port 3 also shares functions as
an I/O for the CPU’s control/status signal and serial bus interface.
With the TMP93CS44, when P30 pin is defined as RD signal output mode (<P30F> = 1),
setting the output latch register <P30> to 0 outputs the RD strobe (Used for the pseudo
static RAM) from the P30 pin even when the internal address area is accessed.
If the output latch register <P30> remains 1, the RD strobe signal is output only when
the external address area is accessed.
When P33 and P34 are used as the serial bus interface I/O pins in I2C bus mode
(P3FC<P34F:P33F> = 11), set open drain outputs (ODE<ODE34:33> = 11).
With the TMP93CS45, which needs external ROMs, P30 outputs the RD signal; P31, the
WR signal, regardless of the values set in function registers <P30F> and <P31F>.
The RD signal is output not only when the external address area is accessed at <P30> =
1 but also the internal address area is accessed at <P30> = 0.
93CS44-58
2004-02-10
TMP93CS44/S45
(1) P30 ( RD ), P31 ( WR )
Reset
for TMP93CS45
Internal data bus
Function control
(on bit basis)
P3FC write
S
Output
latch
A
P3 write
B
S
Selector
Output buffer
P30 ( RD )
P31 ( WR )
RD , WR
P3 read
(2) P32 ( HWR /SCK)
Reset
Direction control
(on bit basis)
P3CR write
Function control
(on bit basis)
Internal data bus
P3FC<P32F> write
Function control
(on bit basis)
P-ch
Programmable
pull up
P3FC<P32M> write
S
Output
latch
S
P32 ( HWR /SCK)
A
S
HWR
P3 write
SCK
A
Selector
Selector
B
Output
buffer
B
S
B
Selector
P3 read
A
SCK
Figure 3.5.6 Port 3 (P30, P31, P32)
93CS44-59
2004-02-10
TMP93CS44/S45
(3) P33 (SDA/SO), P34 (SCL/SI)
Reset
Direction control
(on bit basis)
P3CR write
Internal data bus
Function control
(on bit basis)
P3FC write
S
S
A
Output latch
Selector
P3 write
SDA/SO out
SCL out
Open-drain
possible
ODE<ODE34:33>
B
P33 (SDA/SO)
P34 (SCL/SI)
S
B
Selector
A
P3 read
SDA in
SCL/SI in
Figure 3.5.7 Port 3 (P33 and P34)
(4) P35 (INT0)
Port 35 is a general-purpose I/O port, and also used as an INT0 pin for external
interrupt request input.
Reset
Direction control
(on bit basis)
Internal data bus
P3CR write
S
Output latch
P35 (INT0)
P3 write
S
B
Selector
A
P3 read
Level/edge
detect
INT0
interrupt
IIMC<I0IE>
IIMC<I0LE>
Figure 3.5.8 Port 3 (P35)
93CS44-60
2004-02-10
TMP93CS44/S45
Port 3 Register
7
P3
(0007H)
6
Bit symbol
5
4
3
2
1
0
P35
P34
P33
P32
P31
P30
1
1
1
1
1
1
Read/Write
R/W
After reset
Function
Note 1:
Input mode
(pulled up)
Input mode
Output mode
When port 32 is used in the input mode, P3 register controls the built-in pull-up resistor. Read-modify-write
is prohibited in the input mode or the I/O mode.
Setting the built-in pull-up resistor may be depended on the states of the input pin.
Port 3 Control Register
7
P3CR
(000AH)
Prohibit
readmodifywrite
6
Bit symbol
5
4
3
2
P35C
P34C
P33C
P32C
0
0
0
0
Read/Write
1
0
W
After reset
0: Input
Function
1: Output
I/O setting
0
Input
1
Output
Port 3 Function Register
7
P3FC
(000BH)
Prohibit
readmodifywrite
6
Bit symbol
P32M
Read/Write
W
After reset
5
4
3
2
1
0
P34F
P33F
P32F
P31F
P30F
W
0
Function
0: HWR
1: SCK
0
0: Port
1: SCL/SI
P34 function setting (Note 2)
<P34C>
0
1
<P34F>
0
Input port
Output port
1
Input SI
I/O SCL
P33 function setting (Note 2)
<P33C>
0
1
<P33F>
Note 2: When P33 and P34
are used as the serial
0
Input port
Output port
1
Don’t set
I/O SDA/
Output SO
bus interface I/O pins
in I2C bus mode
(P3FC<P34F:P33F>
= 11), set open-drain
0
0
Port
1
Output
“ HWR ”
0
0
0: Port
0: Port
1: WR
1: RD
P31 ( RD ) function setting
<P30>
0
<P30F>
“0” output
“1” output
1
Always RD
output (for
pseudo
SRAM)
RD output
only for
external
access
P31 ( WR ) function setting
<P31>
0
<P31F>
1
1
1
0
0
P32 function setting
<P32M>
0
<P32F>
outputs
(ODE<ODE34:33> =
0
0: Port
0: Port
1: SDA/SO 1: P32M
“0” output
1
“1” output
WR output only for external
access
Input/output
“SCK”
11).
Figure 3.5.9 Registers for Port 3
93CS44-61
2004-02-10
TMP93CS44/S45
Port 4 (P40 to P47)
Port 4 is a 8-bit general-purpose I/O port. I/O can be set on bit basis. Resetting sets port 4
to the input port. In addition to functioning as a general-purpose I/O port, port 4 also
shares functions as an input for 8-bit timer 0 clock, 16-bit timer 4 and 5 clocks, an output
for 8-bit timer F/F 3, 16-bit timer F/F 4 and 6 output. Writing 1 in the corresponding bit of
the port 4 function register (P4FC) enables output of the timer.
(1) P40 and P41
Reset
Direction control
(on bit basis)
P4CR write
S
P40
(TI0/INT1)
Output latch
P4 write
P4 read
S
B
Selector
A
TI0, INT1
Reset
Internal data bus
3.5.5
Direction control
(on bit basis)
P4CR write
Function control
(on bit basis)
P4FC write
S
Output latch
P4 write
Timer F/F OUT
(TO3: Timer 3)
S
A
Selector
B
P41
(TO3)
B
P4 read
Selector
A
S
Figure 3.5.10 Port 4 (P40 and P41)
93CS44-62
2004-02-10
TMP93CS44/S45
(2) P42 to P47
Reset
Direction control
(on bit basis)
P4CR write
S
P42 (TI4/INT4)
P43 (TI5/INT5)
P45 (TI6/INT6)
P46 (TI7/INT7)
Output latch
P4 write
P4 read
Internal data bus
TI4, INT4
TI5, INT5
TI6, INT6
TI7, INT7
S
B
Selector
A
Reset
Direction control
(on bit basis)
P4CR write
Function control
(on bit basis)
P4FC write
S
Output latch
P4 write
Timer F/F OUT
TO4: Timer 4
TO6: Timer 5
S
A
Selector
B
P44 (TO4)
P47 (TO6)
B
P4 read
Selector
A
S
Figure 3.5.11 Port 4 (P42 to P47)
93CS44-63
2004-02-10
TMP93CS44/S45
Port 4 Register
P4
(000CH)
Bit symbol
7
6
5
4
3
2
1
0
P47
P46
P45
P44
P43
P42
P41
P40
1
1
1
1
1
1
1
1
Read/Write
After reset
R/W
Input mode
Port 4 Control Register
P4CR
(000EH)
Prohibit
readmodifywrite
Bit symbol
7
6
5
4
3
2
1
0
P47C
P46C
P45C
P44C
P43C
P42C
P41C
P40C
0
0
0
0
0
0
0
0
Read/Write
After reset
W
0: Input
Function
1: Output
Port 4 I/O setting
0
Input
1
Output
Port 4 Function Register
7
P4FC
(0010H)
Prohibit
readmodifywrite
6
5
4
3
2
1
Bit symbol
P47F
P44F
P41F
Read/Write
W
W
W
After reset
0
0
Function
Note:
0: Port
1: TO6
0: Port
1: TO4
0
0
0: Port
1: TO3
Setting P41 as TO3
P4FC<P41F>
1
P4CR<P41C>
1
Setting P44 as TO4
P4FC<P44F>
1
P4CR<P44C>
1
Setting P47 as TO6
P4FC<P47F>
1
P4CR<P47C>
1
P40/TI0, P42/TI4, P43/TI5, P45/TI6, P46/TI7 pin does not have a register changing port/function.
For example, when it is used as an input port, the input signal for port is inputted to 8- or 16-bit timer as a
timer input.
Figure 3.5.12 Register for Port 4
93CS44-64
2004-02-10
TMP93CS44/S45
3.5.6
Port 5 (P50 to P57)
Port 5 is an 8-bit input port, also used as an analog input pin for the internal AD
converter. Additionally, P53 is also used as an analog conversion external trigger input pin
( ADTRG ).
Internal data bus
Port 5
P50 to P52
(AN0 to AN2)
P53 (AN3/ ADTRG )
P54 to P57
(AN4 to AN7)
Port 5 read
Conversion
result
register
AD
converter
Channel
selector
AD read
ADTRG
Only for P53 function
Figure 3.5.13 Port 5
Port 5 Register
P5
(000DH)
Bit symbol
7
6
5
4
P57
P56
P55
P54
3
2
1
0
P53
P52
P51
P50
Read/Write
R
After reset
Input mode
Figure 3.5.14 Register for Port 5
Note:
The input channel selection of AD converter is set by AD converter mode register ADMOD1.
93CS44-65
2004-02-10
TMP93CS44/S45
Port 6 (P60 to P67)
•
Ports 60 to 65
Ports 60 to 65 are a 6-bit general-purpose I/O port. I/Os can be set on a bit basis.
Resetting sets P60 to P65 to an input port and connects a pull-up resistor.
It also sets all bits of the output latch register to 1.
In addition to functioning as a general-purpose I/O port, P60 to P65 can also share
function as an I/O for serial channels 0 and 1. Writing “1” in the corresponding bit of
the Port 6 function register (P6FC) enables this function.
Resetting sets the function register value to 0 and sets all bits to input ports.
•
Port 66 and port 67
Port 66 and port 67 are a 2-bit general-purpose I/O port. I/Os can be set on a bit
basis.
The output buffer for P66, P67 is an open-drain type buffer.
Resetting outputs high-impedance (High-Z) because output latch and control
register are set to 1.
In addition to functioning as a general-purpose I/O port, P66, P67 can also function
as a low-frequency oscillator connecting pin (XT1, XT2) for dual clock mode. The dual
clock function can be set by programming system clock control registers SYSCR0,
SYSCR1.
(1) Port 60 (TXD0) and port 63 (TXD1)
Port 60 and port 63 also function as serial channel TXD output pins in addition to I/O
ports.
They have a programmable open-drain function.
Reset
Direction control
(on bit basis)
P6CR write
Internal data bus
3.5.7
Function control
(on bit basis)
P-ch
Programmable
pull up
P6FC write
S
Output latch
P6 write
TXD0, TXD1
P6 read
S
A
Selector
B
Open-drain
possible
ODE<ODE63:60>
P60 (TXD0)
P63 (TXD1)
S
B
Selector
A
Figure 3.5.15 Ports 60 and 63
93CS44-66
2004-02-10
TMP93CS44/S45
(2) Port 61 (RXD0) and port 64 (RXD1)
Port 61 and port 64 are I/O ports, and also used as RXD input pins for serial
channels.
Reset
Internal data bus
Direction control
(on bit basis)
P-ch
Programmable
pull up
P6CR write
S
P61 (RXD0)
P64 (RXD1)
Output latch
S
P6 write
B
Selector
A
P6 read
RXD0, RXD1
Figure 3.5.16 Port 61 and Port 64
(3) Port 62 ( CTS0 /SCLK0) and port 65 ( CTS1 /SCLK1)
Port 62 and port 65 are I/O ports, and also used as a CTS input pin and as a SCLK
I/O pin for serial channels.
Reset
Direction control
(on bit basis)
Internal data bus
P6CR write
Function control
(on bit basis)
P-ch
Programmable
pull up
P6FC write
S
Output latch
S
A
Selector
B
P62 (SCLK0/ CTS0 )
P65 (SCLK1/ CTS1 )
P6 write
SCLK0 OUT
SCLK1 OUT
P6 read
S
B
Selector
A
CTS0 , CTS1
SCLK0, SCLK1
Figure 3.5.17 Port 62 and Port 65
93CS44-67
2004-02-10
TMP93CS44/S45
(4) Port 66 (XT1) and port 67 (XT2)
Port 66 and port 67 are general purpose I/O ports. It is also used as a low-frequency
oscillator connecting pin.
Reset
BUS6
Low-frequency oscillation enable
S
Direction control
(on bit basis)
P6CR write
BUS6
S
Output latch
P66 (XT1)
Output buffer
(Open-drain
output)
P6 write
Internal data bus
S
B
Selector
A
BUS6
P6 read
BUS7
(ON at “1”)
S
Direction control
(on bit basis)
P6CR write
BUS7
S
Output latch
P67 (XT2)
Output buffer
(Open-drain
output)
P6 write
Low-frequency clock (fs)
S
B
Selector
A
BUS7
P6 read
Figure 3.5.18 Port 66 to Port 67
93CS44-68
2004-02-10
TMP93CS44/S45
Port 6 Register
P6
(0012H)
Bit symbol
7
6
5
4
3
2
1
0
P67
P66
P65
P64
P63
P62
P61
P60
1
1
1
1
1
1
1
1
Read/Write
After reset
R/W
Output mode
Note 1:
Input mode
When P6 is used in the input mode, P6 register controls the built-in pull-up resistor. Read-modify-write is
prohibited in the input mode or the I/O mode. Setting the built-in pull-up resistor may be depended on the
states of the input pin.
Port 6 Control Register
P6CR
(0014H)
Prohibit
readmodifywrite
Bit symbol
7
6
5
4
3
2
1
0
P67C
P66C
P65C
P64C
P63C
P62C
P61C
P60C
1
1
0
0
0
0
0
0
Read/Write
After reset
W
0: Input
Function
1: Output
Port 6 I/O setting
0
Input
Note: Output buffer for port 66, 67 is an open-drain output type.
1
Output
Port 6 Function Register
7
P6FC
(0016H)
Prohibit
readmodifywrite
6
5
Bit symbol
P65F
Read/Write
W
After reset
0
Function
4
0: Port
1: SCLK1
3
2
P63F
P62F
1
W
0
0: Port
1: TXD1
0
P60F
W
0
0
0: Port
1: SCLK0
0: Port
1: TXD0
P63 TXD1 output setting (Note)
P6FC<P63F>
1
P60 TXD0 output setting (Note)
P6FC<P60F>
1
P6CR<P63C>
P6CR<P60C>
1
1
P65 SCLK1 output setting
P6FC<P65F>
1
P62 SCLK0 output setting
P6FC<P62F>
1
P6CR<P65C>
P6CR<P62C>
1
1
Note 2: To set the TXD pin to open drain, write “1” in bit0 (for TXD0 pin) or bit1 (for TXD1 pin) of the ODE register.
P61/RXD0, P64/RXD1 pins do not have a register changing port/function.
When using as input ports, the serial receive data is input to SIO.
Note 3:
Notes on using low-frequency oscillation circuit. To connect a low frequency resonator to port 66, 67, it is
necessary to set the following procedures to reduce the consumption power supply.
(Connecting to a resonator)
Set P6CR<P66C:P67C> = “11”, P6<P66:67> = “00”
(Connecting to an oscillator)
Set P6CR<P66C:P67C> = “11”, P6<P66:67> = “10”
Figure 3.5.19 Register for Port 6
93CS44-69
2004-02-10
TMP93CS44/S45
Port 7 (P70 to P77)
Port 7 is an 8-bit general-purpose I/O port. I/O can be set on a bit basis. Port 7 can output
large current and drive LED directly. In addition to I/O port, port 70 also shares functions
as WAIT input pin. Resetting sets the function register P7CR to 0, and all bits to input
ports. Port 7 as an input port. It also sets all bits of the output latch register P7 to 1.
(1) P70 ( WAIT )
Port 70 is a general-purpose I/O port, and also used as an WAIT pin for external
wait input.
Reset
Internal data bus
Direction control
(on bit basis)
P7CR write
S
P70 ( WAIT )
Output latch
P7 write
P7 read
S
B
Selector
A
WAIT
(2) P71 to P77
Reset
Direction control
(on bit basis)
Internal data bus
3.5.8
P7CR write
S
P71 to P77
Output latch
P7 write
P7 read
S
B
Selector
A
Figure 3.5.20 Port 7
93CS44-70
2004-02-10
TMP93CS44/S45
Port 7 Register
P7
(0013H)
Bit symbol
7
6
5
4
3
2
1
0
P77
P76
P75
P74
P73
P72
P71
P70
1
1
1
1
1
1
1
1
Read/Write
After reset
R/W
Input mode
Port 7 Control Register
P7CR
(0015H)
Prohibit
readmodifywrite
Bit symbol
7
6
5
4
3
2
1
0
P77C
P76C
P75C
P74C
P73C
P72C
P71C
P70C
0
0
0
0
0
0
0
0
Read/Write
After reset
Function
W
0: Input
1: Output
Port 7 I/O setting
0
Input
1
Note:
Output
P70/ WAIT pin does not have a register changing port/function.
For example, when it is used as and input port, the input signal is inputted as WAIT input.
When it is used as WAIT input pin, bit<BmWn> of bus width WAIT control register must be specified.
Figure 3.5.21 Register for Port 7
93CS44-71
2004-02-10
TMP93CS44/S45
3.6
Bus Width/Wait Controller and AM8/ AM16 Pin
TMP93CS44/S45 have a built-in controller used to control wait ( WAIT pin) and data bus size
(8 or 16 bits) for any of the three block address areas.
And AM8/ AM16 pin selects external data bus width for TMP93CS45.
3.6.1
AM8/ AM16 pin
(1) TMP93CS44
Set this pin to “H”. After reset, the CPU accesses the internal ROM with 16-bit bus
width. The bus width when the CPU accesses an external area is set by the bus
width/wait control register (Described at 3.6.3) and the registers of Port 1. (The value 1
of this pin is ignored and the value set by register is active.)
(2) TMP93CS45
1.
With fixed external 16-bit data bus and external 16-bit data bus or 8-bit data bus
is selectable
Set this pin to “L”. Port1, AD8 to AD15 and A8 to A15 pins are fixed to AD8 to
AD15 functions. The values set in port 1 control register and port 1 function
register are invalid.
The external data bus width is set by the bus width/wait control register which
is described in section 3.6.3.
It is necessary to set the program memory to be accessed to 16-bit data bus after
reset.
2.
With fixed external 8-bit data bus
Set this pin to “H”. Port1, AD8 to AD15 and A8 to A15 pins are fixed to A8 to
A15 functions. The values set in port 1 control register and port 1 function register
are invalid.
The values of bit4: <B0BUS>, <B1BUS>, and <B2BUS>, in the bus width/wait
control register described in section 3.6.3 are invalid. The external 8-bit data bus
is fixed.
93CS44-72
2004-02-10
TMP93CS44/S45
3.6.2
Address/Data Bus Pins
Port 0/AD0 to AD7, port 1/AD8 to AD15/A8 to A15 and port 2/A16 to A23/A0 to A7
function as address/data bus for connecting the external memories and so on.
(1)
Products
(2)
(3)
TMP93CS45F (Note 4)
(4)
TMP93CS44F (Note 2), (Note 3)
Number of Address Bus
Max 24 (to 16 Mbytes) Max 24 (to 16 Mbytes) Max 16 (to 64 Kbytes)
Pins
Max 8 (to 256 bytes)
Number of Data Bus
Pins
8
16
8
16
Number of Multiplexed
Pins
8
16
0
0
VIL
EA
Mode Pins
Port
Function
AM8/ AM16
VIH
VIH
VIL
Port 0
AD0 to AD7
AD0 to AD7
AD0 to AD7
AD0 to AD7
Port 1
A8 to A15
AD8 to AD15
A8 to A15
AD8 to AD15
Port 2
A16 to A23
A16 to A23
A0 to A7
A0 to A7
A23 to 8
A23 to 8
A23 to 16
VIH
A23 to 16
A15 to 0
A15 to 0
A7 to 0
(Note 1)
AD7 to 0
A7
to 0
D7
to 0
AD15 to 0
Timing Chart
A15
to 0
D15
to 0
AD7 to 0
A7
to 0
D7
to 0
A7 to 0
(Note 1)
AD15 to 0
ALE
ALE
ALE
ALE
RD
RD
RD
RD
A15
to 0
D15
to 0
Note 1: In case of (3) and (4), the data bus signals output the addresses since the signals are
also used as the address bus. Writing “0” to bit CKOCR<ALEEN>, ALE signal can be
stopped outputting.
Note 2: After reset operation, port 0, port 1 and port 2 of TMP93CS44F function as input
ports.
Note 3: In case of TMP93CS44F, all (1) to (4) can be available using P1CR, P1FC, P2CR
and P2FC registers.
Note 4: In case of TMP93CS45F, case (3) and (4) cannot be available.
93CS44-73
2004-02-10
TMP93CS44/S45
3.6.3
Bus Width/Wait Control Registers
Figure 3.6.1 shows control registers.
One block address areas are controlled by 1-byte bus width/wait control registers
(WAITC0, WAITC1, WAITC2).
(1) Data bus size select
Bit4 (<B0BUS>, <B1BUS>, <B2BUS>) of the control register is used to specify data
bus size. Setting this bit to 0 accesses the memory in 16-bit data bus mode; setting it to
1 accesses the memory in 8-bit data bus mode.
Changing data bus size depending on the access address is called dynamic bus sizing.
Table 3.6.1 shows the details of the bus operation.
This bit is changed by the state of AM8/ AM16 pin.
(2) Wait control
Control register bits 3 and 2 (<B0W1:0>, <B1W1:0>, <B2W1:0>) are used to specify
the number of waits.
These bits execute the following operation by setting.
“00”
A 2-state wait is inserted regardless of the WAIT pin status.
“01”
A 1-state wait is inserted regardless of the WAIT pin status.
“10”
A 1-state wait is inserted and the WAIT pin status is sampled. If the pin is
low, inserting the wait maintains the bus cycle until the pin goes high.
“11”
The bus cycle is completed without a wait (0 waits) regardless of the WAIT
pin status.
These bits are initialized to 00 by reset.
(3) Address area specification
Control register bits 1 and 0 (<B0C1:0>, <B1C1:0>, <B2C1:0>) are used to specify
the target address area. Setting these bits to 00 enables settings (Wait state, bus size
etc.) as follows:
•
WAITC0 setting enabled when 7F00H to 7FFFH is accessed.
•
WAITC1 setting enabled when 880H to 7FFFH is accessed.
•
WAITC2 setting enabled when 8000H to 3FFFFFH is accessed.
Setting bits to 01 enables setting for each block when 400000H to 7FFFFFH is
accessed. Setting bits to 10 enables them 800000H to BFFFFFH is accessed. Setting
bits to 11 enables them when C00000H to FFFFFFH is accessed.
93CS44-74
2004-02-10
TMP93CS44/S45
7
WAITC0
(0068H)
Prohibit
readmodifywrite
6
5
Bit symbol
4
3
2
1
0
B0BUS
B0W1
B0W0
B0C1
B0C0
0
0
0
0
Read/Write
W
After reset
Function
0: 16-bit
bus
1: 8-bit bus
0
00: 2 waits
01: 1 wait
10: (1 + N) waits
00:
01:
10:
11:
11: 0 waits
WAITC1
(0069H)
Prohibit
readmodifywrite
WAITC2
(006AH)
Prohibit
readmodifywrite
Bit symbol
B1BUS
B1W1
B1W0
Read/Write
7F00H to 7FFFH
From 400000H
From 800000H
From C00000H
B1C1
B1C0
0
0
W
After reset
0
Function
0: 16-bit
bus
1: 8-bit bus
Bit symbol
B2BUS
0
0
00: 2 waits
01: 1 wait
10: (1 + N) waits
11: 0 waits
B2W1
00:
01:
10:
11:
B2W0
Read/Write
880H to 7FFFH
From 400000H
From 800000H
From C00000H
B2C1
B2C0
0
0
W
After reset
0
Function
0
0
0: 16-bit
00: 2 waits
bus
01: 1wait
1: 8-bit bus 10: (1 + N) waits
11: 0 waits
00:
01:
10:
11:
From 8000H
From 400000H
From 800000H
From C00000H
Figure 3.6.1 Bus Width/Wait Control Registers
Operand
Data Size
8 bits
16 bits
Table 3.6.1 Dynamic Bus Sizing
Operand Start
Memory
CPU Data
CPU Address
Address
Data Size
D15 to D8
D7 to D0
2n + 0
(Even number)
8 bits
2n + 0
xxxxx
b7 to b0
16 bits
2n + 0
xxxxx
b7 to b0
2n + 1
(Odd number)
8 bits
2n + 1
xxxxx
b7 to b0
16 bits
2n + 1
b7 to b0
xxxxx
8 bits
2n + 0
xxxxx
b7 to b0
2n + 1
xxxxx
b15 to b8
16 bits
2n + 0
b15 to b8
b7 to b0
8 bits
2n + 1
xxxxx
b7 to b0
2n + 2
xxxxx
b15 to b8
2n + 1
b7 to b0
xxxxx
2n + 2
xxxxx
b15 to b8
2n + 0
(Even number)
2n + 1
(Odd number)
16 bits
32 bits
2n + 0
(Even number)
8 bits
16 bits
2n + 1
(Odd number)
8 bits
16 bits
2n + 0
xxxxx
b7 to b0
2n + 1
xxxxx
b15 to b8
2n + 2
xxxxx
b23 to b16
2n + 3
xxxxx
b31 to b24
2n + 0
b15 to b8
b7 to b0
2n + 2
b31 to b24
b23 to b16
2n + 1
xxxxx
b7 to b0
2n + 2
xxxxx
b15 to b8
2n + 3
xxxxx
b23 to b16
2n + 4
xxxxx
b31 to b24
2n + 1
b7 to b0
xxxxx
2n + 2
b23 to b16
b15 to b8
2n + 4
xxxxx
b31 to b24
xxxxx: During a read, data input to the bus is ignored. At write, the bus is at high impedance
and the write strobe signal remains non-active.
93CS44-75
2004-02-10
TMP93CS44/S45
3.6.4
Bus Width/Wait Control
An image of the actual bus width/wait control is shown below. Out of the whole memory
area, address areas that can be specified are divided into four parts. Addresses from
000000H to 3FFFFFH are divided differently: 7F00H to 7FFFH is specified for WAITC0;
880H to 7FFFH, for WAITC1; and 8000H to 3FFFFFH, for WAITC2. The reason is that a
device other than ROM (e.g., RAM or I/O) might be connected externally.
7F00H to 7FFFH (256 bytes) for WAITC0 are mapped mainly for possible expansions to
external I/O.
880H to 7FFFH (approx. 31 Kbytes) for WAITC1 are mapped there mainly for possible
extensions to external RAM.
8000H to 3FFFFFH (approx. 4 Mbytes) for WAITC2 are mapped mainly for possible
extensions to external ROM. With the TMP93CS45, which does not have a built-in ROM,
the program is externally read at address FF0000H in this setting (16-bit bus, 2 waits).
With the TMP93CS44 which has a built-in ROM, addresses from FF0000H to FFFFFFH
are used as the internal ROM area; WAITC2 is disabled in this area. After reset, the CPU
reads the program from the built-in ROM in 16-bit bus, 0 WAIT mode.
WAITC0
000000H
7F00H
8000H
WAITC1
880H
<B0C1:0> = 00
WAITC2
<B1C1:0> = 00
<B2C1:0> = 01
400000H
<B0C1:0> = 01
<B1C1:0> = 01
<B2C1:0> = 01
<B0C1:0> = 10
<B1C1:0> = 10
<B2C1:0> = 10
<B0C1:0> = 11
<B1C1:0> = 11
<B2C1:0> = 11
(Mainly for I/O)
(Mainly for RAM)
(Mainly for ROM)
800000H
C00000H
FFFFFFH
Note 1: Access priority is highest for built-in I/O, then built-in memory, and lowest for the bus
width/wait controller.
Note 2: External areas other than WAITC0 to WAITC2 are accessed in 0 WAIT mode. In the
TMP93CS45, when the AM8/ AM16 pin is set to “L”, the data bus width is fixed to 16-bit.
When the AM8/ AM16 pin is set to “H”, it is fixed to 8 bits. In the TMP93CS44, the data
bus width is always fixed to 16 bits.
When using the bus width/wait controller, do not specify the same address area more
than once. (However, when addresses 7F00H to 7FFFH for WAITC0 and 880H to
7FFFH for WAITC1 are specified, in other words, specifications overlap, only the
WAITC0 setting is active.)
93CS44-76
2004-02-10
TMP93CS44/S45
3.6.5
Example of Usage
(1) Example of usage-1
Figure 3.6.2 is an example in which an external memory is connected to the
TMP93CS45. In this example, a ROM is connected using 16-bit bus; a RAM is
connected using 8-bit bus.
Decoder
IOCS
RAMCS
ROMCS
74HC573
D
TMP93CS45
Q
Upper
Address
CS
D
ALE
AD8
to
AD15
EA
Address bus
LE
Q
LE
CS
Upper byte
ROM
OE
CS
Lower byte
ROM
OE
CS
8-bit bus
RAM
OE WE
8-bit bus
I/O
OE WE
AD0
to
AD7
AM8/ AM16
RD
WR
Figure 3.6.2 Example of External Memory Connection (ROM = 16 bits, RAM and I/O = 8 bits)
WAITC0
WAITC1
WAITC2
LD
LD
LD
EQU
EQU
EQU
(WAITC0),
(WAITC1),
(WAITC2),
68H
69H
6AH
XXX10000B
XXX11100B
XXX00111B
; WAITC0 = 8 bits, 2 waits, 7F00H to 7FFFH.
; WAITC1 = 8 bits, 0 waits, 880H to 7EFFH.
; WAITC2 = 16 bits, 1 wait, C00000H to FFFFFFH.
X: Don’t care
93CS44-77
2004-02-10
TMP93CS44/S45
(1) Example of usage-2
Figure 3.6.3 is an example in which an external memory is connected to the
TMP93CS45. In this example, a ROM, RAM, and I/O are connected using 8-bit bus.
Decoder
IOCS
RAMCS
ROMCS
Address bus
TMP93CS45
74HC573
CS
Upper
Address
D
EA
Q
OE
LE
ALE
A8
to
A15
CS
8-bit bus
ROM
CS
8-bit bus
RAM
OE WE
8-bit bus
I/O
OE WE
AD0
to
AD7
AM8/ AM16
RD
WR
Figure 3.6.3 Example of External Memory Connection (ROM, RAM and I/O = 8 bits)
WAITC0
WAITC1
WAITC2
LD
LD
LD
EQU
EQU
EQU
(WAITC0),
(WAITC1),
(WAITC2),
68H
69H
6AH
XXX10000B
XXX11100B
XXX00111B
; WAITC0 = 8 bits, 2 waits, 7F00H to 7FFFH
; WAITC1 = 8 bits, 0 waits, 880H to 7EFFH
; WAITC2 = 8 bits, 1 wait, C00000H to FFFFFFH
X: Don’t care
93CS44-78
2004-02-10
TMP93CS44/S45
(3) Example of usage-3
Figure 3.6.4 is an example in which an external memory is connected to the
TMP93CS44. In this example, ROM 128 Kbytes are connected using 16-bit bus, and
RAM 256 Kbytes are connected using 16-bit bus.
Decoder
ROMCS
RAMCS
TMP93CS44
Upper
address
Latch × 16
AD8 to AD15
D
AD0 to AD7
Address bus
Q
LE
ROM (128 Kbytes × 16)
D8 to D15
D0 to D7
OE
CS
ALE
RAM (128 Kbytes × 8)
I/O1 to I/O8
RD
HWR
OE
R/ W
CS
Upper byte
RAM (128 Kbytes × 8)
WR
I/O1 to I/O8
OE
R/ W
CS
AM8/ AM16
Lower byte
EA
Figure 3.6.4 Example of External Memory Connection (ROM and RAM = 16 bits)
The TMP93CS44 has built-in ROM and RAM. When ROM and RAM have
insufficient capacity, it is possible to connect an external memory as the example of the
external memory connection. In this example, the memory configuration is as follows.
Memory
ROM
Internal
Memory Size
64 Kbytes
External 128 Kbytes
SRAM
Internal
2 Kbytes
External 256 Kbytes
Address
Data Bus
FF0000H to FFFFFFH
16 bits
400000H to 41FFFFH
16 bits
000080H to 00087FH
16 bits
800000H to 83FFFFH
16 bits
93CS44-79
2004-02-10
TMP93CS44/S45
3.7
8-Bit Timers
TMP93CS44/S45 contains four 8-bit timers (Timer 0, 1, 2, 3), each of which can be
operated independently. The cascade connection allows these timers to be used as 16-bit
timer. The following four operating modes are provided for the 8-bit timers.
•
8-bit interval timer mode (4 timers)
•
16-bit interval timer mode (2 timers)
•
8-bit programmable square wave pulse generation (PPG: Variable duty with variable
cycle) output mode (1 timer)
•
8-bit pulse width modulation (PWM: Variable duty with constant cycle) output mode (1
timer)
Figure 3.7.1 shows the block diagram of 8-bit timer (Timer 0, 1), and Figure 3.7.2 shows
the block diagram of 8-bit timer (Timer 2, 3).
Each interval timer consists of an 8-bit up counter, 8-bit comparator, and 8-bit timer
register. Besides, timer flip-flops (TFF1, TFF3), are provided for pair of timer 0/1 and 2/3.
Among the input clock sources for the interval timers, the internal clocks of φT1, φT4,
φT16, and φT256 are obtained from the 9-bit prescaler shown in Figure 3.7.3.
The operation modes and timer flip-flops of the 8-bit timer are controlled by five control
registers T10MOD, T32MOD, TFFCR, TRUN and TRDC.
93CS44-80
2004-02-10
Selector
T10MOD<T0CLK1:0>
TI0 pin
(External input)
φT1
φT4
φT16
Clear
2n − 1
over
flow
93CS44-81
8-bit timer
register
TREG0
8-bit
comparator
(CP0)
φT1
φT16
φT256
8-bit
up counter
(UC1)
RUN
TRUN<T1RUN>
8-bit timer
register
TREG1
8-bit
comparator
(CP1)
T10MOD<T1CLK1:0>
Selector
Internal data bus
INTT0
Match detect
T10MOD<T10M1:0>
8-bit
up counter
(UC0)
RUN
TRUN<T0RUN>
Clear
INTT1
Selector
Match
detect
TFF1
T10MOD<T10M1:0>
TFFCR, T10MOD
control
F/F
Timer
(Timer 4, 5)
TMP93CS44/S45
Figure 3.7.1 Block Diagram of 8-Bit Timers (Timer 0 and 1)
2004-02-10
93CS44-82
Selector
TRDC<TR2DE>
Selector
T32MOD<T2CLK1:0>
PPGTRG
PWMTRG
TREG-WR
φT1
φT4
φT16
Clear
2n − 1
over
flow
φT1
φT16
φT256
Register buffer
8-bit timer
register TREG2
8-bit
comparator
(CP2)
8-bit
up counter
(UC3)
RUN
TRUN<T3RUN>
8-bit timer
register
TREG3
8-bit
comparator
(CP3)
T32MOD<T3CLK1:0>
Selector
Internal data bus
TO2TRG (to serial channels)
INTT2
Match detect
T32MOD<T32M1:0,, PWM21:20>
8-bit
up counter
(UC2)
RUN
TRUN<T2RUN>
Clear
INTT3
Selector
Match
detect
TFF3
T32MOD<T32M1:0>
TFFCR, T32MOD
control
F/F
Timer
TO3
(Shared pin
with P41)
TMP93CS44/S45
Figure 3.7.2 Block Diagram of 8-Bit Timers (Timer 2 and 3)
2004-02-10
TMP93CS44/S45
1.
Prescaler
There are 9-bit prescaler and prescaler clock selection registers to generate input
clock for 8-bit timer 0, 1, 2, 3, 16-bit timer 4, 5 and serial interface 0, 1.
Figure 3.7.3 shows the block diagram. Table 3.7.1 shows prescaler clock resolution
into 8, 16-bit timer.
to CPU
System clock (fSYS)
÷2
fFPH
9-bit prescaler
2 4 8 16 32 64 128 256 512
Selector
Selector
fs
XT1
φT1
φT4
φT16
φT256
÷4
φT1
φT4
φT16
SYSCR0
<PRCK1:0>
Run/stop
and clear
Selector
X1
fc/2
fc/4
to 16-bit timer
4, 5
φ1
φT0
φT2
φT8
φT32
TRUN<PRRUN>
SYSCR1<SYSCK>
fc
to 8-bit timer
0, 1, 2, 3
÷2
to serial
interface
0, 1
fc/8 fc/16
÷2 ÷4 ÷8 ÷16
SYSCR1<GEAR2:0>
Figure 3.7.3 The Block Diagram of Prescaler
Table 3.7.1 Prescaler Clock Resolution to 8- and 16-Bit Timer
at fc = 20 MHz, fs = 32.768 kHz
Select System Select Prescaler
Clock
Clock
<PRCK1:0>
<SYSCK>
1 (fs)
0 (fc)
00 (fFPH)
Prescaler Clock Resolution
Gear Value
<GEAR2:0>
φT1
φT4
φT16
φT256
XXX
fs/2 (244 µs) fs/2 (977 µs)
fs/2 (3.9 ms)
fs/2 (62.5 ms)
000 (fc)
fc/23 (0.4 µs)
fc/25 (1.6 µs)
fc/27 (6.4 µs)
fc/211 (102.4 µs)
001 (fc/2)
fc/2 (0.8 µs)
fc/2 (3.2 µs)
fc/2 (12.8 µs)
fc/212 (204.8 µs)
010 (fc/4)
fc/2 (1.6 µs)
fc/2 (6.4 µs)
fc/2 (25.6 µs)
fc/213 (409.6 µs)
011 (fc/8)
fc/2 (3.2 µs)
fc/2 (12.8 µs) fc/2 (51.2 µs)
fc/214(819.2 µs)
100 (fc/16)
fc/2 (6.4 µs)
fc/2 (25.6 µs) fc/2 (102.4 µs) fc/215 (1.6384 ms)
3
4
5
6
7
5
6
7
8
9
XXX
01
(Low-frequency clock)
XXX
fs/23 (244 µs) fs/25 (977 µs)
XXX
10 (Note)
(fc/16 clock)
XXX
fs/27 (6.4 µs)
7
8
9
10
11
11
fs/27 (3.9 ms)
fs/211 (62.5 ms)
fc/29 (25.6 µs) fc/211 (102.4 µs) fc/215 (1.6384 ms)
XXX: Don’t care
Note: The fc/16 clock as a prescaler clock can not be used when the fs is used as a system clock.
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The clock selected among fFPH clock, fc/16 clock, and fs clock is divided by 4 and
input to this prescaler. This is selected by prescaler clock selection register
SYSCR0<PRCK1:0>.
Resetting sets <PRCK1:0> to “00”, therefore fFPH/4 clock is input.
The 8-bit timer selects between 4 clock inputs: φT1, φT4, φT16, and φT256 among the
prescaler output.
This prescaler can be run or stopped by the timer control register TRUN<PRRUN>.
Counting starts when <PRRUN> is set to “1”, while the prescaler is cleared to zero and
stops operation when <PRRUN> is set to “0”.
When the IDLE1 mode (Operates only oscillator) is used, set TRUN<PRRUN> to “0”
to stop this prescaler before “HALT” instruction is executed.
2.
Up counter
This is an 8-bit binary counter which counts up by the input clock pulse specified by
T10MOD and T32MOD.
The input clock of timer 0, 2 are selected from the external clock from TI0 (Only
timer 0) pin and the three internal clocks φT1, φT4, and φT16, according to the set
value of T10MOD/T32MOD registers.
The input clock of timer 1 and 3 differs depending on the operation mode. When set
to 16-bit timer mode, the overflow outputs of timer 0 and 2 are used as the input clock.
When set to any other mode than 16-bit timer mode, the input clock is selected from
the internal clocks φT1, φT16, and φT256 as well as the comparator output (Match
detection signal) of timer 0, 2 according to the set value of T10MOD and T32MOD
registers.
Example: When T10MOD<T10M1:0> = 01, the overflow output of timer 0 becomes the
input clock of timer 1 (16-bit timer mode).
When T10MOD<T10M1:0> = 00 and T10MOD<T1CLK1:0> = 01, φT1
becomes the input of timer 1 (8-bit timer mode).
Operation mode is also set by T10MOD and T32MOD registers. When reset, it is
initialized to T10MOD<T10M1:0> = 00 and T32MOD<T32M1:0> = 00 whereby the up
counter is placed in the 8-bit timer mode.
The counting and stop and clear of up counter can be controlled for each interval
timer by the timer operation control register TRUN. When reset, all up counters will be
cleared to stop the timers.
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3.
Timer register
This is an 8-bit register for setting an interval time. When the set value of timer
registers TREG0, TREG1, TREG2, TREG3, matches the value of up counter, the
comparator match detect signal becomes active. If the set value is 00H, this signal
becomes active when the up counter overflows.
Timer registers TREG2 are double buffer structure, each of which makes a pair with
register buffer.
The timer flip-flop controll register TRDC<TR2DE> bits control whether the double
buffer structure in the TREG2 should be enabled or disabled. They are disabled when
<TR2DE> = 0 and enabled when they are set to 1.
In the condition of double buffer enable state, the data is transfered from the register
buffer to the timer register when the 2n − 1 overflow occurs in PWM mode, or at the
PPG cycle in PPG mode. Therefore, during timer mode, the double buffer can not be
used.
When reset, it will be initialized to <TR2DE> = 0 to disable the double buffer. To use
the double buffer, write data in the timer register, set <TR2DE> to 1, and write the
following data in the register buffer.
Up counter
Comparator (CP2)
Timer register 2 (TREG2)
Matching detection of PPG
cycle
2n − 1 overflow of PWM
Shift trigger
Selector
TREG2WR
Register buffer 2
Write
Internal data bus
TRDC<TR2DE>
Figure 3.7.4 Configuration of Timer Register 2
Note:
Timer register and the register buffer are allocated to the same memory address.
When <TR2DE> = 0, the same value is written in the register buffer as well as the
timer register, while when <TR2DE> = 1 only the register buffer is written.
The memory address of each timer register is as follows.
TREG0: 000022H
TREG2: 000026H
TREG1: 000023H
TREG3: 000027H
All the registers are write only and cannot be read.
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4.
Comparator
A comparator compares the value in the up counter with the values to which the
timer register is set. When they match, the up counter is cleared to zero and an
interrupt signal (INTT0, INTT1, INTT2, INTT3) is generated. If the timer flip-flop
inversion is enabled, the timer flip-flop is inverted at the same time.
5.
Timer flip-flop (Timer F/F: TFF1, TFF3)
The timer flip-flop is a flip-flop inverted by the match detect signal (8-bit comparator
output) of each interval timer.
Inverting is disabled or enabled by the timer flip-flop control register
TFFCR<TFF3IE, TFF1IE>.
After reset operation, the value of TFF1, TFF3 is undefined. Writing 01 or 10 to
TFFCR<TFF3C1:0, TFF1C1:0> sets 0 or 1 to TFF1, TFF3. Additionally, writing 00 to
this bit inverts the value of TFF1, TFF3. (Software inversion.)
The signal of TFF3 is output through the TO3 pin (Also used as P41). When using as
the timer output, the timer flip-flop should be set by port 4 function register P4FC
beforehand. The output pin of TFF1 does not exist.
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Timer Operation Control Register
7
TRUN
(0020H)
6
Bit symbol
PRRUN
Read/Write
R/W
After reset
0
5
4
3
2
1
0
T5RUN
T4RUN
T3RUN
T2RUN
T1RUN
T0RUN
0
0
R/W
0
Function
0
0
0
Prescaler and timer run/stop control
0: Stop and clear
1: Run (Count up)
Count operation
0
Stop and clear
1
Count
PRRUN: Operation of prescaler
T5RUN : Operation of 16-bit timer (Timer 5)
T4RUN : Operation of 16-bit timer (Timer 4)
T3RUN : Operation of 8-bit timer (Timer 3)
T2RUN : Operation of 8-bit timer (Timer 2)
T1RUN : Operation of 8-bit timer (Timer 1)
T0RUN : Operation of 8-bit timer (Timer 0)
Note: TRUN<Bit6> is always read as “1”.
System Clock Control Register
SYSCR0
(006EH)
Bit symbol
7
6
5
4
3
2
1
0
XEN
XTEN
RXEN
RXTEN
RSYSCK
WUEF
PRCK1
PRCK0
1
0
1
0
0
0
0
0
Read/Write
After reset
Function
R/W
High-frequency Low-frequency High-frequency
oscillator (fc) oscillator (fs) oscillator (fc)
after released
0: Stop
0: Stop
STOP mode
1: Oscillation 1: Oscillation
0: Stop
1: Oscillation
Low-frequency
oscillator (fs)
after released
STOP mode
0: Stop
1: Oscillation
Select clock Warm-up
after released timer (Write)
STOP mode 0: Don’t care
0: fc
1: Start timer
1: fs
(Read)
0: End
warm up
1: Not end
warm up
Select prescaler clock
00: fFPH
01: fs
10: fc/16
11: (Reserved)
Select prescaler input clock
00
fFPH
01
fs
10
fc/16
11
(Reserved)
Figure 3.7.5 8-Bit Timer Related Registers (1/5)
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Timer 0, 1 Mode Control Register
T10MOD
(0024H)
Bit symbol
7
6
3
2
1
0
T10M1
T10M0
T1CLK1
T1CLK0
T0CLK1
T0CLK0
0
0
0
0
0
Read/Write
After reset
Function
5
4
R/W
0
R/W
Operation mode
00: 8-bit timer
01: 16-bit timer
10: −
11: −
Source clock of timer 1
00: TO0TRG
01: φT1
10: φT16
11: φT256
Source clock of timer 0
00: TI0
01: φT1
10: φT4
11: φT16
Input clock of timer 0
00 External Input (TI0)
01
φT1 (Prescaler)
10
φT4 (Prescaler)
11
φT16 (Prescaler)
Input clock of timer 1
T10MOD<T10M1:0> ≠ 01 T10MOD<T10M1:0> = 01
00
Comparator output Overflow output of
timer 0
of timer 0
01
Internal clock φT1
10
Internal clock φT16
11
Internal clock φT256
(16-bit timer mode)
Set the operation mode of
timer 0 and 1.
00 Two 8-bit timers (Timer 0 and timer 1)
01 16-bit timer
10 −
11 −
Figure 3.7.6 8-Bit Timer Related Register (2/5)
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Timer 2 and Timer 3 Mode Control Register
T32MOD
(0028H)
Bit symbol
7
6
5
4
3
2
1
0
T32M1
T32M0
PWM21
PWM20
T3CLK1
T3CLK0
T2CLK1
T2CLK0
0
0
0
0
0
0
0
0
Read/Write
After reset
Function
R/W
Operation mode
00: 8-bit timer
01: 16-bit timer
10: 8-bit PPG
11: 8-bit PWM
PWM cycle
00: Don’t care
01: 26 − 1
10: 27 − 1
11: 28 − 1
Source clock of timer 3
00: TO2TRG
01: φT1
10: φT16
11: φT256
Source clock of timer 2
00: −
01: φT1
10: φT4
11: φT16
Input clock of timer 2
00 Don’t set
01 φT1 (Prescaler)
10 φT4 (Prescaler)
11 φT16 (Prescaler)
Input clock of timer 3
T32MOD<T32M1:0> ≠ 01 T32MOD<T32M1:0> = 01
00
Comparator output Overflow output of
timer 2
of timer 2
01
Internal clock φT1
10
Internal clock φT16
11
Internal clock φT256
(16-bit timer mode)
Select PWM cycle
00 Don’t care
01 (26 − 1) × Input clock frequency of timer 2
10 (27 − 1) × Input clock frequency of timer 2
11 (28 − 1) × Input clock frequency of timer 2
Set the operation mode of timer 2 and 3.
00 Two 8-bit timers (Timer 0 and timer 1)
01 16-bit timer
10 8-bit PPG output
11
8-bit PWM output (Timer 2)
8-bit timer (Timer 3)
Figure 3.7.7 8-Bit Timer Related Register (3/5)
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Timer Flip-Flop Control Register
TFFCR
(0025H)
Bit symbol
7
6
5
4
3
2
1
0
TFF3C1
TFF3C0
TFF3IE
TFF3IS
TFF1C1
TFF1C0
TFF1IE
TFF1IS
1
0
0
1
1
0
Read/Write
After reset
Function
W
1
00: Invert TFF3
01: Set TFF3
10: Clear TFF3
11: Don’t care
R/W
TFF3
inversion
trigger
0: Disable
1: Enable
W
TFF3
inversion
source
0: Timer 2
1: Timer 3
Select inverse signal of timer F/F3
(“Don’t care” except in 8-bit timer mode)
0 Inversion by timer 2
1
Inversion by timer 3
Inversion of timer F/F3 (TFF3)
0 Disable invert
1
Enable invert
00:
01:
10:
11:
Invert TFF1
Set TFF1
Clear TFF1
Don’t care
TFF1
inversion
trigger
0: Disable
1: Enable
0
TFF1
inversion
source
0: Timer 0
1: Timer 1
Select inverse signal of timer F/F1
(“Don’t care” except in 8-bit timer mode)
0 Inversion by timer 0
1
Inversion by timer 1
Inversion of timer F/F1 (TFF1)
0 Disable invert
1
Control of timer F/F3 (TFF3)
Invert the value of TFF3
00
(Software inversion)
R/W
Enable invert
Control of timer F/F1 (TFF1)
Invert the value of TFF1
00
(Software inversion)
01 Set TFF3 to “1”
01 Set TFF1 to “1”.
10 Clear TFF3 to “0”
10 Clear TFF1 to “0”.
11 Don’t care (Note)
11 Don’t care (Note)
Note: TFFCR<TFF3C1:0, TFF1C1:0> is always read as “1”.
Figure 3.7.8 8-Bit Timer Related Register (4/5)
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2004-02-10
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Timer Register Double Buffer Control Register
7
TRDC
(0029H)
6
5
4
3
2
Bit symbol
1
0
−
TR2DE
Read/Write
R/W
After reset
0
0: Double
buffer
disable
1: Double
buffer
enable
Function
0
Always
write “0”.
Operation of timer register 2 double butter
0 Disable
1
Enable
Figure 3.7.9 8-Bit Timer Related Register (5/5)
(1) 8-bit timer mode
Four interval timers 0, 1, 2, 3 can be used independently as 8-bit interval timer.
1.
Generating interrupts in a fixed cycle (in case of timer 1)
To generate timer 1 interrupt at constant intervals using timer 1 (INTT1), first
stop timer 1 then set the operation mode, input clock, and a cycle to T10MOD and
TREG1 register, respectively. Then, enable interrupt INTT1 and start the
counting of timer 1.
Example: To generate timer 1 interrupt every 1 second at fs = 32 kHz, set each register in the following manner.
* Clock condition
TRUN
T10MOD
MSB
7 6 5 4 3 2 1 0
← − X − − − − 0 −
← 0 0 X X 1 0 − −
TREG1
INTET10
TRUN
← 1 1 1
← 1 1 0
← 1 X −
1
1
−
1
0
1
0
−
−
−
−
−
1
−
(
System clock: Low frequency (fs)
Prescaler clock: Low frequency (fs)
LSB
Stop timer 1, and clear it to “0”.
Set the 8-bit timer mode, and select φT16 (4 ms at fs = 32
kHz) as the input clock.
Set the timer register 1 s ÷ φT16 = 250 = FAH
Enable INTT1, and set it to Level 5.
Start timer 1 counting.
X: Don’t care, (: No change
Use the Table 3.7.1 for selecting the input clock.
Note:
The input clock of timer 0 and timer 1 are different from as follows.
Timer 0: TI0 input, (T1, (T4, (T16.
Timer 1: Match output of timer 0, (T1, (T16, (T256.
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2.
Generating a 50% duty square wave pulse
The timer flip-flop is included in timer 1 and 3.
The timer flip-flop (TFF3) is inverted at constant intervals, and its status is
output to timer output pin (TO3). The output pin of TFF1 does not exist.
Example: To output a 2.4 (s square wave pulse from TO3 pin at fc ( 20 MHz, set each register in the following
procedures. Either timer 2 or timer 3 may be used, but this example uses timer 3.
* Clock condition
T32MOD
7 6 5 4 3 2 1 0
← − X − − 0 − − −
← 0 0 X X 0 1 − −
TREG3
TFFCR
← 0
← 1
P4CR
← − − − − − − 1 −
← − X X − X X 1 X
← − X − − 1 − − −
TRUN
P4FC
TRUN
0
0
0
1
0
1
0
0
1
1
−
−
−
−
System clock: High frequency (fs)
Clock gear:
1 (fc)
Prescaler clock: fFPH
Stop timer 3, and clear it to “0”.
Set the 8-bit timer mode, and select φT1 (0.4 µs at fc = 20
MHz) as the input clock.
Set the timer register at 2.4 µs ÷ φT1 ÷ 2 = 3.
Set TFF3 to “0”, and set to invert by the match detect signal
from timer 3.
Select P41 as TO3 pin.
Start timer 3 counting.
X: Don’t care, −: No change
φT1
TRUN
<T3RUN>
Bit7 to 2
Up counter
Bit1
Bit0
0
1
2
3
0
1
2
3
0
1
2
3
0
Comparator timing
Comparator output
(Matching detect)
INTT3
UC3 clear
TFF3
TO3
1.2 µs at fc = 20 MHz
Figure 3.7.10 Square Wave (50% duty) Output Timing Chart
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3.
Making timer 1 count up by match signal from timer 0 comparator
(Same function is achieved by using timer 3 and timer 2)
Set the 8-bit timer mode, and set the comparator output of timer 0 as the input
clock to timer 1.
Comparator output
(Timer 0 match)
Timer 0 up counter
(when TREG0 = 5)
Timer 1 up counter
(when TREG1 = 2)
1
2
3
4
5
1
2
1
3
4
5
2
1
2
3
1
Timer 1 match output
Figure 3.7.11 Timer 1 Count up by Timer 0
(2) 16-bit timer mode
A 16-bit interval timer is configured by using the pair of timer 0 and timer 1 or timer
2 and timer 3.
To make a 16-bit interval timer by cascade connecting timer 0 and timer 1, set timer
0/1 mode register T10MOD<T10M1:0> to 01.
When set in 16-bit timer mode, the overflow output of timer 0 will become the input
clock of timer 1 and 3, regardless of the set value of T10MOD<T1CLK1:0> and
T32MOD<T3CLK1:0>. Table 3.7.1 shows the relation between the cycle of timer
(Interrupt) and the selection of input clock.
The lower 8 bits of the timer (Interrupt) cycle are set by the timer register TREG0 or
TREG2, and the upper 8 bits are set by TREG1 or TREG3. Note that TREG0 and
TREG2 always must be set first. (Writing data into TREG0 and TREG2 disables the
comparator temporarily, and the comparator is restarted by writing data into TREG1
and TREG3.)
Setting example: To generate an interrupt INTT3 every 0.4 seconds at fc = 20 MHz, set the following values for timer
registers TREG2 and TREG3.
* Clock condition
System clock: High frequency (fs)
Clock gear:
1 (fc)
Prescaler clock: fFPH
When counting with input clock of φT16 (6.4 µs at 20 MHz)
0.4 s ÷ 6.4 µs = 62500 = F424H
Therefore, set TREG3 = F4H and TREG2 = 24H, respectively.
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The comparator match signal is output from timer 2 each time the up counter UC2
matches TREG2, where the up counter UC2 is not be cleared.
With the timer 3 comparator, the match detect signal is output at each comparator
timing when up counter UC3 and TREG3 values match. When the match detect signal
is output simultaneously from both comparators of timer 2 and timer 3, the up
counters UC2 and UC3 are cleared to 0, and the interrupt INTT3 is generated. If
inversion is enabled, the value of the timer flip-flop TFF3 is inverted.
Example: When TREG3 = 04H and TREG2 = 80H
Value of up counter
0000H
(UC3, UC2)
Timer 2 comparator
match detect signal
0080H
0180H
0280H
0380H
0480H
Interrupt INTT3
Timer output TO3
Inversion
Figure 3.7.12 Timer Output by 16-Bit Timer Mode
(3) 8-bit PPG (Programmable pulse generation) output mode
Square wave pulse can be generated at any frequency and duty by timer 2. The
output pulse may be either low active or high active. In this mode, timer 3 cannot be
used.
Timer 2 outputs pulse to TO3 pin (Also used as P41).
tH
tL
t
TREG2 and UC2 match
(Interrupt INTT2)
TREG3 and UC2 match
(Interrupt INTT3)
TO3
TREG2
TREG3
Figure 3.7.13 8-Bit PPG Output Waveforms
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In this mode, a programmable square wave is generated by inverting timer output
each time the 8-bit up counter (UC2) matches the timer registers TREG2 and TREG3.
However, it is required that the set value of TREG2 is smaller than that of TREG3.
Though the up counter (UC3) of timer 3 is not used in this mode, UC3 should be set
for counting by setting TRUN<T3RUN> to 1.
Figure 3.7.14 shows the block diagram for this mode.
TRUN<T2RUN>
φT1
φT4
φT16
8-bit
up counter
(UC2)
Selector
TO3
TFFCR
<TFF3C1:0, TFF3IE>
TFF3
Inversion
T32MOD<T2CLK1:0>
INTT2
Comparator
INTT3
Comparator
TREG2
Selector
Shift trigger
TREG2-WR
Register buffer
TRDC<TR2DE>
TREG3
Internal data bus
Figure 3.7.14 Block Diagram of 8-Bit PPG Output Mode
When the double buffer of TREG2 is enabled in this mode, the value of register
buffer will be shifted in TREG2 each time TREG3 matches UC2.
Use of the double buffer makes easy the handling of low duty waves (when duty is
varied).
Match with TREG2
and up counter
(Up counter = Q1)
(Up counter = Q2)
Match with TREG 3
Shift from register buffer
TREG2
(Value to be compared)
Register buffer
Q1
Q2
Q2
Q3
TREG 2 (Register buffer)
write
Figure 3.7.15 Operation of Register Buffer
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Example: Generating 1/4 duty 62.5 kHz pulse (at fc = 20 MHz)
16 µs
* Clock condition
System clock: High frequency (fs)
Clock gear:
1 (fc)
Prescaler clock: fFPH
Calculate the value to be set for timer register.
To obtain the frequency 62.5 kHz, the pulse cycle t should be: t = 1/62.5 kHz = 16 µs.
Given φT1 = 0.4 µs (at 20 MHz),
16 µs ÷ 0.4 µs = 40
Consequently, to set the timer register 3 (TREG3) to TREG3 = 40 = 28H
and then duty to 1/4, t × 1/4 = 16 µs × 1/4 = 4 µs
4 µs ÷ 0.4 µs = 10
Therefore, set timer register 2 (TREG2) to TREG2 = 10 = 0AH.
7 6
− X
1 0
0 0
0 0
0 1
5
−
X
0
1
1
4
−
X
0
0
X
3
0
X
1
1
2
0
X
0
0
1
−
0
1
0
0
−
1
0
0
−
−
−
−
TRUN
T32MOD
TREG2
TREG3
TFFCR
←
←
←
←
←
P4CR
← − − − − − − 1 −
← − X X − X X 1 X
← 1 X − − 1 1 − −
P4FC
TRUN
Stop timer 2, 3 and clear it to “0”.
Set the 8-bit PPG mode, and select φT1 as input clock.
Write “0AH”.
Write “28H”.
Sets TFF3 and enable the inversion and double buffer
enable.
Writing “10” provides negative logic pulse.
Set P41 as the TO3 pin.
Start timer 2 and timer 3 counting.
X: Don’t care, −: No change
93CS44-96
2004-02-10
TMP93CS44/S45
(4) 8-bit PWM Output mode
This mode is valid only for timer 2. In this mode, maximum 8-bit resolution of PWM
pulse can be output.
PWM pulse is output to TO3 pin (also used as P41) when using timer 2. Timer 3 can
also be used as 8-bit timer.
Timer output is inverted when up counter (UC2) matches the set value of timer
register TREG2 or when 2n − 1 (n = 6, 7 or 8; specified by T32MOD<PWM21:20>)
counter overflow occurs. Up counter UC0 is cleared when 2n − 1 counter overflow
occurs.
To use this PWM mode, the following conditions must be satisfied.
(Set value of timer register) < (Set value of 2n − 1 counter overflow)
(Set value of timer register) ≠ 0
TREG2 and
UC2 match
2n − 1
Overflow
(Interrupt INTT2)
TO3
tPWM
(PWM cycle)
Figure 3.7.16 8-Bit PWM Waveforms
Figure 3.7.17 shows the block diagram of this mode.
TO3
TRUN<T2RUN>
φT1
φT4
φT16
Selector
8-bit up counter
(UC2)
TFFCR
<TFF3C1:0,
TFF3IE>
TFF3
Clear
Invert
T32MOD<T2CLK1:0>
2n − 1
overflow
control
Comparator
T32MOD
<T32M1:0> = 11
T32MOD
<PWM21:20>
Overflow
INTT2
TREG2
Selector
Shift trigger
TREG2-WR
TRDC<TR2DE>
Register buffer
Internal data bus
Figure 3.7.17 Block Diagram of 8-Bit PWM Mode
93CS44-97
2004-02-10
TMP93CS44/S45
In this mode, the value of register buffer will be shifted in TREG2 if 2n − 1 overflow is
detected when the double buffer of TREG2 is enabled.
Use of the double buffer makes easy the handling of small duty waves.
Match with TREG2
Up counter = Q1
Up counter = Q2
2n − 1 overflow
Shift into TREG2
TREG2
(Value to be compared)
Q1
Q2
Q2
Register buffer
Q3
TREG2 (Register buffer)
write
Figure 3.7.18 Operation of Register Buffer
Example: To output the following PWM waves to TO3 pin at fc = 20 MHz.
28.8 µs
50.8 µs
* Clock condition
System clock: High frequency (fs)
Clock gear:
1 (fc)
Prescaler clock: fFPH
To realize 50.8 µs of PWM cycle by φT1 = 0.4 µs (at fc = 20 MHz),
50.8 µs ÷ 0.4 µs = 127 = 2n − 1
Consequently, n should be set to 7.
As the period of low level is 28.8 µs, for φT1 = 0.4 µs,
set the following value for TREG2.
28.8 µs ÷ 0.4 µs = 72 = 48H
TRUN
T32MOD
TREG2
TFFCR
P4CR
P4FC
TRUN
MSB
7 6 5 4 3 2 1 0
← − X − − − 0 − −
← 1 1 1 0 − − 0 1
← 0 1 0
← 1 0 1
← − − −
← − X X
← 1 X −
0 1
X −
− −
− X
−
0
0
−
−
X
− 1
−
1
LSB
0
−
−
1 X
−
−
Stop timer 2, and clear it to “0”.
Set 8-bit PWM mode (cycle: 27 − 1) and select φT1 as the
input clock.
Writes “48H”.
Clears TFF3, enable the inversion and double buffer.
Set P41 as the TO3 pin.
Start timer 2 counting.
X: Don’t care, −: No change
93CS44-98
2004-02-10
TMP93CS44/S45
Table 3.7.2 PWM Cycle
at fc = 20 MHz, fs = 32.768 kHz
Select
Select
Prescaler
System
Clock
Clock
<SYSCK> <PRCK1:0>
1 (fs)
00
(fFPH)
0 (fc)
PWM Cycle
Gear Value
<GEAR2:0>
26 − 1
φT1
27 − 1
φT4
φT16
φT1
φT4
28 − 1
φT16
φT1
φT4
φT16
XXX
15.4 ms
61.5 ms
246 ms
31.0 ms
124 ms
496 ms
62.3 ms
249 ms
996 ms
000 (fc)
25.2 µs
100.8 µs
403.2 µs
50.8 µs
203.2 µs
812.8 µs
102.0 µs
408.0 µs
1.63 ms
001 (fc/2)
50.4 µs
201.6 µs
806.4 µs
101.6 µs
406.4 µs
1.63 ms
204.0 µs
816.0 µs
3.26 ms
010 (fc/4)
100.8 µs
403.2 µs
1.61 ms
203.2 µs
812.8 µs
3.26 ms
408.0 µs
1.63 ms
6.53 ms
011 (fc/8)
201.6 µs
806.4 µs
3.23 ms
406.4 µs
1.63 ms
6.52 ms
816.0 µs
3.26 ms
13.06 ms
100 (fc/16)
403.2 µs
1.61 ms
6.45 ms
812.8 µs
3.25 ms
13.04 ms
1.63 ms
6.53 ms
26.11 ms
XXX
01
(Low-frequency
clock)
XXX
15.4 ms
61.5 ms
246 ms
31.0 ms
124 ms
496 ms
62.3 ms
249 ms
996 ms
XXX
10
(fc/16 clock)
XXX
403.2 µs
1.61 ms
6.45 ms
812.8 µs
3.25 ms
13.04 ms
1.63 ms
6.53 ms
26.11 ms
XXX: Don’t care
(5) Timer mode setting registers
Table 3.7.3 shows the list of 8-bit timer modes.
Table 3.7.3 Timer Mode Setting Register
Register Name
T10MOD/T32MOD
TFFCR
Name of Function in
Register
T10M/T32M
PWM2
T1CLK/T3CLK
T0CLK/T2CLK
TFF1IS/TFF3IS
Function
Timer Mode
PWM Cycle
Upper Timer
Input Clock
Lower Timer
Input Clock
Timer F/F Invert
Signal Select
−
External clock
(Only timer 0),
φT1, φT4, φT16
(00, 01, 10, 11)
−
Lower timer
match,
φT1, 16, 256
(00, 01, 10, 11)
External clock
(Only timer 0),
φT1, φT4, φT16
(00, 01, 10, 11)
* External clock
(Only timer 0),
φT1, φT4, φT16
(00, 01, 10, 11)
*
−
* External clock
(Only timer 0),
φT1, φT4, φT16
(00, 01, 10, 11)
*
*
16-bit timer mode
01
8-bit timer × 2 channels
00
−
*
*
*
*
11
8-bit PWM × 1 channel
*
−
10
8-bit PPG × 1 channel
8-bit timer × 1 channel
−
*
*
26 − 1, 27 − 1, 28 − 1
(01, 10, 11)
*
11
−
−
φT1, φT16, φT256
(01, 10, 11)
−
0: Lower timer
output
1: Upper timer
output
−
−
Output disabled
−: Don’t care, *: Don’t set in T10MOD
93CS44-99
2004-02-10
TMP93CS44/S45
3.8
16-Bit Timers/Event Counters
The TMP93CS44/TMP93CS45 contains two (Timer 4 and timer 5) multifunctional 16-bit
timer/event counter with the following operation modes.
•
16-bit interval timer mode
•
16-bit event counter mode
•
16-bit programmable pulse generation (PPG) mode
Can be used following operation modes by capture function.
•
Frequency measurement mode
•
Pulse width measurement mode
•
Time differential measurement mode
Timer/event counter consists of 16-bit up counter, two 16-bit timer registers, two 16-bit
capture registers (One of them applies double buffer), two comparators, capture input controller,
and timer flip-flop and the control circuit.
Timer/event counter is controlled by 4 control registers: T4MOD/T5MOD, T4FFCR/T5FFCR,
TRUN and T45CR.
Figure 3.8.1, 2 shows the block diagram of 16-bit timer/event counter (Timer 4 and timer 5).
Timer 4 and 5 can be used independently.
All timers operate in the same manner, and thus only the operation of timer 4 will be
explained below.
93CS44-100
2004-02-10
TI5
TI4
TFF1
Selector
93CS44-101
Upper byte
Register buffer4
TREG4
Comparator
CP4
16-bit up counter
UC4
T45CR<DB4EN >
Lower byte
Selector
Internal data bus
TREG4-WR
TRUN<T4RUN>
Match detection
Count clock
Trigger
T4MOD<T4CLK1:0>
TI4 external input
φT1
φT4
φT16
T4MOD
<CAP12M1:0>
Capture
control
T4MOD<CAP1IN>
Software capture
Lower byte
Capture register 1
CAP1
Upper byte
Internal data bus
INTTO4
Lower byte
Upper byte
TREG5
Comparator
CP5
T4MOD<CLE>
TRUN<T4RUN>
Capture register 2
CAP2
Clear
Trigger
Upper byte
Lower byte
Match
detection
control
F/F
Timer
T4FFCR
TFF4
TO4
TMP93CS44/S45
INTTR4
INTTR5
INT4
INT5
Figure 3.8.1 Block Diagram of 16-Bit Timer (Timer 4)
2004-02-10
TI7
TI6
TFF1
Selector
93CS44-102
Upper byte
Register buffer 6
TREG6
Comparator
CP6
16-bit up counter
UC5
T45CR<DB6EN >
Lower byte
Selector
Internal data bus
TREG6-WR
TRUN<T5RUN>
Match detection
Count clock
Trigger
T5MOD<T6CLK1:0>
TI6 external input
φT1
φT4
φT16
T5MOD
<CAP34M1:0>
Capture
control
T5MOD<CAP3IN>
Software capture
Lower byte
Capture register 3
CAP3
Upper byte
Internal data bus
INTTO5
Clear
Trigger
Lower byte
Upper byte
TREG7
Comparator
CP7
T5MOD<CLE>
TRUN<T5RUN>
Capture register 4
CAP4
Upper byte
Lower byte
Match
detection
control
F/F
Timer
T5FFCR
TFF6
TO6
TMP93CS44/S45
INTTR7
INTTR6
INT6
INT7
Figure 3.8.2 Block Diagram of 16-Bit Timer (Timer 5)
2004-02-10
TMP93CS44/S45
Timer 4 Mode Control Register
7
T4MOD
(0038H)
6
5
Bit symbol
CAP1IN
Read/Write
W
After reset
1
Function
4
3
CAP12M1 CAP12M0
2
1
0
CLE
T4CLK1
T4CLK0
0
0
R/W
0
0
0: Software Capture timing
capture
00: Disable
1: Don’t care
INT4 occurs at rising
edge.
01: TI4↑
TI5↑
INT4 occurs at rising
edge.
10: TI4↑
TI4↓
INT4 occurs at rising
edge.
11: TFF1↑ TFF1↓
INT4 occurs at rising
edge.
0
0: UC4
clear
disable
1: UC4
clear
enable
Timer 4 source clock
00: TI4 pin
01: φT1
10: φT4
11: φT16
Timer 4 input clock
00 External clock (TI4)
01
φT1
10
φT4
11
φT16
Clearing the up counter UC4
0 Clear disable
1
Clear by match with TREG5.
Capture timing of timer4
Capture control
00 Capture disable
INT4 control
01
CAP1 at TI4 rise
CAP2 at TI5 rise
Interrupt occurs at the
rising edge of TI4
(INT4) input.
10
CAP1 at TI4 rise
CAP2 at TI4 fall
Interrupt occurs at the
falling edge of
TI4 (INT4) input.
11
CAP1 at TFF1 rise
CAP2 at TFF1 fall
Interrupt occurs at the
rising edge of TI4
(INT4) input.
Software capture control
0 The up counter 4 value is loaded to CAP1.
1
Don’t care
Figure 3.8.3 16-Bit Timer/Event Counter Related Register (1/6)
93CS44-103
2004-02-10
TMP93CS44/S45
Timer 4 Flip-Flop Control Register
7
T4FFCR
(0039H)
Bit symbol
6
5
4
3
2
1
0
CAP2T4
CAP1T4
EQ5T4
EQ4T4
TFF4C1
TFF4C0
0
0
Read/Write
After reset
Function
R/W
0
0
TTF4 invert trigger
0: Disable trigger
1: Enable trigger
Invert when Invert when
the UC
the UC
value is
value is
loaded to loaded to
CAP2
CAP1
W
1
1
00: Invert TFF4
01: Set TFF4
10: Clear TFF4
Invert when Invert when 11: Don’t care
the UC
the UC
Always read as “11”.
matches
matches
TREG5
TREG4
Timer flip-flop 4 (TFF4) control
00 Inverts the TFF4 value (Software inversion).
01 Sets TFF4 to “1”.
10 Clear TFF4 to “0”.
11 Don’t care (Always read as “11”.)
Invert when the UC matches TREG4
Timer flip-flop 4 (TFF4) invert trigger
0 Trigger disable (Invert prohibition)
1
Trigger enable (Invert permission)
Invert when the UC matches TREG5
Timer flip-flop 4 (TFF4) invert trigger
0 Trigger disable (Invert prohibition)
1
Trigger enable (Invert permission)
Invert when the UC value is loaded to CAP1
Timer flip-flop 4 (TFF4) invert trigger
0 Trigger disable (Invert prohibition)
1
Trigger enable (Invert permission)
Invert when the UC value is loaded to CAP2
Timer flip-flop 4 (TFF4) invert trigger
0 Trigger disable (Invert prohibition)
1
Trigger enable (Invert permission)
Figure 3.8.4 16-Bit Timer/Event Counter Related Register (2/6)
93CS44-104
2004-02-10
TMP93CS44/S45
Timer 5 Mode Control Register
7
T5MOD
(0048H)
6
5
Bit symbol
CAP3IN
Read/Write
W
After reset
1
Function
0: Software
capture
1: Don’t care
4
3
CAP34M1 CAP34M0
2
1
0
CLE
T5CLK1
T5CLK0
0
0
R/W
0
0
Capture timing
00: Disable
INT6 occurs at rising
edge.
01: TI6↑
TI7↑
INT6 occurs at rising
edge.
10: TI6↑
TI6↓
INT6 occurs at fall
edge.
11: TFF1↑ TFF1↓
INT6 occurs at rising
edge.
0
0: UC5
clear
disable
1: UC5
clear
enable
Timer 5 source clock
00: TI6 pin
01: φT1
10: φT4
11: φT16
Timer 5 input clock
00 External clock (TI6)
01
φT1
10
φT4
11
φT16
Clearing the up counter UC5
0
Clear disable
1
Clear by match with TREG7
Timer 5 capture timing
Capture control
00 Capture disable
01
CAP3 at TI6 rise
CAP4 at TI7 rise
INT6 Control
Interrupt occurs at the
rising edge of TI6
(INT6) input.
CAP3 at TI6 rise
10 CAP4 at TI6 fall
Interrupt occurs at the
falling edge of
TI6 (INT6) input.
CAP3 at TFF1 rise
11 CAP4 at TFF1 fall
Interrupt occurs at the
rising edge of TI6
(INT6) input.
Software capture control
0 The up counter 5 value is loaded to CAP3.
1
Don’t care
Figure 3.8.5 16-Bit Timer/Event Counter Related Register (3/6)
93CS44-105
2004-02-10
TMP93CS44/S45
Timer 5 Flip-Flop Control Register
7
T5FFCR
(0049H)
Bit symbol
6
5
4
3
2
1
0
CAP4T6
CAP3T6
EQ7T6
EQ6T6
TFF6C1
TFF6C0
0
0
Read/Write
After reset
Function
R/W
0
0
TTF6 invert trigger
0: Disable trigger
1: Enable trigger
Invert when Invert when
the UC
the UC
value is
value is
loaded to loaded to
CAP4
CAP3
W
1
1
00: Invert TFF6
01: Set TFF6
10: Clear TFF6
Invert when Invert when 11: Don’t care
the UC
the UC
Always read as “11”.
matches
matches
TREG7
TREG6
Timer flip-flop 6 (TFF6) control
00 Inverts the TFF6 value (Software inversion).
01 Sets TFF6 to “1”.
10 Clear TFF6 to “0”.
11 Don’t care (Always read as “11”.)
Invert when the UC matches TREG6
Timer flip-flop 6 (TFF6) invert trigger
0 Trigger disable (Invert prohibition)
1
Trigger enable (Invert permission)
Invert when the UC matches TREG7
Timer flip-flop 6 (TFF6) invert trigger
0 Trigger disable (Invert prohibition)
1
Trigger enable (Invert permission)
Invert when the UC value is loaded to CAP3
Timer flip-flop 6 (TFF6) invert trigger
0 Trigger disable (Invert prohibition)
1
Trigger enable (Invert permission)
Invert when the UC value is loaded to CAP4
Timer flip-flop 6 (TFF6) invert trigger
0 Trigger disable (Invert prohibition)
1
Trigger enable (Invert permission)
Figure 3.8.6 16-Bit Timer/Event Counter Related Register (4/6)
93CS44-106
2004-02-10
TMP93CS44/S45
Timer 4 and Timer 5 Control Register
7
T45CR
(003AH)
Bit symbol
QCU
Read/Write
R/W
After reset
Function
6
5
4
3
2
1
0
DB6EN
DB4EN
R/W
0
Watchdog
timer/
warm-up
timer
control
0
0
Double buffer
0: Disable
1: Enable
Double
Double
buffer of
buffer of
TREG6
TREG4
Double buffer control
0
Disable
1
Enable
DB6EN: Double buffer of TREG6
DB4EN: Double buffer of TREG4
Watchdog timer/warm-up timer input control
0
Use 7 stage binary counter
1
Note 1:
Not use 7 stage binary counter (Note 1)
In case of unused 7 state binary counter as a warm-up timer, the stable clock must be input from external
circuit.
Note 2:
Bit6 to 2 of T45CR is read as 1.
Figure 3.8.7 16-Bit Timer/Event Counter Related Register (5/6)
93CS44-107
2004-02-10
TMP93CS44/S45
Timer Operation Control Register
7
TRUN
(0020H)
Bit symbol
PRRUN
Read/Write
R/W
After reset
0
6
5
4
3
2
1
0
T5RUN
T4RUN
T3RUN
T2RUN
T1RUN
T0RUN
0
0
R/W
0
Function
0
0
0
Prescaler and timer run/stop control
0: Stop and clear
1: Run (Count up)
Count operation
0
Stop and clear
1
Count
PRRUN: Operation of prescaler
T5RUN: Operation of 16-bit timer (Timer 5)
T4RUN: Operation of 16-bit timer (Timer 4)
T3RUN: Operation of 8-bit timer (Timer 3)
T2RUN: Operation of 8-bit timer (Timer 2)
T1RUN: Operation of 8-bit timer (Timer 1)
T0RUN: Operation of 8-bit timer (Timer 0)
Note: Bit6 of TRUN is read as “1”.
System Clock Control Register
SYSCR0
(006EH)
Bit symbol
7
6
5
4
3
2
1
0
XEN
XTEN
RXEN
RXTEN
RSYSCK
WUEF
PRCK1
PRCK0
1
0
1
0
0
0
0
0
Read/Write
After reset
Function
R/W
High-frequency Low-frequency High-frequency Low-frequency Select clock Warm-up
oscillator (fc) oscillator (fs) oscillator (fc) oscillator (fc) after released timer
after released after released STOP mode (Write)
STOP mode STOP mode
0: Stop
0: Stop
0: Don’t care
0: Stop
0: fc
1: Oscillaton 1: Oscillaton 0: Stop
1: Start timer
1: Oscillaton 1: Oscillaton 1: fs
(Read)
0: End
warm up
1: Not end
warm up
Select gear value of
high frequency (fs)
00: fFPH
01: fs
10: fc/16
11: (Reserved)
Select gear value of high frequency
00
fFPH
01
fs
10
fc/16
11
(Reserved)
1/4 times clock
Figure 3.8.8 16-Bit Timer/Event Counter Related Registers (6/6)
93CS44-108
2004-02-10
TMP93CS44/S45
1.
Prescaler
There are 9-bit prescaler and prescaler clock selection registers to generate input
clock for 8-bit timer 0, 1, 2, 3, 16-bit timer 4, 5 and serial interface 0, 1.
Figure 3.8.9 shows the block diagram. Table 3.8.1 shows prescaler clock resolution
into 8, 16-bit Timer.
to CPU
System clock fSYS
÷2
fFPH
9-bit prescaler
2 4 8 16 32 64 128 256 512
Selector
Selector
÷4
fs
XT1
SYSCR0
<PRCK1:0>
Run/stop
and clear
Selector
TRUN<PRRUN>
SYSCR1<SYSCK>
fc
X1
fc/2
fc/4
÷2
φT1
φT4
φT16
φT256
To 8-bit timer
0, 1, 2, 3
φT1
φT4
φT16
To 16-bit timer
4, 5
φ1
φT0
φT2
φT8
φT32
To serial
interface
0, 1
fc/8 fc/16
÷2 ÷4 ÷8 ÷16
SYSCR1<GEAR2:0>
Figure 3.8.9 The Block Diagram of Prescaler
Table 3.8.1 Prescaler Clock Resolution to 8-Bit Timer and 16-Bit Timer
at fc = 20 MHz, fs = 32.768 kHz
Select System Select Prescaler
Clock
Clock
<SYSCK>
<PRCK1:0>
1 (fs)
0 (fc)
00 (fFPH)
Prescaler Clock Resolution
Gear Value
<GEAR2:0>
φT1
φT4
φT16
φT256
XXX
fs/2 (244 µs) fs/2 (977 µs)
fs/2 (3.9 ms)
fs/2 (62.5 ms)
000 (fc)
fc/23 (0.4 µs)
fc/25 (1.6 µs)
fc/27 (6.4 µs)
fc/211 (102.4 µs)
001 (fc/2)
fc/2 (0.8 µs)
fc/2 (3.2 µs)
fc/2 (12.8 µs)
fc/212 (204.8 µs)
010 (fc/4)
fc/2 (1.6 µs)
fc/2 (6.4 µs)
fc/2 (25.6 µs)
fc/213 (409.6 µs)
011 (fc/8)
fc/2 (3.2 µs)
fc/2 (12.8 µs) fc/2 (51.2 µs)
fc/214(819.2 µs)
100 (fc/16)
fc/2 (6.4 µs)
fc/2 (25.6 µs) fc/2 (102.4 µs) fc/215 (1.6384 ms)
3
4
5
6
7
5
6
7
8
9
XXX
01
(Low-frequency
clock)
XXX
fs/23 (244 µs) fs/25 (977 µs)
XXX
10 (Note)
(fc/16 clock)
XXX
fc/27 (6.4 µs)
7
8
9
10
11
11
fs/27 (3.9 ms)
fs/211 (62.5 ms)
fc/29 (25.6 µs) fc/211 (102.4 µs) fc/215 (1.6384 ms)
16-bit timer
8-bit timer
XXX: Don’t care
Note: The fc/16 clock as a prescaler clock can not be used when the fs is used as a system clock.
93CS44-109
2004-02-10
TMP93CS44/S45
The clock selected among fFPH clock, fc/16 clock, and fs clock is divided by 4 and
input to this prescaler. This is selected by prescaler clock selection register
SYSCR0<PRCK1:0>.
Resetting sets <PRCK1:0> to 00, therefore fFPH/4 clock is input.
The 16-bit timer 4, 5 selects between 3 clock inputs: φT1, φT4, and φT16 among the
prescaler outputs.
This prescaler can be run or stopped by the timer operation control register
TRUN<PRRUN>. Counting starts when <PRRUN> is set to 1, while the prescaler is
cleared to 0 and stops operation when <PRRUN> is set to 0.
When the IDLE1 mode (Operates only oscillator) is used, set TRUN<PRRUN> to 0 to
stop this prescaler before “HALT” instruction is executed.
2.
Up counter
UC4 is a 16-bit binary counter which counts up according to the input clock specified
by T4MOD<T4CLK1:0> register.
As the input clock, one of the internal clocks φT1, φT4, and φT16 from 9-bit prescaler
(also used for 8-bit timer), and external clock from TI4 pin (also used as P42/INT4 pin)
can be selected. When reset, it will be initialized to <T4CLK1:0> = 00 to select TI4
input mode. Counting or stop and clear of the counter is controlled by timer operation
control register TRUN<T4RUN>.
When clearing is enabled, up counter UC4 will be cleared to 0 each time it coincides
matches the timer register TREG5. The “clear enable/disable” is set by T4MOD<CLE>.
If clearing is disabled, the counter operates as a free-running counter.
A timer overflow interrupt (INTTO4) is generated when UC4 overflow occurs.
3.
Timer registers
These two 16-bit registers are used to set the interval time. When the value of up
counter UC4 matches the set value of this timer register, the comparator match detect
signal will be active.
Setting data for both upper and lower timer registers (TREG4 and TREG5) is always
needed. For example, either using 2-byte data transfer instruction or using 1-byte data
transfer instruction twice for lower 8 bits and upper 8 bits in order.
Timer 4
TREG5
TREG4
Upper 8 bits
(TREG4H)
Lower 8 bits
(TREG4L)
Upper 8 bits
(TREG5H)
Lower 8 bits
(TREG5L)
000031H
000030H
000033H
000032H
Timer 5
TREG7
TREG6
Upper 8 bits
(TREG6H)
Lower 8 bits
(TREG6L)
Upper 8 bits
(TREG7H)
Lower 8 bits
(TREG7L)
000041H
000040H
000043H
000042H
TREG4 to TREG7 are write-only registers, so they can not be read by software.
93CS44-110
2004-02-10
TMP93CS44/S45
TREG4 timer register is of double buffer structure, which is paired with register
buffer. The timer control register T45CR<DB4EN> controls whether the double buffer
structure should be enabled or disabled. Disabled when <DB4EN> = 0, while enabled
when <DB4EN> = 1.
When the double buffer is enabled, the timing to transfer data from the register
buffer to the timer register is at the match between the up counter (UC4) and timer
register TREG5.
After reset, TREG4 and TREG5 are undefined. To use the 16-bit timer after reset,
data should be written beforehand.
When reset, it will be initialized to <DB4EN> = 0, whereby the double buffer is
disabled. To use the double buffer, write data in the timer register, set <DB4EN> = 1,
and then write the following data in the register buffer.
TREG4 and register buffer are allocated to the same memory addresses
000030H/000031H. When <DB4EN> = 0, same value will be written in both the timer
register and register buffer. When <DB4EN> = 1, the value is written into only the
register buffer.
4.
Capture register
These 16-bit registers are used to latch the values of the up counter.
Data in the capture registers should be read all 16 bits. For example, using a 2-byte
data load instruction or two 1-byte data load instruction, from the lower 8-bit followed
by the upper 8 bits.
Timer 4
CAP2
CAP1
Upper 8 bits
(CAP1H)
Lower 8 bits
(CAP1L)
Upper 8 bits
(CAP2H)
Lower 8 bits
(CAP2L)
000035H
000034H
000037H
000036H
Timer 5
CAP4
CAP3
Upper 8 bits
(CAP3H)
Lower 8 bits
(CAP3L)
Upper 8 bits
(CAP4H)
Lower 8 bits
(CAP4L)
000045H
000044H
000047H
000046H
CAP1 to CAP4 are read-only registers, so it cannot be written by software.
93CS44-111
2004-02-10
TMP93CS44/S45
5.
Capture input control
This circuit controls the timing to latch the value of up counter UC4 into CAP1,
CAP2. The latch timing of capture register is controlled by register T4MOD<CAP12M
1:0>.
•
When T4MOD<CAP12M1:0> = 00
Capture function is disabled. Disable is the default on reset.
•
When T4MOD<CAP12M1:0> = 01
Data is loaded to CAP1 at the rise edge of TI4 pin (also used as P42/INT4) input,
while data is loaded to CAP2 at the rise edge of TI5 pin (also used as P43/INT5)
input.
•
When T4MOD<CAP12M1:0> = 10
Data is loaded to CAP1 at the rise edge of TI4 pin input, while to CAP2 at the fall
edge. Only in this setting, interrupt INT4 occurs at fall edge.
•
When T4MOD<CAP12M1:0> = 11
Data is loaded to CAP1 at the rise edge of timer flip-flop TFF1, while to CAP2 at
the fall edge.
Besides, the value of up counter can be loaded to capture registers by software.
Whenever “0” is written in T4MOD<CAP1IN> the current value of up counter will be
loaded to capture register CAP1. It is necessary to keep the prescaler in RUN mode
(TRUN<PRRUN> to be “1”).
6.
Comparator
These are 16-bit comparators which compare the up counter UC4 value with the set
value of (TREG4, TREG5) to detect the match. When a match is detected, the
comparators generate an interrupt (INTTR4, INTTR5) respectively. The up counter
UC4 is cleared only when UC4 matches TREG5. (The clearing of up counter UC4 can
be disabled by setting T4MOD<CLE> = 0.)
7.
Timer flip-flop (TFF4)
This flip-flop is inverted by the match detect signal from the comparators and the
latch signals to the capture registers. Disable/enable of inversion can be set for each
element by T4FFCR<CAP2T4, CAP1T4, EQ5T4, EQ4T4>. After reset, the value of
TFF4 is undefined. TFF4 will be inverted when “00” is written in T4FFCR<TFF4C1:0>.
Also it is set to “1” when “01” is written, and set to “0” when “10” is written. The value
of TFF4 can be output to the timer output pin TO4 (also used as P44). Timer output
should be specified by the function register of port 4. (See register for port 4 in Figure
3.5.11.)
93CS44-112
2004-02-10
TMP93CS44/S45
(1) 16-bit timer mode
Generating interrupts at fixed intervals
In this example, the interval time is set in the timer register TREG5 to generate the
interrupt INTTR5.
7
TRUN
INTET54
T4FFCR
T4MOD
TREG5
TRUN
4
3
2
1
0
← −
← 1
← X
← 0
X − 0
1 0 0
X 0 0
0 1 0
6
5
−
1
0
0
− −
0 0
0 1
1 *
−
0
1
*
← *
*
← 1
(** = 01, 10, 11)
* * * * * *
* * * * * *
X − 1 − − −
*
*
−
Stop timer 4.
Enable INTTR5 and sets interrupt level 4. Disable INTTR4.
Disable trigger.
Select internal clock for input and disable the capture
function.
Set the interval time (16 bits).
Start timer 4.
X: Don’t care, −: No change
(2) 16-bit event counter mode
In 16-bit timer mode as described in above, the timer can be used as an event counter
by selecting the external clock (TI4 pin input) as the input clock. To read the value of
the counter, first perform “software capture” once and read the captured value.
The counter counts at the rise edge of TI4 pin input.
TI4 pin can also be used as P42/INT4.
Since both timers operate in exactly the same way, timer 4 is used for the purposes of
explanation.
5
4
3
2
1
0
TRUN
P4CR
INTET54
← −
← −
← 1
7
X −
− −
1 0
0
−
0
−
−
1
− −
0 −
0 0
−
−
0
Stop timer 4.
Set P42 to input mode.
Enable INTTR5 and sets interrupt level 4, while disables
INTTR4.
T4FFCR
T4MOD
TREG5
TRUN
←
←
←
←
X
0
*
X
0 0
1 0
* *
− 1
0
0
*
−
0 1
1 0
* *
− −
1
0
*
−
Disable trigger.
Select TI4 as the input clock.
Set the number of counts (16 bits).
Start timer 4.
X
0
*
1
6
X: Don’t care, −: No change
When used as an event counter, set the prescaler in RUN mode. (TRUN<PRRUN> = 1)
93CS44-113
2004-02-10
TMP93CS44/S45
(3) 16-bit programmable pulse generation (PPG) output mode
Square wave pulse can be generated at any frequency and duty by timer 4. The
output pulse may be either low active or high active.
The PPG mode is obtained by inversion of the timer flip-flop TFF4 that is to be
enabled by the match of the up counter UC4 with the timer register TREG4 or TREG5
and to be output to TO4 (also used as P44). In this mode, the following conditions must
be satisfied.
(Set value of TREG4) < (Set value of TREG5)
Match with TREG4
(Interrupt INTTR4)
Match with TREG5
(Interrupt INTTR5)
TO4 pin
Figure 3.8.10 Programmable Pulse Generation (PPG) Output Waveforms
When the double buffer of TREG4 is enabled in this mode, the value of register
buffer 4 will be shifted in TREG4 at match with TREG5. This feature makes easy the
handling of low duty waves.
Match with TREG4
Up counter = Q1
Up counter = Q2
Match with TREG5
Shift into the TREG5
TREG4
(Value to be compared)
Q1
Q2
Q2
Register buffer
Q3
Write into the TREG4
Figure 3.8.11 Operation of Register Buffer
93CS44-114
2004-02-10
TMP93CS44/S45
Shows the block diagram of this mode.
TRUN<T4RUN>
TI4 pin
φT1
φT4
φT16
16-bit up counter
UC4
Selector
Match
16-bit comparator
Clear
TO4 (PPG output)
F/F
(TFF4)
16-bit comparator
TREG4
Selector
TREG4-WR
Register buffer 4
T45CR<DB4EN>
TREG5
Internal data bus
Figure 3.8.12 Block Diagram of 16-Bit PPG Mode
In 16-bit PPG mode, set the registers is the following order:
7
6
5
4
3
2
1
0
0
−
*
*
0
X
X
*
*
X
X
−
*
*
X
X
0
*
*
X
X
−
*
*
X
X
−
*
*
X
−
−
*
*
−
0
−
*
*
1
T4FFCR
← X X 0
0
1
1
1
0
T4MOD
← 0
0
0
0
1
*
*
P4CR
← −
(** = 01, 10, 11)
− − 1 − − −
−
P4FC
TRUN
← −
← 1
X X 1
X − 1
X X −
− − −
X
−
T45CR
TRUN
TREG4
TREG5
T45CR
←
←
←
←
←
1
Double buffer of TRG4 disable.
Stop timer 4.
Set the duty (16 bits).
Set the cycle (16 bits).
Double buffer of TREG4 enable.
(Change the duty and cycle at the interrupt INTTR5.)
Set the mode to invert TFF4 at the match with
TREG4/TREG5, and also set the TFF4 to “0”.
Select the internal clock for the input, and disable the capture
function.
Assign P44 as TO4.
Start timer 4.
X: Don’t care, −: No change
93CS44-115
2004-02-10
TMP93CS44/S45
(4) Application examples of capture function
Used capture function, they can be applied in many ways, for example:
1. One-shot pulse output from external trigger pulse
2. Frequency measurement
3. Pulse width measurement
4. Time difference measurement
1.
One-shot pulse output from external trigger pulse
Set to T4MOD<CAP12M1:0> = 01.
Set the up counter UC4 in free-running mode with the internal input clock,
input the external trigger pulse from TI4 pin, and load the value of up counter into
capture register CAP1 at the rise edge of the TI4 pin.
When the interrupt INT4 is generated at the rise edge of TI4 input, set the
CAP1 value (c) plus a delay time (d) to TREG4 (= c + d), and set the above set value
(c + d) plus a one-shot pulse width (p) to TREG5 (= c + d + p). When the interrupt
INT4 occurs the T4FFCR<EQ5T4, EQ4T4>register should be set “11” and that the
TFF4 inversion is enabled only when the up counter value matches TREG4 or
TREG5. When interrupt INTTR5 occurs, this inversion will be disabled after
one-shot pulse is output.
The (c), (d) and (p) correspond to c, d and p in Figure 3.8.13.
Set the counter in free-running mode.
Count clock
(Internal clock)
TI4 pin input
(External trigger pulse)
c+d
c
c+d+p
Load the up counter value into capture
register 1 (CAP1) INT4 occurred
Match with TREG4
Match with TREG5
Timer output pin TO4
Inversion
enable
Disables inversion
caused by loading
of the up counter
value into CAP1.
Delay time
(d)
INTTR5 occurred
Inversion
enable
Pulse width
(p)
Figure 3.8.13 One-shot Pulse Output (with Delay)
93CS44-116
2004-02-10
TMP93CS44/S45
Setting example: To output 2 ms one-shot pulse with 3 ms delay to the external trigger
pulse to TI4 pin
* Clock condition
System clock: High frequency (fs)
Clock gear:
1 (fc)
Prescaler clock: fFPH
Main setting
Keep counting (Free runnig)
Count with φT1
T4MOD
← −
−
1
0
1
0
0
1
Load the up counter value into CAP1 at the rise edge of TI4
pin input.
T4FFCR
← X X 0
0
0
0
1
0
Clear TFF4 to 0.
Disable TFF4 inversion.
P4CR
← −
−
−
−
P4FC
INTE45
← −
← −
X X 1
− − −
−
X X −
1 1 0
X
0
INTET54
TRUN
← 1
← 1
0 0
X −
1
−
0 0
− −
0
−
← CAP1 + 3 ms/φT1
← TREG4 + 2 ms/φT1
← X X − − 1 1 −
−
1
0
1
−
−
Select P44 as the TO4 pin.
Enable INT4, and disable INTTR4 and INTTR5.
Start timer 4.
Setting of INT4
TREG4
TREG5
T4FFCR
Enable TFF4 inversion when the up counter value matches
TREG4 or TREG5.
INTET54
← 1
0
0
−
−
−
−
← X X −
−
0
0 −
−
1
Enable INTTR5.
Setting of INTTR5
T4FFCR
INTET54
← 1
1
0
0
−
−
−
−
Disable TFF4 inversion when the up counter value matches
TREG4 or TREG5.
Disable INTTR5.
X: Don’t care, −: No change
When delay time is unnecessary, invert timer flip-flop (TFF4) when the up
counter value is loaded into capture register 1 (CAP1), and set the CAP1 value (c)
plus the one-shot pulse width (p) to TREG5 when the interrupt INT4 occurs. The
TFF4 inversion should be enabled when the up counter (UC4) value matches
TREG5, and disabled when generating the interrupt INTTR5.
93CS44-117
2004-02-10
TMP93CS44/S45
Count clock
(Internal clock)
c+p
c
TI4 pin input
(External trigger pulse)
Load the up counter value into capture
register 1 (CAP1). INT4 occurred
INTTR5 occurred
Load the up-counter value into
capture register 2 (CAP2).
Match with TREG5
Inversion enable
Timer output pin TO4
Pulse width
(p)
Disables inversion caused by loading of
the up counter value into CAP2.
Enables inversion caused by
loading of the up counter
value into CAP1.
Figure 3.8.14 One-shot Pulse Output (without Delay)
2.
Frequency measurement
The frequency of the external clock can be measured in this mode. The clock is
input through the TI4 pin, and its frequency is measured by the 8-bit timers
(Timer 0 and timer 1) and the 16-bit timer/event counter (Timer 4).
The TI4 pin input should be selected for the input clock of Timer 4. Set to
T4MOD<CAP12M1:0> = 11. The value of the up counter is loaded into the capture
register CAP1 at the rise edge of the timer flip-flop (TFF1) of 8-bit timers (Timer 0
and timer 1), and into CAP2 at its fall edge.
The frequency is calculated by the difference between the loaded values in
CAP1 and CAP2 when the interrupt (INTT0 or INTT1) is generated by either 8-bit
timer.
Count clock
(Internal clock)
C1
C2
TFF1
Loading UC16 into CAP1
Loading UC16 into CAP2
C1
C1
C2
C2
INTT0/INTT1
Figure 3.8.15 Frequency Measurement
For example, if the value for the level “1” width of TFF1 of the 8-bit timer is set
to 0.5 seconds and the difference between CAP1 and CAP2 is 100, the frequency
will be 100 ÷ 0.5 [s] = 200 [Hz].
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2004-02-10
TMP93CS44/S45
3.
Pulse width measurement
This mode allows to measure the “H” level width of an external pulse. While
keeping the 16-bit timer/event counter counting (Free running) with the internal
clock input, the external pulse is input through the TI4 pin. Then the capture
function is used to load the UC4 values into CAP1 and CAP2 at the rising edge
and falling edge of the external trigger pulse respectively. The interrupt INT4
occurs at the falling edge of TI4.
The pulse width is obtained from the difference between the values of CAP1 and
CAP2 and the internal clock cycle.
For example, if the internal clock is 0.8 microseconds and the difference
between CAP1 and CAP2 is 100, the pulse width will be 100 × 0.8 µs = 80 µs.
Additionally, the pulse width which is over the UC4 maximum count time
specified by the clock source can be measured by changing software.
Count clock
(Internal clock)
C1
C2
TI4 pin (External pulse)
Loading UC16 into CAP1
C1
C1
C2
Loading UC16 into CAP2
C2
INT4
Figure 3.8.16 Pulse Width Measurement
Note:
Only in this pulse width measuring mode (T4MOD<CAP12M1:0> = 10),
external interrupt INT4 occurs at the falling edge of TI4 pin input. In other
modes, it occurs at the rising edge.
The width of “L” level can be measured by multiplying the difference between
the first C2 and the second C1 at the second INT interrupt and the internal clock
cycle together. See Figure 3.8.17 “Time Difference Measurement”.
93CS44-119
2004-02-10
TMP93CS44/S45
4.
Time difference measurement
This mode is used to measure the difference in time between the rising edges of
external pulses input through TI4 and TI5.
Keep the 16-bit timer/event counter (Timer 4) counting (Free running) with the
internal clock, and load the UC4 value into CAP1 at the rising edge of the input
pulse to TI4. Then the interrupt INT4 is generated.
Similarly, the UC4 value is loaded into CAP2 at the rising edge of the input
pulse to TI5, generating the interrupt INT5.
The time difference between these pulses can be obtained from the difference
between the time counts at which loading the up counter value into CAP1 and
CAP2 was performed. (= (CAP2 − CAP1) × the internal clock cycle.)
Count clock
(Internal clock)
C1
C2
TI4 pin input
TI5 pin input
Loading UC16 into CAP1
Loading UC16 into CAP2
INT4
INT5
Time difference
Figure 3.8.17 Time Difference Measurement
93CS44-120
2004-02-10
TMP93CS44/S45
3.9
Serial Channel
TMP93CS44/TMP93CS45 contains 2 serial I/O channels for full duplex asynchronous
transmission (UART) as well as for I/O extension.
The serial channel has the following operation modes.
I/O interface mode
(Channel 0 and 1)
Mode 0: To transmit and receive I/O data using
the synchronizing signal SCLK for
extending I/O.
UART mode
(Channel 0 and 1)
Mode 1: 7-bit data
Mode 2: 8-bit data
Mode 3: 9-bit data
In mode 1 and mode 2, a parity bit can be added. Mode 3 has wakeup function for making the
master controller start slave controllers in serial link (Multi-controller system).
Figure 3.9.1 shows the data format (for one frame) in each mode.
Serial channel 0 and 1 can be used independently.
• Mode 0 (I/O interface mode)
Bit0
1
2
3
4
5
6
7
Transfer direction
• Mode 1 (7-bit UART mode)
No parity
Start
Bit0
1
2
3
4
5
6
Stop
Parity
Start
Bit0
1
2
3
4
5
6
Parity Stop
• Mode 2 (8-bit UART mode)
No parity
Start
Bit0
1
2
3
4
5
6
7
Stop
Parity
Start
Bit0
1
2
3
4
5
6
7
Parity Stop
• Mode 3 (9-bit UART mode)
Start
Bit0
1
2
3
4
5
6
7
Start
Bit0
1
2
3
4
5
6
7
8
Stop
Bit8 Stop (Wakeup)
When bit8 = 1, address (Select code) is denoted.
When bit8 = 0, data is denoted.
Figure 3.9.1 Data Formats
93CS44-121
2004-02-10
TMP93CS44/S45
The serial channel has a buffer register for transmitting and receiving operations, in order to
temporarily store transmitted or received data, so that transmitting and receiving operations
can be done independently (Full duplex).
However, in I/O interface mode, SCLK (Serial clock) pin is used for both transmission and
receiving, the channel becomes half duplex.
The receiving data register is of a double buffer structure to prevent the occurrence of overrun
error and provides one frame of margin before CPU reads the received data. The receiving data
register stores the already received data while the buffer register receives the next frame data.
By using CTS and RTS (there is no RTS pin, so any 1 port must be controlled by software), it
is possible to halt data send until the CPU finishes reading receive data every time a frame is
received (Handshake function).
In the UART mode, a check function is added not to start the receiving operation by error
start bits due to noise. The channel starts receiving data only when the start bit is detected to
be normal at least twice in three samplings.
When the transmission buffer becomes empty and requests the CPU to send the next
transmission data, or when data is stored in the receiving data register and the CPU is
requested to read the data, INTTX or INTRX interrupt occurs. Besides, if an overrun error,
parity error, or framing error occurs during receiving operation, flag SC0CR/SC1CR<OERR,
PERR, FERR> will be set.
The serial channel 0/1 includes a special baud rate generator, which can set any baud rate by
dividing the frequency of 4 clocks (φT0, φT2, φT8, and φT32) from the internal prescaler (shared
by 8- or 16-bit timer) by the value 1 to 16. In addition, serial channel 0/1 can operated by using
external input clock (SCLK).
In I/O interface mode, it is possible to input synchronous signals as well as to transmit or
receive data by external clock.
93CS44-122
2004-02-10
TMP93CS44/S45
3.9.1
Control registers
The serial channel 0 is controlled by 3 control registers SC0CR, SC0MOD and BR0CR.
Transmitted and received data are stored in register SC0BUF.
The serial channel 1 has same registers (SC1CR, SC1MOD, BR1CR and SC1BUF).
Serial Channel 0 Mode Control Register
SC0MOD
(0052H)
Bit symbol
7
6
5
4
TB8
CTSE0
RXE
WU
Read/Write
3
2
1
0
SM1
SM0
SC1
SC0
0
0
0
0
R/W
After reset
Undefined
Function
Transfer
data
bit8
0
Handshake
function
0: CTS0
disable
1: CTS0
enable
0
Receiving
function
0: Receive
disable
1: Receive
enable
0
Wakeup
function
0: Disable
1: Enable
Serial transmission mode
00: I/O interface
mode
01: 7-bit UART
10: 8-bit UART
11: 9-bit UART
Serial transmission
clock (UART)
00: TO2 Trigger
01: Baud rate
generator 0
10: Internal clock φ1
11: External clock
(SCLK0 input)
Serial transmission clock (for UART mode)
00 Timer 2 match detect signal
01
Baud rate generator
10
Internal clock φ1 (fSYS)
11
External clock (SCLK0 input)
Serial transmission mode
00 I/O Interface mode
01
10
7-bit length
UART
11
8-bit length
9-bit length
Wakeup function
(Don’t care in the modes other than 9-bit UART)
0 Disable
1
Enable
Receiving function
0 Receive disable
1
Handshake function ( CTS0 pin)
0 Disable (Always transferable)
Transmission data bit8
8-bit UART mode
Stores transmission
(Parity)
parity bit
9-bit UART mode
Receive enable
1
Enable
Stores transmission
data bit8
Figure 3.9.2 Serial Channel 0 Related Register (1/7)
93CS44-123
2004-02-10
TMP93CS44/S45
Serial Channel 0 Control Register
SC0CR
(0051H)
Bit symbol
7
6
5
4
3
2
1
0
RB8
EVEN
PE
OERR
PERR
FERR
SCLKS
IOC
Read/Write
R
After reset
Undefined
Function
Received
data
bit8
R/W
0
Parity
0: Odd
1: Even
R (Cleared to “0” when read)
0
Parity
addition
0: Disable
1: Enable
0
0
R/W
0
0
0
0: SCLK0
(
1: Error
)
1: SCLK0
Overrun
Parity
Framing
(
)
0: Baud
rate
generator
1: SCLK0
pin input
Serial transmission clock
(for I/O interface mode) (Note 1)
0 Baud rate generator
1
SCLK0 pin input
Edge selection in SCLK pin input mode
Transmits and receives (
) data at
0
rise edge of SCLK
1
Transmits and receives (
fall edge of SCLK
Framing error flag
Parity error flag
Overrun error flag
) data at
Cleared to 0 when
read. (Note 2)
Enable parity addition
0 Prohibition (Disable)
1
Permission (Enable)
Addition/check of even parity
0 Odd parity
1
Even parity
Receving data bit8
8-bit UART mode
(Parity)
9-bit UART mode
Stores received parity
bit
Stores received data
bit8
Note 1:
To use baud rate generator, set TRUN<PRRUN> to 1, putting the prescaler in RUN mode.
Note 2:
As all error flags are cleared after reading, do not test only a single bit with a bit testing instruction.
Figure 3.9.3 Serial Channel 0 Related Register (2/7)
93CS44-124
2004-02-10
TMP93CS44/S45
Baud Rate Generator 0 Control Register
7
BR0CR
(0053H)
Bit symbol
−
Read/Write
R/W
After reset
Function
6
5
4
3
2
1
0
BR0CK1
BR0CK0
BR0S3
BR0S2
BR0S1
BR0S0
0
0
0
0
0
R/W
0
Always
write “0”.
00:
01:
10:
11:
0
φT0
φT2
φT8
φT32
Setting of the divided frequency
Setting of the divided frequency of baud rate generator
0000
16 divisions
0001
to
1111
1 division (not divided)
to
15 divisions
(Note 2)
Selecting the input clock of baud rate generator
00 Internal clock φT0
01
Internal clock φT2
10
Internal clock φT8
11
Internal clock φT32
Note 1:
To use baud rate generator, set TRUN<PRRUN> to 1, putting the prescaler in RUN mode.
Note 2:
“1 division” of baud rate generator can be used only UART mode. Do not set it in I/O interface mode.
Note 3:
Bit6 of BR0CR is read as 1.
Note 4:
Don’t read from or write to BR0CR register during sending or receiving.
Serial Channel 0 Buffer Register
7
6
5
4
3
2
1
0
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
TB7
TB6
TB5
TB4
TB3
TB2
TB1
TB0
SC0BUF
(0050H)
Bit symbol
Prohibit
readmodifywrite
Read/Write
R (Receiving)/W (Transmission)
After reset
Undefined
Figure 3.9.4 Serial Channel 0 Related Registers (3/7)
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TMP93CS44/S45
Serial Channel 1 Mode Control Register
SC1MOD
(0056H)
7
6
5
4
3
2
1
0
TB8
CTSE1
RXE
WU
SM1
SM0
SC1
SC0
After reset
Undefined
0
0
0
0
0
0
0
Function
Transferred Handshake
function
data
0: CTS1
bit8
disable
1: CTS1
enable
Bit symbol
Read/Write
R/W
Receiving
function
0: Receive
disable
1: Receive
enable
Wakeup
function
0: Disable
1: Enable
Serial transmission mode
00: I/O interface mode
01: 7-Bit UART
10: 8-Bit UART
11: 9-Bit UART
Serial transmission clock
(UART)
00: TO2 trigger
01: Baud rate generator
10: Internal clock φ1
11: External clock (SCLK1
input)
Serial transmission clock (for UART mode)
00 Timer 2 match detect signal
01
Baud rate generator
10
Internal clock φ1 (fSYS)
11
External clock (SCLK1 input)
The clock selection for the I/O interface
mode is controlled by the serial control
register (SC1CR).
Serial transmission mode
00 Serial transmission mode
01
10
7-bit length
UART mode
11
8-bit length
9-bit length
Wakeup function
(Don’t care in the modes other than 9-bit UART)
0 Disable
1
Enable
Receiving control
0 Receive disable
1
Handshake function ( CTS1 pin)
0 Disable (Always transferable)
Transmission data bit8
Stores transmission
8-bit UART mode
(Parity)
parity bit
9-bit UART mode
Receive enable
1
Enable
Stores transmission
data bit8
Figure 3.9.5 Serial Channel 1 Related Register (4/7)
93CS44-126
2004-02-10
TMP93CS44/S45
Serial Channel 1 Control Register
SC1CR
(0055H)
Bit symbol
7
6
5
4
3
2
1
0
RB8
EVEN
PE
OERR
PERR
FERR
SCLKS
IOC
0
0
Read/Write
R
After reset
Undefined
Function
Received
data
bit8
R/W
0
Parity
0: Odd
1: Even
R (Clear to “0” when read)
Parity
addition
0: Disable
1: Enable
0
R/W
0
0
0
0: SCLK1
(
1: Error
)
1: SCLK1
Overrun
Parity
Framing
(
)
0: Baud rate
generator
1: SCLK1
Pin input
Serial transmission clock
(for I/O interface mode) (Note1)
0 Baud rate generate
1
SCLK1 pin input
Edge selection in SCLK pin input mode
Transmits and receives (
) data at
0
rise edge of SCLK
1
Transmits and receives (
fall edge of SCLK
Framing error flag
Parity error flag
Overrun error flag
) data at
Cleared to 0
when read
(Note 2)
Enable parity addition
0 Disable
1
Enable
Addition/check of even parity
0 Odd parity
1
Even parity
Receiving data bit8
8-bit UART mode
(Parity)
9-bit UART mode
Stores transmission
parity bit
Stores transmission
data bit8
Note 1:
To use baud rate generator, set TRUN<PRRUN> to 1, putting the prescaler in RUN mode.
Note 2:
As all error flags are cleared after reading, do not test only a single bit with a bit testing instruction.
Figure 3.9.6 Serial Channel 1 Related Register (5/7)
93CS44-127
2004-02-10
TMP93CS44/S45
Baud Rate Generator 1 Control Register
7
BR1CR
(0057H)
Bit symbol
−
Read/Write
R/W
After reset
Function
6
5
4
3
2
1
0
BR1CK1
BR1CK0
BR1S3
BR1S2
BR1S1
BR1S0
0
φT0
φT2
φT8
φT32
0
0
0
0
0
R/W
0
Always
write “0”.
00:
01:
10:
11:
Setting of the divided frequency
Setting of the divided frequency of baud rate generator
0000
16 divisions
0001
to
1111
1 division (not divided)
to
15 divisions
(Note 2)
Selecting the input clock of baud rate generator
00 Internal clock φT0
01
Internal clock φT2
10
Internal clock φT8
11
Internal clock φT32
Note 1:
To use baud rate generator, set TRUN<PRRUN> to “1”, putting the prescaler in RUN mode.
Note 2:
“1 division” of baud rate generator can be used only UART mode. Do not set it in I/O interface mode.
Note 3:
Bit6 of BR1CR is read as “1”.
Note 4:
Don’t read from or write to BR1CR register during sending or receiving.
Serial Channel 1 Buffer Register
7
6
5
4
3
2
1
0
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
TB7
TB6
TB5
TB4
TB3
TB2
TB1
TB0
SC0BUF
(0054H)
Bit symbol
Prohibit
readmodifywrite
Read/Write
R (Receiving)/W (Transmission)
After reset
Undefined
Figure 3.9.7 Serial Channel 1 Related Registers (6/7)
93CS44-128
2004-02-10
TMP93CS44/S45
Port 6 Function Register
7
6
5
4
P6FC
(0016H)
Bit symbol
P65F
Read/Write
W
Prohibit
readmodifywrite
After reset
2
P62F
1
0
0: Port
1: TXD1
0
P60F
W
0
0: Port
1: SCLK1
Function
3
P63F
W
0
0: Port
1: SCLK0
0
0: Port
1: TXD0
Setting TXD0 output P60
0 Port
1
TXD0 output (Channel 0)
Setting SCLK0 output P62
0 Port
1
SCLK0 output (Channel 0)
Setting TXD1 output P63
0 Port
1
TXD1 output (Channel 1)
Setting SCLK1 output P65
0 Port
1
SCLK1 output (Channel 1)
Open-drain Enable Register
7
ODE
(0058H)
6
5
4
Bit symbol
3
2
1
0
ODE34
ODE33
ODE63
ODE60
0
0
0
P63
0: CMOS
1: Open
drain
0
P60
0: CMOS
1: Open
drain
Read/Write
R/W
After reset
P34
0: CMOS
1: Open
drain
Function
P33
0: CMOS
1: Open
drain
Setting P33 as open-drain output
0 CMOS output
1
Open-drain output
Setting P34 as open-drain output
0 CMOS output
1
Open-drain output
Setting P60 as open-drain output
0 CMOS output
1
Open-drain output
Setting P63 as open-drain output
0 CMOS output
1
Open-drain output
Note: Bit7 to 4 of ODE are read as 1.
Figure 3.9.8 Serial Channel Related Registers (7/7)
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TMP93CS44/S45
3.9.2
Configuration
Figure 3.9.9 shows the block diagram of the serial channel 0.
Serial clock generation circuit
BR0CR<BR0CK1:0> External clock
<BR0S3:0>
TO2TRG
SIOCLK
Selector
Selector
Baud rate
generator
System
clock fSYS (φ1)
UART
mode
SC0MOD
<SC1:0>
÷2
SCLK0 input
(Shared
with P62)
SC0MOD
<SM1:0>
Selector
Selector
Prescaler
(Timer 2 comparator output)
φT0
φT2
φT8
φT32
I/O interface mode
SC0CR
<IOC>
SCLK0 output
(Shared
with P62)
INTRX0
Receive counter
(Only UART ÷ 16)
SC0MOD
<WU>
INTTX0
Serial channel
interrupt
control
TXDCLK
Transmission
control
(Only UART ÷ 16)
RXDCLK
SC0MOD<RXE>
Transmission
counter
(Only UART ÷ 16)
Receive control
(Only UART ÷ 16)
SC0CR
<PE>
<EVEN>
RXD0
(Shared
with P61)
Receive buffer 1 (Shift register)
RB8 Receive buffer 2 (SC0BUF)
CTS0
(Shared with P62)
SC0MOD<CTSE0>
Parity control
Error flag
TB8
Transmission buffer (SC0BUF)
TXD0
(Shared with P60)
SC0CR
<OERR> <PERR> <FERR>
Internal data bus
Figure 3.9.9 Block Diagram of the Serial Channel 0
93CS44-130
2004-02-10
TMP93CS44/S45
Figure 3.9.10 shows the block diagram of the serial channel 1.
Serial clock generation circuit
BR1CR<BR1CK1:0>
External clock
<BR1S3:0>
TO2TRG
SIOCLK
Selector
Selector
Baud rate
generator
System
clock/fSYS (φ1)
UART
mode
SC1MOD
<SC1:0>
÷2
SCLK1 input
(Shared
with P65)
SC1MOD
<SM1:0>
Selector
t
Selector
Prescaler
(Timer 2 comparator output)
φT0
φT2
φT8
φT32
I/O interface mode
SC1CR
<IOC>
SCLK1 output
(Shared
with P65)
INTRX1
Receive counter
(Only UART ÷ 16)
SC1MOD
<WU>
INTTX1
Serial channel
interrupt
control
TXDCLK
Transmission
control
(Only UART ÷ 16)
RXDCLK
SC1MOD<RXE>
Transmission
counter
(Only UART ÷ 16)
Receive control
(Only UART ÷ 16)
SC1CR
<PE>
<EVEN>
RXD1
(Shared
with P64)
Receive buffer 1 (Shift register)
RB8 Receive buffer 2 (SC1BUF)
CTS1
(Shared with P65)
SC1MOD<CTSE1>
Parity control
Error flag
TB8
Transmission buffer (SC1BUF)
TXD1
(Shared with P63)
SC1CR
<OERR> <PERR> <FERR>
Internal data bus
Figure 3.9.10 Block Diagram of the Serial Channel 1
93CS44-131
2004-02-10
TMP93CS44/S45
1.
Prescaler
There are 9-bit prescaler and prescaler clock selection registers to generate input
clock for 8-bit timer 0, 1, 2, 3, 16-bit timer 4, 5, and serial interface 0, 1.
Figure 3.9.11 shows the block diagram. Table 3.9.1 shows prescaler clock resolution
into the baud rate generator.
to CPU
System clock fSYS
÷2
fFPH
9-bit prescaler
2 4 8 16 32 64 128 256 512
Selector
Selector
fs
XT1
φT1
φT4
φT16
φT256
÷4
φT1
φT4
φT16
SYSCR0
<PRCK1:0>
Run/stop
and clear
φ1
φT0
φT2
φT8
φT32
Selector
TRUN<PRRUN>
SYSCR1<SYSCK>
fc
fc/2
fc/4
To 16-bit timer 4
and 5
To serial
interface 0 and
1
fc/8 fc/16
÷2 ÷4 ÷8 ÷16
X1
÷2
To 8-bit
timer 0, 1, 2 and
3
SYSCR1<GEAR2:0>
Figure 3.9.11 The Block Diagram of Prescaler
Table 3.9.1 Prescaler Clock Resolution to Baud Rate Generator
at fc = 20 MHz, fs = 32.768 kHz
Select System Select Prescaler
Gear Value
Clock
Clock
<GEAR2:0>
<SYSCK>
<PRCK1:0>
1 (fs)
0 (fc)
00 (fFPH)
Prescaler Output Clock Resolution
φ1
φT0
φT2
φT8
XXX
fs/2 (61 µs)
fc/2 (0.1 µs) fc/22 (0.2 µs)
fc/24 (0.8 µs)
fc/26 (3.2 µs)
fc/28 (12.8 µs)
001 (fc/2)
fc/22 (0.2 µs) fc/23 (0.4 µs)
fc/25 (1.6 µs)
fc/27 (6.4 µs)
fc/29 (25.6 µs)
010 (fc/4)
fc/2 (0.4 µs) fc/2 (0.8 µs)
fc/2 (3.2 µs)
fc/2 (12.8 µs)
fc/210(51.2 µs)
011 (fc/8)
fc/2 (0.8 µs) fc/2 (1.6 µs)
fc/2 (6.4 µs)
fc/2 (25.6 µs)
fc/211(102.4 µs)
100 (fc/16)
fc/2 (1.6 µs) fc/2 (3.2 µs)
fc/2 (12.8 µs)
fc/2 (51.2 µs)
fc/212(204.8 µs)
3
fs/2 (122 µs) fs/2 (488.5 µs) fs/2 (1.95 µs)
φT32
000 (fc)
2
4
4
4
5
5
6
6
7
8
6
8
9
10
fs/2 (7.8 µs)
8
XXX
01
(Low-frequency
clock)
XXX
−
−
fs/24 (488.5 µs) fs/26 (1.95 µs)
fs/28 (7.8 µs)
XXX
10 (Note)
(fc/16 clock)
XXX
−
−
fc/28 (12.8 µs)
fc/212(204.8 µs)
fc/210 (51.2 µs)
XXX: Don’t care, −: Can not use
Note: The fc/16 clock as a prescaler prescaler clock can not be used when the fs is used as a system clock.
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2004-02-10
TMP93CS44/S45
The clock selected among fFPH clock, fc/16 clock, and fs clock is divided by 4 and
input to this prescaler.
This is selected by prescaler clock selection register SYSCR0<PRCK1:0>.
Resetting sets <PRCK1:0> to “00” and selects the fFPH clock input divided by 4.
The baud rate generator selects between 4 clock inputs: φT0, φT2, φT8, and φT32
among the prescaler outputs.
The prescaler can be run or stopped by the timer operation control register
TRUN<PRRUN>. Counting starts when <PRRUN> is set to “1”, while the prescaler is
cleared to zero and stops operation when <PRRUN> is set to “0”.
When the IDLE1 mode (operates only oscillator) is used, set TRUN<PRRUN> to “0”
to reduce the power consumption of this prescaler before “HALT” instruction is
executed.
2.
Baud rate generator
Baud rate generator comprises a circuit that generates transmission and receiving
clocks to determine the transfer rate of the serial channel.
The input clock to the baud rate generator, φT0, φT2, φT8, or φT32 is generated by
the 9-bit prescaler which is shared by the timers. One of these input clocks is selected
by the baud rate generator control register BR0CR<BR0CK1:0>.
The baud rate generator includes a 4-bit frequency divider, which divides frequency
by 1 to 16 values to determine the transfer rate.
How to calculate a transfer rate when the baud rate generator is used is explained
below.
•
UART mode
•
Input clock of baud rate generator
÷ 16
Frequency divisor of baud rate generator
I/O interface mode
Baud rate =
Baud rate =
Input clock of baud rate generator
÷2
Frequency divisor of baud rate generator
Accordingly, when source clock fc is 12.288 MHz, input clock is φT2 (fc/16), and
frequency divisor is 5, the transfer rate in UART mode becomes as follows:
* Clock condition
Baud rate =
System clock: High frequency (fs)
Clock gear:
1 (fc)
Prescaler clock: fFPH
fc/16
÷ 16
5
= 12.288 × 106 ÷ 16 ÷ 5 ÷ 16 = 9600 (bps)
The maximum baud rate of this baud rate generator is 307.2 kbps.
Table 3.9.2 shows an example of the transfer rate in UART mode.
Also with 8-bit timer 2, the serial channel can get a transfer rate. Table 3.9.3 shows
an example of baud rate using timer 2.
93CS44-133
2004-02-10
TMP93CS44/S45
Table 3.9.2 Selection of UART Transfer Rate (1) (when baud rate generator is used)
Unit (kbps)
Input Clock
fc [MHz]
Frequency Divisor
9.830400
12.288000
14.745600
17.2032
19.6608
φT32
(256/fc)
φT8
(64/fc)
φT2
(16/fc)
φT0
(4/fc)
1
153.600
38.400
9.600
2.400
2
76.800
19.200
4.800
1.200
4
38.400
9.600
2.400
0.600
8
19.200
4.800
1.200
0.300
16
9.600
2.400
0.600
0.150
5
38.400
9.600
2.400
0.600
10
19.200
4.800
1.200
0.300
1
230.400
57.600
14.400
3.600
3
76.800
19.200
4.800
1.200
6
38.400
9.600
2.400
0.600
12
19.200
4.800
1.200
0.300
7
38.400
9.600
2.400
0.600
14
19.200
4.800
1.200
0.300
2
153.600
38.400
9.600
2.400
4
76.800
19.200
4.800
1.200
8
38.400
9.600
2.400
0.600
16
19.200
4.800
1.200
0.300
Note 1: Transfer rate in I/O interface mode is 8 times faster than the values given in the above
table.
Note 2: This table is calculated when fc is selected as a system clock, fc/1 as a clock gear, and
the system clock as a prescaler clock.
Table 3.9.3 Selection of UART Transfer Rate (2) (when timer 2 (input clock φT1) is used)
Unit (kbps)
fc
19.6608
MHz
14.7456
MHz
12.288
MHz
1H
153.6
115.2
96
76.8
62.5
48
2H
76.8
57.6
48
38.4
31.25
24
3H
51.2
38.4
32
4H
38.4
28.8
24
5H
30.72
23.04
19.2
8H
19.2
14.4
12
AH
15.36
11.52
10H
9.6
7.2
6
14H
7.68
5.76
4.8
TREG2
12
MHz
9.8304
MHz
31.25
8
MHz
6.144
MHz
16
19.2
12
9.6
9.6
9.6
6
4.8
4.8
3
2.4
How to calculate the transfer rate (when timer 2 is used):
Transfer rate =
The clock frequency selected by the register SYSCR0<PRCK1:0>
TREG2 × 8 × 16
(when timer 2 (input clock φT1) is used)
Note 1: Timer 2 match detect signal cannot be used as the transfer clock in I/O interface mode.
Note 2: This table is calculated when fc is selected as a system clock, fc/1 as a clock gear, and
the system clock as a prescaler clock.
93CS44-134
2004-02-10
TMP93CS44/S45
3.
Serial clock generation circuit
This circuit generates the basic clock for transmitting and receiving data.
•
I/O interface mode
When in SCLK output mode with the setting of SC0CR<IOC> = 0, the basic clock
will be generated by dividing by 2 the output of the baud rate generator described
before. When in SCLK input mode with the setting of SC0CR<IOC> = 1, the rising
edge or falling edge will be detected according to the setting of SC0CR<SCLKS>
register to generate the basic clock.
•
UART mode
According to the setting of SC0MOD<SC1:0>, the above baud rate generator
clock, internal clock φ1 (Max 625 kbps at fc = 20 MHz), the match detect signal
from timer 0, or external clock SCLK0 will be selected to generate the basic clock
SIOCLK.
4.
Receiving counter
The receiving counter is a 4-bit binary counter used in UART mode and counts up by
SIOCLK clock. 16 pulses of SIOCLK are used for receiving 1 bit of data, and the data
bit is sampled three times at 7th, 8th and 9th clock.
With the three samples, the received data is evaluated by the rule of majority.
For example, if the sampled data bit is “1”, “0” and “1” at 7th, 8th and 9th clock
respectively, the received data is evaluated as “1”. The sampled data “0”, “0” and “1” is
evaluated that the received data is “0”.
5.
Receiving control
•
I/O interface mode
When in SCLK output mode with the setting of SC0CR<IOC> = 0, RXD0 signal
will be sampled at the rising edge of shift clock which is output to SCLK0 pin.
When in SCLK input mode with the setting SC0CR<IOC> = 1 RXD0 signal will
be sampled at the rising edge or falling edge of SCLK0 input according to the
setting of SC0CR<SCLKS> register.
•
UART mode
The receiving control has a circuit for detecting the start bit by the rule of
majority. When two or more “0” are detected during 3 samples, it is recognized as
start bit and the receiving operation is started.
Data being received are also evaluated by the rule of majority.
93CS44-135
2004-02-10
TMP93CS44/S45
6.
Receiving buffer
To prevent overrun error, the receiving buffer has a double buffer structure.
Received data are stored one bit by one bit in the receiving buffer 1 (Shift register
type). When 7 bits or 8 bits of data is stored in the receiving buffer 1, the stored data
are transferred to the receiving buffer 2 (SC0BUF), generating an interrupt INTRX0.
The CPU reads only receiving buffer 2 (SC0BUF). Even before the CPU reads the
receiving buffer 2 (SC0BUF), the received data can be stored in the receiving buffer 1.
However, unless the receiving buffer 2 (SC0BUF) is read before all bits of the next data
are received by the receiving buffer 1, an overrun error occurs. If an overrun error
occurs, the contents of the receiving buffer 1 will be lost, although the contents of the
receiving buffer 2 and SC0CR<RB8> is still preserved.
The parity bit added in 8-bit UART mode and the most significant bit (MSB) in 9-bit
UART mode are stored in SC0CR<RB8>.
When in 9-bit UART mode, the wakeup function of the slave controllers is enabled by
setting SC0MOD<WU> to 1, and interrupt INTRX0 occurs only when SC0CR<RB8> is
set to 1.
7.
Transmission counter
Transmission counter is a 4-bit binary counter which is used in UART mode and,
counts by SIOCLK clock, generating TXDCLK every 16 clock pulses.
SIOCLK
15
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
TXDCLK
Figure 3.9.12 Generation of Transmission Clock
8.
Transmission controller
•
I/O interface mode
In SCLK0 output mode with the setting of SC0CR<IOC> = 0, the data in the
transmission buffer are output bit by bit to TXD0 pin at the rising edge of shift
clock which is output from SCLK0 pin.
In SCLK0 input mode with the setting of SC0CR<IOC> = “1”, the data in the
transmission buffer are output bit by bit to TXD0 pin at the rising edge or falling
edge of SCLK0 input according to the setting of SC0CR<SCLKS> register.
•
UART mode
When transmission data are written in the transmission buffer sent from the
CPU, transmission starts at the rising edge of the next TXDCLK, generating a
transmission shift clock TXDSFT.
93CS44-136
2004-02-10
TMP93CS44/S45
Handshake function
The serial channels use the CTS0 pin to transmit data in units of frames, thus
preventing an overrun error. Use SC0MOD<CTSE0> to enable or disable the
handshake function.
When CTS0 goes high, data transmission is halted after the completion of the
current transmission and is not restarted until CTS0 returns to low. An INTTX0
interrupt is generated to request the CPU for the next data to transmit. When the CPU
write the data to the transmit buffer, processing enters standby mode.
An RTS pin is not provided, but a handshake function can easily be configured if the
receiver sets any port assigned to the RTS function to high (in the receive interrupt
routine) after data receive, and requests the transmitter to temporarily halt
transmission.
TMP93CS44/S45
TMP93CS44/S45
TXD
RXD
CTS
RTS (Any port)
Sender
Receiver
Figure 3.9.13 Handshake Function
Timing to write
Transmission buffer
Send is suspended
CTS0
Note 1
Note 2
13
14
15
16
1
2
3
4
14
15
16
1
2
3
SIOCLK
TXDCLK
Start bit
TXD
Note 1:
Bit0
If the CTS signal rises during transmission, the next data is not sent after the completion of the current
transmission.
Note 2:
Transmission starts at the first TXDCLK clock fall after the CTS signal falls.
Figure 3.9.14 Timing of CTS (Clear to send)
93CS44-137
2004-02-10
TMP93CS44/S45
9.
Transmission buffer
Transmission buffer (SC0BUF) shifts out and sends the transmission data written
from the CPU from the least significant bit (LSB) in order. When all bits are shifted out,
the transmission buffer becomes empty and generates INTTX0 interrupt.
10. Parity control circuit
When serial channel control register SC0CR<PE>is set to 1, it is possible to transmit
and receive data with parity. However, parity can be added only in 7- or 8-bit UART
mode. With SC0CR <EVEN> register, even (odd) parity can be selected.
For transmission, parity is automatically generated according to the data written in
the transmission buffer SC0BUF, and data are transmitted after being stored in
SC0BUF<TB7> when in 7-bit UART mode while in SC0MOD<TB8> when in 8-bit
UART mode. <PE> and <EVEN> must be set before transmission data are written in
the transmission buffer.
For receiving, data are shifted in the receiving buffer 1, and parity is added after the
data are transferred in the receiving buffer 2 (SC0BUF), and then compared with
SC0BUF<RB7> when in 7-bit UART mode and with SC0MOD<RB8> when in 8-bit
UART mode. If they are not equal, a parity error occurs, and SC0CR<PERR> flag is
set.
11. Error flag
Three error flags are provided to increase the reliability of receiving data.
1.
Overrun error <OERR>
If all bits of the next data are received in receiving buffer 1 while valid data are
stored in receiving buffer 2 (SC0BUF), an overrun error will occur.
2.
Parity error <PERR>
The parity generated for the data shifted in receiving buffer 2 (SC0BUF) is
compared with the parity bit received from RXD pin. If they are not equal, a parity
error occurs.
3.
Framing error <FERR>
The stop bit of received data is sampled three times around the center. If the
majority is 0, a framing error occurs.
93CS44-138
2004-02-10
TMP93CS44/S45
12.
Signal generation timing
1)
In UART mode
Receive
Mode
9-Bit
8-Bit + Parity
8-Bit, 7-Bit + Parity, 7-Bit
Timing for Interrupt
Generation
Center of last bit (Bit8)
Center of last bit
(Parity bit)
Center of stop bit
Timing for Framing
Error Generation
Center of stop bit
Center of stop bit
−
Center of last bit
(Parity bit)
Center of stop bit
Center of last bit
(Bit8)
Center of last bit
(Parity bit)
Center of stop bit
Timing for Parity Error
Generation
Timing for Overrun
Error Generation
Note:
Center of stop bit
In 9-bit and 8-bit + parity mode, interrupts coincide with the ninth bit pulse. Thus,
when serving the interrupt, it is necessary to want for a 1-bit period (to allow the
stop bit to be transferred) to allow checking for a framing error.
Send
Mode
Timing for Interrupt
Generation
2)
9-Bit
8-Bit + Parity
8-Bit, 7-Bit + Parity, 7-Bit
Immediately before
stop bit sent
←
←
In I/O interface mode
Timing for Send
Interrupt Generation
Timing for Receive
Interrupt Generation
SCLK0 output mode
Immediately after rise of last SCLK0 signal
(See Figure 3.9.17)
SCLK0 input mode
Immediately after rise (Rising mode) or fall (Falling mode) of
last SCLK0 signal
(See Figure 3.9.18)
SCLK0 output mode
Immediately after final SCLK0 (when received data are
transferred to receive buffer 2 (SC0BUF) (See Figure 3.9.19)
SCLK0 input mode
Immediately after final SCLK0 (when received data are
transferred to receive buffer 2 (SC0BUF) (See Figure 3.9.20)
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2004-02-10
TMP93CS44/S45
3.9.3
Operational description
(1) Mode 0 (I/O interface mode)
This mode is used to increase the number of I/O pins of for transmitting or receiving
data to or from the external shifter register.
This mode includes SCLK output mode to output synchronous clock SCLK0 and
SCLK input mode to input external synchronous clock SCLK0.
Output extension
TMP93CS44/S45
Input extension
TMP93CS44/S45
Shift register
Shift register
A
TXD
B
C
D
E
F
G
H
SI
SCLK
SCK
Port
RCK
A
RXD
SCLK
Port
TC74HC595 or the like
B
C
D
E
F
G
H
QH
CLOCK
S/ L
TC74HC165 or the like
Figure 3.9.15 Example of SCLK Output Mode Connection
Output port extension
TMP93CS44/S45
Input port extension
TMP93CS44/S45
Shift register
Shift register
A
TXD
B
C
D
E
F
G
H
SI
SCLK
SCK
Port
RCK
A
RXD
SCLK
Port
TC74HC595 or the like
External clock
B
C
D
E
F
G
H
QH
CLOCK
S/ L
TC74HC165 or the like
External clock
Figure 3.9.16 Example of SCLK Input Mode Connection
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2004-02-10
TMP93CS44/S45
1.
Transmission
In SCLK output mode, 8-bit data and synchronous clock are output from TXD0
pin and SCLK0 pin, respectively, each time the CPU writes data in the
transmission buffer. When all data is output, INTES0<ITX0C> will be set to
generate INTTX0 interrupt.
Timing to write
transmission data
SCLK0 output
TXD0
Bit0
Bit1
Bit6
Bit7
TXDSFT
ITX0C
(INTTX0 interrupt request)
Figure 3.9.17 Transmitting Operation in I/O Interface Mode (SCLK output mode)
In SCLK output mode, 8-bit data are output from TXD0 pin when SCLK0 input
becomes active while data are written in the transmission buffer by CPU.
When all data are output, INTES0<ITX0C> will be set to generate INTTX0
interrupt.
SCLK0 input
(SCLKS = 0:
Rising edge mode)
SCLK0 input
(SCLKS = 1:
Falling edge mode)
TXD0
Bit0
Bit1
Bit5
Bit6
Bit7
TXDSFT
ITX0C
(INTTX0 interrupt request)
Figure 3.9.18 Transmitting Operation in I/O Interface Mode (SCLK input mode)
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2004-02-10
TMP93CS44/S45
2.
Receiving
In SCLK output mode, synchronous clock is outputted from SCLK0 pin and the
data are shifted in the receiving buffer 1 whenever the receive interrupt flag
INTES0<IRX0C> is cleared by reading the received data. When 8-bit data are
received, the data will be transferred in the receiving buffer 2 (SC0BUF) at the
timing shown below, and INTES0<IRX0C> will be set again to generate INTRX0
interrupt.
IRX0C
SCLK0
Bit0
RXD0
Bit1
Bit2
Bit6
Bit7
Generate
INTRX0
Timing to shift data in
the receiving buffer 2
Figure 3.9.19 Receiving Operation in I/O Interface Mode (SCLK output mode)
In SCLK input mode, the data is shifted in the receiving buffer 1 when SCLK
input becomes active while the receive interrupt flag INTES0<IRX0C> is cleared
by reading the received data. When 8-bit data is received, the data will be shifted
in the receiving buffer 2 (SC0BUF) at the timing shown below, and
INTES0<IRX0C> will be set again to generate INTRX0 interrupt.
SCLK0 input
(SCLKS = 0:
Rising edge mode)
SCLK0 input
(SCLKS = 1:
Falling edge mode)
Bit0
RXD0
Bit1
Bit2
Bit6
Bit7
Generate
INTRX0
Timing to shift data in
the receiving buffer 2
Figure 3.9.20 Receiving Operation in I/O Interface Mode (SCLK input mode)
Note:
For data receiving, the system must be placed in the receive enable state
(SC0MOD<RXE> = 1).
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2004-02-10
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(2) Mode 1 (7-bit UART mode)
7-bit UART mode can be set by setting serial channel mode register
SC0MOD<SM1:0> to 01.
In this mode, a parity bit can be added, and the addition of a parity bit can be
enabled or disabled by serial channel control register SC0CR<PE>, and even parity or
odd parity is selected by SC0CR <EVEN> when <PE> is set to 1 (Enable).
Setting example: When transmitting data with the following format, the control registers should be set as described
below.
Start
Bit 0
1
2
3
4
5
6
Even
parity
Stop
Direction of transmission (Transmission rate: 2400 bps at fc = 12.288 MHz)
System clock: High frequency (fs)
Clock gear:
1 (fc)
Prescaler clock: fFPH
* Clock condition
7
6 5
4
3
2
1
0
P6CR
← −
− −
−
−
−
−
1
P6FC
SC0MOD
SC0CR
BR0CR
TRUN
INTES0
SC0BUF
←
←
←
←
←
←
←
X
0
1
X
X
1
*
−
−
1
1
−
0
*
X
X
X
0
−
0
*
−
0
X
0
−
−
*
−
1
X
1
−
−
*
X
0
0
0
−
−
*
1
1
0
1
−
−
*
X
X
X
0
1
1
*
Select P60 as the TXD pin.
Set 7-bit UART mode.
Add an even parity.
Set transfer rate at 2400 bps.
Start the prescaler for the baud rate generator.
Enable INTTX0 interrupt and set interrupt level 4.
Set data for transmission.
X: Don’t care, −: No change
(3) Mode 2 (8-bit UART mode)
8-bit UART mode can be specified by setting SC0MOD<SM1:0> to 10. In this mode,
parity bit can be added, the addition of a parity bit is enabled or disabled by
SC0CR<PE>, and even parity or odd parity is selected by SC0CR<EVEN> when <PE>
is set to 1 (Enable).
Setting example: When receiving data with the following format, the control register should be set as described below.
Start
Bit0
1
2
3
4
5
6
7
Odd
parity
Stop
Direction of transmission (Transmission rate: 9600 bps at fc = 12.288 MHz)
* Clock condition
System clock: High frequency (fs)
Clock gear:
1 (fc)
Prescaler clock: fFPH
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2004-02-10
TMP93CS44/S45
Main setting
P6CR
SC0MOD
SC0CR
BR0CR
TRUN
INTES0
←
←
←
←
←
←
7
6
5
4
3
2
1
0
−
−
X
0
1
−
0
0
X
X
− −
1 X
1 X
0 1
−
1
X
0
−
0
X
1
0
0
0
0
−
1
0
1
−
−
−
−
−
1
− −
1 0
−
0
−
−
Select P61 (RXD) as the input pin.
Enable receiving in 8-bit UART mode.
Add an odd parity.
Set transfer rate at 9600 bps.
Start the prescaler for the baud rate generator.
Enable INTRX0 interrupt and set interrupt level 4.
X: Don’t care, −: No change
Interrupt processing
ACC ← SC0CR AND 00011100
Check for error.
if ACC ≠ 0 then ERROR
ACC ← SC0BUF
Read the received data.
(4) Mode 3 (9-bit UART mode)
9-bit UART mode can be specified by setting SC0MOD<SM1:0> to 11. In this mode,
parity bit cannot be added.
For transmission, the MSB (9th bit) is written in SC0MOD<TB8>, while in receiving
it is stored in SC0CR<RB8>. For writing and reading the buffer, the MSB is read or
written first then SC0BUF.
Wakeup function
In 9-bit UART mode, the wakeup function of slave controllers is enabled by setting
SC0MOD<WU> to 1. The interrupt INTRX0 occurs only when <RB8> = 1.
TXD
RXD
Master
Note:
TXD
RXD
Slave 1
TXD
RXD
Slave 2
TXD
RXD
Slave 3
TXD pin of the slave controllers must be in open drain output mode.
Figure 3.9.21 Serial Link Using Wakeup Function
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2004-02-10
TMP93CS44/S45
Protocol
1.
Select the 9-bit UART mode for the master and slave controllers.
2.
Set SC0MOD<WU> bit of each slave controller to 1 to enable data receiving.
3.
The master controller transmits one-frame data including the 8-bit select code for
the slave controllers. The MSB (Bit8) <TB8> is set to 1.
Start
Bit0
1
2
3
4
5
6
7
Select code of slave controller
8
Stop
“1”
4.
Each slave controller receives the above frame, and clears <WU> bit to 0 if the
above select code matches its own select code.
5.
The master controller transmits data to the specified slave controller whose
SC0MOD<WU> bit is cleared to 0. The MSB (Bit8) <TB8> is cleared to 0.
Start
Bit0
1
2
3
4
Data
6.
5
6
7
Bit8
Stop
“0”
The other slave controllers (with the <WU> bit remaining at 1) ignore the
receiving data because their MSBs (Bit8 or <RB8>) are set to 0 to disable the
interrupt INTRX0.
The slave controllers (<WU> = 0) can transmit data to the master controller, and
it is possible to indicate the end of data receiving to the master controller by this
transmission.
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2004-02-10
TMP93CS44/S45
Setting example: To link two slave controllers serially with the master controller, and
use the internal clock φ1 as the transfer clock.
TXD
RXD
TXD
Master
RXD
TXD
RXD
Slave 1
Slave 2
Select code
00000001
Select code
00001010
Since serial channels 0 and 1 operate in exactly the same way, channel 0 is used
for the purposes of explanation.
•
Setting the master controller
Main
P6CR
← −
P6FC
INTES0
← X X −
← 1 1 0
−
−
SC0MOD
SC0BUF
← 1
← 0
−
−
−
0
X −
0 1
−
1
X 1
0 1
1
Select P60 as TXD0 pin and P61 as RXD0 pin.
Enable INTTX0 and set the interrupt level 4.
Enable INTRX0 and set the interrupt level 5.
0 1 0
0 0 0
1
0
1 1
0 0
0
1
Set φ1 as the transmission clock in 9-bit UART mode.
Set the select code for slave controller 1.
−
*
−
*
−
*
−
*
Sets TB8 to “0”.
Set data for transmission.
INTTX0 interrupt
← 0
← *
SC0MOD
SC0BUF
•
−
*
−
*
−
*
Setting the slave controller 2
Main
P6CR
← −
P6FC
← X X −
−
−
−
0
X −
−
X 1
ODE
INTES0
SC0MOD
← X X X X −
−
−
1
← 1
← 0
1 1
1 1
0
0
1
0
−
−
0 1
1 1
1
1
1
Select P61 as RXD0 pin and P60 as TXD0 pin (Open-drain
output).
Enable INTRX0 and INTTX0.
Set <WU> to “1” in the 9-bit UART transmission mode with
transfer clock φ1.
INTRX0 interrupt
ACC ← SC0BUF
if ACC = Select code
Then SC0MOD ← − − − 0 − − − −
Clear <WU> to “0”.
93CS44-146
2004-02-10
TMP93CS44/S45
3.10 Serial Bus Interface (SBI)
The TMP93CS44/S45 has a 1-channel serial bus interface which employs a clocked
synchronous 8-bit serial bus interface and an I2C bus.
The serial bus interface is connected to an external device through P33 (SDA) and P34 (SCL)
in the I2C bus mode; and through P32 (SCK), P33 (SO), and P34 (SI) in the clocked synchronous
8-bit SIO mode.
TMP93CS44/S45 has no an arbitration function which is necessary when two or more master
devices scramble for the bus control. In master mode, other devices which are connected on the
same bus need be slave devices (Single master).
Setting of every pins is as follows.
ODE<ODE34:33>
I2C Bus Mode
Clock Synchronous
8-Bit SIO Mode
P3CR<P34C, P33C, P32C> P3FC<P32M, P34F, P33F, P32F>
11
11X
X110
XX
011
010
1111
X: Don’t care
3.10.1
Configuration
INTS2 interrupt request
SCL
SCK
P32
(SCK/ HWR )
SIO
clock
control
Input/
output
control
fc/4
Divider
Transfer
2
I C bus
clock
Noise
canceller
SO
SIO
data control
SI
control
circuit
P34
(SI/SCL)
synchronous
Shift
register
I2C bus
data control
I2CAR
SBIDBR
SBICR1
SBICR3
I2C bus
address
register
SBI data
buffer
register
SBI control
register 1
SBI control
register 3
+
Control
SBICR2/
SBISR
SBI control
register 2/
SBI status
register
P33
(SO/SDA)
Noise
canceller
SDA
Figure 3.10.1 Serial Bus Interface (SBI)
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2004-02-10
TMP93CS44/S45
3.10.2
Serial bus interface (SBI) control
The following registers are used for control and operation status monitoring when using
the serial bus interface (SBI).
•
Serial bus interface control register 1 (SBICR1)
•
Serial bus interface control register 2 (SBICR2)
•
Serial bus interface control register 3 (SBICR3)
•
Serial bus interface data buffer register (SBIDBR)
•
I2C bus address register (I2CAR)
•
Serial bus interface status register (SBISR)
The above registers differ depending on an mode to be used.
Refer to section 3.10.4 “I2C Bus Mode Control” and 3.10.6 “Clock Synchronous 8-Bit SIO
Mode Control”.
3.10.3
The Data Formats in the I2C Bus Mode
The data formats when using the TMP93CS44/S45 in the I2C bus mode are shown below.
(a) Addressing format
1
8 bits
S
Slave address
R A
/ C
W K
1 to 8 bits
1
1 to 8 bits
Data
A
C
K
Data
1
1
A
C P
K
1 or more
(b) Addressing format (with restart)
1
8 bits
S
Slave address
1 to 8 bits
R A
/ C
W K
A
C S
K
Data
1
1
8 bits
1
R A
/ C
W K
Slave address
1 or more
1
1 to 8 bits
1
A
C P
K
Data
1 or more
(c) Free data format
8 bits
S
Data
1
1 to 8 bits
1
1 to 8 bits
A
C
K
Data
A
C
K
Data
1
S:
1
A
C P
K
1 or more
Start condition
R/ W : Direction bit
ACK: Acknowledge bit
P:
Stop condition
2
Figure 3.10.2 Data Format in the I C Bus Mode
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2004-02-10
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3.10.4
I2C Bus Mode Control
The following registers are used for control and operation status monitoring when using
the serial bus interface (SBI) in the I2C bus mode.
Serial Bus Interface Control Register 1
SBICR1
(004BH)
Prohibit
Bit symbol
7
6
5
4
BC2
BC1
BC0
ACK
Read/Write
After reset
read-modify- Function
write
W
0
0
Number of transferred bits
(Note 1)
3
2
1
0
SCK2
SCK1
SCK0
R/W
0
W
0
0
Acknowledge
mode
specification
0
0
Serial clock selection
(Note 2)
Serial clock selection
− kHz
000 N = 4
− kHz
001 N = 5
− kHz
010 N = 6
74.6 kHz
011 N = 7
38.2 kHz
100 N = 8
19.3 kHz
N
=
9
101
9.71 kHz
N
=
10
110
(Reserved)
111
System clock: fc
Clock gear: fc/1
fc = 20 MHz
(Output on SCL pin)
Acknowledge mode specification
0 Not generate clock pulse for acknowledge signal
1
Generate clock pulse for acknowledge signal
Number of transferred bits
<ACK> = 0
<BC2:0> Number of
Bits
Clock
000
8
8
001
1
1
010
2
2
011
3
3
100
4
4
101
5
5
110
6
6
111
7
7
Note 1:
<ACK> =
Number of
Clock
9
2
3
4
5
6
7
8
1
Bits
8
1
2
3
4
5
6
7
Set <BC2:0> to “000” before switching to a clock synchronous 8-bit SIO mode.
Note 2:
Refer to sentence of 3.10.4 (3) “Serial clock”.
Note 3:
This I2C bus circuit does not support high-speed mode. It supports standard mode only.
2
Figure 3.10.3 Register for I C Bus Mode (1/4)
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2004-02-10
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Serial Bus Interface Control Register 2
SBICR2
(004EH)
Prohibit
readmodifywrite
Bit symbol
7
6
5
4
3
2
MST
TRX
BB
PIN
SBIM1
SBIM0
1
0
Read/Write
After reset
Function
W (R/W
0
Master/
slave
selection
0
Transmitter/
receiver
selection
Note 1
)
0
Start/stop
condition
generation
1
0
W
Cancel
INTS2
request
0
Serial bus interface
operating mode selection
(Note 2)
SBI operating mode selection
00 Port mode (Serial bus interface output disable)
01
SIO mode
10
I2C bus mode
11
(Reserved)
Cancel INTS2 request
0 −
1
Cancel interrupt service request
Start/stop condition generation
0 Generate the stop condition
1
Generate the start condition
Transmitter/receiver selection
0 Receiver
1
Transmitter
Master/slave selection
0 Slave
1
Note 1:
Note 2:
Master
This register functions as the SBISR by reading.
Switch a mode to the port mode after confirming that the bus is free.
Switch a mode to the I2C bus mode and the clocked-synchronous 8-bit SIO mode after confirming that input
signals via port are high level.
2
Figure 3.10.4 Register for I C Bus Mode (2/4)
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2004-02-10
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Serial Bus Interface Status Register
SBISR
(004EH)
Bit symbol
6
5
4
3
2
1
0
TRX
BB
PIN
AL
AAS
AD0
LRB
0
0
Transmitter/ I2C bus
status
receiver
monitor
selection
status
monitor
1
INTS2
request
status
monitor
Read/Write
After reset
Prohibit
readmodifywrite
7
MST
Function
R
0
Master/
slave
selection
status
monitor
0
0
Noise
detection
monitor
Slave
address
match
detection
monitor
0
GENERAL
CALL
detection
monitor
0
Last received
bit monitor
Last received bit monitor
0 Last received bit “0”
1
Last received bit “1”
GENERAL CALL detection monitor
0 Non GENERAL CALL detected
1
GENERAL CALL detected
Slave address match detection monitor
Non slave address match or
0
GENERAL CALL detected
1
Slave address match or GENERAL
CALL detected
Noise detection monitor
0 Non noise detected
1
Noise detected
INTS2 request status
0 Interrupt service requested
1
Interrupt service cancelled
2
I C bus status monitor
0 Bus free
1
Bus busy
Transmitter/receiver selection status monitor
0 Receiver
1
Transmitter
Master/slave selection status monitor
0 Slave
1
Master
Note: Bits 7 to 2 of this register function as the SBICR2 by writing.
2
Figure 3.10.5 Register for I C Bus Mode (3/4)
93CS44-151
2004-02-10
TMP93CS44/S45
Serial Bus Interface Control Register 3
7
SBICR3
(004FH)
6
5
4
3
2
1
0
Bit symbol
SWRST
Read/Write
R/W
After reset
0
Software
reset
Function
0: Don’t care
1: Initialize
SBI
Software reset
0 Don’t care
1
Initialize SBI (after initializing SBI,
SWRST is automatically cleared to “0”).
Serial Bus Interface Data Buffer Register
7
6
5
4
3
2
1
0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
SBIDBR
(004CH)
Bit symbol
Read/Write
R (Receive)/W (Send)
Prohibit
readmodify
-write
After reset
Undefined
Note 1:
Note 2:
When writing the send data, start from the MSB (Bit7). Receiving data is placed from LSB (Bit0).
SBIDBR can’t be read the written data. Therefore read-modify-write instruction (e.g., “BIT” instruction) is
prohibitted.
Note 3:
Written data in SBIDBR is cleared by INTS2 signal.
2
I C Bus Address Register
I2CAR
(004DH)
Bit symbol
6
5
4
SA6
SA5
SA4
SA3
Read/Write
After reset
Prohibit
read-modify
-write
7
Function
3
2
1
0
SA2
SA1
SA0
ALS
0
0
W
0
0
0
0
0
Slave address selection.
0
Address
recognition
mode
specification
Address recognition mode specification
0 Slave address recognition
1
Non slave address recognition
2
Figure 3.10.6 Register for I C Bus Mode (4/4)
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2004-02-10
TMP93CS44/S45
(1) Acknowledge mode specification
Set SBICR1<ACK> to “1” for operation in the acknowledge mode. The
TMP93CS44/S45 generates an additional clock pulse for an acknowledge signal when
operating in the master mode. In the transmitter mode during the clock pulse cycle, the
SDA pin is released in order to receive the acknowledge signal from the receiver. In the
receiver mode during the clock pulse cycle, the SDA pin is set to the low level in order to
generate the acknowledge signal.
Set <ACK> to 0 for operation in the non-acknowledge mode. The TMP93CS44/S45
does not generate a clock pulse for the acknowledge signal when operating in the
master mode.
In the acknowledgment mode, when the TMP93CS44/S45 is the slave mode, clocks
are counted for the acknowledge signal. During the clock for the acknowledge signal,
when a received slave address matches to a slave address set to the I2CAR or a
GENERAL CALL is received, the SDA pin is set to low level generating an
acknowledge signal.
After a received slave address matches to a slave address set to the I2CAR and a
GENERAL CALL is received, in the transmitter mode during the clock for the
acknowledge signal, the SDA pin is released in order to receive the acknowledge signal
from the receiver. In the receiver mode, the SDA pin is set to low level generating an
acknowledge signal.
In the non-acknowledgment mode, when the TMP93CS44/S45 is the slave mode,
clocks for the acknowledge signal are not counter.
(2) Number of transfer bits
SBICR1<BC2:0> are used to select a number of bits for transmitting and receiving
data.
Since <BC2:0> are cleared to 000 as a start condition, a slave address and direction
bit transmissions are executed in 8 bits. Other than these, <BC2:0> retain a specified
value.
(3) Serial clock
1.
Clock source
SBICR1<SCK2:0> are used to select a maximum transfer frequency output on
the SCL pin in the master mode. Set the baud rates, which have been calculated
according to the formula below, to meet the specifications of the I2C bus, such as
the smallest pulse width of tLOW.
tHIGH
tLOW
tLOW = 2n/fFPH
tHIGH = 2n/fFPH + 12/fFPH
fscl = 1/(tLOW + tHIGH)
fFPH
=
2 × 2n + 12
1/fscl
<SCK2:0>
(Bits 2 to 0 in the SBICR1)
000
001
010
011
100
101
110
n
4
5
6
7
8
9
10
Figure 3.10.7 Clock Source
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2004-02-10
TMP93CS44/S45
2.
Clock synchronization
The I2C bus has a clock synchronization function to meet the transfer speed to a
slow processing device when a transfer is performed between device which have
different process speed.
The clock synchronization functions when the SCL pin is high level and the SCL
line of the bus is low level in the serial bus interface circuit. The serial bus
interface circuit waits counting a clock pulse in high level until the SCL line of the
bus is high level. When the SCL line of the bus is high level, the serial bus
interface circuit starts counting during high level. The clock synchronization
function holds clocks which are output from the serial interface circuit to be high
level.
The slave device can stop the clock output of the master device on one word or
one bit basis.
Additionally, the transfer speed by the master device matches to the process
speed of the slave device.
SCL pin (Master device)
Wait
Start counting high-level width of a
clock pulse
SCL pin (Slave device)
SCL (Bus)
Figure 3.10.8 Clock Synchronization
(4) Slave address and address recognition mode specification
To operate the TMP93CS44/S45 in the addressing format which recognizes the slave
address, set I2CAR<ALS> to 0 and set the slave address to the I2CAR<SA6:0>.
To operate the serial bus interface circuit in the free data format which does not
recognize the slave address, set <ALS> to 1. When the TMP93CS44/S45 used in the
free data format, the slave address and the direction bit are not recognized. They are
handled as data just after generation of start conditions.
(5) Master/slave selection
Set SBICR2<MST> to 1 for operating the TMP93CS44/S45 as a master device.
<MST> is cleared to 0 by the hardware after a stop condition on a bus is detected.
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2004-02-10
TMP93CS44/S45
(6) Transmitter/receiver selection
Set SBICR2<TRX> to 1 for operating the TMP93CS44/S45 as a transmitter. Set
<TRX> to 0 for operation as a receiver. When data with an addressing format is
transferred in the slave mode, when a slave address with the same value that an
I2CAR or the GENERAL CALL is received (All 8-bit data are 0 after the start
condition), <TRX> is set to 1 by the hardware if the direction bit (R/W) sent from the
master device is 1, and is set to 0 by the hardware if the bit is 0. In the master mode,
after the acknowledge signal is returned from the slave device, <TRX> is set to 0 by the
hardware if a transmitted direction bit is 1, and set to 1 by the hardware if it is 0. When
the acknowledge signal is not returned, the current condition is maintained.
<TRX> is cleared to 0 by the hardware after the stop condition on the I2C bus is
detected.
The following shows <TRX> change conditions in each mode and <TRX> after
changing.
Mode
<TRX> after
Changing
Direction Bit
Change Condition
0
A received slave address is the same as
a value set to I2CAR.
Slave Mode
1
0
Master Mode
0
1
1
ACK signal is returned.
1
0
When the TMP93CS44/S45 operates in the free data format, the slave address and
the direction bit are not recognized. They are handled as data just after generating a
start condition. The TRX was not changed by the hardware.
(7) Start/stop condition generation
When SBICR2<BB> is 0, the start condition and slave address and direction bit are
output by writing 1 to SBICR2<MST, TRX, BB, PIN>. It is necessary to set 1 to
SBICR1<ACK> beforehand.
SCL line
1
2
3
4
5
6
7
8
SDA line
A6
A5
A4
A3
A2
A1
A0
R/ W
Start condition
Slave address and the direction bit
9
Acknowledge signal
Figure 3.10.9 Start Condition Generation and Slave Address Generation
When SBICR2<BB> is 1, a sequence of generating the stop condition is started by
writing 1 to <MST, TRX, PIN> and 0 to <BB>. Do not modify the contents of <MST,
TRX, BB, PIN> until the stop condition is generated on a bus.
When a stop condition is generated and the SCL line on the bus is set to low level by
another device, a stop condition is generated after releasing the SCL line.
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2004-02-10
TMP93CS44/S45
SCL line
SDA line
Stop condition
Figure 3.10.10 Stop Condition Generation
The bus condition can be indicated by reading the contents of <BB>. <BB> is set to 1
when the start condition on a bus is detected, and is set to 0 when the stop condition is
detected.
(8) Cancel interrupt service request
When the TMP93CS44/S45 is the master mode and transferring a number of clocks
set by the SBICR1<BC2:0> and the SBICR1<ACK> is complete, a serial bus interface
interrupt request (INTS2) is generated.
In the slave mode, the INTS2 is generated when the received slave address is the
same as the value set to the I2CAR and an acknowledge signal is output, when a
GENERAL CALL is received and an acknowledge signal is output, or when
transferring/receiving data is complete after the received slave address is the same as
the value set to the I2CAR and a GENERAL CALL is received.
When the serial bus interface interrupt request occurs, the SBISR<PIN> is cleared
to 0. During the time that the PIN is 0, the SCL pin is set to low level.
Either writing or reading data to or from the SBIDBR sets the <PIN> to 1.
The time from the <PIN> being set to 1 until the SCL pin is released takes tLOW.
Although the <PIN> can be set to 1 by the program, the <PIN> is not cleared to 0
when it is written 0.
(9) Serial bus interface operation mode selection
SBICR2<SBIM1:0> is used to specify the serial bus interface operation mode. Set
<SBIM1:0> to 10 when used in the I2C bus mode after confirming that input signal via
port is high level.
Switch a mode to port after making sure that a bus is free.
(10) Noise detection monitor
The I2C bus is easy to be affected by noise, because the bus is driven by the open
drain and the pull-up resistor.
With the TMP93CS44/S45, the SDA pin output and the SDA line level are compared
at a rise of the SCL line on the bus, and whether data are output correctly on the bus is
detected only in the master transmitter mode.
When the SDA pin output differs from the SDA line level, the SBISR<AL> is set to 1.
When the AL is set to 1, the SDA pin is released and the MST and the TRX are
cleared to 0 by the hardware. The TMP93CS44/S45 changes to the slave receiver mode,
and continues outputting clocks unit transferring data when the AL was set to 1 is
completed.
Either writing or reading data to or from the SBIDBR, or writing data to the SBICR2
clears to the AL to 0.
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2004-02-10
TMP93CS44/S45
SCL (Bus)
SDA pin
SDA (Bus)
Noise
Noise detection
<AL>
<MST>
<TRX>
Figure 3.10.11 Noise Detection Monitor
(11) Slave address match detection monitor
SBISR<AAS> is set to 1 in the slave mode, in the address recognition mode (I2CAR
<ALS> = 0) when receiving the GENERAL CALL or the slave address with the same
value that is set to the I2CAR. When <ALS> is 1, <AAS> is set to 1 after receiving the
first 1 word of data. <AAS> is set to 0 by writing/reading data to/from a data buffer
register.
(12) GENERAL CALL detection monitor
SBISR<AD0> is set to 1 in the slave mode, when the GENERAL CALL is received
(All 8-bit data are 0 after the start condition). <AD0> is set to 0 when the start or stop
condition is detected on a bus.
(13) Last received bit monitor
The SDA line value stored at the rising edge of the SCL line is sent to SBISR<LRB>.
In the acknowledge mode, immediately after the INTS2 interrupt request is generated,
the acknowledge signal is read by reading the contents of <LRB>.
(14) Software reset function
Software reset function is used to initialize the SBI which is rocked by external noise,
etc. When SBICR3<SWRST> is set to 1, the internal reset signal pulse is generated
and inputted into the SBI circuit.
All command registers and state registers are initialized to initial values. <SWRST>
is automatically set to 0 after the SBI circuit is initialized.
(15) Serial bus interface data buffer register (SBIDBR)
The SBIDBR register can read out the receiving data and write the sending data.
After the start condition generated in the master mode, set the slave address and the
direction bit in this register.
(16) I2C bus address register (I2CAR)
I2CAR<SA6:0> sets the slave address when the TMP93CS44/S45 are operated as the
slave devices. Setting I2CAR<ALS> = 0, the slave address output from master device is
recognized, and the data format is changed to the addressing format. Setting
I2CAR<ALS> = 1, the slave address is not recognized, and the data format is changed
to the free data format.
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2004-02-10
TMP93CS44/S45
3.10.5
Data Transfer in I2C Bus Mode
(1) Device initialization
First, set SBICR1<ACK, SCK2:0>. Specify 0 to bits 7 to 5 and 3 in the SBICR1.
Set the slave address <SA6:0> and <ALS> to I2CAR (<ALS> = 0 when the
addressing format).
Subsequently, set 0 to <MST, TRX, BB>; 1 to <PIN>; 10 to <SBIM1:0>; and 0 to bits 0
and 1 in the SBICR2. The slave receiver mode is set.
Note:
The initialization of the serial bus interface circuit must be complete within the time
from all devices which are connected to the bus have initialized to any device does
not generate a start condition. If not, there is a possibility that another device starts
transferring before an end of the initialization of the serial bus interface circuit. Data
can not be received correctly.
(2) Start condition and slave address generation
Confirm a bus free status (when SIBSR<BB> = 0).
Set the SBICR1<ACK> to 1 and specify a slave address and a direction bit to be
transmitted to the SBIDBR.
When the SBISR<BB> is 0, the start condition are generated and the slave address
and the direction bit which are set to the SBIDBR are output on a bus by wiring 1 to
the SBICR2<MST, TRX, BB> and PIN. An INTS2 interrupt request occurs at the 9th
falling edge of the SCL clock cycle, and the <PIN> is cleared to 0. The SCL pin is pulled
down to the low-level while the <PIN> is 0. When an interrupt request occurs, the
<TRX> changes by the hardware according to the direction bit only when an
acknowledge signal is returned from the slave device.
Note : Do not write a slave address to be output to the SBIDBR while data are transferred.
If data is written to the SBIDBR, data to been outputting may be destroyed.
SCL pin
1
2
3
4
5
6
7
8
SDA pin
A6
A5
A4
A3
A2
A1
A0
R/ W
Start condition
Slave address + Direction bit
9
Acknowledge signal
from a slave device
<PIN>
INTS2
interrupt request
Figure 3.10.12 Start Condition Generation and Slave Address Transfer
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2004-02-10
TMP93CS44/S45
(3) 1-word data transfer
Test SBISR<MST> by the INTS2 interrupt process after a 1-word data transfer is
completed, and determine whether the mode is a master or slave.
1.
When <MST> is “1” (Master mode)
Test SBISR<TRX> and determine whether the mode is a transmitter or
receiver.
When <TRX> is “1” (Transmitter mode)
Check SBISR<LRB>. When <LRB> is 1, a receiver does not request data.
Implement the process to generate the stop condition (Described later) and
terminate data transfer.
When <LRB> is 0, the receiver requests new data. When the next transmitted
data is 8 bits, write it to the SBIDBR. When the next transmitted data is other
than 8 bits, set SBICR1<BC2:0>, set SBICR1<ACK> to 1, and write the
transmitted data to the SBIDBR. After writing the data, SBISR<PIN> becomes 1,
the serial clock pulse is generated for transferring a new 1 word of data from the
SCL pin, and then the 1-word data is transmitted. After the data is transmitted,
the INTS2 interrupt request occurs. <PIN> becomes 0 and the SCL pin is set to
the low level. If the data to be transferred is more than one word in length, repeat
the procedures from <LRB> test mentioned above.
SCL pin
1
2
3
4
5
6
7
8
D7
D6
D5
D4
D3
D2
D1
D0
9
Write to SBIDBR
SDA pin
Acknowledge signal
from a receiver
<PIN>
INTS2
interrupt request
Figure 3.10.13 Example of when <BC2:0> = “000”, <ACK> = “1” (Transmitter mode)
When <TRX> is “0” (Receiver mode)
When the next transmitted data is other than 8 bits, set SBICR1<BC2:0> again.
Set <ACK> to 1 and read the received data from the SBIDBR to release the SCL
line. The read data is undefined immediately after the slave address is set. After
the data is read, <PIN> becomes 1. Serial clock pulse for transferring new 1 word
of data is defined SCL and outputs “L” level from SDA pin with acknowledge
timing.
The INTS2 interrupt request then occurs and <PIN> becomes 0. The SCL pin is
set to the low level. The TMP93CS44/S45 outputs a clock pulse for 1 word of data
transfer and the acknowledge signal each time that received data is read from the
SBIDBR.
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2004-02-10
TMP93CS44/S45
Read SBIDBR
SCL pin
1
2
3
4
5
6
7
8
SDA pin
D7
D6
D5
D4
D3
D2
D1
D0
9
New D7
Acknowledge signal
to a transmitter
<PIN>
INTS2
interrupt request
Figure 3.10.14 Example of when <BC2:0> = “000”, <ACK> = “1” (Receiver mode)
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2004-02-10
TMP93CS44/S45
In order to terminate the transmitting data to the transmitter, set <ACK> to 0
before reading data which is 1 word before the last data to be received. The last
data does not generate a clock pulse for the acknowledge signal. After the data is
transmitted and an interrupt request has occurred, set <BC2:0> to 001 and read
the data. The TMP93CS44/S45 generates a clock pulse for a 1-bit data transfer.
Since the master device is a receiver, the SDA line of the bus keeps the high level.
The transmitter receives the high-level signal as the ACK signal. The receiver
indicates to the transmitter that data transfer is complete.
After 1-bit data is received and the interrupt request has occurred, the
TMP93CS44/S45 generates the stop condition and terminates data transfer.
SCL pin
1
2
3
4
5
6
7
8
SDA pin
D7
D6
D5
D4
D3
D2
D1
D0
1
Acknowledge signal
sent to a transmitter
<PIN>
INTS2
interrupt request
“0” → <ACK> Read SBIDBR
"001" → <BC2:0>
Read SBIDBR
Output of master
Output of slave
Figure 3.10.15 Termination of Data Transfer in Master Receiver Mode
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2004-02-10
TMP93CS44/S45
2.
When <MST> is “0” (Slave mode)
In the slave mode, the TMP93CS44/S45 operates either in normal slave mode or
in recovery process after a noise detection.
In the slave mode, an INTS2 interrupt request occurs when the serial bus
interface circuit receives a slave address or a GENERAL CALL from the master
device, or when a GENERAL CALL is received and data transfer is complete after
matching a received slave address. In the master mode, the TMP93CS44/S45
operates in a slave mode if a noise is detected. An INTS2 interrupt request occurs
when word data transfer terminates after a noise detection. When an INTS2
interrupt request occurs, the SBISR<PIN> is reset, and the SCL pin is set to low
level. Either reading or writing from or to the SBIDBR or setting the <PIN> to 1
releases the SCL pin after taking tLOW time.
The TMP93CS44/S45 tests the SBISR<AL>, the SBISR<TRX>, the <AAS>, and
the <AD0> and implements processes according to conditions listed in the next
table.
Table 3.10.1 Operation in the Slave Mode
<TRX>
<AL>
1
0
0
0
<AAS> <AD0>
Conditions
Process
1
0
In the slave receiver mode, the
Set the number of bits in 1 word to <BC2:0>
TMP93CS44/S45 receives a slave
and write transmitted data to the SBIDBR.
address of which the direction bit sent
from the master is “1”.
0
0
In the slave transmitter mode, 1-word
data is transmitted.
1
1/0
Read the SBIDBR for setting <PIN> to “1”
In the slave receiver mode, the
(Reading dummy data) or write “1” to <PIN>.
TMP93CS44/S45 receives a slave
address or GENERAL CALL of which
the direction bit sent from the master is
“0”.
0
1/0
Set the number of bits in a word to <BC2:0>
In the slave receiver mode, the
TMP93CS44/S45 terminates receiving and read received data from the SBIDBR.
of 1-word data.
93CS44-162
Check <LRB>. If <LRB> is set to “1”, set <PIN>
to “1” since the receiver does not request next
data. Then, clear <TRX> to “0” release the
bus. If <LRB> is set to “0”, set the number of
bits in a word to <BC2:0> and write transmitted
data to the SBIDBR since the receiver
requests next data.
2004-02-10
TMP93CS44/S45
(4) Stop condition generation
When SBISR<BB> is 1, a sequence of generating a stop condition is started by
writing 1 to SBICR2<MST, TRX, PIN>, and 0 to <BB>. Do not modify the contents of
<MST, TRX, BB, PIN> until the stop condition is generated on the bus. When
SBICR2<MST, TRX, PIN> are written “1” and <BB> is written “0” (generate stop
condition in master mode), <BB> changes to “0” by internal SCL changes to “1”,
without waiting stop condition. To check whether SCL and SDA pin are “1” by sensing
their ports is needed to detect bus free condition.
“1” → <MST>
“1” → <TRX>
“0” → <BB>
“1” → <PIN>
Stop condition
Internal SCL
SCL pin
SDA pin
<PIN>
<BB> (Read)
Figure 3.10.16 Stop Condition Generation
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2004-02-10
TMP93CS44/S45
(5) Restart
Restart is used to change the direction of data transfer between a master device and
a slave device during transferring data. The following explains how to restart the
TMP93CS44/S45.
Clear 0 to the <MST>, <TRX>, and <BB> and set 1 to the <PIN>. The SDA pin
retains the high level and the SCL pin is released. Since a stop condition is not
generated on the bus, the bus is assumed to be in a busy state from other devices. And
confirm SCL pin, that SCL pin is released and become bus-free state by SBISR<BB> =
“0” or signal level “1” of SCL pin in port mode. Test the <LRB> until it becomes 1 to
check that the SCL line of the bus is not set to low level by other devices. After
confirming that the bus stays in a free state, generate a start condition with procedure
(2).
In order to meet setup time when restarting, take at least 4.7 µs of waiting time by
software from the time of restarting to confirm that the bus is free until the time to
generate the start condition.
“1” → <MST>
“1” → <TRX>
“1” → <BB>
“1” → <PIN>
“0” → <MST>
“0” → <TRX>
“0” → <BB>
“1” → <PIN>
4.7 µs (Min)
Start condition
SCL (Bus)
SCL pin
9
SDA pin
<LRB>
<BB>
<PIN>
Figure 3.10.17 Timing Diagram when Restarting the TMP93CS44/S45
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2004-02-10
TMP93CS44/S45
3.10.6
Clock Synchronous 8-Bit SIO Mode Control
The following registers are used for control and operation status monitoring when using
the serial bus interface (SBI) in the clock synchronous 8-bit SIO mode.
Serial Bus Interface Control Register 1
SBICR1
(004BH)
Bit symbol
6
5
4
2
1
0
SIOINH
SIOM1
SIOM0
SCK2
SCK1
SCK0
0
0
0
0
0
Read/Write
After reset
Prohibit
readmodifywrite
7
SIOS
W
Indication
transfer
start/stop
0: Stop
1: Start
Function
3
Continue/
abort
transfer
0: Continue
1: Abort
W
Transfer mode select
00: 8-bit transmit
01: (Reserved)
10: 8-bit transmit/receive
11: 8-bit receive
0
0
Serial clock selection
Serial clock selection
000 fc/25 (625 kHz)
fc/26 (312.5 kHz)
fc/27 (156.3 kHz)
System clock: fc
fc/28 ( 78.13 kHz)
Clock gear: fc/1
fc/29 ( 39.06 kHz)
fc = 20 MHz (Output on SCK PIN)
fc/210 ( 19.53 kHz)
fc/211 ( 9.77 kHz)
External clock (Input from SCK pin)
001
010
011
100
101
110
111
Transfer mode select
00 8-bit transmit mode
01
Reserved
10
8-bit transmit/receive mode
11
8-bit receive mode
Continue/abort transfer
0 Continue transfer
1
Abort transfer (Automatically cleared after abort)
Indicate transfer start/stop
0 Stop
1
Note:
Start
Set <SIO> to 0 and <SIOINH> to 1 when setting the transfer mode and the serial clock.
Serial Bus Interface Data Buffer Register
7
6
5
DB7
DB6
DB5
4
3
2
1
0
DB4
DB3
DB2
DB1
DB0
SBIDBR
(004CH)
Bit symbol
Read/Write
R (Receive)/W (Send)
Prohibit
readmodifywrite
After reset
Undefined
Figure 3.10.18 Registers for SIO Mode (1/2)
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2004-02-10
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Serial Bus Interface Control Register 2
7
SBICR2
(004EH)
6
5
4
Bit symbol
2
SBIM0
Read/Write
1
0
W
After reset
Prohibit
readmodifywrite
3
SBIM1
0
0
Serial bus interface
operation mode selection
Function
00: Port mode
01: SIO mode
10: I2C bus mode
11: (Reserved)
Serial bus interface operation mode selection
00 Port mode (Serial bus interface output disable)
01
SIO mode
10
I2C bus mode
11
(Reserved)
Note 1:
Switch a mode to port after data transfer is complete.
Note 2:
Switch a mode to SIO mode after confirming that input signals via port are high level.
Serial Bus Interface Status Register
7
SBISR
(004EH)
6
5
4
Bit symbol
2
SEF
Read/Write
1
0
R
After reset
Prohibit
readmodifywrite
3
SIOF
0
Serial
tarnsfer
operating
status
monitor
Function
0
Shift
operating
status
monitor
Shift operating status monitor
0 Shift operation terminated
1
Shift operation in process
Serial transfer operating status monitor
0 Transfer terminated
1
Transfer in process
Figure 3.10.19 Registers for SIO Mode (2/2)
93CS44-166
2004-02-10
TMP93CS44/S45
(1) Serial clock
1.
Clock source
SBICR1<SCK2:0> are used to select the following functions.
Internal clock
In the internal clock mode, any of seven frequencies can be selected. The
serial clock is output to the outside on the SCK pin. The SCK pin becomes a
high level when data transfer starts. When writing (in the transmit mode) or
reading (in the receive mode) data cannot follow the serial clock rate, an
automatic-wait function is executed to stop the serial clock automatically and
hold the next shift operation until reading or writing is complete.
Automatic-wait function
SCK pin output
1
2
7
3
8
1
a0 a1 a2 a5 a6 a7
SO pin output
Write transmitted
data
2
6
7
8
1
2
3
b0 b1 b4 b5 b6 b7 c0 c1 c2
a
b
c
Figure 3.10.20 Automatic-wait Function
External clock (<SCK2:0> = 111)
An external clock supplied to the SCK pin is used as the serial clock. In
order to ensure shift operation, a pulse width of at least 4 machine cycles is
required for both high and low levels in the serial clock. The maximum data
transfer frequency is 625 kHz. (fc = 20 MHz.)
SCK pin
tSCKL tSCKH
tSCKL, tSCKH > 4 tcyc
tcyc: 4/fFPH (in NORMAL mode, IDLE mode)
Figure 3.10.21 External Clock
93CS44-167
2004-02-10
TMP93CS44/S45
2.
Shift edge
The leading edge is used to transmit data, and the trailing edge is used to
receive data.
Leading edge shift
Data is shifted on the leading edge of the serial clock (at the falling edge of
the SCK pin input/output).
Trailing edge shift
Data is shifted on the trailing edge of the serial clock (at the rising edge of
the SCK pin input/output).
SCK pin
SO pin
Shift register
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
76543210 *7654321 **765432 ***76543 ****7654 *****765 ******76
Bit7
*******7
(a) Leading edge
SCK pin
SI pin
Shift register
Bit0
********
Bit1
0*******
Bit2
10******
Bit3
Bit4
Bit5
Bit6
Bit7
210***** 3210**** 43210*** 543210** 6543210* 76543210
(b) Trailing edge
*: Don’t care
Figure 3.10.22 Shift Register
93CS44-168
2004-02-10
TMP93CS44/S45
(2) Transfer mode
SBICR1<SIOM1:0> are used to select a transmit, receive, or transmit/receive mode.
1.
8-bit transmit mode
Set a control register to a transmit mode and write data to the SBIDBR.
After the data is written, set SBICR1<SIOS> to 1 to start data transfer. The
transmitted data is transferred from the SBIDBR to the shift register and output
to the SO pin in synchronous with the serial clock, starting from the least
significant bit (LSB). When the data is transferred to the shift register, the
SBIDBR becomes empty. The INTS2 (Buffer empty) interrupt request is
generated to request new data.
When the internal clock is used, the serial clock will stop and automatic-wait
function will be initiated if new data is not loaded to the data buffer register after
the specified 8-bit data is transmitted. When new data is written, automatic-wait
function is canceled.
When the external clock is used, data should be written to the SBIDBR before
new data is shifted. The transfer speed is determined by the maximum delay time
between the time when an interrupt request is generated and the time when data
is written to the SBIDBR by the interrupt service program.
When the transmit is started, after SBISR<SIOF> goes 1 the same value as the
final bit of the last data is output until the falling edge of the SCK.
Transmitting data is ended by clearing <SIOS> to 0 with the buffer empty
interrupt service program or setting SBICR1<SIOINH> to 1. When <SIOS> is
cleared, the transmitted mode ends when all data is output. In order to confirm if
data is surely transmitted by the program, set <SIOF> to be sensed. <SIOF> is
cleared to 0 when transmitting is complete. When <SIOINH> is set to 1,
transmitting data stops. <SIOF> turns 0.
When the external clock is used, it is also necessary to clear <SIOS> to 0 before
new data is shifted; otherwise, dummy data is transmitted and operation ends.
93CS44-169
2004-02-10
TMP93CS44/S45
Clear <SIOS>
<SIOS>
<SIOF>
<SEF>
SCK pin (Output)
* a0
SO pin
a1
a2
a3
a4
a5
a6
a7
b0
b1
b2
b3
b4
b5
b6
b7
b6
b7
INTS2 interrupt request
a
SBIDBR
b
Write transmitted data
(a) Internal clock
Clear <SIOS>
<SIOS>
<SIOF>
<SEF>
SCK pin (Input)
* a0
SO pin
a1
a2
a3
a4
a5
a6
a7
b0
b1
b2
b3
b4
b5
INTS2 interrupt request
SBIDBR
a
b
Write transmitted data
(b) External clock
Figure 3.10.23 Transfer Mode
Example: Program to stop transmitting data (when external clock is used).
STEST1:
BIT
SEF, (SBISR)
; If <SEF> = 1 then loop.
JR
NZ, STEST1
STEST2:
BIT
2, (P3)
; If SCK = 0 then loop.
JR
Z, STEST2
LD
(SBICR1), 00000111B
; <SIOS> ← 0.
93CS44-170
2004-02-10
TMP93CS44/S45
SCK pin
<SIOF>
SO pin
Bit6
Bit7
tSODH = Min 3.5/fFPH [s] (in NORMAL mode)
Figure 3.10.24 Transmitted Data Hold Time at End of Transmit
2.
8-bit receive mode
Set the control register to a receive mode and SBICR1<SIOS> to 1 for switching
to the receive mode. Data is received from the SI pin to the shift register in
synchronous with the serial clock, starting from the least significant bit (LSB).
When the 8-bit data is received, the data is transferred from the shift register to
the SBIDBR. The INTS2 (Buffer full) interrupt request is generated to request to
read the received data. The data is then read from the SBIDBR by the interrupt
service program.
When the internal clock is used, the serial clock will stop and automatic-wait
function will be initiated until the received data is read from the SBIDBR.
When the external clock is used, since shift operation is synchronized with the
clock pulse provided externally, the received data should be read from the
SBIDBR before next serial clock input. If the received data is not read, further
data to be received is canceled. The maximum transfer speed when the external
clock is used is determined by the delay time between the time when an interrupt
request is generated and the time when received data is read.
Receiving data is ended by clearing <SIOS> to 0 with the buffer full interrupt
service program or setting SBICR1<SIOINH> to 1. When <SIOS> is cleared,
received data is transferred to the SBIDBR in complete blocks. The received mode
ends when the transfer is complete. In order to confirm if data is surely received
by the program, set SBISR<SIOF> to be sensed. <SIOF> is cleared to 0 when
receiving is complete. After confirming that receiving has ended, the last data is
read. When <SIOINH> is set to 1, receiving data stops. <SIOF> turns 0 (the
received data becomes invalid, therefore no need to read it).
Note:
When the transfer mode is switched, the SBIDBR contents are lost. In case
that the mode needs to be switched, receiving data is concluded by clearing
<SIOS> to 0, read the last data, and then switch the mode.
93CS44-171
2004-02-10
TMP93CS44/S45
Clear <SIOS>
<SIOS>
<SIOF>
<SEF>
SCK pin (Output)
a0
SI pin
a1
a2
a3
a4
a5
a6
a7
b0
b1
b2
b3
b4
b5
b6
b7
INTS2 interrupt request
a
b
Read received data
Read received data
SBIDBR
Figure 3.10.25 Receive Mode (Example: Internal clock)
3.
8-bit transmit/receive mode
Set a control register to a transmit/receive mode and write data to the SBIDBR.
After the data is written, set SBICR1<SIOS> to 1 to start transmitting/receiving.
When transmitting, the data is output from the SO pin on the leading edges in
synchronous with the serial clock, starting from the least significant bit (LSB).
When receiving, the data is input to the SI pin on the trailing edges of the serial
clock. The 8-bit data is transferred from the shift register to the SBIDBR, and the
INTS2 interrupt request occurs. The interrupt service program reads the received
data from the data buffer register and writes data to be transmitted. The SBIDBR
is used for both transmitting and receiving. Transmitted data should always be
written after received data is read.
When the internal clock is used, automatic-wait function is initiated until
received data is read and next data is written.
When the external clock is used, since the shift operation is synchronized with
the external clock, received data is read and transmitted data is written before
new shift operation is executed. The maximum transfer speed when the external
clock is used is determined by the delay time between the time when an interrupt
request is generated and the time when received data is read and transmitted
data is written.
When the transmit is started, after SBISR<SIOF> = 1 output from the SO pin
holds final bit of last data until falling edge of the SCK.
Transmitting/receiving data is ended by clearing <SIOS> to 0 by the INTS2
interrupt service program or setting SBICR1<SIOINH> to 1. When <SIOS> is
cleared, received data is transferred to the SBIDBR in complete blocks. The
transmit/receive mode ends when the transfer is complete. In order to confirm if
data is surely transmitted/received by the program, set SBISR<SIOF> to be
sensed. <SIOF> becomes 0 after transmitting/receiving is complete. When
<SIOINH> is set, transmitting/receiving data stops. <SIOF> turns 0.
Note:
When the transfer mode is switched, the SBIDBR contents are lost. In case
that the mode needs to be switched, transmitting/receiving data is concluded
by clearing <SIOS> to 0, read the last data, and then switch the transfer mode.
93CS44-172
2004-02-10
TMP93CS44/S45
Clear <SIOS>
<SIOS>
<SIOF>
<SEF>
SCK pin (Output)
SO pin
* a0
a1
a2
a3
a4
a5
a6
a7
b0
b1
b2
b3
b4
b5
b6
b7
c0
c1
c2
c3
c4
c5
c6
c7
d0
d1
d2
d3
d4
d5
d6
d7
SI pin
INTS2 interrupt request
a
SBIDBR
c
Write transmitted
data (a)
b
Read received Write transmitted
data (c) data (b)
d
Read received
data (d)
Figure 3.10.26 Transmit/Receive Mode (Example: Internal clock)
SCK pin
<SIOF>
SO pin
Bit6
Bit7 in last transmitted word
tSODH = Min 4/fFPH [s] (in NORMAL mode)
Figure 3.10.27 Transmitted Data Hold Time at End of Transmit/Receive
93CS44-173
2004-02-10
TMP93CS44/S45
3.11 AD Converter
TMP93CS44/S45 incorporate a high-speed, high-precision 10-bit analog/digital converter (AD
converter) with 8-channel analog input.
Figure 3.11.1 is a block diagram of the AD converter. The 8-channel analog input pins (AN0 to
AN7) are also used as input-only port 5 and can be also used as input ports.
Internal data bus
ADMOD1
<ADCH2:0>
<ADTRGE>
<VREFON>
ADMOD0
<EOCF> <ADBF> <ITM0> <REPET> <SCAN> <ADS>
Decoder
Scan
Repeat
Interrupt
ADTRG
Busy
End
Start
Channel select
AD converter
control circuit
INTAD
interrupt
AN6 (P56)
AN5 (P55)
AN4 (P54)
AN3/ ADTRG (P53)
AN2 (P52)
AN1 (P51)
AN0 (P50)
Multiplexer
Analog input
AN7 (P57)
AD conversion
result register
ADREG04L to 37L
ADREG04H to 37H
Sample
hold
VREFH
DA converter
VREFL
Figure 3.11.1 Block Diagram of AD Converter
Note 1:
When the power supply current is reduced in IDLE2, IDLE1, STOP mode, there is possible to set
a standby enabling the internal comparator due to a timing. Stop operation of AD converter before
execution of “HALT” instruction.
Note 2:
In regard to the lowest operation frequency.
The operation of AD converter is guaranteed with clock of fFPH ≥ 4 MHz (Used fc clock). Is not
guaranteed with fs clock.
93CS44-174
2004-02-10
TMP93CS44/S45
3.11.1
AD converter registers
AD converter is controlled by two AD mode control registers (ADMOD0 and ADMOD1).
AD conversion result is stored in eight AD conversion result registers (ADREG04H/L,
ADREG15H/L, ADREG26H/L, ADREG37H/L).
AD Mode Control Register 0
7
ADMOD0
(005EH)
Bit symbol
EOCF
Read/Write
After reset
Function
6
5
4
3
AD8F
−
−
ITM0
R
0
2
1
0
REPET
SCAN
ADS
0
0
R/W
0
AD
conversion
end flag
AD
conversion
busy flag
0: Conversion in
progress
1: Conversion is
idle
1: Conversion end
1: Conversion in
progress
0
0
0
Always write Always write Specifies
Repeat mode Scan mode
“0”.
interrupts for specification specification
“0”.
fixed channel 0: Single
0: Fixed/repeat
converchannel
conversion
sion mode
mode
mode.
1: Repeat
1: Channel
0: Every
converscan mode
conversion mode
sion
1: Every four
conversions
0
AD
conversion
start
0: Don’t
care
1: Start
conversion
Always read
as “0”.
AD conversion start
0 Don’t care
1
Start AD conversion
AD scan mode specification
0 AD conversion fixed-channel mode
1
AD conversion channel scan mode
AD repeat mode specification
0 AD single conversion mode
1
AD repeat conversion mode
AD specifies interrupts for fixed
channel/repeat conversion mode
Fixed channel/repeat conversion mode
<SCAN> = “0”, <REPET> = “1”
0
Generates interrupt every conversion
1
Generates interrupt every four
conversions
AD conversion busy flag
0 AD conversion is idle
1
AD conversion in progress
AD conversion end flag
0 AD conversion in progress
1
AD conversion end
Figure 3.11.2 Register for AD Converter (1/4)
93CS44-175
2004-02-10
TMP93CS44/S45
AD Mode Control Register 1
7
ADMOD1
(005FH)
6
Bit symbol
VREFON
Read/Write
R/W
After reset
1
Function
5
4
3
2
1
0
ADTRGE
ADCH2
ADCH1
ADCH0
0
0
0
0
R/W
String
resistor
External
Analog input channel
trigger start
0: OFF
selection
control
1: ON
0: Disable
1: Enable
Analog input channel selection
<SCAN>
<ADCH2:0>
000
001
010
011 (Note)
100
101
110
111
1
Channel
scan
0
Channel
fix
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN0
AN0 → AN1
AN0 → AN1 → AN2
AN0 → AN1 → AN2 → AN3
AN4
AN4 → AN5
AN4 → AN5 → AN6
AN4 → AN5 → AN6 → AN7
Conversion start control by external trigger
( ADTRG pin input)
0 Disable
1
Enable
Analog reference voltage control
0 OFF
1
ON
Set the <VREFON> bit to 1 before starting
conversion (before writing 1 to
ADMOD0<ADS>).
Note: As the AN3 and the ADTRG are the same pin, <ADCH2:0> = 011 can’t be set when <ADTRGE> is set to 1
and ADTRG is used.
Figure 3.11.3 Register for AD Converter (2/4)
93CS44-176
2004-02-10
TMP93CS44/S45
AD Conversion Result Register 0/4 Low
ADREG04L
(0060H)
Bit symbol
7
6
ADR01
ADR00
5
Read/Write
R
After reset
Undefined
Stores lower 2 bits of
AD conversion result.
Function
4
3
2
1
0
ADR0RF
R
0
Conversion
result tored
flag
1: Exist result
AD Conversion Result Register 0/4 High
ADREG04H Bit symbol
(0061H)
Read/Write
7
6
5
4
ADR09
ADR08
ADR07
ADR06
3
2
1
0
ADR05
ADR04
ADR03
ADR02
R
After reset
Undefined
Stores upper 8 bits of AD conversion result.
Function
AD Conversion Result Register 1/5 Low
ADREG15L
(0062H)
Bit symbol
7
6
ADR11
ADR10
5
Read/Write
R
After reset
Undefined
Stores lower 2 bits of AD
conversion result.
Function
4
3
2
1
0
ADR1RF
R
0
Conversion
result stored
flag
1: Exist result
AD Conversion Result Register 1/5 High
ADREG15H Bit symbol
(0063H)
Read/Write
7
6
5
4
ADR19
ADR18
ADR17
ADR16
3
2
1
0
ADR15
ADR14
ADR13
ADR12
R
After reset
Undefined
Stores upper 8 bits of AD conversion result.
Function
9
8
7
6
5
4
3
2
1
0
Channel x conversion result
ADREGxH
7 6 5
4
3
2
1
0
7
6
5
4
3
2
ADREGxL
1 0
• Bits 5 to 1 are always read as 1.
• Bit0 is conversion result stored flag bit <ADRxRF>.
<ADRxRF> is set to 1 when the AD conversion result is
stored. Reading either the ADREGxH or the ADREGxL
registers clears <ADRxRF> to 0.
Figure 3.11.4 Register for AD Converter (3/4)
93CS44-177
2004-02-10
TMP93CS44/S45
AD Conversion Result Register 2/6 Low
ADREG26L
(0064H)
Bit symbol
7
6
ADR21
ADR20
5
Read/Write
R
After reset
Undefined
Stores lower 2 bits of
AD conversion result.
Function
4
3
2
1
0
ADR2RF
R
0
Conversion
result stored
flag
1: Exist result
AD Conversion Result Register 2/6 High
ADREG26H Bit symbol
(0065H)
Read/Write
7
6
5
4
ADR29
ADR28
ADR27
ADR26
3
2
1
0
ADR25
ADR24
ADR23
ADR22
R
After reset
Undefined
Stores upper 8 bits of AD conversion result.
Function
AD Conversion Result Register 3/7 Low
ADREG37L
(0066H)
Bit symbol
7
6
ADR31
ADR30
5
Read/Write
R
After reset
Undefined
Stores lower 2 bits of
AD conversion result.
Function
4
3
2
1
0
ADR3RF
R
0
Conversion
result stored
flag
1: Exist result
AD Conversion Result Register 3/7 High
ADREG37H Bit symbol
(0067H)
Read/Write
7
6
5
4
ADR39
ADR38
ADR37
ADR36
3
2
1
0
ADR35
ADR34
ADR33
ADR32
R
After reset
Undefined
Stores upper 8 bits of AD conversion result.
Function
9
8
7
6
5
4
3
2
1
0
Channel x conversion result
ADREGxH
7 6 5
4
3
2
1
0
7
6
5
4
3
2
ADREGxL
1 0
• Bits 5 to 1 are always read as 1.
• Bit0 is conversion result stored flag bit <ADRxRF>.
<ADRxRF> is set to 1 when the AD conversion result is
stored. Reading either the ADREGxH or the ADREGxL
registers clears <ADRxRF> to 0.
Figure 3.11.5 Register for AD Converter (4/4)
93CS44-178
2004-02-10
TMP93CS44/S45
3.11.2
Operation
(1) Analog reference voltage
High analog reference voltage is applied to the VREFH pin, and low analog reference
voltage is applied to the VREFL pin. The voltage between VREFH and VREFL is
divided into 1024 increments using a string resistor. AD conversion is based on
comparing the analog input voltage with these reference voltage increments.
To turn the switch between VREFH and VREFL off, write 0 to the
ADMOD1<VREFON> bit.
To start AD conversion when the switch is off, first write 1 to <VREFON>. After that,
wait at 3 µs long enough to get the stabilized oscillation, write 1 to ADMOD0<ADS>.
(2) Selecting analog input channels
The procedure for selecting analog input channels depends on the operating mode of
the AD converter.
•
When analog input channel is used to fix (ADMOD0<SCAN> = 0)
To set ADMOD1<ADCH2:0>, selecting one channel from analog input pins AN0
to AN7.
•
When analog input channel is used to scan (ADMOD0<SCAN> = 1)
To set ADMOD1<ADCH2:0>, selecting one channel from 8 scan mode.
Table 3.11.1 shows the analog input channel selection each operating mode.
A reset initializes ADMOD0<SCAN> to 0 and ADMOD1<ADCH2:0> to 000, selecting
pin AN0 for the AD converter input.
The pins not used as analog input channels can be used as general-purpose input
ports (P5).
Table 3.11.1 Analog Input Channel Selection
<ADCH2:0>
Fixed channel
<SCAN> = 0
Channel scan
<SCAN> = 1
000
AN0
AN0
001
AN1
AN0 → AN1
010
AN2
AN0 → AN1 → AN2
011
AN3
AN0 → AN1 → AN2 → AN3
100
AN4
AN4
101
AN5
AN4 → AN5
110
AN6
AN4 → AN5 → AN6
111
AN7
AN4 → AN5 → AN6 → AN7
(3) Starting AD conversion
AD conversion starts when ADMOD0<ADS> to 1, or ADMOD1<ADTRGE> is set to 1
and the falling edge is input through ADTRG pin.
When AD conversion starts, AD conversion busy flag ADMOD0<ADBF> is set to 1,
indicating AD conversion is in progress.
Writing 1 to <ADS> while conversion is in progress restarts the conversion. Check
the conversion result stored flag ADREGxL<ADRxRF> to determine whether the AD
conversion data are valid at this time.
Inputting the falling edge to the ADTRG pin while conversion is in progress is
invalid.
93CS44-179
2004-02-10
TMP93CS44/S45
(4) AD conversion modes and completion interrupt
Follow the four AD conversion modes are supported.
•
Fixed channel single conversion mode
•
Channel scan single conversion mode
•
Fixed channel repeat conversion mode
•
Channel scan repeat conversion mode
AD conversion mode can selected by setting AD mode control register
ADMOD0<REPET, SCAN>.
When AD conversion end, AD conversion completion interrupt INTAD request
occurs. And the ADMOD0<EOCF> flag is set to 1 to indicate that AD conversion has
completed.
1.
Fixed channel single conversion mode
Fixed channel single conversion
ADMOD0<REPET, SCAN> to 00.
mode
can
be
specified
by
setting
In this mode, conversion of the specified single channel is executed once only.
After conversion is completed, ADMOD0<EOCF> is set to 1, ADMOD0<ADBF> is
cleared to 0 and occurs INTAD interrupt request.
2.
Channel scan single conversion mode
Channel scan single conversion
ADMOD0<REPET, SCAN> to 01.
mode
can
be
specified
by
setting
In this mode, conversion of the specified channel are executed once only. After
conversion is completed, ADMOD0<EOCF> is set to 1, ADMOD0<ADBF> is
cleared to 0 and occurs INTAD interrupt request.
3.
Fixed channel repeat conversion mode
Fixed channel repeat conversion
ADMOD0<REPET, SCAN> to 10.
mode
can
be
specified
by
setting
In this mode, conversion of the specified single channel is executed repeatedly.
After conversion is completed, ADMOD0<EOCF> is set to 1, ADMOD0<ADBF>
remains 1 not changed to 0. The timing of INTAD interrupt request can selected
by setting of ADMOD0<ITM0>.
When <ITM0> is set to 0, interrupt request occurs after every conversion.
When <ITM0> is set to 1, interrupt request occurs after every fourth
conversion.
4.
Channel scan repeat conversion mode
Channel scan repeat conversion
ADMOD0<REPET, SCAN> to 11.
mode
can
be
specified
by
setting
In this mode, specified channels are converted repeatedly. After every scan
convert completion, ADMOD0<EOCF> is set to 1 and INTAD interrupt request
occurs. ADMOD0<ADBF> remains 1, not changed to 0.
To stop the repeat conversion mode (3. and 4.), write 0 to ADMOD0<REPET>.
After the current conversion is completed, repeat conversion mode is terminated,
and ADMOD0<ADBF> is cleared to 0.
If the device enters the IDLE2, IDLE1 or STOP modes during AD conversion,
the conversion halt immediately. After the halt mode is released, AD conversion
restarts from the beginning in repeat conversion mode (3. and 4.), it does not
restart in single conversion mode (1. and 2.).
93CS44-180
2004-02-10
TMP93CS44/S45
Table 3.11.2 shows the relations between AD conversion modes and interrupt request.
Table 3.11.2 Relation between AD Conversion Modes and Interrupt Request
ADMOD0
<ITM0> <REPET> <SCAN>
Mode
Interrupt Request
Timing
Fixed channel
single conversion mode
After conversion
X
0
0
Channel scan
single conversion mode
After conversion
X
0
1
After every conversion
0
After every fourth
conversion
1
0
1
After every scan
conversion
X
1
1
Fixed channel repeat
conversion mode
Channel scan
repeat conversion mode
X: Don’t Care
(5) AD conversion time
140 states (14 µs at fc = 20 MHz) are required for AD conversion of one channel.
(6) Storing and reading the AD conversion result
AD conversion results are stored in AD conversion result registers high/low
(ADREG04H/L to ADREG37H/L). These registers are read only.
In fixed channel repeat conversion mode, AD conversion results are stored in order
from ADREG04H/L to ADREG37H/L. Except in this mode, AD conversion results for
channel AN0 and AN4, AN1 and AN5, AN2 and AN6, AN3 and AN7 are stored
severally ADREG04H/L, ADREG15H/L, ADREG26H/L, ADREG37H/L.
Table 3.11.3 shows correspondence between analog input channels and AD
conversion result registers.
Table 3.11.3 Correspondence between Analog Input Channels and
AD Conversion Result Registers
Analog Input
Channel (port 5)
AD Conversion Result Registers
Fixed Channel Repeat
Conversion Modes
Conversion Mode
except Right
(Every fourth conversion)
AN0
ADREG04H/L
AN1
ADREG15H/L
AN2
ADREG26H/L
AN3
ADREG37H/L
AN4
ADREG04H/L
AN5
ADREG15H/L
AN6
ADREG26H/L
AN7
ADREG37H/L
ADREG04H/L
ADREG15H/L
ADREG26H/L
ADREG37H/L
AD conversion result registers bit0 is AD conversion result stored flag <ADRxRF>.
The flag shows that whether those registers are read or not. When AD conversion
results are stored in those registers (ADREGxH or ADREGxL), this flag is set to 1.
When each register is read, this flag is cleared to 0, and AD conversion end flag
ADMOD0<EOCF> is also cleared to 0.
93CS44-181
2004-02-10
TMP93CS44/S45
Setting example:
1. This example converts the analog input voltage at the AN3 pin. The INTAD
interrupt routine writes the result to memory address 0800H.
Main routine setting:
7 6
INTE0AD
ADMOD1
ADMOD0
5
4
3
← 1 1 0 0 −
← 1 X X X 0
← X X 0 0 0
2 1 0
− −
0 1
0 0
−
1
1
Enables INTAD and sets level 4.
Sets analog input channel to AN3.
Starts AD conversion in fixed channel single conversion
mode.
Example of interrupt routine processing:
WA
← ADREG37
Reads ADREG37L and ADREG37H values and writes them
to WA (16 bits).
WA
(0800H)
> > 6
← WA
Shifts right WA six times and zero fills the upper bits.
Writes contents of WA to memory address 0800H.
2.
INTE0AD
ADMOD1
ADMOD0
This example repeatedly converts the analog input voltages at pins AN0 to AN2,
using channel scan repeat conversion mode.
← 1 0 0 0 −
← 1 X X X 0
← X X 0 0 0
− −
0 1
1 1
−
0
1
Disables INTAD.
Sets AN0 to AN2 as analog input channels.
Starts AD conversion in channel scan repeat conversion
mode.
X: Don’t care, −: No change
93CS44-182
2004-02-10
TMP93CS44/S45
3.12 Watchdog Timer (Runaway detecting timer)
TMP93CS44/S45 contain a watchdog timer of runaway detecting.
The watchdog timer (WDT) is used to return the CPU to the normal state when it detects that
the CPU has started to malfunction (Runaway) due to causes such as noise. When the watchdog
timer detects a malfunction, it generates a non-maskable interrupt INTWD to notify the CPU of
the malfunction.
Connecting the watchdog timer output to the reset pin internally forces a reset.
This watchdog timer consists of 7-stage and 15-stage binary counters.
These binary counters are also used as a warm-up timer for the internal oscillator
stabilization. This is used for releasing the stop and before changing system clock.
3.12.1
Configuration
Figure 3.12.1 shows the block diagram of the watchdog timer (WDT).
RESET
Internal reset
WDMOD<RESCR>
WDTI interrupt
SYSCR0<WUEF>
Enable
Reset
WDMOD<WDTE>
Q S
Interrupt control
R
Selector
÷2
7-stage
binary
counter
Selector
Selector
WDMOD<WARM>
T45CR<QCU>
Selector
27
WDMOD
<WDTP1:0>
Selector
Write disable code to
WDCR
(B1H)
29 211 213 215
SYSCR0<WUEF>
15-stage binary counter
Reset
Reset
WDT/warm-up changing
Write clear code to
WDCR
(4EH)
HALT instruction
(STOP, IDLE1 mode)
fc/fs changing of warm-up clock
Selector
CPU
fs
Selector
XT1
fc
X1
fc/2
fc/4
÷2
SYSCR1<SYSCK>
fc/8 fc/16
÷2 ÷4 ÷8 ÷16
SYSCR1<GEAR2:0>
Figure 3.12.1 Block Diagram of Watchdog Timer/Warm-up Timer
93CS44-183
2004-02-10
TMP93CS44/S45
The watchdog timer consists of 7-stage and 15-stage binary counters which use system
clock (fSYS) as the input clock. The 15-stage binary counter has fSYS/215, fSYS/217, fSYS/219
and fSYS/221 output. Selecting one of the outputs with the WDMOD<WDTP1:0> register
generates a watchdog timer interrupt and outputs watchdog timer out when an overflow
occurs. The binary counter for the watchdog timer should be cleared to 0 with runaway
detecting result software (Instruction) before an interrupt occurs.
Example:
LDW
LD
SET
(WDMOD), B100H
(WDCR), 4EH
7, (WDMOD)
; Disable.
; Write clear code.
; Enable again.
The runaway detecting result can also be connected to the reset pin internally. In this
case, the watchdog timer resets itself.
WDT counter
n
n
Overflow
0
WDT interrupt
WDT clear
(Software)
Clear code of write
Figure 3.12.2 Normal Mode
Overflow
WDT counter
n
WDT interrupt
Internal reset
8 to 20 states (12.8 to 32 µs at 20 MHz)
Figure 3.12.3 Reset Mode
For warm-up counter, 27 and 29 output of 15-stage binary counter can be selected using
WDMOD<WARM> register. When a stable-external oscillator is used, shorter warm-up
time is available using T45CR<QCU> register. When <QCU> = 1, counting value 27 is
selected. When the watchdog timer is in operation, this shorter warm-up time function
cannot be available. This function can be available by setting <QCU> = 0.
93CS44-184
2004-02-10
TMP93CS44/S45
3.12.2
Control Registers
Watchdog timer (WDT) is controlled by two control registers WDMOD and WDCR.
(1) Watchdog timer mode register (WDMOD)
1.
Setting the detecting time of watchdog timer <WDTP>
This 2-bit register is used to set the watchdog timer interrupt time for detecting
the runaway. This register is initialized to WDMOD<WDTP1:0> = 00 when reset.
The defecting time of WDT is shown Table 3.12.1.
2.
Watchdog timer enable/disable control register <WDTE>
When reset, WDMOD<WDTE> is initialized to 1 enable the watchdog timer.
To disable, it is necessary to set this bit to 0 and write the disable code (B1H) in
the watchdog timer control register WDCR. This makes it difficult for the
watchdog timer to be disabled by runaway.
However, it is possible to return from the disable state to enable state by merely
setting <WDTE> to 1.
3.
Watchdog timer out reset connection <RESCR>
This register is used to connect the output of the watchdog timer with RESET
terminal, internally. Since WDMOD<RESCR> is initialized to 0 at reset, a reset
by the watchdog timer will not be performed.
(2) Watchdog timer control register (WDCR)
This register is used to disable and clear of binary counter the watchdog timer
function.
•
Disable control
By writting the disable code (B1H) in this WDCR register after clearing
WDMOD<WDTE> to 0, the watchdog timer can be disabled.
WDMOD
WDCR
← 0
← 1
−
0
− −
1 1
−
0
−
0
X X
0 1
Clear WDMOD<WDTE> to “0”.
Write the disable code (B1H).
X: Don’t care, −: No change
•
Enable control
Set WDMOD<WDTE> to 1.
•
Watchdog timer clear control
The binary counter can be cleared and resume counting by writing clear code
(4EH) into the WDCR register.
WDCR
← 0
1
0 0
1
1
1
0
Write the clear code (4EH).
93CS44-185
2004-02-10
TMP93CS44/S45
Watchdog Timer Mode Control Register
WDMOD
(005CH)
Bit symbol
7
6
5
4
3
2
1
0
WDTE
WDTP1
WDTP0
WARM
HALTM1
HALTM0
RESCR
DRVE
1
0
0
0
Read/Write
R/W
After reset
Function
WDT
Select detecting time
control
00: 2 /fSYS
15
0: Disable
1: Enable
0
Warm-up
time
0
0
01: 217/fSYS
00: RUN mode
10: 219/fSYS
01: STOP mode
11: 221/fSYS
10: IDLE1 mode
0
1: Internally
connects
WDT out
to the
reset pin
Standby mode
1: Drive the
pin even
in STOP
mode
11: IDEL2 mode care
(See Table 3.12.1)
Please refer to the section 3.3
“Dual Clock, Standby Function”.
Watchdog timer enable/disable control
0 Disable
1
Watchdog timer out control
0 Don’t care
Enable
1
Connects WDT out to a reset
at fc = 20M Hz, fs = 32.768 kHz
Selection of warm-up time when changing clock
WDMOD<WARM>
Changing to Normal (fc)
14
Changing to Slow (fc)
0 (2 /oscillation frequency)
0.8192 ms
500 ms
0 (216/oscillation frequency)
3.2768 ms
2000 ms
Selection of warm-up time when returning from the stop mode at fc = 20M Hz, fs = 32.768 kHz
Warm-up Time
System Clock
Gear Value
T45CR<QCU>
=0
T45CR<QCU> = 1
Selection <SYSCK>
<GEAR2:0>
<WARM> = 0
<WARM> = 1
<WARM> = X
1 (fs)
0 (fc)
XXX
(Don’t care)
0.500 s
2.000 s
3.9 ms
000 (fc)
0.8192 ms
3.277 ms
6.4 µs
001 (fc/2)
1.638 ms
6.544 ms
12.8 µs
010 (fc/4)
3.277 ms
13.107 ms
25.6 µs
011 (fc/8)
6.554 ms
26.214 ms
51.2 µs
100 (fc/16)
13.107 ms
52.429 ms
102.4 µs
Note: When the watchdog timer is in operation, T45CR<QCU> is set to 0.
Figure 3.12.4 Watchdog Timer Related Register (1/2)
93CS44-186
2004-02-10
TMP93CS44/S45
Watchdog Timer Control Register
7
WDCR
(005DH)
6
5
4
3
Bit symbol
−
Read/Write
W
1
0
−
After reset
Function
2
B1H: WDT disable code
4EH: WDT clear code
Disable/clear WDT
B1H
Disable code
4EH
Clear code
Others
Don’t care
Note: When the watchdog timer is in operation, T45CR<QCU> is set to 0.
Figure 3.12.5 Watchdog Timer Related Register (2/2)
Table 3.12.1 Watchdog Timer Detecting Time
at fc = 20M Hz, fs = 32.768 kHz
System Clock
Gear Value
Selection
<GEAR2:0>
<SYSCK>
1 (fs)
0 (fc)
XXX
(Don’t care)
00
2.000 s
Watchdog Timer Detecting Time
WDMOD<WDTP1:0>
01
10
8.000 s
32.000 s
11
128.000 s
000 (fc)
3.277 ms
13.107 ms
52.429 ms
209.715 ms
001 (fc/2)
6.554 ms
26.214 ms
104.858 ms
419.430 ms
010 (fc/4)
13.107 ms
53.429 ms
209.715 ms
838.861 ms
011 (fc/8)
26.214 ms
104.858 ms
419.430 ms
1.678 s
100 (fc/16)
52.429 ms
209.715 ms
838.861 ms
3.355 s
93CS44-187
2004-02-10
TMP93CS44/S45
3.12.3
Operation
The watchdog timer generates interrupt INTWD after the detecting time set in the
WDMOD<WDTP1:0>. The watchdog timer must be zero cleared by software before an
INTWD interrupt is generated. If the CPU malfunctions (Runaway) due to causes such as
noise, but does not execute the instruction used to clear the binary counter, the binary
counter overflows and an INTWD interrupt is generated. The CPU detects malfunction
(Runaway) due to the INTWD interrupt and it is possible to return to normal operation by
an anti-malfunction program. By connecting the watchdog timer out pin to peripheral
devices’ resets, a CPU malfunction can also be acknowledged to other devices.
The watchdog timer restarts operation immediately after resetting is released.
The watchdog timer stops its operation in the IDLE1 and STOP modes. In the RUN mode,
the watchdog timer is enabled.
However, the function can be disabled when entering the RUN, IDLE2 mode.
Example:
1. Clear the binary counter
WDCR
← 0
1
0
0
1 1
1
0
Write clear code (4EH).
2. Set the watchdog timer detecting time to 217/fSYS
WDMOD
← 1
0
1
−
− −
X X
3. Disable the watchdog timer
WDMOD
WDCR
← 0
← 1
− −
0 1
−
1
− −
0 0
X X
0 1
Clear WDTE to 0.
Write disable code (B1H).
4. Set IDLE1 mode
WDMOD
← 0
−
−
−
1 0
X X
WDCR
← 1
0
1
1
0 0
0
1
Executes halt command
Disables WDT and sets IDLE1 mode.
Set the HALT mode.
5. Set the STOP mode (Warm-up time: 216/fSYS)
WDMOD
← − − −
Executes halt command
1
0 1
X X
Set the STOP mode.
Execute HALT instruction. Set the HALT
mode.
X: Don’t care, −: No change
93CS44-188
2004-02-10
TMP93CS44/S45
4.
Electrical Characteristics
4.1
“X” used in an expression shows a cycle of clock fFPH selected
by SYSCR1<SYSCK>. If a clock gear or a low speed oscillator
is selected, a value of “X” is different. The value as an example
is calculated at fc, gear = 1/fc (SYSCR1<SYSCK, GEAR2:0> =
0000).
Maximum Ratings
(TMP93CS44F, TMP93CS45F)
Parameter
Rating
Unit
VCC
−0.5 to 6.5
V
Input voltage
VIN
−0.5 to VCC + 0.5
V
Output current (Per 1 pin) P7
IOL1
20
mA
Output current (Per 1 pin) except P7
IOL2
2
mA
Output current (P7 total)
ΣIOL1
80
mA
Output current (Total)
ΣIOL
120
mA
Output current (Total)
ΣIOH
−80
mA
Power dissipation (Ta = 85 °C)
PD
350
mW
Soldering temperature (10 s)
TSOLDER
260
°C
Storage temperature
TSTG
−65 to 150
°C
Operating temperature
TOPR
−40 to 85
°C
Note:
4.2
Symbol
Power supply voltage
The maximum ratings are rated values which must not be exceeded during
operation, even for an instant. Any one of the ratings must not be exceeded. If
any maximum rating is exceeded, a device may break down or its performance
may be degraded, causing it to catch fire or explode resulting in injury to the
user. Thus, when designing products which include this device, ensure that no
maximum rating value will ever be exceeded.
DC Characteristics (1/2)
Ta = −40 to 85°C
Parameter
Symbol
Power supply voltage
VCC
Input
low
voltage
AD0 to AD15
VIL
Port 2 to port 7
(except P35)
VIL1
Input
high
voltage
Condition
fc = 4 to 20 MHz
fc = 4 to 12.5 MHz
fs = 30 to
34 kHz
Min
Typ. (Note)
4.5
2.7
Max
Unit
5.5
V
VCC ≥ 4.5 V
0.8
VCC < 4.5 V
0.6
−0.3
VCC = 2.7 to 5.5 V
0.3 VCC
RESET , NMI , INT0
VIL2
EA , AM8/ AM16
VIL3
0.3
X1
VIL4
0.2 VCC
AD0 to AD 15
VIH
Port 2 to port 7
(except P35)
VIH1
RESET , NMI , INT0
VIH2
EA , AM8/ AM16
VIH3
X1
VIH4
0.25 VCC
VCC ≥ 4.5 V
2.2
VCC < 4.5 V
2.0
0.7 VCC
VCC = 2.7 to 5.5 V
V
VCC + 0.3
0.75 VCC
VCC − 0.3
0.8 VCC
IOL = 1.6 mA
Output low voltage
VOL
Output low current (P7)
IOL7
VOL = 1.0 V
VOH1
IOH = −400 µA
(VCC = 3 V ± 10%)
2.4
V
VOH2
IOH = −400 µA
(VCC = 5 V ± 10%)
4.2
V
Output high voltage
0.45
(VCC = 2.7 to 5.5 V)
(VCC = 5 V ± 10%)
16
(VCC = 3 V ± 10%)
7
V
mA
Note: Typical values are for Ta = 25°C and VCC = 5 V unless otherwise noted.
93CS44-189
2004-02-10
TMP93CS44/S45
DC Characteristics (2/2)
Parameter
Symbol
Condition
Min
Typ. (Note 1)
Max
Unit
−3.5
mA
Darlington drive current
(8 output pins max)
IDAR
(Note 2)
VEXT = 1.5
REXT = 1.1 kΩ
(VCC = 5 V ± 10% only)
Input leakage current
ILI
0.0 ≤ VIN ≤ VCC
0.02
±5
Output leakage current
ILO
0.2 ≤ VIN ≤ VCC − 0.2
0.05
±10
Power down voltage
(at stop, RAM back up)
VSTOP
VIL2 = 0.2VCC,
VIH2 = 0.8VCC
2.0
6.0
VCC = 5.5 V
45
130
VCC = 4.5 V
50
160
VCC = 3.3 V
70
280
VCC = 2.7 V
90
400
RESET pull-up resistor
RRST
Pin capacitance
CIO
Schmitt width
RESET , NMI , INT0
VTH
Programmable
pull-up resistor
RKH
fc = 1 MHz
10
0.4
45
130
50
160
VCC = 3.3 V
70
280
VCC = 2.7 V
90
25
17
25
12
17
3.5
5
NORMAL (Note 3)
6.5
10
VCC = 3 V ± 10%
fc = 12.5 MHz
(Typ. VCC = 3.0 V)
IDLE2
ICC
IDLE1
SLOW (Note 3)
RUN
IDLE2
VCC = 3 V ± 10%
fs = 32.768 kHz
(Typ. VCC = 3.0 V)
Ta ≤ 50°C
STOP
5.0
9
4.5
6.5
0.8
1.5
20
45
16
40
15
25
5
IDLE1
VCC =
2.7 V
to 5.5 V
Ta ≤ 70°C
Ta ≤ 85°C
V
kΩ
pF
kΩ
400
19
IDLE1
RUN
µA
V
VCC = 4.5 V
VCC = 5 V ± 10%
fc = 20 MHz
IDLE2
1.0
VCC = 5.5 V
NORMAL (Note 3)
RUN
−1.0
mA
µA
15
10
0.2
Note 1:
Typical values are for Ta = 25°C and VCC = 5 V unless otherwise noted.
Note 2:
IDAR is guranteed for total of up to 8 ports.
Note 3:
ICC measurement conditions (NORMAL, SLOW).
Only CPU is operational; output pins are open and input pins are fixed.
20
µA
50
(Reference) Definition of IDAR
REXT
IDAR
VEXT
93CS44-190
2004-02-10
TMP93CS44/S45
4.3
AC Characteristics
(1) VCC = 5 V ± 10%
No.
Parameter
Symbol
Variable
Min
Max
31250
16 MHz
Min Max
20 MHz
Unit
Min Max
1 Oscillation period (= X)
tOSC
50
62.5
50
2 CLK pulse width
tCLK
2X − 40
85
60
ns
ns
3 A0 to A23 valid → CLK hold
tAK
0.5X − 20
11
5
ns
4 CLK valid → A0 to A23 hold
tKA
1.5X − 70
24
5
ns
5 A0 to A15 valid → ALE fall
tAL
0.5X − 15
16
10
ns
6 ALE fall → A0 to A15 hold
tLA
0.5X − 20
11
5
ns
7 ALE high pulse width
tLL
X − 40
23
10
ns
8 ALE fall → RD / WR fall
tLC
0.5X − 25
6
0
ns
9 RD / WR rise → ALE rise
tCL
0.5X − 20
11
5
ns
10 A0 to A15 valid → RD / WR fall
tACL
X − 25
38
25
ns
11 A0 to A23 valid → RD / WR fall
tACH
1.5X − 50
44
25
ns
12 RD / WR rise → A0 to A23 hold
tCA
0.5X − 25
13 A0 to A15 valid → D0 to D15 input
tADL
3.0X − 55
133
95
ns
14 A0 to A23 valid → D0 to D15 input
tADH
3.5X − 65
154
110
ns
15 RD fall → D0 to D15 input
tRD
2.0X − 60
65
40
ns
16 RD low pulse width
tRR
2.0X − 40
85
60
17 RD rise → D0 to D15 hold
tHR
0
0
0
ns
18 RD rise → A0 to A15 output
tRAE
X − 15
48
35
ns
19
tWW
2.0X − 40
85
60
ns
tDW
2.0X − 55
70
45
ns
tWD
0.5X − 15
WR low pulse width
20 D0 to D15 valid → WR rise
21
WR rise → D0 to D15 hold
22 A0 to A23 valid → WAIT input
23 A0 to A15 valid → WAIT input
24
RD / WR fall → WAIT hold
(1 + N) WAIT
mode
(1 + N) WAIT
mode
(1 + N) WAIT
mode
tAPH
26 A0 to A23 valid → Port hold
tAPH2
WR rise → Port valid
2.0X + 0
108
125
2.5X − 120
2.5X + 50
tCP
ns
ns
85
ns
70
ns
100
36
206
200
ns
10
129
3.0X − 80
tAWL
tCW
0
16
3.5X − 90
tAWH
25 A0 to A23 valid → Port input
27
6
ns
5
175
200
ns
ns
200
ns
AC measuring conditions
• Output level: High 2.2 V, low 0.8 V, CL = 50 pF
(However CL = 100 pF for AD0 to AD15, A0 to A23, ALE, RD , WR , HWR , CLK)
• Input level:
High 2.4 V, low 0.45 V (AD0 to AD15)
High 0.8 × VCC, low 0.2 × VCC (except for AD0 to AD15)
93CS44-191
2004-02-10
TMP93CS44/S45
(2) VCC = 3 V ± 10%
No.
Parameter
Symbol
Variable
Min
Max
31250
12.5 MHz
Unit
Min Max
1 Oscillation period (= X)
tOSC
80
80
ns
2 CLK pulse width
tCLK
2X − 40
120
ns
3 A0 to A23 valid → CLK hold
tAK
0.5X − 30
10
ns
4 CLK valid → A0 to A23 hold
tKA
1.5X − 80
40
ns
5 A0 to A15 valid → ALE fall
tAL
0.5X − 35
5
ns
6 ALE fall → A0 to A15 hold
tLA
0.5X − 35
5
ns
7 ALE high pulse width
tLL
X − 60
20
ns
8 ALE fall → RD / WR fall
tLC
0.5X − 35
5
ns
9 RD / WR rise → ALE rise
tCL
0.5X − 40
0
ns
10 A0 to A15 valid → RD / WR fall
tACL
X − 50
30
ns
11 A0 to A23 valid → RD / WR fall
tACH
1.5X − 50
70
ns
12 RD / WR rise → A0 to A23 hold
tCA
0.5X − 40
13 A0 to A15 valid → D0 to D15 input
tADL
3.0X − 110
130
ns
14 A0 to A23 valid → D0 to D15 input
tADH
3.5X − 125
155
ns
15 RD fall → D0 to D15 input
tRD
2.0X − 115
45
ns
16 RD low pulse width
tRR
2.0X − 40
17 RD rise → D0 to D15 hold
tHR
0
0
ns
18 RD rise → A0 to A15 output
tRAE
X − 25
55
ns
19
0
ns
120
ns
tWW
2.0X − 40
120
ns
20 D0 to D15 valid → WR rise
tDW
2.0X − 120
40
ns
WR rise → D0 to D15 hold
tWD
0.5X − 40
0
21
WR low pulse width
22 A0 to A23 valid → WAIT input
23 A0 to A15 valid → WAIT input
24
RD / WR fall → WAIT hold
(1 + N) WAIT
mode
(1 + N) WAIT
mode
(1 + N) WAIT
mode
tAPH
26 A0 to A23 valid → Port hold
tAPH2
WR rise → Port valid
3.0X − 100
tAWL
tCW
25 A0 to A23 valid → Port input
27
3.5X − 130
tAWH
tCP
2.0X + 0
ns
150
ns
140
ns
160
2.5X − 195
2.5X + 50
ns
5
250
200
ns
ns
200
ns
AC measuring conditions
• Output level: High 0.7 × VCC, low 0.3 × VCC, CL = 50 pF
• Input level: High 0.9 × VCC, low 0.1 × VCC
93CS44-192
2004-02-10
TMP93CS44/S45
(3) Read cycle
tOSC
X1/XT1
tCLK
CLK
tAK
tKA
A0 to A23
tAWH
tAWL
tCW
WAIT
tAPH
tAPH2
Port input
(Note)
tADH
tCA
tRR
RD
tACH
tACL
AD0 to AD15
tRD
tLC
A0 to A15
tAL
tADL
tHR
tRAE
D0 to D15
tLA
tCL
ALE
tLL
Note:
Since the CPU accesses the internal area to read data from a port, the control signals of external
pins such as RD and CS are not enabled. Therefore, the above waveform diagram should be
regarded as depicting internal operation. Please also note that the timing and AC characteristics of
port input/output shown above are typical representation. For details, contact your local Toshiba
sales representative.
93CS44-193
2004-02-10
TMP93CS44/S45
(4) Write cycle
X1/XT1
CLK
A0 to A23
WAIT
Port output
(Note)
tWW
WR , HWR
tDW
AD0 to AD15
A0 to A15
tCP
tWD
D0 to D15
ALE
Note:
Since the CPU accesses the internal area to write data to a port, the control signals of external pins
such as WR and CS are not enabled. Therefore, the above waveform diagram should be regarded
as depicting internal operation. Please also note that the timing and AC characteristics of port
input/output shown above are typical representation. For details, contact your local Toshiba sales
representative.
93CS44-194
2004-02-10
TMP93CS44/S45
4.4
Serial Channel Timing
(1) I/O interface mode
1.
SCLK input mode
(Note 1)
Parameter
Variable
Symbol
Min
12.5 MHz
32.768 MHz
Min
Max
Max
Min
Max
20 MHz
Min
Unit
Max
tSCY
16X
488 µs
1.28 µs
0.8 µs
ns
Output data
→ Falling edge of SCLK
tOSS
tSCY/2 − 5X −
50
91.5 µs
190
100
ns
SCLK rising/falling edge
→ Output data hold
tOHS
5X − 100
152 µs
300
150
ns
SCLK rising/falling edge
→ Input data hold (Note 2)
tHSR
0
0
0
0
ns
SCLK rising/falling edge
→ Effective data input (Note 2)
tSRD
SCLK cycke
tSCY − 5X − 100
336 µs
780
450
ns
Note 1: When fs is used as system clock or fs divided by 4 is used as input clock to prescaler.
Note 2: SCLK rising/falling timing; SCLK rising in the rising mode of SCLK,
SCLK falling in the falling mode of SCLK.
2.
SCLK output mode
(Note)
Parameter
Variable
Symbol
Min
Max
8192X
12.5 MHz
32.768 MHz
Min
Max
Min
Max
20 MHz
Min
Unit
Max
488 µs 250 ms 1.28 µs 655.36 µs 0.8 µs 409.6 µs ns
SCLK cycle (Programmable)
tSCY
16X
Output data
→ SCLK rising edge
tOSS
tSCY − 2X − 150
427 µs
970
550
ns
SCLK rising edge
→ Output data hold
tOHS
2X − 80
60 µs
80
20
ns
SCLK rising edge
→ Input data hold
tHSR
0
0
0
0
ns
SCLK rising edge
→ Effective data input
tSRD
tSCY − 2X − 150
428 µs
970
550
ns
Note: When fs is used as system clock or fs divided by 4 is used as input clock to prescaler.
tSCY
SCLK
Output mode/
input rising edge mode
SCLK
(Input falling edge mode)
tOSS
Output data
TXD
tOHS
0
1
2
tSRD
Input data
RXD
0
Valid
3
tHSR
1
Valid
2
Valid
3
Valid
(2) UART mode (SCLK0 and SCLK1 are external input)
(Note)
Parameter
Variable
Symbol
Min
Max
32.768 MHz
Min
Max
12.5 MHz
Min
Max
20 MHz
Min
Unit
Max
SCLK cycle
tSCY
4X + 20
122 µs
340
220
ns
SCLK low level pulse width
tSCYL
2X + 5
6 µs
165
105
ns
SCLK high level pulse width
tSCYH
2X + 5
6 µs
165
105
ns
Note: When fs is used as system clock or fs divided by 4 is used as input clock to prescaler.
93CS44-195
2004-02-10
TMP93CS44/S45
4.5
AD Conversion Characteristics
AVCC = VCC, AVSS = VSS
Parameter
Analog reference voltage ( + )
Symbol
Power Supply
VREFH
Analog reference voltage ( − )
VREFL
Analog input voltage range
VAIN
Typ.
Max
VCC − 0.2 V
VCC
VCC
VCC = 3 V ± 10%
VCC − 0.2 V
VCC
VCC
VCC = 5 V ± 10%
VSS
VSS
VSS + 0.2 V
VCC = 3 V ± 10%
VSS
VSS
VSS + 0.2 V
VREFL
Analog current for analog reference
IREF
voltage
(VREFL =
<VREFON> = 1
0 V)
<VREFON> = 0
Error
(except quantization errors)
Min
VCC = 5 V ± 10%
−
Unit
V
VREFH
VCC = 5 V ± 10%
0.5
1.5
VCC = 3 V ± 10%
0.3
0.9
mA
µA
VCC = 2.7 to 5.5 V
0.02
5.0
VCC = 5 V ± 10%
±1.0
±3.0
VCC = 3 V ± 10%
±1.0
±5.0
LSB
10
Note 1: 1LSB = (VREFH − VREFL)/2 [V]
Note 2: The operation above is guaranteed for fFPH ≥ 4 MHz.
Note 3: The value ICC includes the current which flows through the AVCC pin.
4.6
Event Counter Input Clock (External input clock: TI0, TI4, TI5, TI6, TI7)
Parameter
Variable
Min
Max
Symbol
12.5 MHz
Min
Max
20 MHz
Min
Max
Unit
Clock cycle
tVCK
8X + 100
740
500
Low level clock pulse width
tVCKL
4X + 40
360
240
ns
High level clock pulse width
tVCKH
4X + 40
360
240
ns
12.5 MHz
Min
Max
20 MHz
Min
Max
4.7
ns
Interrupt and Capture Operation
(1) NMI and INT0 interrupts
Parameter
Symbol
Variable
Min
Max
Unit
NMI , INT0 low level pulse width
tINTAL
4X
320
200
ns
NMI , INT0 high level pulse width
tINTAH
4X
320
200
ns
12.5 MHz
Min
Max
20 MHz
Min
Max
(2) INT1, INT4 to INT7 interrupts and capture
Variable
Min
Max
Parameter
Symbol
INT1, INT4 to INT7 low level pulse
width
tINTBL
4X + 100
420
300
ns
INT1, INT4 to INT7 high level pulse
width
tINTBH
4X + 100
420
300
ns
93CS44-196
Unit
2004-02-10
TMP93CS44/S45
4.8
Serial Bus Interface Timing
(1) I2C bus mode
Parameter
Symbol
START command → SDA fall
Variable
Typ.
Min
Max
Unit
tGSTA
3X
ns
tHD:STA
2nX
ns
SCL low level pulse width
tLOW
2nX
ns
SCL high level pulse width
tHIGH
2nX + 12X
ns
Hold time START condition
Data hold time (Input)
tHD:IDAT
0
ns
Data setup time (Input)
tSU:IDAT
250
ns
Data hold time (Output)
tHD:ODAT
7X
11X
tODAT
STOP command → SDA fall
tFSDA
3X
SDA falling edge → SCL rising edge
tFDRC
2nX
ns
tSU:STO
2nX + 16X
ns
Setup time STOP condition
2nX − tHD:ODAT
ns
Data output → SCL rising edge
ns
ns
Note: “n” value is set by SBICR1<SCK2:0>.
STOP command
START command
SDA
tHD:ODAT
tGSTA
tODAT
tLOW
tFSDA
tFDRC
SCL
tHD:STA
tHD:IDAT
tHIGH
tSU:IDAT
93CS44-197
tSU:STO
2004-02-10
TMP93CS44/S45
(2) Clock synchronous 8-bit SIO mode
1.
SCK input mode
Parameter
Variable
Symbol
Min
Unit
Max
SCK cycle
tSCY2
25X
ns
SCK falling edge → Output data hold
tOHS2
6X
ns
Output data → SCK rising edge
tOSS2
tSCY2 − 6X
ns
SCK rising edge → Input data hold
tHSR2
6X
ns
Input data → SCK rising edge
tISS2
0
ns
2.
SCK output mode
Parameter
Variable
Symbol
Min
Max
211X
Unit
SCK cycle
tSCY2
25X
SCK falling edge → Output data hold
tOHS2
2X
Output data → SCK rising edge
tOSS2
tSCY2 − 2X
ns
SCK rising edge → Input data hold
tHSR2
2X
ns
Input data → SCK rising edge
tISS2
0
ns
ns
tOSS2
tSCY2
SCK
(Input/output mode)
ns
tISS2
tOHS2
SO
(Output data)
SI
(Input data)
tHSR2
93CS44-198
2004-02-10
TMP93CS44/S45
5.
Table of Special Function Registers
The special function registers (SFRs) include the I/O ports and peripheral control registers
allocated to the 128-byte addresses from 000000H to 00007FH.
(1) I/O port
(2) I/O port control
(3) Clock control
(4) Interrupt control
(5) Bus width/wait control
(6) Timer control
(7) Serial channel control
(8) Serial bus interface control
(9) Watchdog timer control
(10) AD converter control
Configuration of the table
Symbol
Name
Address
7
6
1
0
→ Bit symbol
→ Read/Write
→ Initial value after reset
→ Remarks
Note:
“Prohibit RMW” in the table means that you cannot use RMW instructions on these
registers.
(Example)
When setting only bit0 of register P0CR, “SET 0, (0002H)” cannot be used. The LD
(Transfer) instruction must be used to write all 8 bits.
93CS44-199
2004-02-10
TMP93CS44/S45
Table 5.1 I/O Register Address Map
Address
Name
Address
Name
000000H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
P0
P1
P0CR
(Reserved)
P1CR
P1FC
P2
P3
P2CR
P2FC
P3CR
P3FC
P4
P5
P4CR
(Reserved)
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
TRUN
(Reserved)
TREG0
TREG1
T10MOD
TFFCR
TREG2
TREG3
T32MOD
TRDC
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
P4FC
(Reserved)
P6
P7
P6CR
P7CR
P6FC
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
TREG4L
TREG4H
TREG5L
TREG5H
CAP1L
CAP1H
CAP2L
CAP2H
T4MOD
T4FFCR
T45CR
Note:
(Reserved)
(Reserved)
(Reserved)
Address
Name
Address
Name
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
TREG6L
TREG6H
TREG7L
TREG7H
CAP3L
CAP3H
CAP4L
CAP4H
T5MOD
T5FFCR
(Reserved)
SBICR1
SBIDBR
I2CAR
SBICR2
SBICR3
60H
61H
62H
63H
64H
65H
66H
67H
68H
69H
6AH
6BH
6CH
6DH
6EH
6FH
ADREG04L
ADREG04H
ADREG15L
ADREG15H
ADREG26L
ADREG26H
ADREG37L
ADREG37H
WAITC0
WAITC1
WAITC2
(Reserved)
(Reserved)
CKOCR
SYSCR0
SYSCR1
50H
51H
52H
53H
54H
55H
56H
57H
58H
59H
5AH
5BH
5CH
5DH
5EH
5FH
SC0BUF
SC0CR
SC0MOD
BR0CR
SC1BUF
SC1CR
SC1MOD
BR1CR
ODE
70H
71H
72H
73H
74H
75H
76H
77H
78H
79H
7AH
7BH
7CH
7DH
7EH
7FH
INTE0AD
INTE45
INTE67
INTET10
INTET32
INTET54
INTET76
INTEO54
INTES0
INTES1
INTE1S2
IIMC
DMA0V
DMA1V
DMA2V
DMA3V
(Reserved)
WDMOD
WDCR
ADMOD0
ADMOD1
Do not access addresses which do not have register names allocated.
93CS44-200
2004-02-10
TMP93CS44/S45
(1) I/O port
Symbol
P0
P1
P2
P3
Name
Port 0
Address
Port 1
01H
Port 2
06H
(Prohibit
RMW*)
Port 3
07H
(Prohibit
RMW*)
Port 4
0CH
P5
Port 5
0DH
Port 6
12H
(Prohibit
RMW*)
P7
Port 7
6
5
4
3
2
1
0
P06
P05
P04
P03
P02
P01
P00
P12
P11
P10
0
0
0
P22
P21
P20
1
1
1
P32
P31
P30 (Note1)
00H
P4
P6
7
P07
13H
P17
P16
P15
0
0
0
P27
P26
P25
1
1
1
P35
R/W
Undefined
Input mode
P14
P13
R/W
0
0
Input mode
P24
P23
R/W
1
1
Input mode
P34
P33
R/W
1
P47
P46
P45
1
1
1
P57
P56
P55
P67
P66
P65
1
1
Output mode
P77
P76
1
1
1
P75
1
1
1
1
Input mode
P44
P43
P42
R/W
1
1
1
Input mode
P54
P53
P52
R
Input mode
P64
P63
P62
R/W
1
1
1
Input mode
P74
P73
P72
R/W
1
1
1
Input mode
1
1
Output mode
P41
P40
1
1
P51
P50
P61
P60
1
1
P71
P70
1
1
Note 1: When P30 pin is defined as RD signal output mode (P30F = 1), clearing the output latch
register P30 to 0 outputs the RD strobe from P30 pin for PSRAM, even when the internal
address is accessed. If the output latch register P30 remains 1, the RD strobe is output only
when the external address is accessed.
Note 2: Port 66 and 67 are also used as XT1, XT2. Therefore these pins are open drain output type.
Read/Write
R/W: Either read or write is possible.
R:
Only read is possible.
W: Only write is possible.
Prohibit RMW: Prohibit read-modify-write.
(Prohibit RES/SET/TSET/CHG/STCF/ANDCF/ORCF/XORCF instruction.)
Prohibit RMW*: Read-modify-write is prohibited when controlling the PU resistor.
93CS44-201
2004-02-10
TMP93CS44/S45
(2) I/O port control
Symbol
Name
Address
P0CR
Port 0
control
register
02H
(Prohibit
RMW)
P1CR
Port 1
control
register
04H
(Prohibit
RMW)
P1FC
Port 1
function
register
05H
(Prohibit
RMW)
P2CR
Port 2
control
register
08H
(Prohibit
RMW)
P2FC
Port 2
function
register
09H
(Prohibit
RMW)
P3CR
Port 3
control
register
0AH
(Prohibit
RMW)
P3FC
Port 3
function
register
0BH
(Prohibit
RMW)
P4CR
Port 4
control
register
0EH
(Prohibit
RMW)
P4FC
Port 4
function
register
10H
(Prohibit
RMW)
P6CR
Port 6
control
register
14H
(Prohibit
RMW)
P7CR
Port 7
control
register
15H
(Prohibit
RMW)
P6FC
Port 6
function
register
16H
(Prohibit
RMW)
Note:
7
6
5
4
3
2
1
0
P07C
P06C
P05C
P04C
P03C
P02C
P01C
P00C
W
0
0
0
0
0
0
0
0: Input 1: Output (when external access, set as AD7 to AD0 and cleared to “0”.)
P17C
P16C
P15C
P14C
P13C
P12C
P11C
P10C
W
0
0
0
0
0
0
0
0
<<Refer to the “P1FC”>>
P17F
P16F
P15F
P14F
P13F
P12F
P11F
P10F
W
0
0
0
0
0
0
0
0
P1FC/P1CR = 00: Input 01: Output 10: AD15 to AD8 11: A15 to A8
P27C
P26C
P25C
P24C
P23C
P22C
P21C
P20C
W
0
0
0
0
0
0
0
0
<<Refer to the “P2FC”>>
P27F
P26F
P25F
P24F
P23F
P22F
P21F
P20F
W
0
0
0
0
0
0
0
0
P2FC/P2CR = 00: Input 01: Output 10: A7 to A0 11: A23 to A16
P35C
P34C
P33C
P32C
W
0
0
0
0
0: Input
0: Output
P32M
P34F
P33F
P32F
P31F
P30F
W
W
0
0
0
0
0
0
0: Port
0: Port
0: Port
0: Port
0: Port
0: HWR
1: RD
1: SCK
1: SCL/SI 1: SDA/SO 1: P32M
1: WR
P47C
P46C
P45C
P44C
P43C
P42C
P41C
P40C
W
0
0
0
0
0
0
0
0
0: Input
0: Output
P47F
P44F
P41F
W
W
W
0
0
0
0: Port
0: Port
0: Port
1: TO6
1: TO4
1: TO3
P67C
P66C
P65C
P64C
P63C
P62C
P61C
P60C
W
1
1
0
0
0
0
0
0
0: Input
0: Output
P77C
P76C
P75C
P74C
P73C
P72C
P71C
P70C
W
0
0
0
0
0
0
0
0
0: Input
0: Output
P65F
P63F
P62F
P60F
W
W
W
0
0
0
0
0: Port
0: Port
0: Port
0: Port
1: SCLK1
1: TXD1
1: SCLK0
1: TXD0
0
With the TMP93CS45, which requires an external ROM, port 0 functions as AD0 to AD7; port 1,
AD8 to AD15 or A8 to A15; P30, the RD signal; P31, the WR signal, regardless of the values set
in P0CR, P1CR, P1FC, P30F and P31F.
93CS44-202
2004-02-10
TMP93CS44/S45
(3) Clock control
Symbol
Name
Address
7
6
−
−
5
4
3
2
R/W
CKOCR
Clock
output
control
register
0
006DH
1
0
ALEEN
CLKEN
R/W
0/1
0/1
0
Always write “0”.
ALE pin
CLK pin
control
control
0: High-Z
0: High-Z
output
output
SYSCR0
System
clock
control
register 0
XEN
XTEN
RXEN
1
0
1
RXTEN
RSYSCK
R/W
0
0
WUEF
006EH
0: Stop
1: Oscillation
1: Oscillation
1: CLK output
PRCK1
PRCK0
0
0
0
High-frequency Low-frequency High-frequency Low-frequency Select clock
Warm-up
oscillator (fc)
oscillator (fs) oscillator (fc)
oscillator (fs) after released timer
0: Stop
1: ALE output
after released
STOP mode
after released
STOP mode
STOP mode
(Write)
0: fc
0: Don’t care
0: Stop
0: Stop
1: fs
1: Start timer
1: Oscillation
1: Oscillation
Select prescaler clock
00: fFPH
01: fs
10: fc/16
11: (Reserved)
(Read)
0: End
warm up
1: Not end
warm up
SYSCK
0
SYSCR1
System
clock
control
register 1
GEAR2
GEAR1
R/W
1
0
GEAR0
0
Select system Select gear value of high frequency (fc)
clock
000: fc
006FH
0: fc
001: fc/2
1: fs
010: fc/4
(Note 2)
011: fc/8
100: fc/16
101: (Reserved)
110: (Reserved)
111: (Reserved)
Note 1: The value after reset of <CLKEN>, <ALEEN> is following:
TMP93CS44: 0 (High-impedance output)
TMP93CS45: 1 (CLK or ALE output)
But during reset, CLK pin is pulled up internally regardless of the products.
Note 2: The high-frequency oscillator will be enabled regardless the value of SYSCR0<XEN> when
SYSCR1<SYSCK> is clear to 0.
On the other hand, the low-frequency oscillator will be enabled regardless the value of
SYSCR0<XTEN> when SYSCR1<SYSCK> is set to 1.
93CS44-203
2004-02-10
TMP93CS44/S45
(4) Interrupt control (1/2)
Symbol
INTE0AD
INTE45
INTE67
INTET10
INTET32
INTET54
INTET76
INTEO54
INTES0
INTES1
INTE1S2
Name
Address
INT0/AD
enable
register
0070H
(Prohibit
RMW)
INT4/5
enable
register
0071H
(Prohibit
RMW)
INT6/7
enable
register
7
IADC
R/W
0
I5C
R/W
0
0072H
(Prohibit
RMW)
I7C
R/W
0
0073H
(Prohibit
RMW)
IT1C
R/W
0
0074H
(Prohibit
RMW)
IT3C
R/W
0
0075H
(Prohibit
RMW)
IT5C
R/W
0
INTT7/6
enable
register
0076H
(Prohibit
RMW)
IT7C
R/W
0
INTTO
5/4
enable
register
0077H
(Prohibit
RMW)
ITO5C
R/W
0
INTRX0/
TX0
enable
register
0078H
(Prohibit
RMW)
ITX0C
R/W
0
INTRX1/
TX1
enable
register
0079H
(Prohibit
RMW)
ITX1C
R/W
0
INT1/
INTS2
enable
register
007AH
(Prohibit
RMW)
I1C
R/W
0
INTT1/0
enable
register
INTT3/2
enable
register
INTT5/4
enable
register
IxxM2
IxxM1
IxxM0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
IxxC
6
5
4
INTAD
IADM2
IADM1
W
0
0
INT5
I5M2
I5M1
W
0
0
INT7
I7M2
I7M1
W
0
0
INTT1 (Timer 1)
IT1M2
IT1M1
W
0
0
INTT3 (Timer 3)
IT3M2
IT3M1
W
0
0
INTTR5 (TREG5)
IT5M2
IT5M1
W
0
0
INTTR7 (TREG7)
IT7M2
IT7M1
W
0
0
INTTO5
ITO5M2
ITO5M1
W
0
0
INTTX0
ITX0M2
ITX0M1
W
0
0
INTTX1
ITX1M2
ITX1M1
W
0
0
INT1
I1M2
I1M1
W
0
0
3
2
1
0
I0M1
W
0
I0M0
I4M1
W
0
I4M0
INT0
IADM0
0
I0C
R/W
0
I0M2
0
0
INT4
I5M0
0
I4C
R/W
0
I4M2
0
0
INT6
I7M0
0
IT1M0
0
IT3M0
0
IT5M0
0
IT7M0
0
ITO5M0
0
ITX0M0
0
ITX1M0
0
I1M0
0
I6C
R/W
0
IT0C
R/W
0
IT2C
R/W
0
IT4C
R/W
0
IT6C
R/W
0
ITO4C
R/W
0
IRX0C
R/W
0
IRX1C
R/W
0
IS2C
R/W
0
I6M2
I6M1
W
0
0
INTT0 (Timer 0)
IT0M2
IT0M1
W
0
0
INTT2 (Timer 2)
IT2M2
IT2M1
W
0
0
INTTR4 (TREG4)
IT4M2
IT4M1
W
0
0
INTTR6 (TREG6)
IT6M2
IT6M1
W
0
0
INTTO4
ITO4M2
ITO4M1
W
0
0
INTRX0
IRX0M2
IRX0M1
W
0
0
INTRX1
IRX1M2
IRX1M1
W
0
0
INTS2
IS2M2
IS2M1
W
0
0
I6M0
0
IT0M0
0
IT2M0
0
IT4M0
0
IT6M0
0
ITO4M0
0
IRX0M0
0
IRX1M0
0
IS2M0
0
Function (Write)
Prohibits interrupt request.
Sets interrupt request level to 1.
Sets interrupt request level to 2.
Sets interrupt request level to 3.
Sets interrupt request level to 4.
Sets interrupt request level to 5.
Sets interrupt request level to 6.
Prohibits interrupt request.
Function (Read)
0
Indicates no interrupt request.
1
Indicates interrupt request.
Function (Write)
Clears interrupt request flag.
− − − − − Don’t care − − − − −
93CS44-204
2004-02-10
TMP93CS44/S45
Interrupt control (2/2)
Symbol
Name
Address
DMA0V
DMA 0
request
vector
7CH
(Prohibit
RMW)
DMA1V
DMA 1
request
vector
7DH
(Prohibit
RMW)
DMA2V
DMA 2
request
vector
7EH
(Prohibit
RMW)
DMA3V
DMA 3
request
vector
7FH
(Prohibit
RMW)
7
6
5
4
3
DMA0V4
DMA0V3
0
DMA1V4
0
DMA2V4
0
DMA3V4
IIMC
Interrupt
input
mode
control
0
−
W
0
Always
write “0”.
7BH
(Prohibit
RMW)
2
1
0
DMA0V2 DMA0V1 DMA0V0
W
0
0
0
0
Micro DMA0 start vector
DMA1V3 DMA1V2 DMA1V1 DMA1V0
W
0
0
0
0
Micro DMA1 start vector
DMA2V3 DMA2V2 DMA2V1 DMA2V0
W
0
0
0
0
Micro DMA2 start vector
DMA3V3 DMA3V2 DMA3V1 DMA3V0
W
0
0
0
0
Micro DMA3 start vector
I0IE
I0LE
NMIREE
W
0
0
0
1: INT0
0: INT0
1: Operainput
edge
tion
enable
mode
even at
1: INT0
NMI
level
rising
mode
edge
(5) Bus width/wait control
Symbol
WAITC0
Name
Block 0
WAIT
control
register
Address
68H
(Prohibit
RMW)
7
6
5
4
3
2
1
0
B0BUS
B0W1
B0W0
W
0
B0C1
B0C0
0
0: 16-bit
bus
1: 8-bit
bus
B1BUS
WAITC1
Block 1
WAIT
control
register
69H
(Prohibit
RMW)
WAITC2
Block 2
WAIT
control
register
6AH
(Prohibit
RMW)
0
0: 16-bit
bus
1: 8-bit
bus
B2BUS
0
0: 16-bit
bus
1: 8-bit
bus
93CS44-205
0
00: 2 waits
01: 1 wait
10: (1 + N) waits
11: 0 waits
B1W1
B1W0
W
0
0
00: 2 waits
01: 1 wait
10: (1 + N) waits
11: 0 waits
B2W1
B2W0
W
0
0
00: 2 waits
01: 1 wait
10: (1 + N) waits
11: 0 waits
0
0
00: 7F00H to 7FFFH
01: 400000H to
10: 800000H to
11: C00000H to
B1C1
B1C0
0
0
00: 880H to 7FFFH
01: 400000H to
10: 800000H to
11: C00000H to
B2C1
B2C0
00:
01:
10:
11:
1
1
8000H to
400000H to
800000H to
C00000H to
2004-02-10
TMP93CS44/S45
(6) Timer control (1/3)
Symbol
Name
Address
TRUN
Timer
control
register
20H
TREG0
8-bit
timer
register 0
22H
(Prohibit
RMW)
TREG1
8-bit
timer
register 1
23H
(Prohibit
RMW)
T10
MOD
8-bit
timer 0
and 1
source
CLK and
mode
control
register
24H
TFFCR
8-bit
timer
flip-flop
control
register
25H
TREG2
8-bit
timer
register 2
26H
(Prohibit
RMW)
TREG3
8-bit
timer
register 3
27H
(Prohibit
RMW)
T32
MOD
8-bit
timer 2
and 3
source
CLK and
mode
control
register
28H
TRDC
Timer
register
double
buffer
control
register
29H
7
6
PRRUN
R/W
0
T10M1
T10M0
R/W
0
0
00: 8-bit timer
01: 16-bit timer
10: −
11: −
TFF3C1
TFF3C0
W
1
1
00: Invert TFF3
01: Set TFF3
10: Clear TFF3
11: Don’t care
T32M1
T32M0
0
0
00: 8-bit timer
01: 16-bit timer
10: 8-bit PPG
11: 8-bit PWM
5
4
T5RUN
T4RUN
3
2
1
0
T3RUN
T2RUN
T1RUN
T0RUN
R/W
0
0
0
0
0
0
Prescaler and timer run/stop control
0: Stop and clear
1: Run (Count up)
−
W
Undefined
−
W
Undefined
T1CLK1
T1CLK0
T0CLK1
T0CLK0
R/W
0
0
0
0
00: TO0TRG
00: TI0 INPUT
01: φT1
01: φT1
10: φT16
10: φT4
11: φT256
11: φT16
TFF3IE
TFF3IS
TFF1C1
TFF1C0
TFF1IE
TFF1IS
R/W
W
R/W
0
0
1
1
0
0
1: TFF3
TFF3
00: Invert TFF1
1: TFF1
TFF1
invert
inversion
invert
inversion
01: Set TFF1
enable select
enable select
10: Clear TFF1
0: Timer 2 11: Don’t care
0: Timer 0
1: Timer 3
1: Timer 1
−
W
Undefined
−
W
Undefined
PWM21
PWM20
T3CLK1
T3CLK0
T2CLK1
T2CLK0
R/W
0
0
0
0
0
0
00: −
00: TO2TRG
00: −
01: 26 − 1 PWM
01: φT1
01: φT1
10: 27 − 1 cycle
10: φT16
10: φT4
11: 28 − 1
11: φT256
11: φT16
TR2DE
−
R/W
0
0
0: Double Always
write “0”.
buffer
disable
1: Double
buffer
enable
93CS44-206
2004-02-10
TMP93CS44/S45
Timer control (2/3)
Symbol
TREG4L
TREG4H
TREG5L
TREG5H
Name
16-bit
timer
register 4
low
16-bit
timer
register 4
high
16-bit
timer
register 5
low
16-bit
timer
register 5
high
Address
7
6
5
4
3
30H
(Prohibit
RMW)
−
W
Undefined
31H
(Prohibit
RMW)
−
W
Undefined
32H
(Prohibit
RMW)
−
W
Undefined
33H
(Prohibit
RMW)
−
W
Undefined
CAP1L
Capture
register 1
low
34H
CAP1H
Capture
register 1
high
35H
CAP2L
Capture
register 2
low
36H
CAP2H
Capture
register 2
high
37H
T4MOD
16-bit
timer 4
source
CLK and
mode
control
register
38H
T4FFCR
16-bit
timer 4
flip-flop
control
register
39H
CAP1IN
W
1
0:Software
capture
1: Don’t
care
2
−
R
Undefined
−
R
Undefined
−
R
Undefined
−
R
Undefined
CAP12M1 CAP12M0
CLE
R/W
0
0
0
Capture timing
1: UC4
clear
00: Disable
enable
01: TI4
↑ TI5 ↑
10: TI4
↑ TI4 ↓
11: TTF1 ↑ TTF1 ↓
CAP2T4
CAP1T4
EQ5T4
EQ4T4
R/W
0
0
0
0
TFF4 invert trigger
0: Disable trigger
1: Enable trigger
1
0
T4CLK1
T4CLK0
0
0
Source clock
00: TI4
01: φT1
10: φT4
11: φT16
TFF4C1
TFF4C0
W
1
1
00: Invert TFF4
01: Set TFF4
10: Clear TFF4
Invert when Invert when Invert when Invert when 11: Don’t care
the UC value the UC value the UC
is loaded to is loaded to matches
CAP2
CAP1
TREG5
93CS44-207
the UC
matches
TREG4
2004-02-10
TMP93CS44/S45
Timer control (3/3)
Symbol
T45CR
TREG6L
TREG6H
TREG7L
TREG7H
Name
T4 and T5
control
register
16-bit
timer
register 6
low
16-bit
timer
register 6
high
16-bit
timer
register 7
low
16-bit
timer
register 7
high
Address
3AH
7
6
5
4
Undefined
−
W
Undefined
−
W
Undefined
−
43H
(Prohibit
RMW)
CAP3H
Capture
register 3
high
45H
CAP4L
Capture
register 4
low
46H
CAP4H
Capture
register 4
high
47H
T5MOD
16-bit
timer 5
source
CLK and
mode
control
register
48H
T5FFCR
16-bit
timer 5
flip-flop
control
register
49H
0
−
42H
(Prohibit
RMW)
44H
1
W
41H
(Prohibit
RMW)
Capture
register 3
low
2
DB6EN
DB4EN
R/W
0
0
Double buffer
0: Disable
1: Enable
Double
Double
buffer of
buffer of
TREG6
TREG4
40H
(Prohibit
RMW)
CAP3L
3
QCU
R/W
0
Warm-up
timer
control
W
Undefined
CAP3IN
W
1
0:Software
capture
1: Don’t
care
−
R
Undefined
−
R
Undefined
−
R
Undefined
−
R
Undefined
CAP34M1 CAP34M0
CLE
R/W
0
0
0
Capture timing
1: UC5
clear
00: Disable
enable
01: TI6
↑ TI7 ↑
10: TI6
↑ TI6 ↓
11: TTF1 ↑ TTF1 ↓
CAP4T6
CAP3T6
EQ7T6
EQ7T6
R/W
0
0
0
0
TFF6 invert trigger
0: Disable trigger
1: Enable trigger
T5CLK1
T5CLK0
0
0
Source clock
00: TI6
01: φT1
10: φT4
11: φT16
TFF6C1
TFF6C0
W
1
1
00: Invert TFF6
01: Set TFF6
10: Clear TFF6
Invert when Invert when Invert when Invert when 11: Don’t care
the UC value the UC value the UC
is loaded to is loaded to matches
CAP4
CAP3
TREG7
93CS44-208
the UC
matches
TREG6
2004-02-10
TMP93CS44/S45
(7) Serial channel control
Symbol
SC0BUF
SC0CR
Name
Serial
channel 0
buffer
register
Serial
channel 0
control
register
Address
50H
(Prohibit
RMW)
51H
7
6
RB7
TB7
RB6
TB6
TB8
Serial
channel 0
SC0MOD
mode
control
register
Undefined
52H
Transmission
data bit8
Baud rate 0
control
register
53H
SC1BUF
Serial
channel 1
buffer
register
54H
(Prohibit
RMW)
Serial
channel 1
control
register
4
3
2
CTSE0
RXE
WU
SM1
SM0
1
0
RB1
TB1
RB0
TB0
SCLKS
IOC
R/W
0
0
0: SCLK0 1: Input
SCLK0 pin
1: SCLK0
SC1
SC0
R/W
BR0CR
SC1CR
5
RB5
RB4
RB3
RB2
TB5
TB4
TB3
TB2
R (Receiving)/W (Transmission)
Undefined
RB8
EVEN
PE
OERR
PERR
FERR
R
R/W
R (Cleared to “0” by reading.)
Undefined
0
0
0
0
0
Receiving Parity
1: Error
1: Parity
data bit8 0: Odd
enable
Overrun
Parity
Framing
1: Even
55H
0
1: CTS0
enable
−
R/W
0
Fix at
“0”.
RB7
TB7
RB6
TB6
RB8
R
EVEN
0
Undefined
Receiving Parity
data bit8 0: Odd
1: Even
TB8
0
0
0
0
0
0
1: Receive 1: Wakeup 00: I/O interface
00: TO2 trigger
enable
enable 01: UART 7-bit
01: Baud rate generator
10: UART 8-bit
10: Internal clock φ1
11: External clock SCLK0
11: UART 9-bit
BR0CK1 BR0CK0
BR0S3
BR0S2
BR0S1
BR0S0
R/W
0
0
0
0
0
0
00: φT0
Set frequency divisor
01: φT2
0000:
16 divisions
10: φT8
0001
11: φT32
to
1 to 15 divisions
1111
RB5
RB4
RB3
RB2
RB1
RB0
TB5
TB4
TB3
TB2
TB1
TB0
R (Receiving)/W (Transmission)
Undefined
PE
OERR
PERR
FERR
SCLKS
IOC
R/W
R (Cleared to “0” by reading.)
R/W
0
0
0
0
0
0
1: Parity
0: SCLK1 1: Input
1: Error
enable
SCLK1 pin
Overrun
Parity
Framing
1: SCLK1
CTSE1
RXE
WU
SM1
SM0
SC1
SC0
0
0
R/W
Serial
channel 1
SC1MOD
mode
control
register
Undefined
56H
Transmission
data bit8
0
1: CTS1
enable
0
0
0
0
1: Receive 1: Wakeup 00: I/O interface
enable
enable 01: UART 7-bit
10: UART 8-bit
11: UART 9-bit
00: TO2 trigger
01: Baud rate
generator
10: Internal clock φ1
11: External clock SCLK1
BR1CR
ODE
Baud rate 1
control
register
Serial
open-drain
enable
57H
−
R/W
0
Fix at
“0”.
BR1CK1
BR1CK0
BR1S3
BR1S2
BR1S1
BR1S0
R/W
00:
01:
10:
11:
0
φT0
φT2
φT8
φT32
58H
93CS44-209
0
0
0
0
Set frequency divisor
0000:
16 divisions
0001
to
1 to 15 divisions
1111
ODE34
ODE33
ODE63
R/W
0
0
0
1: P34
1: P33
1: P63
open
open
open
drain
drain
drain
0
ODE60
0
1: P60
open
drain
2004-02-10
TMP93CS44/S45
(8) Serial bus interface control (1/2)
Symbol
Name
Address
4BH
(I2C bus
mode)
SBICR1
Serial bus
interface
control
register 1
(Prohibit
RMW)
7
6
5
4
BC2
BC1
W
0
BC0
ACK
R/W
0
0
000: 8
100: 4
001: 1
101: 5
010: 2
110: 6
011: 3
111: 7
SIOS
4BH
(SIO
mode)
(Prohibit
RMW)
4EH
(I C bus
mode)
SBICR2
Serial bus
interface
control
register 2
(Prohibit
RMW)
000: 4
1: Enable
SIOM0
0
0
0
SCK0
0
0: Disable
SIOM1
1
SCK1
W
0
0
Indicate
transfer
start/stop
0: Stop
1: Start
0
Continue/
abort
transfer
0: Continue
1: Abort
0
Setting of the divide value “n”
Acknowledge
mode
specification
SIOINH
2
SCK2
100: 8
001: 5
101: 9
010: 6
110: 10
011: 7
111: (Reserved)
SCK2
SCK1
W
0
W
MST
2
0
Number of transfer bits
3
0
Transfer mode select
SCK0
0
Serial clock selection
00: 8-bit transmit
000: fFPH/25
01: (Reserved)
001: fFPH/2
6
101: fFPH/2
10: 8-bit transmit/receive
010: fFPH/27
110: PH/211
8
11: 8-bit receive
TRX
BB
0
0
011: fFPH/2
PIN
SBIM1
SBIM0
0
0
100: fFPH/29
10
111: External clock (SCK pin)
W
0
Master/
slave
selection
0: Slave
1: Master
1
Cancel
INTS2
request
0: Don’t
care
1: Cancel
Transmitter/ Start/stop
generation
receiver
selection
(when the
0: Receiver MST, TRX,
1: Transmitter PIN are “1”)
0: Stop
1: Start
Serial bus interface
operating mode
selection
00: Port mode
01: SIO mode
10: I2C bus mode
11: (Reserved)
SBIM1
SBIM0
W
4EH
(SIO
mode)
0
0
Serial bus interface
operating mode
selection
00: Port mode
01: SIO mode
(Prohibit
RMW)
2
10: I C bus mode
11: (Reserved)
MST
4EH
(I2C bus
mode)
(Prohibit
RMW)
SBISR
Serial bus
interface
status
register
TRX
BB
PIN
AL
AAS
AD0
LRB
0
GENERAL
CALL
detection
monitor
1: Detect
0
Last
received
bit monitor
0: “0”
1: “1”
R
0
0: Slave
0
I2C bus
status
monitor
0: Bus free
1: Bus
0: Receiver
busy
1: Master
1: Transmitter
Master/
slave
selection
status
monitor
0
Transmitter/
receiver
selection
status
monitor
1
INTS2
request
status
monitor
0: Request
1: Cancel
0
Noise
detection
monitor
1: detect
0
Slave
address
much
detection
monitor
1: Detect
SIOF
SEF
R
4EH
(SIO
mode)
0
Serial
transfer
operating
status
monitor
0: Terminated
1: In
process
(Prohibit
RMW)
93CS44-210
0
Shift
operating
status
monitor
0: Terminated
1: In
process
2004-02-10
TMP93CS44/S45
Serial bus interface control (2/2)
Symbol
Name
Address
SBICR3
Serial bus
interface
status
register 3
4FH
SBIDBR
Serial bus
interface
data
buffer
register
4CH
(Prohibit
RMW)
7
6
DB7
5
DB6
DB5
4
3
2
1
0
DB2
DB1
SWRST
R/W
0
Software
reset
0: −
1: Initialize
SBI
DB0
SA2
SA1
SA0
ALS
0
0
0
DB4
DB3
R (Receive)/W (Send)
Undefined
SA6
SA5
SA4
SA3
W
I2CAR
I2C bus
address
register
4DH
(Prohibit
RMW)
0
0
0
0
0
Address
recognition
mode
Slave address selection
0: Enable
1: Disable
(9) Watchdog timer
Symbol
Name
Watchdog
timer mode
WDMOD
control
register
Address
5CH
7
6
5
4
WDTE
WDTP1
WDTP0
WARM
1
1: WDT
enable
00:
01:
10:
11:
0
215/fSYS
217/fSYS
219/fSYS
221/fSYS
0
3
2
1
0
HALTM1 HALTM0
RESCR
DRVE
R/W
0
0
0
0
0
Warm-up HALT mode
1: Connect 1: Drive
the pin
timer
internally
00: RUN mode
WDT out
in STOP
0: 214/inputted 01: STOP mode
mode
to reset
frequency
10: IDLE1 mode
pin
1: 216/ inputted
11: IDLE2 mode
frequency
WDCR
Watchdog
timer
control
register
−
W
−
5DH
B1H: WDT disable code
93CS44-211
4EH: WDT clear code
2004-02-10
TMP93CS44/S45
(10) AD converter control
Symbol
Name
Address
7
6
5
4
3
2
1
0
EOCF
AD8F
−
−
ITM0
REPET
SCAN
ADS
R
ADMOD
0
ADMOD
1
AD mode
control
register 0
AD mode
control
register 1
5EH
5FH
0
1: End
0
1: Busy
0
Always
write “0”.
0
Always
write “0”.
VREFON
R/W
1
0: OFF
1: ON
R/W
0
0
0
0
0: Every
0: Single 0: fixed1: START
conversion 1: Repeat
channel
1: Every
1: Scan
four
conversion
ADTRGE
ADCH2
ADCH1
ADCH0
R/W
0
0
0
0
External
trigger start
control
Analog input
channel selection
0: Disable
1: Enable
AD
conversion
AD
result
REG04L
register
0/4 low
ADR01
*1)
AD
conversion
AD
result
REG04H
register
0/4 high
AD
conversion
AD
result
REG15L
register
1/5 low
60H
AD
conversion
AD
result
REG26L
register
2/6 low
AD
conversion
AD
result
REG37L
register
3/7 low
AD
conversion
result
register
3/7 high
result stored flag
ADR07
ADR06
ADR05
ADR04
ADR03
ADR02
Stores upper eight bits of AD conversion result
62H
ADR10
ADR1RF
R
0
R
Undefined
Stores lower two bits of
AD conversion result
ADR19
ADR18
Conversion
result stored flag
ADR17
ADR16
ADR15
ADR14
ADR13
ADR21
64H
ADR12
R
Undefined
Stores upper eight bits of AD conversion result
63H
ADR20
R
Undefined
Stores lower two bits of
AD conversion result
ADR29
ADR28
ADR2RF
R
0
Conversion
result stored flag
ADR27
ADR26
ADR25
ADR24
ADR23
ADR22
R
Undefined
65H
Stores upper eight bits of AD conversion result
ADR31
*1)
AD
REG37H
Conversion
R
Undefined
ADR11
*1)
AD
conversion
AD
result
REG26H
register
2/6 high
ADR0RF
R
0
R
Undefined
Stores lower two bits of
AD conversion result
ADR09
ADR08
61H
*1)
AD
conversion
AD
result
REG15H
register
1/5 high
ADR00
66H
ADR30
ADR3RF
R
0
R
Undefined
Stores lower two bits of
AD conversion result
ADR39
67H
ADR38
Conversion result
stored flag
ADR37
ADR35
ADR34
R
Undefined
Stores upper eight bits of AD conversion result
Converted data of channel x
*1: Data to be stored in AD conversion result register low are the
lower 2 bits of the conversion result. The contents of the 5 to 1
bits of this register are always read as 1. Bit0 conversion
result stored flag bit <ADRxRF>, <ADRxRF> is set to 1 when
the AD conversion result is stored.
Reading either the ADREGxH or the ADREGxL registers
clears <ADRxRF> to 0.
ADR36
9
8
7
6
5
4
3
2
7
6
5
4
3
2
1
0
93CS44-212
ADREGxH
1
ADR33
ADR32
0
7
6
5
4
ADREGxL
3 2 1
0
This is “1” when this is read.
2004-02-10
TMP93CS44/S45
6.
Port Section Equivalent Circuit Diagram
•
Reading the circuit diagram
Basically, the gate symbols written are the same as those used for the standard CMOS logic
IC [74HCXX] series.
The dedicated signal is described below.
STOP:
•
This signal becomes active 1 when the HALT mode setting register is set to the
STOP mode (WDMOD<HALTM1:0> = 0, 1) and the CPU executes the HALT
instruction. When the drive enable bit WDMOD<DRVE> is set to 1, however,
STOP remains at 0.
The input protection resistance ranges from several tens of ohms to several hundreds of ohms.
■
P0 (AD0 to AD7), P1 (AD8 to AD15/A8 to A15), P4 and P7
VCC
Output data
P-ch
Output enable
STOP
N-ch
I/O
Input data
Input enable
■
P2 (A16 to A23/A0 to A7), P32, P61, P62, P64 and P65
VCC
Output data
P-ch
Output enable
STOP
VCC
N-ch
Programmable
pull-up resistor
P-ch
I/O
Input data
Input enable
93CS44-213
2004-02-10
TMP93CS44/S45
■
P30 ( RD ) and P31 ( WR )
VCC
Output data
P-ch
OUT
STOP
N-ch
■
P33 (SO/SDA) and P34 (SI/SCL)
VCC
Output data
P-ch
Open-drain
output enable
N-ch
STOP
I/O
Input data
Input enable
■
P35 (INT0)
VCC
Output data
P-ch
Output enable
STOP
N-ch
I/O
Input data
Interrupt request signal
■
Schmitt
P50 to P52 (AN0 to AN2), P54 to P57 (AN4 to AN7)
Analog input
channel select
P-ch
Input
Analog input
N-ch
Input data
Input enable
93CS44-214
2004-02-10
TMP93CS44/S45
■
P53 (AN3 / ADTRG )
Analog input
channel select
P-ch
Input
Analog input
N-ch
Input data
Input enable
AD trigger
STOP
■
P60 (TXD0) and P63 (TXD1)
VCC
Output data
P-ch
VCC
Open-drain
output enable
Programmable
pull-up resistor
N-ch
P-ch
STOP
I/O
Input data
Input enable
■
P66 (XT1) and P67 (XT2)
Clock
Input enable
Oscillator
Input data
Output data
output enable
P67 (XT2)
N-ch
N-ch
P-ch
Input enable
Input data
Output data
output enable
P66 (XT1)
N-ch
STOP
Low-frequency
oscillation enable
93CS44-215
2004-02-10
TMP93CS44/S45
■
NMI
Input
NMI
Schmitt
■
CLK
VCC
Output enable
VCC
P-ch
Internal CLK
P-ch
OUT
N-ch
STOP
Internal reset
Test circuit
Input enable
■
EA
Input data
■
Input
AM8/ AM16
Input data
■
Input
ALE
VCC
Internal ALE
P-ch
OUT
Output enable
N-ch
93CS44-216
2004-02-10
TMP93CS44/S45
■
RESET
VCC
Input
Internal reset
Schmitt
WDTOUT
Reset enable
■
X1 and X2
Clock
Oscillator
X2
P-ch
N-ch
High-frequency
oscillation enable
X1
■
VREFH and VREFL
VREFON
P-ch
VREFH
String
resistance
VREFL
93CS44-217
2004-02-10
TMP93CS44/S45
7.
Points of Note and Restriction
(1) Notation
1.
2.
Explanation of a built-in I/O register: Register symbol<Bit symbol>
Example: TRUN<T0RUN> … Bit T0RUN of register TRUN
Read-modify-write instruction
An instruction in which the CPU executes following by one instruction.
1.
2.
3.
CPU reads data of the memory.
CPU modifies the data.
CPU writes the data to the same memory.
Example 1: SET
3, (TRUN) … Set bit3 of TRUN
Example 2: INC
1, (100H) … Increment the data of 100H
•
A sample read-modify-write instructions using the TLCS-900
Exchange
EX
(mem), R
Arithmetic operation
3.
ADD (mem), R/#
SUB (mem), R/#
INC #3, (mem)
Logical operation
ADC
SBC
DEC
(mem), R/#
(mem), R/#
#3, (mem)
AND (mem), R/#
XOR (mem), R/#
Bit manipulation
OR
(mem), R/#
STCF #3/A, (mem)
RES #3, (mem)
CHG #3, (mem)
Rotate and shift
SET #3, (mem)
TSET #3, (mem)
RLC (mem)
RL
(mem)
SLA (mem)
SLL (mem)
RLD (mem)
fc, fs, fFPH, fSYS, 1 state
RRC
RR
SRA
SRL
RRD
(mem)
(mem)
(mem)
(mem)
(mem)
The clock frequency input from pins X1 and X2 pin is called fc, and the clock frequency
input from XT1, XT2 pin is called fs. The clock frequency selected by SYSCR1<SYSCK,
GEAR2:0>is called system clock fFPH, and the clock frequency given by fFPH divided by 2 is
called fSYS. One cycle of fSYS is called 1 state.
93CS44-218
2004-02-10
TMP93CS44/S45
(2) Care points
1.
The operation voltage
The operation voltage of TMP93PW44A is VCC = 4.5 to 5.5 V though the operation voltage
of TMP93CS44/45, TMP93PS44, TMP93CU44, and TMP93CW44 is VCC = 2.7 to 5.5V.
Especially, be careful when TMP93CU44, TMP93CW44, and TMP93PW44A are used.
Please refer to the section 4 “Electric Characteristic” for details of each product.
2.
EA , AM8/ AM16 pin
Fix these pins VCC or VSS unless changing voltage.
3.
TEST1, TEST2 pin
Connect TEST1 pin with TEST2 pin.
4.
HALT mode (IDLE1)
When IDLE1 mode (Oscillator operation only) is used, set TRUN<PRRUN> to 0 to stop
prescaler before “HALT” instruction is executed.
5.
Warm-up counter
The warm-up counter operates when STOP mode is released even if the system is using
an external oscillator. As a result, it takes warm-up time from inputting the releasing
request to outputting the system clock.
6.
Programmable pull-up resistor
The programmable pull-up resistors can be turned ON/OFF by the program when the
ports are used as input ports. When the ports are used as the output ports, they can not be
selected ON/OFF by the program.
The data registers (e.g., P6 register) are used for the pull-up resistors ON/OFF.
Consequently, read-modify-write instructions are prohibited.
7.
Watchdog timer
The watchdog timer starts operation immediately after the reset is released. When the
watchdog timer is not used, disable it.
8.
AD Converter
The string register between VREFH and VREFL pins can be cut by a program to reduce
power consumption. When the standby mode is used, disable the resistor using the program
before the “HALT” instruction is executed.
9.
CPU (Micro DMA)
Only the “LDC cr, r”, “LDC r, cr” instructions can be used to access the control registers in
the CPU (like the transfer source address register (DMASn)).
10. POP SR instruction
Please execute POP SR instruction during DI condition.
11. Releasing the HALT mode by requesting an interruption
Usually, interrupts can release all halts status. However, the interrupts = ( NMI , INT0)
which can release the HALT mode may not be able to do so if they are input during the
period CPU is shifting to the HALT mode (for about 3 clocks of fFPH) with IDLE1 or STOP
mode (RUN and IDLE2 are not applicable to this case). (In this case, an interrupt request is
kept on hold internally.)
If another interrupt are generated after it has shifted to HALT mode completely, halt
status can be released without difficultly. The priority of this interrupt is compare with that
of the interrupt kept on hold internally, and the interrupt with higher priority is handled
first followed by the other interrupt.
93CS44-219
2004-02-10
93CS44-220
Package
P-LQFP80-1212-0.50E
C00000H to FFFFFFH
CS2
Mapping Area
(WAITC2<B2C1:0> = 11)
Operation Voltage
880H to 7FFFH
CS1
Mapping Area
(WAITC1<B1C1:0> = 00)
C00000H to FEFFFFH
2 Kbytes (80H to 87FH)
None
64-Kbyte
mask ROM
(FF0000H to FFFFFFH)
Built-in ROM
Built-in ROM
TMP93CS45
TMP93CS44
TMP93CU44
2.7 to 5.5 V
C00000H to FEFFFFH
C00000H to FE7FFFH
C80H to 7FFFH
3 Kbytes
(80H to C7FH)
64-Kbyte
96-Kbyte
OTP
mask ROM
(FF0000H to FFFFFFH) (FE8000H to FFFFFFH)
TMP93PS44
128-Kbyte
OTP
(FE0000H to FFFFFFH)
TMP93PW44A
P-QFP80-1420-0.80B
4.5 to 5.5 V
C00000H to FDFFFFH
1080H to 7FFFH
4 Kbytes (80H to 107FH)
128-Kbyte
mask ROM
(FE0000H to FFFFFFH)
TMP93CW44
8.
ITEM
TMP93CS44/S45
TMP93XX44/45 Different Points
2004-02-10
TMP93CS44/S45
9. Package Dimensions
P-LQFP80-1212-0.50E
Unit: mm
60
41
61
40
80
21
20
0.22 0.05
1.25 TYP.
0.5
93CS44-221
0.08
2004-02-10
TMP93CS44/S45
93CS44-222
2004-02-10