REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A In accordance with N.O.R. 5962-R182-94. 94-04-26 M. A. FRYE B In accordance with N.O.R. 5962-R192-94. 94-06-01 M. A. FRYE C In accordance with N.O.R. 5962-R059-95. 95-01-25 M. A. FRYE D In accordance with N.O.R. 5962-R206-95. 95-10-11 M. A. FRYE E In accordance with N.O.R. 5962-R094-96. 96-04-10 M. A. FRYE F In accordance with N.O.R. 5962-R252-97. 97-03-21 R. MONNIN G Incorporate previous notice of revisions. Redrawn. 97-07-10 R. MONNIN H Add a footnote to unity gain bandwidth and slew rate tests in table I. Update boilerplate. -rrp 01-05-07 R. MONNIN J Add footnote 3/ to tests tOD, tDO, and tD, in table I. Add footnote 6/ to tests PS, tOS, and fMAX in table I. - gt 02-04-03 R. MONNIN THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. REV SHEET REV J SHEET 15 REV STATUS REV J J J J J J J J J J J J J J OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY RICK OFFICER STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216 http://www.dscc.dla.mil CHECKED BY RAJESH PITHADIA APPROVED BY RAYMOND MONNIN MICROCIRCUIT, LINEAR, PHASE SHIFT RESONANT CONTROLLER, MONOLITHIC SILICON DRAWING APPROVAL DATE 94-04-05 REVISION LEVEL J SIZE CAGE CODE A 67268 SHEET DSCC FORM 2233 APR 97 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. 1 OF 5962-94555 15 5962-E324-02 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 94555 Federal stock class designator \ RHA designator (see 1.2.1) 01 M R X Device type (see 1.2.2) Device class designator (see 1.2.3) Case outline (see 1.2.4) Lead finish (see 1.2.5) / \/ Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type 01 Generic number Circuit function UC1875 Phase shift resonant controller UVLO Turn-on UVLO Turn-off 10.75 V 9.25 V 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, nonJAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals R X GDIP1-T20 or CDIP2-T20 CQCC1-N28B 20 28 3 CQCC1-N28 28 Package style Dual-in-line Square leadless chip carrier with thermal pads Square leadless chip carrier 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-94555 A REVISION LEVEL J SHEET 2 1.3 Absolute maximum ratings. 1/ Supply voltage (VC, VIN) ......................................................... Output current, source or sink: DC ........................................................................................ Pulse (0.5 µs) ....................................................................... Analog I/O pins....................................................................... Operating junction temperature (TJ)....................................... Storage temperature range .................................................... Lead temperature (soldering, 10 seconds) ............................ Thermal resistance, junction-to-case (θJC) ............................. Thermal resistance, junction-to-ambient (θJA): Case R ................................................................................. Cases X and 3...................................................................... 20 V 0.5 A 3A -0.3 V to 5.3 V 150°C -65°C to +150°C 300°C See MIL-STD-1835 85°C/W 65°C/W 1.4 Recommended operating conditions. Supply voltage (VC, VIN) ......................................................... 12 V Ambient operating temperature (TA) ...................................... -55°C to +125°C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in the solicitation. SPECIFICATION DEPARTMENT OF DEFENSE MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. STANDARDS DEPARTMENT OF DEFENSE MIL-STD-883 MIL-STD-1835 - Test Method Standard Microcircuits. Interface Standard Electronic Component Case Outlines. HANDBOOKS DEPARTMENT OF DEFENSE MIL-HDBK-103 MIL-HDBK-780 - List of Standard Microcircuit Drawings. Standard Microcircuit Drawings. (Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-94555 A REVISION LEVEL J SHEET 3 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Logic diagram(s). The logic diagram(s) shall be as specified on figure 2. 3.2.4 Timing diagram(s). The timing diagram(s) shall be as specified on figure 3. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked as listed in MIL-HDBK-103. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change as defined in MIL-PRF-38535, appendix A. 3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 110 (see MIL-PRF-38535, appendix A). STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-94555 A REVISION LEVEL J SHEET 4 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55°C ≤ TA ≤ +125°C unless otherwise specified Group A subgroups Device type Limits 2/ Min Unit Max Supply current section Input current startup IIS VIN = 8 V, VC = 20 V, RSLOPE = open, IDELAY = 0 mA 1,2,3 01 600 µA Output switch supply current startup IIS VIN = 8 V, VC = 20 V, RSLOPE = open, IDELAY = 0 mA 1,2,3 01 100 µA Input supply current IIN 1,2,3 01 40 mA Output switch supply current IC 1,2,3 01 30 mA 1 01 Voltage reference section Output voltage VOUT TA = +25°C Load regulation VLD VREF = -10 mA 1,2,3 01 20 mV Line regulation VLN +VIN = 11 V to 20 V 1,2,3 01 10 mV Total variation VT Line, load, temperature 1,2,3 01 5.1 V 4.92 5.08 V Error amplifier section Offset voltage VIO 1,2,3 01 15 mV Input bias current IIB 1,2,3 01 3 µA Open loop voltage gain AVOL VCOMP = 1 V to 4 V 4,5,6 01 60 dB Common mode rejection ratio CMRR VCM = 1.5 V to 5.5 V 4,5,6 01 75 dB Power supply rejection ratio PSRR VIN = 11 V to 20 V 4,5,6 01 85 dB Output sink current ISI VCOMP = 1 V 1,2,3 01 1 mA See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-94555 A REVISION LEVEL J SHEET 5 TABLE I. Electrical performance characteristics – Continued. Test Symbol Conditions 1/ -55°C ≤ TA ≤ +125°C unless otherwise specified Group A subgroups Device type Limits 2/ Min Unit Max Error amplifier section - Continued Output source current ISO VCOMP = 4 V 1,2,3 01 Output voltage, high VOH ICOMP = -0.5 mA 1,2,3 01 4 5 V Output voltage, low VOL ICOMP = 1 mA 1,2,3 01 0 1 V Unity gain bandwidth 3/ UGBW 4,5,6 01 5 MHz Slew rate SR 4,5,6 01 6 V/µs 3/ -0.5 mA Pulse width modulator section Zero phase shift voltage VZPS 4/ 1,2,3 01 0.55 Pulse width modulator 5/ 6/ phase shift PS VCOMP > (ramp peak + ramp offset) 4,5,6 01 98 102 0 2 VCOMP < (zero phase shift voltage) 6/ tOS Ramp to output delay 3/ tOD Output skew 5/ VCOMP < 1 V V % 9,10,11 01 ±20 ns 9,10,11 01 125 ns 4 01 1.15 MHz Oscillator section Initial accuracy IA TA = +25°C Voltage stability VS VIN = 11 V to 20 V 4,5,6 01 Total variation VT Line, temperature 1,2,3 01 Clock output pulse width tCLKO RCLK/SYNC = 3.9 kΩ 4,5,6 01 Maximum frequency fMAX RfSET = 5 kΩ 4,5,6 01 6/ 0.85 2 0.80 % 1.20 MHz 100 ns 2 MHz See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-94555 A REVISION LEVEL J SHEET 6 TABLE I. Electrical performance characteristics – Continued. Test Symbol Conditions 1/ -55°C ≤ TA ≤ +125°C unless otherwise specified Group A subgroups Device type Limits 2/ Min Unit Max Ramp generator / slope compensation section µA Minimum ramp current IRMIN ISLOPE = 10 µA, VfSET = VREF 1,2,3 01 Maximum ramp current IRMAX ISLOPE = 1 mA, VfSET = VREF 1,2,3 01 -0.8 mA Ramp peak, clamping level voltage VCL RfSET = 100 kΩ 1,2,3 01 3.8 V Input bias current IIB C+C/S = 3 V 1,2,3 01 Threshold voltage VTH 1,2,3 01 Delay to output 3/ tDO 9,10,11 01 -14 Current limit section 2.4 5 µA 2.6 V 150 ns -3 µA SOFT-START / reset delay section Charge current ICH VS-S = 0.5 V 1,2,3 01 -20 Discharge current IDCH VS-S = 1 V 1,2,3 01 120 µA Restart threshold voltage VRTH 1,2,3 01 4.3 V OUTPUT drivers section Output low level voltage VOL IOUT = 50 mA 1,2,3 01 0.4 V Output high level voltage VOH IOUT = -50 mA 1,2,3 01 2.5 V See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-94555 A REVISION LEVEL J SHEET 7 TABLE I. Electrical performance characteristics – Continued. Test Symbol Conditions 1/ -55°C ≤ TA ≤ +125°C unless otherwise specified Group A subgroups Device type Limits 2/ Unit Min Max DELAY SET section DELAY SET voltage VDS IDELAY = -500 µA DELAY time 3/ tD IDELAY = -250 µA 7/ 1,2,3 01 2.3 2.6 V 9,10,11 01 150 600 ns 1/ Unless otherwise specified, VS = +VIN = 12 V, frequency set resistance RfSET = 12 kΩ, frequency set capacitance CfSET = 330 pF, slope resistance RSLOPE = 12 kΩ, ramp capacitance CRAMP = 200 pF, DELAY SET capacitance CDS A-B = CDS C-D = 0.01 µF, DELAY SET current IDS A-B = IDS C-D = -500 µA. 2/ The algebraic convention, whereby the most negative value is a minimum and the most positive is a maximum, is used in this table. Negative current shall be defined as conventional current flow out of a device terminal. 3/ Not production tested. 4/ Zero phase shift voltage has a temperature coefficient of about -2 mV/°C. 5/ Phase shift percentage (0% = 0°, 100% = 180°) is defined as: θ = (200/T) φ % . θ is the phase shift, and φ and T are defined in figure 3. At 0% phase shift, φ is the output skew. 6/ Not tested at -55°C but guaranteed by bench testing. -12 7/ Delay time can be programmed via resistors from the delay set pins to ground. Delay time = (62.5 x 10 ) seconds/ IDELAY. IDELAY = delay set voltage/RDELAY. The recommended range for IDELAY is 25µA ≤ IDELAY ≤ 1 mA. 4. QUALITY ASSURANCE PROVISIONS 4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. 4.2.1 Additional criteria for device class M. a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition B. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015. (2) TA = +125°C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-94555 A REVISION LEVEL J SHEET 8 Device type 01 Case outlines R Terminal number X and 3 Terminal symbol 1 VREF VIN 2 E/A OUT (COMP) PWR GND 3 E/A (-) OUTPUT B (OUT B) 4 E/A (+) OUTPUT A (OUT A) 5 C/S (+) NC 6 SOFT-START NC 7 DELAY SET C/D DELAY SET A/B 8 OUTPUT D (OUT D) FREQ SET 9 OUTPUT C (OUT C) CLOCK/SYNC 10 VC SLOPE 11 VIN RAMP 12 POWER GND NC 13 OUTPUT B (OUT B) NC 14 OUTPUT A (OUT A) GND 15 DELAY SET A/B NC 16 FREQ SET VREF 17 CLOCK/SYNC E/A OUT 18 SLOPE NC 19 RAMP NC 20 GND E/A (-) 21 --- E/A (+) 22 --- C/S (+) 23 --- SOFTSTART 24 --- DELAY SET C/D 25 --- NC 26 --- OUTPUT D (OUT D) 27 --- OUTPUT C (OUT C) 28 --- VC NC = No connection FIGURE 1. Terminal connections. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-94555 A REVISION LEVEL J SHEET 9 FIGURE 2. Logic diagram. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-94555 A REVISION LEVEL J SHEET 10 Phase shift, output skew and delay time definitions. Duty cycle = t/T. Period = T. TDHL (A to C) = TDHL (B to D) = φ FIGURE 3. Timing diagram. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-94555 A REVISION LEVEL J SHEET 11 TABLE II. Electrical test requirements. Test requirements Interim electrical parameters (see 4.2) Final electrical parameters (see 4.2) Group A test requirements (see 4.4) Group C end-point electrical parameters (see 4.4) Group D end-point electrical parameters (see 4.4) Group E end-point electrical parameters (see 4.4) Subgroups (in accordance with MIL-STD-883, method 5005, table I) Device class M ---- Subgroups (in accordance with MIL-PRF-38535, table III) Device class Q ---- Device class V ---- 1,2,3,4,5, 1/ 6,9,10,11 1,2,3,4,5,6, 9,10,11 1, 4 1,2,3,4,5, 1/ 6,9,10,11 1,2,3,4,5,6, 9,10,11 1, 4 1,2,3,4,5, 1/ 6,9,10,11 1,2,3,4,5,6, 9,10,11 1, 4 1, 4 1, 4 1, 4 ---- ---- ---- 1/ PDA applies to subgroup 1. 4.2.2 Additional criteria for device classes Q and V. a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015 of MIL-STD-883. b. Interim and final electrical test parameters shall be as specified in table II herein. c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in MIL-PRF-38535, appendix B. 4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). 4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). 4.4.1 Group A inspection. a. Tests shall be as specified in table II herein. b. Subgroups 7 and 8 in table I, method 5005 of MIL-STD-883 shall be omitted. 4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table II herein. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-94555 A REVISION LEVEL J SHEET 12 4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883: a. Test condition B. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005 of MIL-STD-883. b. TA = +125°C, minimum. c. Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. 4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005 of MIL-STD-883. 4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table II herein. 4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured (see 3.5 herein). a. End-point electrical parameters shall be as specified in table II herein. b. For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All device classes must meet the postirradiation end-point electrical parameter limits as defined in table I at TA = +25°C ±5°C, after exposure, to the subgroups specified in table II herein. c. When specified in the purchase order or contract, a copy of the RHA delta limits shall be supplied. 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor prepared specification or drawing. 6.1.2 Substitutability. Device class Q devices will replace device class M devices. 6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal. 6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus when a system application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544. 6.4 Comments. Comments on this drawing should be directed to DSCC-VA , Columbus, Ohio 43216-5000, or telephone (614) 692-0547. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-94555 A REVISION LEVEL J SHEET 13 6.5 Abbreviations, symbols, and definitions. GND Signal ground. All voltages are measured with respect to ground (GND). The timing capacitor, on the FREQ SET pin, and bypass capacitor on the VREF pin, bypass capacitors on VIN and the ramp capacitor, on the RAMP pin, should be connected directly to the ground plane near the signal ground pin. PWR GND Power ground. VC should be bypassed with a ceramic capacitor from the VC pin to the section of the ground plane that is connected to PWR GND. Any required bulk reservoir capacitor should parallel this one. Power ground and signal ground may be joined at a signal point to optimize noise rejection and minimize DC drops. VC Output switch supply voltage. This pin supplies power to the drivers and their associated bias circuitry. Connect VC to a stable source above 3 V for normal operation, above 12 V for best performance. This supply should be bypassed directly to the PWR GND pin with low ESR, low ESL capacitors. VIN Primary chip supply voltage. This pin supplies power to the logic and analog circuitry on the integrated circuitry that is not directly associated with driving the output stages. FREQ SET Oscillator frequency set pin. A resistor and a capacitor from FREQ SET to GND will set oscillator frequency according to the following relationship: f = 4/(RfSET x CRAMP). CLK/SYNC Bi-directional clock and synchronization pin. Used as an output, this pin provides a clock signal. As an input, this pin provides a synchronization point. SLOPE Set ramp slope.slope compensation. A resistor from this pin to VCC will set the current used to generate the ramp. Connecting this resistor to the DC input line will provide voltage feed forward. RAMP Voltage ramp. This pin is the input to the pulse width modulator comparator. Connect a capacitor from here to GND. A voltage ramp is developed at this pin with a slope: (dV/dT) = (sense voltage/RSLOPE x CRAMP). E/A OUT (COMP) Error amplifier output. This is the gain stage for overall feedback control. Error amplifier output voltage levels below 1 volt will force 0° phase shift. Since the error amplifier has a relatively low current drive capability, the output may be overridden by driving with a sufficiently low impedance source. E/A(+) This pin is normally connected to a reference voltage used for comparison with the sensed power supply output voltage level at the E/A(-) pin. E/A(-) This pin is normally connected to the voltage divider resistors which sense the power supply output level. SOFT START SOFT START will remain at GND as long as VIN is below the UVLO threshold. SOFT START will be pulled up to about 4.8 V by an internal 9 µA current source when VIN becomes valid (assuming a non-fault condition). In the event of a current-fault (C/S (+) voltage exceeding 2.5 V), SOFT START will be pulled to GND and then ramp to 4.8 V. If a fault occurs during the SOFT START cycle, the outputs will be immediately disabled and SOFT START must charge fully prior to resetting the fault latch. For paralleled controllers, the SOFT START pins may be paralleled to a single capacitor, but the change currents will be additive. CURRENT SENSE (+) The positive input to the current-fault comparator whose reference is set internally to fixed 2.5 V (separate from VREF). When the voltage at this pin exceeds 2.5 V, the current-fault latch is set, the outputs are forced off and a SOFT START cycle is initiated. If a constant voltage above 2.5 V is applied to this pin the outputs are disabled from switching and held in a low state until the C/S (+) pin is brought below 2.5 V. The outputs may begin switching at 0 degrees phase shift before the SOFT START pin begins to rise, this condition will not prematurely deliver power to the load. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-94555 A REVISION LEVEL J SHEET 14 OUTPUTS A, B, C, D The outputs are 2 A totem-pole drivers optimized for both MOSFET gates and level shifting transformers. The outputs operate as pair with a nominal 50% duty cycle. The A-B pair is intended to drive one half bridge in the external power stage and is synchronized with the clock waveform. The C-D pair will drive the other half-bridge with switching phase shifted with respect to the A-B outputs. DELAY SET A-B, DELAY SET C-D Output delay control. The users programmed current flowing from these pins to GND set the turn-on delay for the corresponding output pair. This delay is introduced between turn-off of one switch and turn-on of another in the same leg of the bridge to provide a dead time in which the resonant switching of the external power switches takes place. Separate delays are provided for the two half bridges to accommodate differences in the resonant capacitor charging currents. VREF This pin is an accurate 5 V voltage reference. This output is capable of delivering about 60 mA to peripheral circuitry and is internally short circuit current limited. 6.6 Sources of supply. 6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535. The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to this drawing. 6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103. The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted by DSCC-VA. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-94555 A REVISION LEVEL J SHEET 15 STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 02-04-03 Approved sources of supply for SMD 5962-94555 are listed below for immediate acquisition information only and shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by DSCC-VA. This bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. Standard microcircuit drawing PIN 1/ 5962-9455501MRA 5962-9455501MXA 5962-9455501M3A 5962-9455501V3A 5962-9455501VRA Vendor CAGE number 01295 3/ 01295 01295 01295 Vendor similar PIN 2/ UC1875J/883BC UC1875LP/883BC UC1875L/883BC UC1875LQMLV UC1875JQMLV 1/ The lead finish shown for each PIN representing a hermetic package is the most readily available from the manufacturer listed for that part. If the desired lead finish is not listed contact the vendor to determine its availability. 2/ Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. 3/ Not available from an approved source of supply. Vendor CAGE number 01295 Vendor name and address Texas Instruments, Incorporated 13500 North Central Express way P.O. Box 655303 Dallas, TX 75265 Point of contact: 6412 Highway 75 South Sherman, TX 75090-0084 The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in the information bulletin.