Quad UV/OV Positive/Negative Voltage Supervisor ADM2914 FEATURES APPLICATIONS Server supply monitoring FPGA/DSP core and I/O voltage monitoring Telecommunications equipment Medical equipment FUNCTIONAL BLOCK DIAGRAM VCC TIMER ADM2914 VH1 TIMER 500mV VL1 VH2 UV 500mV VL2 OUTPUT LOGIC VH3 500mV OV VL3 MUX VH4 LOGIC 500mV REF LATCH/DIS REF VL4 SEL GND 08170-001 Quad UV/OV positive/negative supervisor Supervises up to 2 negative rails Adjustable UV and OV input thresholds High threshold accuracy over temperature: ±1.5% 1 V buffered reference output Open-drain UV and OV reset outputs Adjustable reset timeout with disable option Outputs guaranteed down to VCC of 1 V Glitch immunity 62 µA supply current 16-lead QSOP package Figure 1. GENERAL DESCRIPTION The ADM2914 is a quad voltage supervisory IC ideally suited for monitoring multiple rails in a wide range of applications. Each monitored rail has two dedicated input pins, VHx and VLx, which allows each rail to be monitored for both overvoltage (OV) and undervoltage (UV) conditions. A common active low undervoltage (UV) and overvoltage (OV) pin is shared by each of the monitored voltage rails. The ADM2914 includes a 1 V buffered reference output, REF, that acts as an offset when monitoring a negative voltage. The three-state SEL pin determines the polarity of the third and fourth inputs, that is, it configures the device to monitor positive or negative supplies. the VCC pin to limit the current flow into the VCC pin to no greater than 10 mA. The ADM2914 uses the internal shunt regulator to regulate VCC if the supply line exceeds the absolute maximum ratings. The ADM2914 is available in two models. The ADM2914-1 offers a latching overvoltage output that can be cleared by toggling the LATCH input pin. The ADM2914-2 has a disable pin that can override and disable both the OV and UV output signals. The ADM2914 is available in a 16-lead QSOP package. The device operates over the extended temperature range of −40°C to +125°C. The device incorporates an internal shunt regulator that enables the device to be used in higher voltage systems. This feature requires a resistor to be placed between the main supply rail and Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. ADM2914 TABLE OF CONTENTS Features .............................................................................................. 1 Voltage Monitoring Example .................................................... 10 Applications ....................................................................................... 1 Power-Up and Power-Down ..................................................... 11 Functional Block Diagram .............................................................. 1 UV/OV Timing Characteristics ............................................... 11 General Description ......................................................................... 1 Timer Capacitor Selection ........................................................ 11 Revision History ............................................................................... 2 UV and OV Rise and Fall Times .............................................. 12 Specifications..................................................................................... 3 UV/OV Output Characteristics ............................................... 12 Absolute Maximum Ratings ............................................................ 4 Glitch Immunity ......................................................................... 12 ESD Caution .................................................................................. 4 Undervoltage Lockout (UVLO) ............................................... 12 Pin Configurations and Function Descriptions ........................... 5 Shunt Regulator .......................................................................... 12 Typical Performance Characteristics ............................................. 6 OV Latch (ADM2914-1) ........................................................... 12 Theory of Operation ........................................................................ 8 Disable (ADM2914-2) ............................................................... 12 Voltage Supervision ...................................................................... 8 Typical Applications ....................................................................... 13 Polarity Configuration ................................................................. 8 Outline Dimensions ....................................................................... 15 Monitoring Pin Connections ...................................................... 9 Ordering Guide .......................................................................... 15 Threshold Accuracy ................................................................... 10 REVISION HISTORY 5/09—Revision 0: Initial Version Rev. 0 | Page 2 of 16 ADM2914 SPECIFICATIONS TA = −40°C to +85°C. Typical values at TA = 25°C, unless otherwise noted. VCC = 3.3 V, VLx = 0.45 V, VHx = 0.55 V, LATCH = VCC, SEL = VCC, DIS = open, unless otherwise noted. Table 1. Parameter SHUNT REGULATOR VCC Shunt Regulator Voltage, VSHUNT VCC Shunt Regulator Load Regulation, ΔVSHUNT SUPPLY Supply Voltage, VCC 1 Minimum VCC Output Valid, VCCR(MIN) Supply Undervoltage Lockout, VCC(UVLO) Supply Undervoltage Lockout Hysteresis, ΔVCC(HYST) Supply Current, ICC REFERENCE OUTPUT Reference Output Voltage, VREF UNDERVOLTAGE/OVERVOLTAGE CHARACTERISTICS Undervoltage/Overvoltage Threshold, VUOT Undervoltage/Overvoltage Threshold to Output Delay, tUOD VHx, VLx Input Current, IVHL UV/OV Timeout Period, tUOTO OV LATCH CLEAR INPUT (ADM2914-1) OV Latch Clear Threshold Input High, VLATCH(IH) Min Typ Max Unit Test Conditions/Comments 6.2 6.2 6.6 6.6 200 6.9 7.0 300 V V mV ICC = 5 mA TA = −40°C to +125°C ICC = 2 mA to 10 mA 1.9 5 2 25 62 VSHUNT 1 2.1 50 100 V V V mV μA DIS = 0 V DIS = 0 V, VCC rising DIS = 0 V VCC = 2.3 V to 6 V 0.985 0.985 1 1 1.015 1.020 V V IVREF = ±1 mA TA = −40°C to +125°C 492.5 50 500 125 6 6 8.5 8.5 507.5 500 ±15 ±30 12.5 14 mV μs nA nA ms ms 2.3 TA = −40°C to +125°C CTIMER = 1 nF TA = −40°C to +125°C V 1.2 OV Latch Clear Threshold Input Low, VLATCH(IL) 0.8 V LATCH Input Current, ILATCH ±1 μA VLATCH > 0.5 V 0.8 3 V V μA VDIS > 0.5 V μA μA μA μA mV VTIMER = 0 V TA = −40°C to +125°C VTIMER = 1.6 V TA = −40°C to +125°C Referenced to VCC DISABLE INPUT (ADM2914-2) DIS Input High, VDIS(IH) DIS Input Low, VDIS(IL) DIS Input Current, IDIS TIMER CHARACTERISTICS TIMER Pull-Up Current, ITIMER(UP) TIMER Pull-Down Current, ITIMER(DOWN) TIMER Disable Voltage, VTIMER(DIS) OUTPUT VOLTAGE Output Voltage High, UV/OV, VOH 1.2 1 2 −1.3 −1.2 1.3 1.2 −180 −2.1 −2.1 2.1 2.1 −270 −2.8 −2.8 2.8 2.8 V VCC = 2.3 V; IUV/OV = −1 μA 0.1 0.3 V VCC = 2.3 V; IUV/OV = 2.5 mA 0.01 0.15 V VCC = 1 V; IUV = 100 μA 0.4 V V V V μA μA ISEL = ±10 μA TA = −40°C to +125°C 1 Output Voltage Low, UV/OV, VOL THREE-STATE INPUT SEL Low Level Input Voltage, VIL High Level Input Voltage, VIH Pin Voltage When Left in High-Z State, VZ 1.4 0.7 0.6 0.9 0.9 SEL High, Low Input Current, ISEL Maximum SEL Input Current, ISEL(MAX) 1 VHx = VUOT − 5 mV or VLx = VUOT + 5 mV 1.1 1.2 ±25 ±30 SEL tied to VCC or GND The maximum voltage on the VCC pin is limited by the input current. The VCC pin has an internal 6.5 V shunt regulator and, therefore, a low impedance supply greater than 6 V may exceed the maximum allowed input current. When operating from a higher supply than 6 V, always use a dropping resistor. Rev. 0 | Page 3 of 16 ADM2914 ABSOLUTE MAXIMUM RATINGS Table 3. Thermal Resistance Table 2. Parameter VCC UV, OV TIMER VLx, VHx, LATCH, DIS, SEL ICC Reference Load Current (IREF) IUV, IOV Rating −0.3 V to +6 V −0.3 V to +16 V −0.3 V to (VCC + 0.3 V) −0.3 V to +7.5 V 10 mA ±1 mA 10 mA Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec) −65°C to +150°C −40°C to +125°C 300°C Package Type 16-Lead QSOP ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 4 of 16 θJA 104 Unit °C/W ADM2914 16 VCC VH1 1 16 VCC VL1 2 15 TIMER VL1 2 15 TIMER VH2 3 14 SEL VH2 3 14 SEL 13 LATCH VL2 4 ADM2914-2 13 DIS 12 UV VH3 5 TOP VIEW (Not to Scale) 12 UV VL3 6 11 OV VL3 6 11 OV VH4 7 10 REF VH4 7 10 REF VL4 8 9 GND VL4 8 9 GND VL2 4 ADM2914-1 VH3 5 TOP VIEW (Not to Scale) 08170-002 VH1 1 Figure 2. ADM2914-1 Pin Configuration 08170-011 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 3. ADM2914-2 Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 3 2 4 5 7 Mnemonic ADM2914-1 ADM2914-2 VH1 VH1 VH2 VH2 VL1 VL1 VL2 VL2 VH3 VH3 VH4 VH4 6 8 VL3 VL4 VL3 VL4 9 10 GND REF GND REF 11 OV OV 12 UV UV 13 LATCH DIS 14 SEL SEL 15 TIMER TIMER 16 VCC VCC Description Voltage High Input 1 and Voltage High Input 2. If the voltage monitored by VH1 or VH2 drops below 0.5 V, an undervoltage condition is detected. Connect to VCC when not in use. Voltage Low Input 1 and Voltage Low Input 2. If the voltage monitored by VL1 or VL2 rises above 0.5 V, an overvoltage condition is detected. Tie to GND when not in use. Voltage High Input 3 and Voltage High Input 4. The polarity of these inputs is determined by the state of the SEL pin (see Table 5). When the monitored input is configured as a positive voltage and the voltage monitored by VH3 or VH4 drops below 0.5 V, an undervoltage condition is detected. Conversely, when the input is configured as a negative voltage and the input drops below 0.5 V, an overvoltage condition is detected. Connect to VCC when not in use. Voltage Low Input 3 and Voltage Low Input 4. The polarity of these inputs is determined by the state of the SEL pin (see Table 5). When the monitored input is configured as a positive voltage and the voltage monitored by VL3 or VL4 rises above 0.5 V, an overvoltage condition is detected. Conversely, when the input is configured as a negative voltage and the input rises above 0.5 V, an undervoltage condition is detected. Tie to GND when not in use. Device Ground. Buffered Reference Output. This pin is a 1 V reference that is used as an offset when monitoring negative voltages. This pin can source or sink 1 mA, and drive loads up to 1 nF. Larger capacitive loads may lead to instability. Leave unconnected when not in use. Overvoltage Reset Output. OV is asserted low if a negative polarity input voltage drops below its associated threshold or if a positive polarity input voltage exceeds its threshold. The ADM2914-1 allows OV to be latched low. The ADM2914-2 holds OV low for an adjustable timeout period determined by the TIMER capacitor. This pin has a weak pull-up to VCC and can be pulled up to 16 V externally. Leave this pin unconnected when not in use. Undervoltage Reset Output. UV is asserted low if a negative polarity input voltage exceeds its associated threshold or if a positive polarity input voltage drops below its threshold. UV is held low for an adjustable timeout period set by the external capacitor tied to the TIMER pin. The UV pin has a weak pull-up to VCC and can be pulled up to 16 V externally via an external pull-up resistor. Leave this pin unconnected when not in use. OV Latch Bypass Input/Clear Pin. When pulled high, the OV latch is cleared. When held high, the OVoutput has the same delay and output characteristics as the UV output. When pulled low, the OV output is latched when asserted. (Applies only to the ADM2914-1.) OV and UV Disable Input. When pulled high, the OV and UV outputs are held high irrespective of the state of the VHx and VLx input pins. However, if a UVLO condition occurs, the OV and UV outputs are asserted. This pin has a weak internal pull-down (2 µA) to GND. Leave this pin unconnected when not in use. (Applies only to the ADM2914-2.) Input Polarity Select. This three-state input pin allows the polarity of VH3, VL3, VH4, and VL4 to be configured. Connect to VCC or GND, or leave open to select one of three possible input polarity configurations (see Table 5). Adjustable Reset Delay Timer. Connect an external capacitor to the TIMER pin to program the reset timeout delay. Refer to Figure 15 in the Typical Performance Characteristics section. Connect this pin to VCC to bypass the timer. Supply Voltage. VCC operates as a direct supply for voltages up to 6 V. For voltages greater than 6 V, it operates as a shunt regulator. A dropping resistor must be used in this configuration to limit the current to less than 10 mA. When used without the resistor, the voltage at this pin must not exceed 6 V. A 0.1 μF bypass capacitor or greater should be used. Rev. 0 | Page 5 of 16 ADM2914 TYPICAL PERFORMANCE CHARACTERISTICS 6.80 0.505 6.75 0.503 6.70 0.502 6.65 VCC (V) 0.501 0.500 0.499 –40°C 6.60 +25°C 6.55 +85°C 0.498 6.50 0.497 10 20 30 40 TEMPERATURE (°C) 50 60 70 6.40 0 80 95 1.004 REFERENCE VOLTAGE, VREF (V) 1.005 90 VCC = 6V VCC = 2.3V 65 55 –15 10 35 TEMPERATURE (°C) 1.002 1.001 1.000 0.999 0.998 0.997 60 0.996 0.995 –40 85 Figure 5. Supply Current vs. Temperature 0 20 40 TEMPERATURE (°C) 60 80 1000 200µA 1mA 2mA 5mA 10mA 6.70 800 6.65 6.60 6.55 6.50 08170-014 6.45 –15 10 35 TEMPERATURE (°C) 60 RESET ASSERTED ABOVE THE LINE 900 TRANSIENT DURATION (µs) 6.75 VCC (V) –20 Figure 8. Buffered Reference Voltage vs. Temperature 6.80 6.40 –40 10 1.003 08170-013 60 50 –40 8 700 VCC = 6V 600 500 400 VCC = 2.3V 300 200 08170-017 ICC (µA) VCC = 3.3V 75 70 6 Figure 7. VCC Shunt Voltage vs. ICC 100 80 4 ICC (mA) Figure 4. Input Threshold Voltage vs. Temperature 85 2 08170-016 0 08170-014 0.496 0.495 –40 –30 –20 –10 6.45 08170-012 THRESHOLD VOLTAGE, VUOT (V) 0.504 100 0 0.1 85 Figure 6. VCC Shunt Voltage vs. Temperature 1 10 COMPARATOR OVERDRIVE (% OF VTH) Figure 9. Transient Duration vs. Comparator Overdrive Rev. 0 | Page 6 of 16 100 ADM2914 3.0 12 PULL-DOWN CURRENT IUV (mA) 11 10 9 8 7 –15 10 35 TEMPERATURE (°C) 60 2.0 1.5 1.0 UV = 50mV 0.5 08170-021 6 –40 –0.5 0 85 Figure 10. UV/OV Timeout Period vs. Temperature 0.9 1000 0.8 900 2 3 4 SUPPLY VOLTAGE, VCC (V) 5 6 800 WITH 10kΩ PULL-UP +85°C 700 UV/OV, VOL (mV) 0.6 0.5 0.4 0.3 600 +25°C 500 400 – 40°C 0.2 300 0.1 08170-019 –0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 SUPPLY VOLTAGE, VCC (V) 0.8 0.9 08170-022 200 WITHOUT PULL-UP 0 100 0 1.0 0 5 10 15 ISINK (mA) Figure 11. UV Output Voltage vs. VCC Figure 14. UV/OV Voltage Output Low vs. Output Sink Current 10k 5.0 UV/OV TIMEOUT PERIOD, tUOTO (ms) VHx = 0.55V SEL = VCC 4.5 4.0 3.5 3.0 2.5 2.0 1.5 08170-020 1.0 0.5 0 0 1 2 3 SUPPLY VOLTAGE, VCC (V) 4 1k 100 10 1 0.1 5 08170-023 UV VOLTAGE (V) 1 Figure 13. ISINK, IUV vs. VCC 0.7 UV VOLTAGE (V) UV = 150mV 0 08170-018 UV/OV TIMEOUT PERIOD, tUOTO (ms) VHx = 0.45V SEL = VCC 2.5 1 10 100 TIMER PIN CAPACITANCE CTIMER (nF) Figure 15. UV/OV Timeout Period vs. Capacitance Figure 12. UV Output Voltage vs. VCC Rev. 0 | Page 7 of 16 1000 ADM2914 THEORY OF OPERATION VOLTAGE SUPERVISION POLARITY CONFIGURATION The ADM2914 supervises up to four voltage rails for overvoltage and undervoltage conditions. Two pins, VHx and VLx, are assigned to monitor each rail, one for overvoltage detection and the other for undervoltage detection. Each pin is connected to the input of an internal voltage comparator, and its voltage level is internally compared with a 0.5 V voltage reference with accuracy of ±1.5%. The ADM2914 is capable of monitoring supply voltages of both positive and negative polarities. The SEL pin is a three-state pin that determines the polarity of Input 3 and Input 4. As summarized in Table 5, the SEL pin is either connected to GND, VCC, or left unconnected. The output of each of the internal undervoltage comparators is tied to a common UV output pin. Likewise, the outputs of the internal overvoltage comparators are tied to a common OV output pin. PSU Conversely, when an input is configured to monitor a negative voltage, UVx and OVx are swapped internally. The negative voltage for monitoring is then connected as shown in Figure 18. VHx is still connected to the high-side tap and VLx is still connected to the low-side tap. Within this configuration, an undervoltage condition occurs when the monitored voltage is less negative than the programmed threshold, and an overvoltage condition occurs when the monitored voltage is more negative than the configured threshold. 5V 3.3V 2.5V 1.8V VCC VH1 VL1 SEL TIMER VH2 When an input is configured to monitor a positive voltage, using the three-resistor scheme shown in Figure 17, VHx is connected to the high-side tap of the resistor divider and VLx is connected to the low-side tap of the resistor divider. SYSTEM ADM2914 VL2 VH3 UV VL3 OV VH4 VL4 GND 08170-003 REF LATCH/DIS Figure 16. Typical Applications Diagram Table 5. Polarity Configuration SEL Pin Connected to VCC Left Unconnected Connected to GND Polarity Positive Positive Negative Input 3 UV Condition VH3 < 0.5 V VH3 < 0.5 V VL3 > 0.5 V OV Condition VL3 > 0.5 V VL3 > 0.5 V VH3 < 0.5 V Rev. 0 | Page 8 of 16 Polarity Positive Negative Negative Input 4 UV Condition VH4 < 0.5 V VL4 > 0.5 V VL4 > 0.5 V OV Condition VL4 > 0.5 V VH4 < 0.5 V VH4 < 0.5 V ADM2914 MONITORING PIN CONNECTIONS Positive Voltage Monitoring Scheme When monitoring a positive supply, the desired nominal operating voltage for monitoring is denoted by VM, IM is the nominal current through the resistor divider, VOV is the overvoltage trip point, and VUV is the undervoltage trip point. VM To trigger the undervoltage condition, the high-side voltage, VPH, must exceed the 0.5 V threshold on the VHx pin. The high-side voltage, VPH, is given by the following equation: RY + R Z V PH = VUV R X + RY + R Z Because RZ is already known, RY can be expressed as follows: RY = ADM2914 RX VPH VHx RY UVx RX = OVx VPL 08170-004 RZ (2) (V M ) −R −R (I M ) Z Y (3) If VM, IM, VOV, or VUV changes, each step must be recalculated. Figure 17. Positive Undervoltage/Overvoltage Monitoring Configuration Figure 17 illustrates the positive voltage monitoring input connection. Three external resistors, RX, RY, and RZ, divide the positive voltage for monitoring, VM, into high-side voltage, VPH, and low-side voltage, VPL. The high-side voltage is connected to the corresponding VHx pin, and the low-side voltage is connected to the corresponding VLx pin. Negative Voltage Monitoring Scheme Figure 18 shows the circuit configuration for negative supply voltage monitoring. To monitor the negative voltage, a 1 V reference voltage is required to connect to the end node of the voltage divider circuit. This reference voltage is generated internally and is output through the REF pin. REF To trigger an overvoltage condition, the low-side voltage (in this case, VPL) must exceed the 0.5 V threshold on the VLx pin. The low-side voltage, VPL, is given by the following equation: RZ V PL = VOV R X + RY + R Z (0.5)(V M ) −R (VUV )(I M ) Z When RY and RZ are known, RX is calculated using the following equation: 0.5V VLx = 0. 5 V ADM2914 RZ VNH VHx = 0. 5 V RY OVx 0.5V UVx VNL RX R X + RY + R Z = VM IM VM Figure 18. Negative Undervoltage/Overvoltage Monitoring Configuration Therefore, RZ, which sets the desired trip point for the overvoltage monitor, is calculated using the following equation: RZ = (0.5)(V M ) (VOV )(I M ) 08170-005 Also, VLx (1) The equations described in the Positive Voltage Monitoring Scheme section need some minor modifications for use with negative voltage monitoring. The 1 V reference voltage is added to the overall voltage drop; it must therefore be subtracted from VM, VUV, and VOV before using each in the previous equations. To monitor a negative voltage level, the resistor divider circuit divides the voltage differential level between the 1 V reference voltage and the negative supply voltage into high-side voltage, VNH, and low-side voltage, VNL. Similar to the positive voltage monitoring scheme, the high-side voltage, VNH, is connected to the corresponding VHX pin, and the low-side voltage, VNL, is connected to the corresponding VLX pin. Refer to the Voltage Monitoring Example section for more information. Rev. 0 | Page 9 of 16 ADM2914 THRESHOLD ACCURACY The reset threshold accuracy is fundamental, especially at lower voltage levels. Consider an FPGA application that requires a 1 V core voltage input with tolerance of ±5%, where the supply has a specified regulation, for example, ±1.5%. As shown in Figure 19, to ensure that the supply is within the FPGA input voltage requirement range, its voltage level must be monitored for UV and OV conditions. The voltage swing on the supply itself causes the voltage band available for setting the monitoring threshold to be quite narrow. In this example, the threshold voltages, including the tolerances, must fit within a monitor region of only 0.035 V. The ADM2914 device with 0.1% resistors can achieve this level of accuracy. VOLTAGE device, including all the tolerance factors, must fit within the 1.015 V to 1.05 V range. Similarly, the UV threshold range must be between 0.95 V and 0.985 V. The four worst-case scenarios of minimum and maximum undervoltage and overvoltage thresholds are calculated as follows: Minimum overvoltage threshold (R X 0.1%) (RY 0.1%) VOV _ MIN (0.5 V 1.5%)1 R Z 0.1% (96,500 6420)(0.999) 0.49251 (96,500)(1.001) 1.016 V 1.015 V Maximum overvoltage threshold 1.05V +1.5% SUPPLY REGULATION 1V CORE VOLTAGE 0.985V (R X 0.1%) (RY 0.1%) VOV _ MAX (0.5 V 1.5%)1 R Z 0.1% 1.049 V 1.05 V 3.5% RANGE FOR OV MONITORING –1.5% SUPPLY REGULATION –5% TOLERANCE The maximum and minimum overvoltage threshold values lie within the 1.015 V to 1.05 V range specified. The minimum and maximum undervoltage thresholds are calculated as follows: 3.5% RANGE FOR UV MONITORING 0.95V tUOTO UV 08170-006 1.015V +5% TOLERANCE TIME Minimum undervoltage threshold (R X 0.1%) VUV _ MIN (0.5 V 1.5%)1 R 0.1% R 0.1% Y Z 0.953 V 0.95 V Figure 19. Monitoring Threshold Accuracy Example VOLTAGE MONITORING EXAMPLE To illustrate how the ADM2914 device works in a real application, consider the 1 V input example shown in Figure 19, with the addition of a −12 V rail. Maximum undervoltage threshold (R X 0.1%) VUV _ MAX (0.5 V 1.5%)1 R R 0 . 1 % 0 . 1 % Y Z 0.984 V 0.985 V The first step is to choose the nominal current flow through both voltage divider circuits, for example, 5 μA. For the 1 V ± 5% input, due to the specified ±1.5% regulation of the supply, the UV and OV thresholds should be set in the middle of the voltage monitoring band. In this case, on the ±3.25% points of the supply, the UV threshold is 0.9675 V and the OV threshold is 1.0325 V. Again, these values fit within the specified undervoltage monitoring range. All four worst-case scenarios satisfy the tolerance requirement; therefore, the design approach is valid. –12V RAIL 1V RAIL 5V Input these values into Equation 1. (0.5)1 96.5 kΩ 1.03255 10 6 96.5kΩ VH1 VCC OV 6.42Ω Insert the value of RZ into Equation 2. VL1 (0.5)1 RY 96.5 kΩ 6.42 kΩ 0.96755 10 6 96.5kΩ UV ADM2914 2.49MΩ VL3 23.4kΩ VH3 Then substitute the calculated values for RZ and RY into Equation 3. 89.8kΩ SEL REF 1 RX 96.5 kΩ 6.42 kΩ 96.5 kΩ 5 10 6 GND This design approach meets the application specifications. As described previously, the 1 V rail is specified with an input requirement of ±5% and a supply tolerance of ±1.5%. This effectively means that the OV threshold of the monitoring Rev. 0 | Page 10 of 16 08170-007 RZ Figure 20. Positive and Negative Supply Monitor Example ADM2914 Next, consider a −12 V input, which is specified with a ±20% input. The threshold accuracy required by the supply is chosen to be within ±5% of the −12 V rail. Therefore, the overvoltage threshold is set to −13.5 V, and the undervoltage threshold is −10.5 V. The negative voltage scheme configuration requires that the 1 V reference voltage be accounted for in Equation 1 to Equation 3. The 1 V reference voltage is subtracted from VM, VUV, and VOV, and the absolute value of the result is taken. VHx MONITOR TIMING VHx Equation 1 becomes (0.5)( − 12 − 1 ) ( − 13.5 − 1 )(5 ×10 −6 ) ≈ 89.8 kΩ tUOD Insert the value of RZ into Equation 2. RY = ( (0.5) − 12 − 1 ) ( − 10.5 − 1 )(5 ×10 −6 ) VUOT 1V UV − 89.8 kΩ ≈ 23.4 kΩ VHx MONITOR TIMING (TIMER PIN TIED TO VCC) To calculate RX, insert the value of RZ and RY into Equation 3. RX = tUOTO ( − 12 − 1 ) ( − 89.8 kΩ ) − (23.4 kΩ ) ≈ 2.49 MΩ −6 VUOT VHx 5 × 10 tUOD POWER-UP AND POWER-DOWN On power-up, when VCC reaches 1 V, the active low UV output is asserted, and the OV output pulls up to VCC. When the voltage on the VCC pin reaches 1 V, the ADM2914 is guaranteed to assert UV low and OV high. When VCC exceeds 1.9 V (minimum), the VHx and VLx inputs take control. When VCC and each of the VHx inputs are valid, an internal timer begins. Subsequent to an adjustable time delay, UV weakly pulls high. tUOD 1V UV WHEN AN INPUT IS CONFIGURED TO MONITOR A NEGATIVE VOLTAGE, VHx WILL TRIGGER AN OVERVOLTAGE CONDITION. 08170-024 RZ = Refer to Figure 15 in the Typical Performance Characteristics section, which illustrates the delay time as a function of the timer capacitor value. A minimum capacitor value of 10 pF is required. The chosen timer capacitor must have a leakage current that is less than the 1.3 µA TIMER pin charging current. To bypass the timeout period, connect the TIMER pin to VCC. Figure 21. VHx Positive Voltage Monitoring Timing Diagram VLx MONITOR TIMING UV/OV TIMING CHARACTERISTICS VLx UV is an active low output. It is asserted when any of the four monitored voltages is below its associated threshold. When the voltage on the VCC pin is above 2 V, an internal timer holds UV low for an adjustable period, tUOTO, after the voltage on all the monitoring rails rises above their thresholds. This allows time for all monitored power supplies to stabilize after powerup. Similarly, any monitored voltage that falls below its threshold initiates a timer reset, and the timer starts again when all the monitoring rails rise above their thresholds. VUOT tUOD OV tUOTO 1V VLx MONITOR TIMING (TIMER PIN TIED TO VCC) The UV and OV outputs are held asserted after all faults have cleared for an adjustable timeout period, determined by the value of the external capacitor attached to the TIMER pin. VLx VUOT tUOD tUOD TIMER CAPACITOR SELECTION OV 1V WHEN AN INPUT IS CONFIGURED TO MONITOR A NEGATIVE VOLTAGE, VLx WILL TRIGGER AN UNDERVOLTAGE CONDITION. Figure 22. VLx Positive Voltage Monitoring Timing Diagram C TIMER = (t UOTO )(115)(10 −9 ) F/sec Rev. 0 | Page 11 of 16 08170-025 The UV and OV timeout period on the ADM2914 is programmable via the external timer capacitor, CTIMER, placed between the TIMER pin and ground. The timeout period, tUOTO, is calculated using the following equation: ADM2914 UV AND OV RISE AND FALL TIMES UNDERVOLTAGE LOCKOUT (UVLO) The UV and OV output rise times (from 10% to 90%) can be approximated using the following formula: The ADM2914 has an undervoltage lockout circuit that monitors the voltage on the VCC pin. When the voltage on VCC drops below 1.9 V (minimum), the circuit is activated. The UV output is asserted and the OV output is cleared and not allowed to assert. When VCC recovers, UV exhibits the same timing characteristics as if an undervoltage condition had occurred on the inputs. t R ≈ 2.2(R PULL −UP )(C LOAD ) where: RPULL-UP is the internal weak pull-up resistance with an approximate value of 400 kΩ at room temperature with VCC > 1 V. CLOAD is the external load capacitance on the output pin. When a fault occurs, the UV or OV output fall time can be expressed as t F ≈ 2.2(R PULL − DOWN )(C LOAD ) where RPULL-DOWN is the internal pull-down resistance, which is approximately 50 Ω. Assuming a load capacitance of 150 pF, the fall time is 16.5 ns. UV/OV OUTPUT CHARACTERISTICS Both the OV and UV outputs have a strong pull-down to ground and a weak internal pull-up to VCC. This permits the pins to behave as open-drain outputs. When the rise time on the pin is not critical, the weak pull-up removes the requirement for an external pull-up resistor. The open-drain configuration allows for wire-OR’ing of outputs, which is particularly useful when more than one signal needs to pull down on the output. At VCC = 1 V, a maximum VOL = 0.15 V at UV is guaranteed. At VCC = 1 V, the weak pull-up current on OV is almost turned on. Consequently, if the state and pull-up strength of the OV pin are important at very low VCC, an external pull-up resistor of no more than 100 kΩ is advised. By adding an external pull-up resistor, the pull-up strength on the OV pin is greater. Therefore, if it is connected in a wire-OR’ed configuration, the pull-down strength of any single device must account for this additional pull-up strength. GLITCH IMMUNITY The ADM2914 is immune to short transients that may occur on the monitored voltage rails. The device contains internal filtering circuitry that provides immunity to fast transient glitches. Figure 9 illustrates glitch immunity performance by showing the maximum transient duration without causing a reset pulse. Glitch immunity makes the ADM2914 suitable for use in noisy environments. SHUNT REGULATOR The ADM2914 is powered via the VCC pin. The VCC pin can be directly connected to a voltage rail of up to 6 V. In this mode, the supply current of the device does not exceed 100 µA. An internal shunt regulator allows the ADM2914 to operate at higher input voltage levels by placing a shunt resistor in series between the supply rail and the VCC pin to limit the input current to less than 10 mA. Use Figure 7 in the Typical Performance Characteristics section to assist in determining the value of this resistance. Choose an appropriate location on the curve to accommodate variations in VCC due to changes in current through the dropper resistor. OV LATCH (ADM2914-1) If an overvoltage condition occurs when the LATCH pin is pulled low, the OV pin latches low. Pulling LATCH high clears the latch. If an OV condition clears while LATCH is high, the latch is bypassed and the OV pin behaves in the same way as the UV pin, with an identical timeout period. If the LATCH pin is pulled low while the timeout period is active, the OV pin latches low, as in normal operation. DISABLE (ADM2914-2) Pulling the DIS pin high disables both the UV and OV outputs, and forces both outputs to remain weakly pulled high, regardless of any faults that are detected at the inputs. If a UVLO condition is detected, the UV output is asserted and pulls low; however, the timeout function is bypassed. As soon as the UVLO condition clears, the UV output pulls high. To guarantee normal operation when the pin is left unconnected, DIS has a weak 2 µA internal pull-down current. Rev. 0 | Page 12 of 16 ADM2914 TYPICAL APPLICATIONS PSU 5V1 3.3V1 2.5V1 1.8V1 1.5MΩ VCC VH1 SEL 1MΩ 10.7kΩ VL1 TIMER VH2 162kΩ SYSTEM ADM2914 111kΩ 11.7kΩ VL2 174kΩ 1.82kΩ VH3 UV VL3 OV 137kΩ VH4 3.48kΩ VL4 51.7kΩ LATCH/DIS REF GND 08170-008 27.1kΩ NOTES 11.5% SUPPLY TOLERANCE AND 5% INPUT TOLERANCE REQUIREMENT. Figure 23. Typical Application Diagram for Monitoring 5 V, 3.3 V, 2.5 V, and 1.8 V +12V1 PSU 1kΩ –5V2 1.98MΩ VH1 VCC SEL 5.62kΩ VL1 TIMER VH2 SYSTEM ADM2914 83.5kΩ VL2 1.96MΩ VH3 UV VL3 OV VH4 27.1kΩ VL4 LATCH/DIS 167kΩ GND NOTES 11.5% SUPPLY TOLERANCE AND 5% INPUT TOLERANCE REQUIREMENT. 23% SUPPLY TOLERANCE AND 15% INPUT TOLERANCE REQUIREMENT. Figure 24. Typical Application Diagram for Monitoring +12 V and −5 V Rev. 0 | Page 13 of 16 08170-009 REF ADM2914 PSU +48V1 +16V1 –3.3V2 –48V 3 11.5MΩ VCC VH1 8.45kΩ SEL 681kΩ VL1 TIMER VH2 117kΩ 1.43kΩ SYSTEM ADM2914 1.5MΩ VL2 21.3kΩ 26.1kΩ VH3 UV VL3 OV 2.87MΩ VH4 187kΩ 5.56kΩ VL4 LATCH/DIS 27.1kΩ REF GND Figure 25. Typical Application Diagram for Monitoring +48 V, +16 V, −3.3 V, and −48 V Rev. 0 | Page 14 of 16 08170-010 NOTES 11.5% SUPPLY TOLERANCE AND 10% INPUT TOLERANCE REQUIREMENT. 22% SUPPLY TOLERANCE AND 15% INPUT TOLERANCE REQUIREMENT. 34% SUPPLY TOLERANCE AND 15% INPUT TOLERANCE REQUIREMENT. ADM2914 OUTLINE DIMENSIONS 0.197 (5.00) 0.193 (4.90) 0.189 (4.80) 16 9 1 8 0.244 (6.20) 0.236 (5.99) 0.228 (5.79) 0.010 (0.25) 0.006 (0.15) 0.069 (1.75) 0.053 (1.35) 0.065 (1.65) 0.049 (1.25) 0.010 (0.25) 0.004 (0.10) COPLANARITY 0.004 (0.10) 0.158 (4.01) 0.154 (3.91) 0.150 (3.81) 0.025 (0.64) BSC SEATING PLANE 0.012 (0.30) 0.008 (0.20) 8° 0° 0.050 (1.27) 0.016 (0.41) 0.020 (0.51) 0.010 (0.25) 0.041 (1.04) REF 012808-A COMPLIANT TO JEDEC STANDARDS MO-137-AB CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 26. 16-Lead Shrink Small Outline Package [QSOP] (RQ-16) Dimensions shown in inches and (millimeters) ORDERING GUIDE Model ADM2914-1ARQZ1 ADM2914-1ARQZ-RL71 ADM2914-2ARQZ1 ADM2914-2ARQZ-RL71 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 16-Lead Shrink Small Outline Package [QSOP] 16-Lead Shrink Small Outline Package [QSOP] 16-Lead Shrink Small Outline Package [QSOP] 16-Lead Shrink Small Outline Package [QSOP] Z = RoHS Compliant Part. Rev. 0 | Page 15 of 16 Package Option RQ-16 RQ-16 RQ-16 RQ-16 ADM2914 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08170-5/09(0) Rev. 0 | Page 16 of 16