ROHM BD9007F

Single-chip Type with built-in FET Switching Regulator Series
Flexible Step-down
Switching Regulators
with Built-in Power MOSFET
BD9006F, BD9006HFP, BD9007F, BD9007HFP
No.09027EAT35
●Overview
The high-accuracy frequency flexible step-down switching regulator is a switching regulator with built-in POWER MOS FET,
which withstands high pressure. The operational frequency is freely configurable with external resistance. It features a wide
input voltage range (7V~35V) and a high frequency accuracy of ±5% (BD9006F, BD9006HFP; f=200~500kHz), Furthermore,
an external synchronization input pin enables synchronous operation with external clock.
●Features
1) Minimal external components
2) Wide input voltage range: 7V～35V
3) Frequency voltage accuracy: ±5%(BD9006F,BD9006HFP ; f=200～500kHz)
±20%(BD9007F, BD9007HFP)
4) Built-in P-ch POWER MOS FET
5) Output voltage setting enabled with external resistor: 0.8V～VIN
6) Reference voltage accuracy: 0.8V±2%
7) Wide operating temperature range: -40℃～+105℃
8) Low dropout: 100% ON duty cycle
9) Standby mode supply current: 0µA (Typ.)
10) Oscillation frequency variable with external resistor: 50～500kHz
11) External synchronization enabled
12) Soft start function: soft start time fixed to 5ms (Typ.)
13) Built-in overcurrent protection circuit
14) Built-in thermal shutdown protection circuit
15) High-power HRP7 package mounted (BD9006HFP,BD9007HFP)
16) Compact SOP8 package mounted (BD9006F,BD9007F)
●Applications
All fields of industrial equipment, such as Flat TV, printer, DVD, car audio, car navigation,
and communication such as ETC, AV, and OA.
●Product lineup
Item
Output Current
Input Range
Oscillation Frequency Range
BD9006F,BD9006HFP
BD9007F,BD9007HFP
2A
2A
7V～35V
7V～35V
50～500kHz
50～500kHz
Oscillation Frequency Accuracy
±5%
±20%
External Synchronous Function
Provided
Provided
Standby Function
Operating Temperature
Package
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© 2009 ROHM Co., Ltd. All rights reserved.
Provided
Provided
-40℃～+105℃
-40℃～+105℃
SOP8/HRP7
SOP8/HRP7
1/17
2009.05 - Rev.A
Technical Note
BD9006F, BD9006HFP, BD9007F, BD9007HFP
●Absolute Maximum Ratings (Ta=25oC)
Parameter
Symbol
Limits
Unit
Power Supply Voltage
VIN
36
V
Output Switch Pin Voltage
VSW
VIN
V
Output Switch Current
ISW
*1
A
EN/SYNC Pin Voltage
VEN/SYNC
VIN
VRT,VFB,VINV
7
RT, FB, INV Pin Voltage
Power Dissipation
HRP7
SOP8
Pd
2
V
5.5 *2
0.69
W
*3
W
Operating Temperature Range
Topr
-40～+105
℃
Storage Temperature Range
Tstg
-55～+150
℃
Tjmax
150
℃
BD9006F,BD9006HFP
BD9007F,BD9007HFP
Unit
7～35
7～35
V
Output Switch Current
～2
～2
A
Output Voltage (min pulse width)
250
250
ns
Oscillation Frequency
50～500
50～500
kHz
Oscillation Frequency set Resistance
27～360
27～360
kΩ
BD9006F,BD9006HFP
BD9007F,BD9007HFP
Unit
5～35
5～35
V
Maximum Junction Temperature
*1
*2
*3
Should not exceed Pd-value.
Reduce by 44mW/℃ over 25℃,when mounted on 2-layerPCB of 70×70×1.6mm3
(PCB incorporates thermal via. Copper foil area on the reverse side of PCB: 10.5×10.5mm2
Copper foil area on the reverse side of PCB: 70×70mm2
Reduce by 5.52mW/℃ over 25℃,when mounted on 2-layer PCB of 70×70×1.6mm3
●Recommended Operating Range
Parameter
Operating Power Supply Voltage
●Possible Operating Range
Parameter
Operating Power Supply Voltage
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© 2009 ROHM Co., Ltd. All rights reserved.
2/17
2009.05 - Rev.A
Technical Note
BD9006F, BD9006HFP, BD9007F, BD9007HFP
●Electrical Characteristics
◎BD9006F,BD9006HFP (Unless otherwise specified, Ta=25℃, VIN=13.2V, VEN/SYNC=5V)
Parameter
Symbol
Spec Values
Unit
Conditions
Min.
Typ.
Max.
ISTB
-
0
10
µA
VEN/SYNC=0V
IQ
-
4
6.5
mA
IO=0A,RT=51kΩ,VINV=0.7V
RON
-
0.3
0.6
Ω
Operating Output Current
Of Overcurrent Protection
IOLIMIT
2
4
-
A
Output Leak Current
IOLEAK
-
0
30
µA
VIN=35V, VEN/SYNC=0V
Reference Voltage 1
VREF1
0.784
0.800
0.816
V
VFB=VINV
Reference Voltage 2
VREF2
0.780
0.800
0.820
V
VIN=10～16V,VFB=VINV
Reference Voltage Input Regulation
∆VREF
-
0.5
-
%
IB
-1
-
-
µA
VINV=0.6V
Maximum FB Voltage
VFBH
2.2
2.4
-
V
VINV=0V
Minimum FB Voltage
VFBL
-
0.5
0.6
V
VINV=2V
IFBSINK
-0.47
-1.16
-2.45
mA
VFB=1V,VINV=1V
IFBSOURCE
1
5
15
mA
VFB=1V,VINV=0.6V
TSS
3
5
9
mS
Ta=-40～105℃
FOSC
285
300
315
kHz
RT=51kΩ
∆FOSC
-
0.5
-
%
Output ON Voltage
VENON
2.6
-
-
V
Output OFF Voltage
VENOFF
-
-
0.8
V
Sink Current
IEN/SYNC
-
35
90
µA
FSYNC
495
500
505
kHz
Standby Circuit Current
Circuit Current
【SW Block】
POWER MOS FET ON Resistance
ISW=50mA
【Error Amp Block】
Input Bias Current
FB Sink Current
FB Source Current
Soft Start Time
【Oscillator Block】
Oscillation Frequency
Frequency Input Regulation
VIN=10～16V
【Enable/Sync Input Block】
External Sync Frequency
VEN/SYNC Sweep Up,
Ta=-40～105℃
VEN/SYNC Sweep Down,
Ta=-40～105℃
RT=51kΩ,
EN/SYNC=500kHz,Duty 50%
*Not designed to be radiation resistant.
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© 2009 ROHM Co., Ltd. All rights reserved.
3/17
2009.05 - Rev.A
Technical Note
BD9006F, BD9006HFP, BD9007F, BD9007HFP
●Electrical Characteristics
◎BD9007F,BD9007HFP (Unless otherwise specified, Ta=25℃, VIN=13.2V, VEN/SYNC=5V)
Parameter
Symbol
Spec Values
Unit
Conditions
Min.
Typ.
Max.
ISTB
-
0
10
µA
VEN/SYNC=0V
IQ
-
4
6.5
mA
IO=0A,RT=51kΩ,VINV=0.7V
RON
-
0.3
0.6
Ω
Operating Output Current
Of Overcurrent Protection
IOLIMIT
2
4
-
A
Output Leak Current
IOLEAK
-
0
30
µA
VIN=35V, VEN/SYNC=0V
Reference Voltage 1
VREF1
0.784
0.800
0.816
V
VFB=VINV
Reference Voltage 2
VREF2
0.780
0.800
0.820
V
VIN=10～16V,VFB=VINV
Reference Voltage Input Regulation
∆VREF
-
0.5
-
%
IB
-1
-
-
µA
VINV=0.6V
Maximum FB Voltage
VFBH
2.2
2.4
-
V
VINV=0V
Minimum FB Voltage
VFBL
-
0.5
0.6
V
VINV=2V
IFBSINK
-0.47
-1.16
-2.45
mA
VFB=1V,VINV=1V
IFBSOURCE
1
5
15
mA
VFB=1V,VINV=0.6V
TSS
3
5
9
mS
Ta=-40～105℃
FOSC
240
300
360
kHz
RT=51kΩ
∆FOSC
-
0.5
-
%
Output ON Voltage
VENON
2.6
-
-
V
Output OFF Voltage
VENOFF
-
-
0.8
V
Sink Current
IEN/SYNC
-
35
90
µA
FSYNC
495
500
505
kHz
Standby Circuit Current
Circuit Current
【SW Block】
POWER MOS FET ON Resistance
ISW=50mA
【Error Amp Block】
Input Bias Current
FB Sink Current
FB Source Current
Soft Start Time
【Oscillator Block】
Oscillation Frequency
Frequency Input Regulation
VIN=10～16V
【Enable/Sync Input Block】
External Sync Frequency
VEN/SYNC Sweep Up,
Ta=-40～105℃
VEN/SYNC Sweep Down,
Ta=-40～105℃
RT=51kΩ,
EN/SYNC=500kHz,Duty 50%
*Not designed to be radiation resistant.
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© 2009 ROHM Co., Ltd. All rights reserved.
4/17
2009.05 - Rev.A
Technical Note
BD9006F, BD9006HFP, BD9007F, BD9007HFP
●Reference Data
105
0.812
0.808
0.804
0.800
0.796
0.792
0.788
52.0
51.5
51.0
50.5
50.0
RT=330kΩ
49.5
49.0
48.5
48.0
-25
0
25
50
75
102
101
100
OSCILATING FREQUENCY:fosc[kHz]
312
309
RT=51kΩ
300
297
294
291
288
-25
0
25
50
75
100 125
-25
0
25
50
75
10
9
515
8
510
RT=30kΩ
500
495
490
485
480
0
25
50
75
5
4
3
2
1
0
0
5
10
15
20
25
30
35
3
Inflection Point
From Top: VEN=7V (Ta=105℃)
VEN=6.8V (Ta=25℃)
VEN=6.4V(Ta=-40℃)
1.2
1.0
0.8
0.6
0.4
1.2
10
15
20
25
30
35
0.0
40
CONVERSION EFFICIENCY [%]
FET ON RESISTANCE:RON[Ω]
From Top: Ta=105℃
Ta=25℃
Ta=-40℃
0.8
0.6
0.4
0.2
0.0
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
OUTPUT CURRENT:Io[A]
OUTPUT CURRENT:Io[A]
Fig.10 ON Resistance VIN=13.2V
(All series)
Fig.11 ON Resistance VIN=35V
(All series)
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5/17
1.0
1.5
2.0
Fig.9 ON Resistance VIN=7V
(All series)
1.2
1.0
0.5
OUTPUT CURRENT:Io[A]
90
0.5
40
0.0
5
1.4
0.0
35
0.2
100
0.0
30
0.4
1.4
0.2
25
0.6
1.6
0.4
20
0.8
1.6
0.6
15
From Top: Ta=105℃
Ta=25℃
Ta=-40℃
1.0
Fig.8 EN/SYNC Input Current
(All series)
From Top: Ta=105℃
Ta=25℃
Ta=-40℃
10
1.4
INPUT VOLTAGE:VEN/SYNC[V]
1.2
5
Fig.6 Standby Current (All series)
0.2
0
Fig.7 Circuit Current
(All series)
0.8
Ta=25℃,-
2
1.6
1.4
INPUT VOLTAGE: VIN[V]
1.0
Ta=105℃
4
INPUT VOLTAGE:VIN[V]
0.0
40
125
5
0
FET ON RESISTANCE:RON[Ω]
EN/SYNC INPUT CURRENT:[mA]
6
100
6
100 125
1.6
Ta=105℃
上から
From
Top: Ta=105℃
Ta=25℃
Ta=25℃
Ta=-40℃
Ta=-40℃
75
0
-25
Fig.5 Frequency vs. Ambient
temperature (All series)
8
50
7
AMBIENT TEMPERATURE:Ta[℃]
Fig.4 Frequency vs. Ambient
temperature (All series)
25
1
-50
100 125
0
Fig.3 Frequency vs. Ambient
temperature (All series)
520
505
-25
AMBIENT TEMPERATURE:Ta[℃]
525
AMBIENT TEMPERATURE:Ta[℃]
7
96
-50
475
285
-50
97
Fig.2 Frequency vs. Ambient
temperature (All series)
315
303
98
AMBIENT TEMPERATURE:Ta[℃]
Fig.1 Output reference voltage vs. Ambient
temperature (All series)
306
RT=160kΩ
99
95
-50
100 125
AMBIENT TEMPERATURE:Ta[℃]
OSCILATING FREQUENCY:fosc[kHz]
103
STAND-BY CURRENT:ISTB [μA]
-50
CIRCUIT CURRENT: ICC[mA]
104
47.5
0.784
FET ON RESISTANCE:RON[Ω]
OSCILATING FREQUENCY:fosc[kHz
52.5
OSCILATING FREQUENCY:fosc[kHz]
REFERENCE VOLTAGE:VREF[V]
0.816
80
70
60
50
5.0V
出力
From上から
Top: 5.0V
output
3.3V
output
3.3V
出力
2.5V output
2.5V出力
1.5V output
40
30
1.5V出力
20
10
0
0.0
0.5
1.0
VIN=13.2V
f=100kHz
Ta=25℃
1.5
2.0
OUTPUT CURRENT:Io[A]
Fig.12 Efficiency f=100kHz
(All series)
2009.05 - Rev.A
Technical Note
BD9006F, BD9006HFP, BD9007F, BD9007HFP
90
80
70
60
50
From Top: 5.0V output
3.3V output
2.5V output
1.5V output
40
30
VIN=13.2V
f=300kHz
Ta=25℃
20
10
0
10
80
70
60
50
From Top: 5.0V output
3.3V output
2.5V output
1.5V output
40
30
VIN=13.2V
f=500kHz
Ta=25℃
20
10
0
0.0
0.5
1.0
1.5
2.0
Fig.13 Efficiency f=300kHz
(All series)
6
4
0.5
1.0
1.5
0
2.0
5
4
3
2
Vo=5V
f=300kHz
Ta=25℃
1
0
INPUT VOLTAGE VIN [V]
INPUT VOLTAGE VIN [V]
6
1
0.5
1.0
1.5
2.0
0.5
1.0
1.5
2.0
OUTPUT CURRENT:Io[A]
Fig.16 The lowest voltage of
possible operation (All series)
Fig.17 The lowest voltage of
possible operation (All series)
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4
3
2
Vo=5V
f=300kHz
Ta=105℃
0
0.0
OUTPUT CURRENT:Io[A]
© 2009 ROHM Co., Ltd. All rights reserved.
5
5
1
0
0.0
4
Fig.15 Over-current Protection
Operation Current (All series)
7
Vo=5V
f=300kHz
Ta=-40℃
3
Fig.14 Efficiency f=500kHz
(All series)
6
2
2
OUTPUT CURRENT:Io[A]
7
3
1
OUTPUT CURRENT:Io[A]
6
4
VIN=13.2V
f=300kHz
Vo=5V
2
7
5
From Left: Ta=105℃
Ta=-40℃
Ta=25℃
8
0
0.0
OUTPUT CURRENT:Io[A]
INPUT VOLTAGE VIN [V]
OUTPUT VPLTAGE:Vo [V]
CONVERSION EFFICIENCY [%]
100
90
CONVERSION EFFICIENCY [%]
100
6/17
0.0
0.5
1.0
1.5
2.0
OUTPUT CURRENT:Io[A]
Fig.18 The lowest voltage of
possible operation (All series)
2009.05 - Rev.A
Technical Note
BD9006F, BD9006HFP, BD9007F, BD9007HFP
●Block Diagrams / Application circuit / PIN assignment
(BD9006F,BD9007F)
(BD9006HFP,BD9007HFP)
PVIN
１
VIN
VIN
220μF
５
８
+
+
220μF
VREG
2μF
１
EN/SYNC
７
Vref
2μF
Internal
Bias
Internal
Bias
SOFT
START
SYNC
SYNC
SOFT
START
5V
+
INV
ERROR AMP
４
COMPARATOR
+
+
-
CURRENT LIMIT
Slope
INV
SDWN
DRV
SDWN
２
SW
33μH
UVLO/
TSD
DRIVER
SW
SDWN
２
33μH
UVLO/
TSD
330μF
OSC
GND
FB
４
47kΩ
３
６
VIN FB INV EN/SYNC
SW GND RT
FB
GND
６
RT
51 KΩ
51 KΩ
15 KΩ
15 KΩ
Fig.19
Pin name
1
PVIN
2
47 KΩ
３
RT
No.
Vo
+
30 KΩ
７
PVIN
DRV
Set
330μF
OSC
INV
FB
SDWN
Reset
+
Slope
+
30 KΩ
SW
-
0.8V
22000pF
Vo
CURRENT LIMIT
COMPARATOR
+
+
DRIVER
Set
-
PWM
ERROR AMP
５
Reset
+
0.8V
22000pF
GND EN/SYNC
VIN RT
5V
+
-
PWM
EN/SYNC
Fig.20
No.
Pin name
Power system power supply input
1
VIN
Power supply input
SW
Output
2
SW
Output
3
FB
Error Amp output
3
FB
Error Amp output
4
INV
Output voltage feedback
4
GND
Ground
5
INV
Output voltage feedback
Frequency setting resistor connection
6
RT
Frequency setting resistor connection
Ground
7
5
Function
EN/SYNC Enable/Synchronizing pulse input
6
RT
7
GND
8
VIN
Power supply input
FIN
Function
EN/SYNC Enable/Synchronizing pulse input
-
Ground
*VIN and PVIN must be shorted before use
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7/17
2009.05 - Rev.A
BD9006F, BD9006HFP, BD9007F, BD9007HFP
Technical Note
●Description of operations
・ERROR AMP
The ERROR AMP block is an error amplifier used to input the reference voltage (0.8V Typ.) and the INV pin voltage. The
output FB pin controls the switching duty and output voltage Vo. These INV and FB pins are externally mounted to
facilitate phase compensation. Inserting a capacitor and resistor between these pins enables adjustment of phase margin.
(Refer to recommended examples on pages 11~13.)
・SOFT START
The SOFT START block provides a function to prevent the overshoot of the output voltage Vo through gradually
increasing the normal rotation input of the error amplifier when power supply turns ON to gradually increase the switching
Duty. The soft start time is set to 5msec (Typ.).
・SYNC
By making the “EN/SYNC” terminal less than 0.8V, the circuit can be shut down.
Furthermore, by applying pulse with higher frequency than the configured oscillation frequency to the “EN/SYNC”
terminal, external sync is possible. (Sync possible with double the configured frequency-configured frequency or 500kHz)
・OSC(Oscillator)
This circuit generates the pulse wave to be input to the slope, and by connecting resistance to “RT”, 50~500kHz
oscillating frequency can be configured. (Refer to p.11 Fig.24)
・slope
This block generates saw tooth waves from the clock generated by the OSC. The generated saw tooth waves are sent
to PWM COMPARATOR.
・PWM COMPARATOR
The PWM COMPARATOR block is a comparator to make comparison between the FB pin and internal saw tooth wave
and output a switching pulse
The switching pulse duty varies with the FB value. (min Duty width : 250ns.)
・TSD (Thermal Shut Down)
In order to prevent thermal destruction/thermal runaway of the IC, the TSD block will turn OFF the output when the chip
temperature reaches approximately 150℃ or more. When the chip temperature falls to a specified level, the output will be
reset. However, since the TSD is designed to protect the IC, the chip junction temperature should be provided with the
thermal shutdown detection temperature of less than approximately.150℃.
・CURRENT LIMIT
While the output POWER P-ch MOS FET is ON, if the voltage between drain and source (ON resistance×load current)
exceeds the reference voltage internally set with the IC, this block will turn OFF the output to latch. The overcurrent
protection detection values have been set as shown below:
BD9006F,BD9006HFP, BD9007F,BD9007HFP ・・・ 4A (Typ.)
Furthermore, since this overcurrent protection is an automatically reset, after the output is turned OFF and latched, the
latch will be reset with the RESET signal output by each oscillation frequency.
However, this protection circuit is only effective in preventing destruction from sudden accident. It does not support for the
continuous operation of the protection circuit (e.g. if a load, which significantly exceeds the output current capacitance, is
normally connected). Furthermore, since the overcurrent protection detection value has negative temperature
characteristics, consider thermal design.
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8/17
2009.05 - Rev.A
Technical Note
BD9006F, BD9006HFP, BD9007F, BD9007HFP
●Timing Chart
(All series)
・Basic Operation
VIN
Internal
slope
FB
SW
VEN/SYNC
Fig.21
●External synchronizing function
In order to activate the external synchronizing function, connect the frequency setting resistor to the RT pin and then input a
synchronizing signal to the EN/SYNC pin. As the synchronizing signal, input a pulse wave higher than a frequency
determined with the setting resistor (RT).
However, the external sync frequency should be configured at less than double the configured frequency.
(ex.) When the configured frequency is 100kHz, the external sync frequency should be less than 200kHz.
Furthermore, the pulse wave’s LOW voltage should be under 0.8V and the HIGH voltage over 2.6V (when the HIGH voltage
is over 6V the EN/SYNC input current increases [see p.4 Fig.8]), the through rate of stand-up (and stand-down) under
20V/μS.
BD9006HFP
1
2
3
4
5
6
7
VIN
VIN=13.2V
220μF
VI N
SW
FB
GND
INV
RT
EN/SY NC
C28
C IN
2μF
SW
33μH
L1
REG
C2
open
GND
C3
RT
open
51kΩ
D1
R1
47kΩ
GND
R3
30kΩ
C0
330μF
Ven/sync=0～5V
f=450kHz
SR=20V/μs
Duty=50%
C1
22000pF
R2
15kΩ
GND
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© 2009 ROHM Co., Ltd. All rights reserved.
Fig.22 External Sync Sample Circuit
(Vo=3.3V, Io=1A, f=300kHz, EN/SYNC=450kHz)
9/17
2009.05 - Rev.A
Technical Note
BD9006F, BD9006HFP, BD9007F, BD9007HFP
●Description of external components
L1
VIN
VIN
＋
C28
Vo
SW
CIN
D1
＋
Co
R1
RT
INV
RT
R2
FB
EN/SYNC
GND
R3
C1
Fig.23
Design Procedure
Sample Calculations
Vo=Output voltage, VIN (Max.)=Maximum input voltage
Io (Max.)=Maximum load current, f=Oscillation frequency
When Vo=3.3V, VIN (Typ.)=13.2V
Io(Max.)=1A and f=300kHz
1. Setting or output voltage
Output voltage can be obtained by the formula shown below:
When VO=3.3V and R2=15kΩ
Vo=0.8×(1+R1/R2)
Use the formula to select the R1 and R2.
Furthermore, set the R2 to 30kΩ or less.
Select the current passing through the R1 and R2 to be small
enough for the output current.
3.3=0.8×(1+R1/15kΩ)
R1=46.875kΩ≒47kΩ
R1=47kΩ
2. Selection of coil (L1)
When VIN=13.2V, Vo=3.3V, Io=1A and f=300kHz,
The value of the coil can be obtained by the formula shown
L1=(13.2-3.3)×3.3/{13.2×300k×(1×0.3)}
below:
=27.5µH≒33µH
L1=(VIN-Vo)×Vo / (VIN×f×∆Io)
∆Io: Output ripple current
∆Io should typically be approximately 20 to 30% of Io.
If this coil is not set to the optimum value, normal (continuous)
L1=33µH
Oscillation may not be achieved. Furthermore, set the value of
the coil with an adequate margin so that the peak current
passing through the coil will not exceed the rated current of the
coil.
3. Selection of output capacitor (Co)
VIN=13.2V, Vo=3.3V, L=33µH, f=300kHz
The output capacitor can be determined according to the
∆IL=(13.2-3.3)×3.3/(33×10-6×300×103×13.2)
output ripple voltage ∆Vo(p-p) required. Obtain the required
=0.25
ESR value by the formula shown below and then select the
∆IL=0.25A
capacitance.
∆IL=(VIN-Vo)×Vo/(L×f×VIN)
∆Vpp=∆IL×ESR+(∆IL×Vo)/(2×Co×f×VIN)
Set the rating of the capacitor with an adequate margin to the
output voltage. Also, set the maximum allowable ripple current
with an adequate margin to ∆IL. Furthermore, the output rise
time should be shorter than the soft start time. Select the
output capacitor having a value smaller than that obtained by
the formula shown below.
CMAX =
3.0m×(ILIMIT-Io(Max))
Vo
ILIMIT：2A (BD9006F,BD9006HFP, BD9007F,BD9007HFP)
If this capacitances is not optimum, faulty startup may result.
When ILIMIT: 2A, Io(Max)=1A, Vo=3.3V
CMAX =3.0m×(2-1)/3.3
≒910µ
CMAX=910µF
(※3.0m is soft start time(min).)
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10/17
2009.05 - Rev.A
Technical Note
BD9006F, BD9006HFP, BD9007F, BD9007HFP
Design Method
Sample Calculations
4. Selection of diode (D1)
Set diode rating with an adequate margin to the
maximum load current. Also, make setting of the rated
inverse voltage with an adequate margin to the
maximum input voltage.
A diode with a low forward voltage and short reverse
recovery time will provide high efficiency.
5. Selection of input capacitor (CIN, C28)
Two capacitors, ceramic capacitor CIN and bypass
capacitor C28 should be inserted between the VIN and
GND. Be sure to insert a ceramic capacitor of 2 to 10µF
for the CIN. The capacitor C28 should have a low ESR
and a significantly large ripple current. The ripple
current IRMS can be obtained by the following formula:
IRMS=Io×√
When VIN(max.)=35V
Io=(max.)2A
Diode ratings must include:
Current over 2A
Withstand minimum 35V
When VIN=13.2V, Vo=3.3V and Io=1A:
2
IRMS=1×√ 3.3×(13.2-3.3)/(13.2)
IRMS=0.433A
Vo×(VIN-Vo)/VIN2
Select capacitors that can accept this ripple current.
If the capacitance of CIN and C28 is not optimum, the IC
may malfunction.
6. Setting of oscillating frequenPcy
Referring Fig.24 on the following page, select R for the
oscillating frequency to be used.
7. Setting of phase compensation (R3 and C1)
The phase margin can be set through inserting a capacitor
or a capacitor and resistor between the INV pin and the
FB pin. Each set value varies with the output coil,
capacitance, I/O voltage, and load. Therefore, set the
phase compensation to the optimum value according to
these conditions. (For details, refer to Application circuit on
page.11～)
If this setting is not optimum, output oscillation may
result.
When f=300kHz
From p.11 Fig.24, a resistance of RT=51kΩ is selected.
RT=51kΩ
※Please contact us if there are any questions regarding phase
compensation configuration.
The set values listed above are all reference values. On the actual mounting of the IC, the characteristics may vary with the routing of wirings
and the types of parts in use. In the connection, it is recommended to thoroughly verify these values on the actual system prior to use.
※
●Directions for pattern layout of PCB
GND
①
R3
RT
C3
EN
③
⑧
C1
SIGNAL GND
②
C28
RT
INV
GND
FB
SW
VIN
BD9006HFP
L1
CIN
⑧
D1
POWER
GND
L
O
A
D
R1
R2
C2
④
① Arrange the wirings shown by heavy lines as short as possible in
a broad pattern.
② Locate the input ceramic capacitor CIN as close to the VIN-GND
pin as possible.
③ Locate the RT as close to the GND pin as possible.
④ Locate the R1 and R2 as close to the INV pin as possible, and
provide the shortest wiring from the R1 and R2 to the INV pin.
⑤ Locate the R1 and R2 as far away from the L1 as possible.
⑥ Separate POWER GND (Schottky diode, I/O capacitor’s GND)
and SIGNAL GND (RT, GND), so that SW noise doesn’t have an
effect on SIGNAL GND at all.
⑦ Design the POWER wire line as wide and short as possible.
⑧ Additional pattern for C2 and C3 expand compensation flexibility.
⑤
⑥
Fig.24
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© 2009 ROHM Co., Ltd. All rights reserved.
11/17
2009.05 - Rev.A
Technical Note
BD9006F, BD9006HFP, BD9007F, BD9007HFP
D1
R4
L1
C2
R2
RT
C2
R1
R3
R4
Co
C3
D1
C1
C1
C3
R3
L1
C28
CIN
RT
C28
CIN
R2
R1
Co
Fig.25 BD9006F Reference Layout Pattern
Fig.26 BD9006HFP Reference Layout Pattern
※As shown above ,design the GND pattern as large as possible within inner layer.
※Gray zones indicate GND.
RT[kΩ]
27
30
33
36
39
43
47
51
56
62
68
75
82
91
500
OSCILATION FREQUENCY:fosc[kHz]
450
400
350
300
250
200
150
100
50
0
100
200
OSCILATING FREQUENCY SETTEING
RESISTANCE:RT[kΩ]
Fig.27 RT Resistance Values vs.
Oscillating Frequency
300
fosc[kHz]
537
489
449
415
386
353
324
300
275
250
229
209
192
174
RT[kΩ]
100
110
120
130
150
160
180
200
220
240
270
300
330
360
fosc[kHz]
160
146
134
124
108
102
91
82
75
69
61
55
50
46
※ The values in the graph for oscillating frequency are Typical values, and variance of±5%
forBD9006F/HFP and ±20% for BD9007F/HFP should be considered.
●Phase Compensation setting procedure
1． Application stability conditions
The following section describes the stability conditions of the negative feedback system.
Since the DC/DC converter application is sampled according to the switching frequency, GBW (frequency at 0-dB gain) of
the overall system should be set to 1/10 or less of the switching frequency. The following section summarizes the
targeted characteristics of this application.
・At a 1 (0-dB) gain, the phase delay is 150˚ or less (i.e. the phase margin is 30˚ or more).
・The GBW for this occasion is 1/10 or less of the switching frequency.
Responsiveness is determined with restrictions on the GBW. To improve responsiveness, higher switching frequency
should be provided.
Replace a secondary phase delay (-180˚) with a secondary phase lead by inserting two-phase leads, to ensure the
stability through the phase compensation. Furthermore, the GBW (i.e., frequency at 0-dB gain) is determined according
to phase compensation capacitance provided for the error amplifier. Consequently, in order to reduce the GBW, increase
the capacitance value.
(1) Typical integrator (low pass filter)
Feedback
R
FB
A
(2) Open loop characteristics of integrator
Gain
[dB]
A
-20dB/decade
GBW(b)
0
0
Phase
[ °] 90
C
(a)
-180
Point (a) fa=
[Hz]
f
-90°
位相マージン
Phase
margin
1
2πRCA
Point (b) fb=GBW=
-180°
f
1
[Hz]
2πRC
Since the error amplifier is provided with (1) or (2) phase compensation, the low pass filter is applied. In the case of the
DC/DC converter application, the R becomes a parallel resistance of the feedback resistance.
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© 2009 ROHM Co., Ltd. All rights reserved.
12/17
2009.05 - Rev.A
Technical Note
BD9006F, BD9006HFP, BD9007F, BD9007HFP
2． For output capacitors having high ESR, such as electrolyte capacitor
For output capacitors that have high ESR (i.e., several Ω), the phase compensation setting procedure becomes
comparatively simple. Since the DC/DC converter application has a LC resonant circuit attached to the output, a -180˚
phase-delay occurs in that area. If ESR component is present, however a +90˚ phase-lead occurs to shift the phase
delay to -90˚. Since the phase delay should be set within 150˚, it is a very effective method but tends to increase the
ripple component of the output voltage.
(1) LC resonant circuit
(2) With ESR provided
Vcc
Vcc
L
C
Vo
＋
RESR
C
1
2π√LC
fr =
L
Vo
1
[Hz]: Resonance
2π√LC
1
fESR =
[Hz]: Phase lead
2πRESRC
fr =
[Hz]
At this resonance point, a-180˚
phase-delay occurs.
A -90˚ phase-delay occurs.
According to changes in phase characteristics, due to the ESR, only one phase lead should be inserted.
For this phase lead, select either of the methods shows below:
(3) Insert Feedback Resistance in the C.
(4) Insert the R3 in integrator.
Vo
Vo
C1
R3
C2
INV
R2
Phase lead fz =
C2
R1
R1
A
1
2πC1R1
INV
FB
R2
Phase lead fz =
[Hz]
FB
A
1
2πC2R3
[Hz]
To cancel the LC resonance, the frequency to insert the phase lead should be set close to the LC resonant frequency.
The setting above have is estimated. Consequently, the setting may be adjusted on the actual system. Furthermore, since
these characteristics vary with the layout of PCB loading conditions, precise calculations should be made on the actual system.
3．For output capacitors having low ESR, such as low impedance electrolyte capacitor or OS-CON
In order to use capacitors with low ESR (i.e., several tens of mΩ), two phase-leads should be inserted so that a -180˚phasedelay, due to LC resonance, will be compensated. The following section shows a typical phase compensation procedure.
(1) Phase compensation with secondary phase lead
Vo
R1
C1
INV
R3
Phase lead：fz1
=
1
2πR1C1
[Hz]
Phase lead：fz2
=
1
2πR3C2
[Hz]
=
1
2π√LC
[Hz]
C2
A
FB
LC resonant：fr
R2
frequency
To set phase lead frequency, insert both of the phase leads close to the LC resonant frequency. According to empirical
rule, setting the phase lead frequency fZ2 with R3 and C2 lower than the LC resonant frequency fr, and the phase lead
frequency fZ1 with the R1 and C1 higher than the LC resonant frequency fr, will provide stable application conditions.
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© 2009 ROHM Co., Ltd. All rights reserved.
13/17
2009.05 - Rev.A
Technical Note
BD9006F, BD9006HFP, BD9007F, BD9007HFP
VO
DC/DC converter
controller
+
+
①
②
RL
②
Vm
Maximum load
Load
0
①
0
Inadequate phase margin
Output
voltage
Adequate phase margin
t
<Reference>
Measurement of open loop of the DC/DC converter
To measure the open loop of the DC/DC converter, use the gain phase
analyzer or FRA to measure the frequency characteristics.
<Procedure>
1. Check to ensure output causes no oscillation at the maximum
load inclosed loop.
2. Isolate ① and ② and insert Vm
(with amplitude of approximately.100mVpp).
3. Measure (probe) the oscillation of ① to that of ②.
Furthermore, the phase margin can also be measured with the load
responsiveness. Measure variations in the output voltage when
instantaneously changing the load from no load to the maximum load. Even
though ringing phenomenon is caused, due to low phase margin, no ringing
takes place. Phase margin is provided. However, no specific phase margin
can be probed.
※Please contact us if you have any questions regarding phase compensation.
●Heat Loss
For thermal design, be sure to operate the IC within the following conditions.
(Since the temperatures described hereunder are all guaranteed temperature, take margin into account.)
1. The ambient temperature Ta is to be 105℃ or less.
2. The chip junction temperature Tj is to be 150℃ or less.
The chip junction temperature Tj can be considered in the following two patterns:
To obtain Tj from the IC surface temperature TC in actual use state, Tj=Ta+θj－a×W
< Reference value > θj－c :HRP7
7℃/W
SOP8 32.5℃/W
To obtain Tj from the ambient temperature Ta in actual use state,Tj=TC+θj－c×W
< Reference. value >
θj－a :
HRP7 89.3℃/W Single piece of IC
2
54.3℃/W 2-layer PCB (Copper foil area on the front side of PCB: 15×15mm )
2
22.7℃/W 2-layer PCB (Copper foil area on the front side of PCB: 70×70mm )
3
PCB size: 70×70×1.6mm (PCB incorporates thermal via.)
Copper foil area on the front side of PCB: 10.5×10.5mm2
θj－a :
SOP8 222.2℃/W Single piece of IC
181.8℃/W 1-layer PCB
PCB size: 70×70×1.6mm3
The heat loss W of the IC can be obtained by the formula shown below:
Vo
2
+ VIN × Icc + Tr × VIN × Io × f
W = Ron × Io ×
VIN
Ron: ON resistance of IC (refer to page.4)
Io: Load current
Vo: Output voltage
VIN: Input voltage ICC: Circuit current (refer to page.3)
Tr: Switching rise/fall time (approximately 20nsec)
f: Oscillation frequency
Tr
1
VIN
2
① Ron × Io
SW wave from
②2×
1
2
× Tr ×
1
T
× VIN × Io
=Tr × VIN × Io× f
GND
2
T=
1
f
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© 2009 ROHM Co., Ltd. All rights reserved.
14/17
2009.05 - Rev.A
Technical Note
BD9006F, BD9006HFP, BD9007F, BD9007HFP
RT
SW
VIN
INV
Internal Power
Internal Power
VIN
VIN
VIN
SW
RT
INV
167kΩ
EN/SYNC
FB
Internal Power
VIN
EN/
SYNC
1kΩ
60kΩ
222
kΩ
221
kΩ
145
kΩ
139
kΩ
Internal Power
VIN
20Ω
FB
1kΩ
1kΩ
Fig.28 Equivalent circuit
●Notes for use
1. Absolute maximum ratings
If excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break
down the devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. If any over rated
values will expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as fuses.
2. GND potential
Ground-GND potential should maintain at the minimum ground voltage level. Furthermore, no terminals should be lower
than the GND potential voltage including electric transients.
3. Thermal design
Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.
4. Inter-pin shorts and mounting errors
When attaching to the set substrate, pay special attention to the direction and proper placement of the IC. If the IC is attached
incorrectly, it may be destroyed.
Furthermore, when using the IC with VIN and EN/SYNC terminals shorted, and the 5-pin (SOP8 package) or 7-pin (HRP7
package) EN/SYNC terminal and 6-pin RT terminal are shorted, the IC may also be damaged when VIN>7V.
5. Operation in strong electromagnetic field
Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to
malfunction.
6. Inspection with set printed circuit board
When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress.
Always discharge capacitors after each process or step. Always turn the IC’s power supply off before connecting it to, or
removing it from a jig or fixture, during the inspection process. Ground the IC during assembly steps as an antistatic
measure. Use similar precaution when transporting and storing the IC.
7. IC pin input (Fig. 26)
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements to keep them isolated. P-N
junctions are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic, creating
a parasitic diode or transistor. For example, the relation between each potential is as follows:
・When GND>pin A and GND>pin B, the P-N junction operates as a parasitic diode.
・When pin B >GND>pin A, the P-N junction operates as a parasitic transistor. Parasitic diodes can occur inevitably in
the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits, operational
faults, or physical damage. Accordingly, methods by which parasitic diodes operate, such as applying a voltage that is
lower than the GND (P substrate) voltage to an input pin, should not be used.
Resistor
Transistor (NPN)
(Terminal A)
(Terminal A)
Parasitic Element
(Terminal B)
(Terminal B)
P Substrate
Parasitic Element
P Substrate
Parasitic Element
Parasitic Element
Fig.29 Typical simple construction of monolithic IC
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15/17
2009.05 - Rev.A
Technical Note
BD9006F, BD9006HFP, BD9007F, BD9007HFP
8. GND wiring pattern
It is recommended to separate the large-current GND pattern from the small-signal GND pattern and establish a single
ground at the reference point of the set PCB, so that resistance to the wiring pattern and voltage fluctuations due to a
large current will cause on fluctuations in voltages of the small-signal GND. Prevent fluctuations in the GND wiring pattern
of external parts.
9. Temperature protection (thermal shut down) circuit
This IC has a built-in temperature protection circuit to prevent the thermal destruction of the IC. As described above, be
sure to use this IC within the power dissipation range. Should a condition exceeding the power dissipation range continue,
the chip temperature Tj will rise to activate the temperature protection circuit, thus turning OFF the output power element.
Then, when the tip temperature Tj falls, the circuit will be automatically reset. Furthermore, if the temperature protection
circuit is activated under the condition exceeding the absolute maximum ratings, do not attempt to use the temperature
protection circuit for set design.
10. On the application shown below, if there is a mode in which VIN and each pin potential are inverted, for example, if the
VIN is short-circuited to the Ground with external diode charged, internal circuits may be damaged. To avoid damage, it is
recommended to insert a backflow prevention diode in the series with VIN or a bypass diode between each pin and VIN.
Bypass diode
Backflow prevention diode
Vcc
Pin
Fig.30
●Thermal reduction characteristics
HRP7
SOP8
0.8
9
8
POWER DISSIPATION：PD [W]
POWER DISSIPATION：PD [W]
10
④7.3W
7
6
③5.5W
5
4
3
②2.3W
2
1
0
①1.4W
25
50
75
100
125
0.6
②
①
0.5
0.4
0.3
0.2
0.1
0
150
AMBIENT TEMPERATURE：Ta [℃]
25
50
75
100
125
150
AMBIENT TEMPERATURE：Ta [℃]
① Single piece of IC
3
PCB Size: 70×70×1.6mm (PCB incorporates thermal via)
Copper foil area on the front side of PCB: 10.5×10.5mm2
② 2-layer PCB (Copper foil area on the reverse side of PCB: 15×15mm2)
③ 2-layer PCB (Copper foil area on the reverse side of PCB: 70×70mm2)
④ 4-layer PCB (Copper foil area on the reverse side of PCB: 70×70mm2)
Fig.31
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© 2009 ROHM Co., Ltd. All rights reserved.
0.7
16/17
① Single piece of IC
② When mounted on ROHM standard PCB
(Glass epoxy PCB of 70mm×70mm×1.6mm)
Fig.32
2009.05 - Rev.A
Technical Note
BD9006F, BD9006HFP, BD9007F, BD9007HFP
●Ordering part number
B
D
9
Part No.
0
0
6
Part No.
9006, 9007
H
F
P
-
Package
F
: SOP8
HFP
: HRP7
T
R
Packaging and forming specification
E2: Embossed tape and reel
(SOP8)
TR: Embossed tape and reel
(HRP7)
SOP8
<Tape and Reel information>
5.0±0.2
(MAX 5.35 include BURR)
6
+6°
4° −4°
5
4.4±0.2
6.2±0.3
1 2
3
0.9±0.15
7
0.3MIN
8
Tape
Embossed carrier tape
Quantity
2500pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
4
0.595
1.5±0.1
+0.1
0.17 -0.05
0.11
S
1.27
0.42±0.1
Direction of feed
1pin
Reel
(Unit : mm)
∗ Order quantity needs to be multiple of the minimum quantity.
HRP7
<Tape and Reel information>
1.017±0.2
9.395±0.125
(MAX 9.745 include BURR)
8.82±0.1
1.905±0.1
Tape
Embossed carrier tape
Quantity
2000pcs
0.08±0.05
0.8875
Direction
of feed
TR
The direction is the 1pin of product is at the upper right when you hold
( reel on the left hand and you pull out the tape on the right hand
)
1pin
+5.5°
4.5° −4.5°
+0.1
0.27 -0.05
0.73±0.1
1.27
10.54±0.13
0.835±0.2
1 2 3 4 5 6 7
1.523±0.15
(7.49)
8.0±0.13
(5.59)
0.08 S
S
Direction of feed
(Unit : mm)
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© 2009 ROHM Co., Ltd. All rights reserved.
Reel
17/17
∗ Order quantity needs to be multiple of the minimum quantity.
2009.05 - Rev.A
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.
The Products specified in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard
against the possibility of physical injury, fire or any other damage caused in the event of the
failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM
shall bear no responsibility whatsoever for your use of any Product outside of the prescribed
scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or
system which requires an extremely high level of reliability the failure or malfunction of which
may result in a direct threat to human life or create a risk of human injury (such as a medical
instrument, transportation equipment, aerospace machinery, nuclear-reactor controller,
fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of
any of the Products for the above special purposes. If a Product is intended to be used for any
such special purpose, please contact a ROHM sales representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may
be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to
obtain a license or permit under the Law.
Thank you for your accessing to ROHM product informations.
More detail product informations and catalogs are available, please contact us.
ROHM Customer Support System
http://www.rohm.com/contact/
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R0039A