Freescale Semiconductor, Inc. ¨ Freescale Semiconductor, Inc... MICROPROCESSORS THE MOTOROLA GATEWAY BOARD (MCF5202 Microprocessor To MC68EC000 Bus Interface Card) Jeff Miller October 15, 1997 1.0 Introduction The integrated Gateway circuit board will bridge an existing MC68EC000 system to the new ColdFire¨ MCF5202 VL-RISC microprocessor, to evaluate the possibility of moving toward a higher performance architecture. It can be used to evaluate system enhancements such as on-chip instruction and/or data cache and bursting to external memory. It can also be used to port software code to the ColdFire architecture directly in a customerÕs system as opposed to the traditional method of porting code to an evaluation platform. This paper describes the use and operation of the Gateway board as well as technical information that can be used as a reference design. 2.0 Gateway Board Overview 2.1 Software Considerations The principal use of this board is to help port system software code from the M68000 architecture to the ColdFire architecture. Users will have to recompile the system software to target the MCF5202 instead of targeting the M68000. Even though the system will see a hardware interface that looks like a MC68EC000, the software must consist of ColdFire instructions for the MCF5202 to work properly. Refer to Section 8, ÒPorting from M68K Architecture,Ó of the MCF5202 UserÕs Manual for an overview of the issues encountered when upgrading from the M68000 to the ColdFire microprocessor. In addition, youÕll have to keep three key things in mind while porting system software code from the MC68EC000 system to the MCF5202 system 1. 2. 3. mapping 32-bit MCF5202 addresses to 24-bit 68EC000 addresses cache coherency RMW cycles MOTOROLA GATEWAY BOARD For More Information On This Product, Go to: www.freescale.com 1 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. 2.1.1 Mapping 32-bit MCF5202 addresses to 24-bit 68EC000 addresses The Gateway board transfers only the lower 24-bits of the address from the MCF5202 to the MC68EC000. This should make no difference in porting the system software (because a 24-bit addressing scheme can still be used, with the upper 8-bits as a ÒdonÕt-careÒ) except when the on-chip cache is to be used. The MCF5202 allows speciÞc regions of address space to be assigned access control attributes via the Access Control Registers (ACR0 and ACR1). Also, within the MCF5202Õs Cache Control Register (CACR), the default cache mode can be set up for regions that are not mapped by the ACRs. Refer to the ÒCacheÓ section of the ColdFire MCF5202 UserÕs Manual for more details. The MCF5202 ACRs use address bits 31-24 to determine the region of space to which the corresponding access control attributes are assigned. Because the original M68000 system used only addresses 23-0, this at Þrst glance may seem to cause a problem when considering caching certain areas of memory that are smaller than 16Mbytes. However, virtual-to-physical memory mapping can be used to map unique regions in the 24-bit address space to unique 16Mbyte regions in the 32-bit address space, such that certain areas of the physical memory map can take advantage of the MCF5202 caching schemes. One example of implementing this would be to simply concatenate A[31:24] = $01 in front of the Þrst 24-bit address region, and control the caching scheme for this region using ACR0. Then concatenate A[31:24] = $02 in front of the second 24-bit address region, which will have a separate caching scheme, and control the caching scheme for this region with ACR1. Finally, concatenate A[31:24] = $03 in front of the third 24-bit address region, which could have yet another caching scheme, and control the caching scheme for this region using the default cache mode in the CACR register. This example memory map translation is shown in Table 1. Table 1: Example Memory Map Translation 68000 MEMORY MAP A[23:0] CONTENTS CACHE CONTROL Instructions ACR0 $000000 5202 MEMORY MAP A[31:0] $01000000 $1FFFFF $011FFFFF $200000 $02200000 Data ACR1 $3FFFFF $023FFFFF $400000 $03400000 I/O CACR $FFFFFF $03FFFFFF For this example, ACR0 can be set up such that everything within the region $01xxxxxx, which includes $01000000 - $011FFFFF containing instructions, can have a speciÞc cache attribute such as copyback. ACR1 can be set up such that everything within the region $02xxxxxx, which includes $02200000 - $023FFFFF containing data, can have another speciÞc cache attribute such as writethrough. The CACR can be set up such that everything not mapped by the ACRs, which includes $03400000 - $03FFFFFF containing I/O, can have a third cache attribute such as cache inhibit. Now, when the software code is compiled, the new MCF5202 memory map that is speciÞc to the customerÕs system must be used when assigning the corresponding instruction, data, and I/O sections. 2.1.2 Cache Coherency If the MCF5202 has its cache on and in copyback mode, and if there is another bus master in the system that can arbitrate the system bus away from the MCF5202 and modify a shared piece of memory, users should be careful about maintaining cache coherency. Cache coherency is the term used to describe the act of keeping the on-chip cache consistent (or coherent) with external memory, if other masters will be using the same memory. Refer to the ÒCache CoherencyÓ section of the ColdFire MCF5202 UserÕs Manual. If cache coherency is required, then the simplest way to resolve this problem is to control the shared memory region with one of the ACRs and set this ACRÕs 2 GATEWAY BOARD For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. cache mode to cache-inhibit. This will require the microprocessor to go to external memory to get accurate data as opposed to having a cache hit within internal memory which could possibly contain stale data. 2.1.3 RMW cycles If the TAS instruction is used in the original M68000 code for implementing the locked or read-modify-write transfer sequence in hardware, then new code will have to be written that essentially implements the same locked transfer in software. This can be done by raising the interrupt mask to 7 and then executing the read, modify, and write instructions, and then lowering the mask back down to the appropriate level. This will ensure that the sequence of instructions between the raising and lowering of the mask will execute uninterrupted, except for a level 7 interrupt which is nonmaskable. Freescale Semiconductor, Inc... 2.2 Hardware Considerations The target system must have a female 68-pin PLCC socket such that it could hold a 68EC000 PLCC FN package not a 68EC000 QFP FU package. The Gateway board has a male connector arranged in a PLCC FN fashion that will sit in this socket. The Gateway board can operate in 8- or 16-bit data mode. The board can handle interrupt acknowledge cycles for external vector number acquisition or the AVEC* signal can be used to allow internal vector generation. One difference between the MCF5202 and the 68EC000 is that DA*[1:0] is always asserted whether AVEC* is asserted or not. Also, the interrupt level being acknowledged is driven onto A/D[4:2] by the MCF5202, which has to be routed onto address lines A[3:1] for the 68EC000. See Figure 3 for more details. The board also has control logic to handle bus arbitration for alternate bus masters. If the HALT signal is asserted, the processor will stop bus activity at the completion of the current bus cycle and will place all control signals in the inactive state and place all three-state lines in the high-impedance state. 3.0 Performance The Gateway board performance will be Þrst discussed generally and then speciÞcally with an industry-standard benchmark. For each bus cycle, there is one extra clock required from the beginning of the ColdFire MCF5202 microprocessor bus cycle to the beginning of the 68EC000 bus cycle. This is due to the multiplexed ATM signal on the ColdFire which is required to create the FC signals on the 68EC000 bus. Also, there are some bus clocks inherent to the ColdFire cycle that occur after the 68EC000 bus cycle is done. This is zero to two extra clocks, depending on the size of the access and whether the access is a read or a write. Therefore, because the fastest possible bus transaction for the 68EC000 is 4 bus clocks, the fastest Gateway board bus transaction can be as few as 5 bus clocks for the Þrst bus access of a longword write, or as many as 7 bus clocks if doing, for example, a single byte read. Table 2 and Table 3,compare all possible combinations of accesses between the MCF5202 and the MC68EC000. MOTOROLA GATEWAY BOARD For More Information On This Product, Go to: www.freescale.com 3 Freescale Semiconductor, Inc. Table 2: Bus Clock Timing Comparison (16-bit mode) Freescale Semiconductor, Inc... MCF5202 DATA ACCESS READ/ WRITE GATEWAY BOARD BUS CLOCKS EQUIVALENT MC68EC000 BUS CLOCKS TO GET SAME DATA Byte, Word Long Read 7 6+7=13 4 4+4=8 Byte, Word Long Write 7 5+7=12 4 4+4=8 Line Fill (4 Longs) Read 6+6+6+6+6+6+6+7=49 4+4+4+4+4+4+4+4=32 Line Fill (4 Longs) Write 5+5+5+5+5+5+5+7=42 4+4+4+4+4+4+4+4=32 Table 3: Bus Clock Timing Comparison (8-bit mode) MCF5202 DATA ACCESS READ/ WRITE Byte GATEWAY BOARD BUS CLOCKS EQUIVALENT MC68EC000 BUS CLOCKS TO GET SAME DATA 7 4 6+7=13 4+4=8 Long 6+6+6+7=25 4+4+4+4=16 Byte 7 4 5+7=12 4+4=8 5+5+5+7=22 4+4+4+4=16 Word Word Read Write Long Line Fill (4 Longs) Read 6+6+6+6+6+6+6+6+ 6+6+6+6+6+6+6+7=97 4+4+4+4+4+4+4+4+ 4+4+4+4+4+4+4+4=64 Line Fill (4 Longs Write 5+5+5+5+5+5+5+5+ 5+5+5+5+5+5+5+7=82 4+4+4+4+4+4+4+4+ 4+4+4+4+4+4+4+4=64 The industry standard Dhrystone 2.1 benchmark was run on the Motorola Gateway board, as well as some other systems, and the results are shown in Table 4. If you notice in Table 4, the Gateway board requires about a 7.5MHz increase in frequency (12.5MHz to 20MHz) to get about the same MIPS performance of the 68EC000 evaluation board. This is attributable to the handshaking required between the MCF5202 and the 68EC000. Notice, however, if the internal cache of the MCF5202 is used, the MIPS performance of the system is increased dramaticallyÑmore than 8 times better than with cache off. In addition, if system bus interface changes are made to take advantage of the MCF5202 bus interface, such as widening the data bus and allowing bursting (which will be discussed later), even greater system performance will result. 4 GATEWAY BOARD For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Table 4: Dhrystone 2.1 Benchmark Performance DATA WIDTH MC68EC000 Board 16 bit 12.5 MHz 8-8-8-8-8-8-8-8 N/A 1.01 Gateway Board 8 bit 20 MHz R: 10-10-10-11-10-10-10-1110-10-10-11-10-10-10-11 W: 9- 9- 9-11- 9- 9- 9-119- 9- 9-11- 9- 9- 9-11 Off 0.56 Gateway Board 16 bit 20 MHz R: 10-11-10-11-10-11-10-11 W: 9-11- 9-11- 9-11- 9-11 Off 1.07 Gateway Board 8 bit 20 MHz R: 10-10-10-10-10-10-10-1010-10-10-10-10-10-10-11 W: 9- 9- 9- 9- 9- 9- 9- 99- 9- 9- 9- 9- 9- 9-11 Copy-Back 5.95 Gateway Board 16 bit 20 MHz R: 10-10-10-10-10-10-10-11 W: 9- 9- 9- 9- 9- 9- 9-11 Copy-Back 9.12 MCF5202 Board 32 bit 20 MHz 8-4-4-4 Copy-Back 12.6 FREQUENCY DRAM ACCESSES (TO GET 16 BYTES) CACHE MODE MIPS (@ GIVEN FREQUENCY) SYSTEM 4.0 Potential Performance and System Improvements To fully take advantage of the MCF5202 performance in a target system, the 68EC000 bus could be changed to interface better to the MCF5202 bus. First, the maximum frequency of operation for the Gateway boardÕs MCF5202 is 33MHz, which can be a substantial improvement over the 12.5MHz, 16.7MHz, or even the 20MHz version of the 68EC000. So, if the 68EC000 system was designed to operate at higher frequencies, this would be an easy way to increase overall system performance. Second, the 16-bit 68EC000 data bus could be widened to 32-bits so that the MCF5202 can get a longword in one bus transaction instead of the two bus transactions that are required now through the Gateway board. Three, when the MCF5202 does a burst access (gives one address, expects 4 longwords of data), if the 68EC000 system could be changed to provide the secondary 3 longwords faster than the full bus transaction required by the current 68EC000 system, the overall MCF5202 performance can be improved dramatically. For example, if the data bus was widened to 32-bits and page mode DRAM was used in the system, the MCF5202 could potentially do a cache line Þll (4 longwords) in 7 bus clocks (4-1-1-1) instead of 49 bus clocks (6-6-6-6-6-6-6-7). The MCF5202 was chosen for the Gateway board because of its on-chip 2KB uniÞed cache that allows customers to experiment among various on-chip memory conÞgurations. For example, the 2KB uniÞed cache can be conÞgured to be 2KB of I-cache only, 2KB of D-cache only, 1KB of I-cache and 1KB of D-cache, or as a normal 2KB uniÞed cache with a dynamic mixture of both instructions and data. Other ColdFire microprocessors can be selected according to speciÞc system requirements. For example, the MCF5204, which would not require latches and buffers because it has a demultiplexed address and data bus (just like the 68EC000) has a little less on-chip memory (512 byte I-cache and 512 byte SRAM) compared to the MCF5202. Therefore, using the MCF5204 would most likely give a little less performance, but would save overall system cost. 5.0 Debug Support There is a ColdFire BDM connector (labeled J2) on the Gateway board that is a 26-pin Berg Connector arranged in two rows of thirteen pins each. This connector is commonly used by software debugger vendors to allow such features as real-time trace, real-time debug, and background debug. MOTOROLA GATEWAY BOARD For More Information On This Product, Go to: www.freescale.com 5 Freescale Semiconductor, Inc. 6.0 Bus Operation The Gateway board supports a synchronous interface between the MCF5202 bus and the MC68EC000 bus. The waveforms in this document are meant to provide a functional description of the bus cycles required for data transfer operations. The examples below show a longword read and write to a 16-bit wide data bus of the MC68EC000 as well as an Interrupt Acknowledge Cycle. Note that at all times the MCF5202 will not burst (TBI*=0) and that the address phase lasts for only one clock (AA*=0). Figure 1: Longword Read To A 16-Bit Port PS1 Freescale Semiconductor, Inc... w PS1 w PS2 S0 PS3 S2 PS4 S4 PS5 S6 PS1 w PS1 w PS2 S0 PS3 S2 PS4 S4 PS5 S6 PS1 w PS1 w PS1 w CLOCK TS* R/W* TT[1:0] 00 ATM SIZ[1:0] 00 AD[31:16] ADDR AD[15:0] ADDR DA*[1:0] 10 READ D[31:16] ADDR READ D[15:0] ADDR 01 01 FC[2:0] A[23:0] AS* UDS LDS DTACK* D[15:8] READ D[31:24] READ D[15:8] D[7:0] READ D[23:16] READ D[7:0] 6 GATEWAY BOARD For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Figure 2: Longword Write To A 16-Bit Port PS1 w PS1 w PS2 S0 PS3 S2 PS4 S4 PS5 S6 PS1 w PS2 S0 PS3 S2 PS4 S4 PS5 S6 PS1 w PS1 w PS1 w CLOCK TS* R/W* TT[1:0] 00 Freescale Semiconductor, Inc... ATM SIZ[1:0] 00 AD[31:16] ADDR AD[15:0] ADDR 10 WRITE D[31:16] ADDR WRITE D[15:0] ADDR DA*[1:0] 01 01 FC[2:0] A[23:0] AS* UDS LDS DTACK* D[15:8] WRITE D[31:24] WRITE D[15:8] D[7:0] WRITE D[23:16] WRITE D[7:0] MOTOROLA GATEWAY BOARD For More Information On This Product, Go to: www.freescale.com 7 Freescale Semiconductor, Inc. Figure 3: Interrupt-Acknowledge Operation PS1 w PS1 w PS2 S0 PS3 S2 PS4 S4 PS5 S6 PS1 w PS1 w PS1 w PS2 S0 PS3 S2 PS4 S4 PS5 S6 PS1 w PS1 w PS1 w CLOCK TS* R/W* TT[1:0] 11 Freescale Semiconductor, Inc... ATM SIZ[1:0] 01 01 AD[31:24] VECTOR AD[23:5] AD[4:2] IPL LEVEL IPL LEVEL AD[1:0] 01 or 10 DA*[1:0] 01 or 10 AVEC* IPL*[2:0] FC[2:0] A[23:4] A[3:1] IPL LEVEL IPL LEVEL A0 AS* UDS LDS DTACK* D[15:8] D[7:0] VECTOR IACK CYCLE (VECTOR NUMBER ACQUISITION) 8 IACK CYCLE (AUTOVECTORED) GATEWAY BOARD For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 7.0 PLD State Diagram Figure 4: SimpliÞed PLD State Diagram TS Reset Freescale Semiconductor, Inc... TS BR68K BR68K Grant to 68EC000 Bus Master BDCF BR68K No Grant TS Wait for beginning of ColdFire cycle Grant to ColdFire No Grant TS Assert other control signals BR68K Data Acknowledge to the MCF5202 Begin a 68EC000 cycle DTACK BDCF Wait for Acknowledge from 68EC000 DTACK 8.0 PLD ABEL Code MODULE TITLE gateway 'The controlling signals between a 5202 and a 68EC000' gateway device 'ispLSI'; pLSI pLSI pLSI pLSI property property property property 'PART ispLSI1016-80LT44'; 'IGNORE_FIXED_PIN OFF'; 'PULLUP ON'; 'Y1_AS_RESET ON'; pLSI property 'LOCK AVEC pLSI property 'LOCK HALT pLSI property 'LOCK PCLK "pLSI property 'LOCK SDI pLSI property 'LOCK TT1 pLSI property 'LOCK TT0 pLSI property 'LOCK ATM pLSI property 'LOCK BR68K "pLSI property 'LOCK SDO pLSI property 'LOCK SIZ1 pLSI property 'LOCK BDCF "pLSI property 'LOCK SCLK "pLSI property 'LOCK RSTI MOTOROLA 1'; 2'; 5'; 8'; 9'; 10'; 11'; 15'; 18'; 19'; 21'; 27'; 29'; GATEWAY BOARD For More Information On This Product, Go to: www.freescale.com 9 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. "pLSI property 'LOCK ISPMODE pLSI property 'LOCK AD0 pLSI property 'LOCK MODE pLSI property 'LOCK SIZ0 pLSI property 'LOCK RnW pLSI property 'LOCK DTACK pLSI property 'LOCK TS pLSI property 'LOCK AENORM pLSI property 'LOCK AEIACK pLSI property 'LOCK FC2 pLSI property 'LOCK FC1 pLSI property 'LOCK FC0 pLSI property 'LOCK BG68K pLSI property 'LOCK BGCF pLSI property 'LOCK LDAT pLSI property 'LOCK OEBA8 pLSI property 'LOCK OEAB8 pLSI property 'LOCK OEBA16 pLSI property 'LOCK OEAB16 pLSI property 'LOCK UDS pLSI property 'LOCK LDS pLSI property 'LOCK ADLT pLSI property 'LOCK AS pLSI property 'LOCK DA1 pLSI property 'LOCK DA0 pLSI property 'LOCK AEUP 30'; 38'; 40'; 41'; 42'; 43'; 44'; 3'; 4'; 12'; 13'; 14'; 16'; 20'; 22'; 23'; 24'; 25'; 26'; 31'; 32'; 33'; 34'; 35'; 36'; 37'; "-----------------------------------------------------------------------------------------DECLARATIONS "Inputs - All Positive Logic !AVEC pin 1 istype 'input'; !HALT pin 2 istype 'input'; PCLK pin 5 istype 'input'; " pin 8 istype 'input'; TT1 pin 9 istype 'input'; TT0 pin 10 istype 'input'; ATM pin 11 istype 'input'; !BR68K pin 15 istype 'input'; " pin 18 istype 'input'; SIZ1 pin 19 istype 'input'; !BDCF pin 21 istype 'input'; " pin 27 istype 'input'; !RSTI pin istype 'input'; " pin 30 istype 'input'; AD0 pin 38 istype 'input'; MODE pin 40 istype 'input'; SIZ0 pin 41 istype 'input'; RnW pin 42 istype 'input'; !DTACK pin 43 istype 'input'; !TS pin 44 istype 'input'; "Outputs !AENORM !AEIACK FC2 FC1 FC0 10 All pin pin pin pin pin Positive Logic 3 istype 'output'; 4 istype 'output'; 12 istype 'output'; 13 istype 'output'; 14 istype 'output'; "nAVEC "nHALT "CLK from motherboard to uP SDI - only used for in-circuit programming of PLD "nBR68K SDO - only used for in-circuit programming of PLD "nBDCF SCLK - only used for in-circuit programming of PLD "pin 29 - nRSTI - RESET pin ISPMODE - only used for in-circuit programming of PLD "AD0 (unlatched) "Dedicated IN3 - 0=8-bit, 1=16-bit "nDTACK "nTS "Addr Enable for NORM Op - AENORM=0=HIZ, AENORM=1=output "Addr Enable for IACK Op - AEIACK=0=HIZ, AEIACK=1=output GATEWAY BOARD For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... !BG68K !BGCF LDAT !OEBA8 !OEAB8 !OEBA16 !OEAB16 !UDS !LDS !ADLT !AS !DA1 !DA0 !AEUP pin pin pin pin pin pin pin pin pin pin pin pin pin pin 16 20 22 23 24 25 26 31 32 33 34 35 36 37 istype istype istype istype istype istype istype istype istype istype istype istype istype istype 'output'; 'output'; 'output'; 'output'; 'output'; 'output'; 'output'; 'output'; 'output'; 'output'; 'output'; 'output'; 'output'; 'output'; "nBG68K "nBGCF "(!nLE16_8) - 0=transparent latches, L-2-H=latches data "nOEBA8 =0=HIZ, 1=output from B (TDAT) to A (AD) enabled "nOEAB8 =0=HIZ, 1=output from A (AD) to B (TDAT) enabled "nOEBA16=0=HIZ, 1=output from B (TDAT) to A (AD) enabled "nOEAB16=0=HIZ, 1=output from A (AD) to B (TDAT) enabled "nUDS "nLDS "Addr Latch - 0=transparent latches, L-2-H=latches data "nAS "nDA1 "nDA0 "Addr Enable for A[23:8] - AEUP=0=HIZ, AEUP=1=output "----------------------------------------------------------------------------------------"Internal Nodes PQ0,PQ1,PQ2 A0 ATMA NQ1 NQ2 NCLK BQ0,BQ1 node istype node istype node istype node istype node istype node; node istype "Constants c,k,x,z = .C.,.K.,.X.,.Z.; 'reg, buffer'; 'reg,buffer'; 'reg,buffer'; 'reg'; 'reg'; 'reg,buffer'; "this is used for test vectors "State Value Constants psreg PS0 PS1 PS2 PS3 PS4 PS5 = = = = = = = PSTATE0 PSTATE1 PSTATE2 PSTATE3 PSTATE4 PSTATE5 bsreg BS0 BS1 BS2 BS3 [PQ2,PQ1,PQ0]; [0,0,0]; [0,0,1]; [0,1,1]; [0,1,0]; [1,1,0]; [1,0,0]; = = = = = = = = = = = "Positive Clk State Register "!PQ2&!PQ1&!PQ0 "!PQ2&!PQ1&PQ0 Ò!PQ2&PQ1&PQ0 "!PQ2&PQ1&!PQ0 "PQ2&PQ1&!PQ0 "PQ2&!PQ1&!PQ0 !PQ2&!PQ1&!PQ0; !PQ2&!PQ1&PQ0; !PQ2&PQ1&PQ0; !PQ2&PQ1&!PQ0; PQ2&PQ1&!PQ0; PQ2&!PQ1&!PQ0; [BQ1,BQ0]; [0,0]; [0,1]; [1,1]; [1,0]; "BusArb State Register Equations "Initializations psreg.clk = PCLK; psreg.ar = RSTI; A0.clk = TS; MOTOROLA "AD0 is latched when TS is asserted GATEWAY BOARD For More Information On This Product, Go to: www.freescale.com 11 Freescale Semiconductor, Inc. ATMA.clk = TS; "ATM is latched when TS is asserted NQ1.ar = RSTI; NQ2.ar = RSTI; NQ1.clk= PCLK; NQ2.clk= !PCLK; bsreg.clk = PCLK; bsreg.ar = RSTI; "Clock NegClk machine 1 with pos clk "Clock NegClk machine 2 with the inverted pos clk Freescale Semiconductor, Inc... "Output enables AS.oe UDS.oe LDS.oe FC0.oe FC1.oe FC2.oe = = = = = = !BG68K; !BG68K; !BG68K; !BG68K; !BG68K; !BG68K; Òenable Òenable "enable "enable "enable "enable when when when when when when the the the the the the 68K 68K 68K 68K 68K 68K is is is is is is not not not not not not granted granted granted granted granted granted the the the the the the bus bus bus bus bus bus "Sequential Logic A0 := AD0; ATMA := ATM; NQ1 := !NQ1; NQ2 := NQ1; "----------------------------------------------------------------------------------------"Combinational Logic NCLK = NQ1 !$ NQ2; - (See NOTE 2) "XNOR the outputs of the two NegClk state machines to produce NCLK " AS is asserted for PS3, PS4, and the posclk of PS5 AS = PSTATE3 # PSTATE4 # PSTATE5&!NCLK; " OEBA16 = " OEBA8 = OEBA16 = (CF is master & not halted & during AS)&(16-bit read & !IACK) (!BG68K & !HALT & AS) & ( RnW&MODE & !(TT1 & TT0) ); OEBA8 = (CF is master & not halted & during AS)&(8-bit read # IACK) (!BG68K & !HALT & AS) & ( RnW&!MODE # TT1&TT0 ); " OEAB16 = " OEAB8 = OEAB16 = (CF is master & not halted & during AS)&(16-bit write) (!BG68K & !HALT & AS) & ( !RnW&MODE ); OEAB8 = (CF is master & not halted & during AS)&(8-bit write (!BG68K & !HALT & AS) & ( !RnW&!MODE ); " UDS = (Read&PS3 # PS4 UDS = (RnW&PSTATE3 # PSTATE4 # " LDS = (Read&PS3 # PS4 LDS = (RnW&PSTATE3 # PSTATE4 # # PCLK&PS5) & (16-bit) & !( Odd & Byte ) PSTATE5&!NCLK) & MODE & !( A0 & !SIZ1&SIZ0 ); # PCLK&PS5) & !(16-bit & Even & Byte & !IACK) PSTATE5&!NCLK) & !( MODE & !A0 & !SIZ1&SIZ0 & !(TT1&TT0) ); DA1 = PSTATE5 & MODE; DA0 = PSTATE5 & !MODE; LDAT = PSTATE5 & NCLK; "PS5 & 16-bit "PS5 & !16-bit "PS5 & NCLK "ADLT = (TS&PS1 # PS2 # PS3 # PS4 # PCLK&PS5) ADLT = (TS&PSTATE1 # PSTATE2 # PSTATE3 # PSTATE4 # PSTATE5&!NCLK); AENORM = (!BG68K & !HALT) & !(TT1&TT0); AEIACK = (!BG68K & !HALT) & (TT1&TT0); AEUP = (!BG68K & !HALT); 12 "(CF is master & not halted) & !(IACK-Access) "(CF is master & not halted) & (IACK-Access) "(CF is master & not halted) GATEWAY BOARD For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. "Function Codes for EC000 - (See NOTE 1) " FC2 = ( (ATM & Normal-Access) # (IACK-Access) ) FC2 = ( ATM # (TT1&TT0) ); " FC1 = ( (ATMA & Normal-Access) # (IACK-Access) ) FC1 = ( ATMA # (TT1&TT0) ); " FC0 = ( (!ATMA & Normal-Access) # (IACK-Access) ) FC0 = ( !ATMA # (TT1&TT0) ); "----------------------------------------------------------------------------------------STATE_DIAGRAM psreg; Freescale Semiconductor, Inc... STATE PS0: "RESET and waiting for TS to de-assert IF TS THEN PS0; ELSE PS1; "Wait for TS to de-assert STATE PS1: "Waiting for TS to assert, Beginning of ColdFire cycle IF !TS THEN PS1; ELSE PS2; "Waiting for TS to assert STATE PS2: "Beginning of 68K cycle, assert FCÕs and Address IF HALT THEN PS2; ELSE PS3; ÒIf HALT is asserted then stay in state 2 "else goto state 3 STATE PS3: "Assert other control signals GOTO PS4; "Unconditionally goto state 4 STATE PS4: "Waiting for DTACK from 68K IF (TT1 & TT0 & AVEC) THEN PS5; ELSE IF (DTACK) THEN PS5; ELSE PS4; STATE PS5: GOTO PS1; "if TT[1:0]=11 (IACK and AVEC) then "goto state 5 (just DA the cycle) "else if (Normal or IACK without AVEC), look for DTACK "goto state 5 "else stay in state 4 "Data acknowledge to ColdFire "Unconditionally goto state 1 "------------------------------------------------------------------------------------------ STATE_DIAGRAM bsreg; STATE BS0: BGCF=1; BG68K=0; IF BR68K THEN BS1; ELSE BS0; MOTOROLA "Give the bus to CF, and wait for Request "Assert Grant to CF "Do not assert Grant to 68K "If there is a Bus Request, "goto state 1 "else if no request, "stay in state 0 GATEWAY BOARD For More Information On This Product, Go to: www.freescale.com 13 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. STATE BS1: BGCF=0; BG68K=0; IF !BDCF THEN BS2; ELSE BS1; "Got a Request, wait for CF to quit driving the bus "Do not assert either Grant "If CF is not driving the bus, "then goto state 2 "else if CF is driving the bus, "stay in state 1 STATE BS2: Request to go away BGCF=0; BG68K=1; IF BR68K THEN BS2; ELSE BS3; "Done driving the bus, give the bus to 68K, wait for "Do not assert Grant to CF "Assert Grant to 68K "If 68K is still requesting the bus, "then stay in state 2 "else if no longer requesting the bus, "goto state 3 STATE BS3: BGCF=0; BG68K=0; GOTO BS0; "Request went away, delay one clock, then bus back to CF "Do not assert either Grant "goto state 0 "------------------------------------------------------------------------------------------"NOTE 1: " " " " " " " " " ATMa ATMd TT1 TT0 FC2 FC1 FC0 Notes 0 1 0 1 X X X 0 0 1 1 X X X 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 0 1 1 0 ? 1 0 1 0 1 0 ? 1 1 0 1 0 0 ? 1 Normal User Data Normal User Instruction Normal Supervisor Data Normal Supervisor Instruction Reserved Emulator Access CPU Space or IACK "NOTE 2: "RnW " " " " " " " " " " " " 1 1 1 1 1 1 0 0 0 0 0 MODE 1 1 1 1 1 0 1 1 1 1 0 A0 (!SIZ1& SIZ0) 0 0 0 1 1 x 0 0 1 1 x 1 1 0 1 0 x 1 0 1 0 x AENORM 1 0 x x x x x x x x x AEIACK 0 1 x x x x x x x x x UDS 1 1 1 0 1 0 1 1 0 1 0 LDS OExxxx Notes 0 1 1 1 1 1 0 1 1 1 1 OEBA16 OEBA8 OEBA16 OEBA16 OEBA16 OEBA8 OEAB16 OEAB16 OEAB16 OEAB16 OEAB8 Read,16-bit,even,byte,Normal Read,16-bit,even,byte,IACK Read,16-bit,even,!byte Read,16-bit,odd, byte Read,16-bit,odd,!byte (N/A) Read,8-bit Write,16-bit,even,byte Write,16-bit,even,!byte Write,16-bit,odd,byte Write,16-bit,odd,!byte (N/A) Write,8-bit END 14 GATEWAY BOARD For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 9.0 Block Diagram Figure 5: Gateway Board Block Diagram ColdFire MCF5202 PLD B D M A D A/D 10.0 Gateway Board Physical Layout Figure 6: Physical Layout (Actual Size) 60 1 3.5 in. ColdFire Gateway Board S/N 27 43 U3 25 26 J2 J2 U5 U4 U2 U1 26 J3 26 44 J1 10 ISP J1 44 J3 10 60 BDM 1 2 9 61 U6 U9 Solder Side 1 9 U8 U7 Component Side 61 Freescale Semiconductor, Inc... 68EC000 Connector (68-pin PLCC) 2 in. MOTOROLA GATEWAY BOARD For More Information On This Product, Go to: www.freescale.com 15 Freescale Semiconductor, Inc. 11.0 Gateway Board Bill Of Material Freescale Semiconductor, Inc... Table 5: Bill Of Material ITEM QTY MANUFACTURER 1 1 Motorola XCF5202PU33A U1 IC, MCF5202, 33 MHz, 100pin, TQFP 2 1 Lattice ISPLSI1016-90LT44 U2 IC, PLD, 44 pins, TQFP 3 4 Motorola MC74F573DW U3-U5, U9 IC, 74F573, 20 pins, SOL20 4 3 Motorola MC74F543DW U6-U8 IC, 74F543, 24 pins, SOL24 5 4 Venkel CR1206-8W-103JT R1-R4 Res, 10K, 5%, 1/8W, 1206 6 4 Venkel CR1206-8W-472JT R5-R8 Res, 4.7K, 5%, 1/8W, 1206 7 4 Samtec TMS-117-55-G-S J1 Conn, HDR, 17 pins, 50Mil ctr, single row, 1X17 8 1 AMP 1-103783-3 J2 Conn, HDR, 26 pins, 100Mil ctr, dual row, 2X13 9 1 AMP 1-87499-3 J3 Conn, HDR, 8 pins, 100Mil ctr, single row, 1X8 10 1 Samwa Venkel CS3216X7R103K500R C1206X7R500-103KNE C1 Cap, 0.01UF, 10%, 50V, 1206 11 1 Panasonic S1012-36-ND C2 Cap, 33UF, 10%, 16V, 1206, TANT 12 22 Samwa Venkel CS3216X7R104K500R C1206X7R500-104KNE C3-C24 Cap,0.1UF, 10%, 50V, 1206 13 1 Samwa Venkel CS3216COG100K500R C1206C0G500-100JNE C25 Cap, 10PF, 10%, 50V, 1206 16 PART NO. REF. DES. DESCRIPTION GATEWAY BOARD For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 12.0 ColdFire Gateway Board Schematics (1 of 2) 87 CLK nRST 67 RST BKPT DSI DSO DSCLK DDATA0 DDATA1 DDATA2 DDATA3 PST0 PST1 PST2 PST3 74 73 72 71 70 81 82 83 84 56 57 58 59 TCK TMS/BKPT TDI/DSI TDO/DSO TRST/DSCLK DDATA0 DDATA1 DDATA2 DDATA3 PST0 PST1 PST2 PST3 GND 85 JCE VCC GND GND 76 77 78 MTMOD0 MTMOD1 MTMOD2 VCC 75 HIZ AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 89 90 91 92 95 96 97 98 1 2 3 4 5 8 9 10 11 14 15 16 17 20 21 22 23 26 27 28 29 30 33 34 A/D0 A/D1 A/D2 A/D3 A/D4 A/D5 A/D6 A/D7 A/D8 A/D9 A/D10 A/D11 A/D12 A/D13 A/D14 A/D15 A/D16 A/D17 A/D18 A/D19 A/D20 A/D21 A/D22 A/D23 A/D24 A/D25 A/D26 A/D27 A/D28 A/D29 A/D30 A/D31 R/W TT0 TT1 SIZ0 SIZ1 ATM 39 35 36 41 42 63 RNW TT0 TT1 SIZ0 SIZ1 ATM TS AA DTIP DA0 DA1 TEA TBI 40 48 47 43 44 55 54 nTS GND BR BD BG 50 49 51 nDA0 nDA1 nTEA GND 64 65 66 nIPL0 nIPL1 nIPL2 AVEC 62 nAVEC 6 12 18 24 31 37 45 52 61 68 79 86 93 99 GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC 7 13 19 25 32 38 46 53 60 69 80 88 94 100 1 11 OE C AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 2 3 4 5 6 7 8 9 D0 D1 D2 D3 D4 D5 D6 D7 GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC GND ISPEN Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 10 PF 19 18 17 16 15 14 13 12 A16 A17 A18 A19 A20 A21 A22 A23 VCC GND 33 UF VCC GND 0.1 UF VCC GND 0.1 UF VCC U3 74F573 AEUPPER ADLT 1 11 OE C AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 2 3 4 5 6 7 8 9 D0 D1 D2 D3 D4 D5 D6 D7 nBDCF nBGCF IPL0 IPL1 IPL2 0.01UF AEUPPER ADLT GND 0.1 UF VCC GND 0.1 UF VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 19 18 17 16 15 14 13 12 A8 A9 A10 A11 A12 A13 A14 A15 GND 0.1 UF VCC GND 0.1 UF VCC GND 0.1 UF VCC GND 0.1 UF VCC 0.1 UF U5 74F573 AEIACK ADLT 1 11 AD5 AD2 AD3 AD4 AD5 AD5 AD6 AD7 2 3 4 5 6 7 8 9 VCC GND 0.1 UF OE C D0 D1 D2 D3 D4 D5 D6 D7 GND VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 19 18 17 16 15 14 13 12 A0 A1 A2 A3 A4 A5 A6 A7 GND 0.1 UF VCC GND 0.1 UF VCC GND 0.1 UF VCC GND 0.1 UF VCC AENORM ADLT OE C AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 2 3 4 5 6 7 8 9 D0 D1 D2 D3 D4 D5 D6 D7 GND 0.1 UF U4 74F573 1 11 VCC GND 0.1 UF Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 19 18 17 16 15 14 13 12 A0 A1 A2 A3 A4 A5 A6 A7 VCC GND 0.1 UF VCC GND 0.1 UF VCC GND 0.1 UF VCC GND 0.1 UF VCC 4.7K nRST VCC nBGCF 10K nTEA MOTOROLA VCC nIPL1 4.7K VCC nIPL0 10K BKPT 4.7K 4.7K nIPL2 10K VCC DSI VCC 4.7K VCC ISPEN GND 0.1 UF VCC GND 0.1 UF VCC VCC 10K VCC BYPASS FOR U1 CLK U9 74F573 BYPASS FOR U2 - U9 Freescale Semiconductor, Inc... U1 MCF5202 GND VCC GATEWAY BOARD For More Information On This Product, Go to: www.freescale.com 17 Freescale Semiconductor, Inc. ColdFire Gateway Board Schematics (2 of 2) J1 / B EC000 CONN J1 / A EC000 CONN Freescale Semiconductor, Inc... D12 D11 D10 D9 D8 D7 D6 D5 GND D4 D3 D2 D1 D0 nAS UDS LDS RNW nDTACK nBG68K nBR68K VCC VCC CLK GND GND MODE nHALT nRST 61 62 63 64 65 66 67 68 1 2 3 4 5 6 7 8 9 nAVEC nTEA nIPL2 nIPL1 nIPL0 FC2 FC1 FC0 A0 A1 A2 A3 GND A4 A5 A6 A7 A8 A9 A10 A11 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 J2 BDM CONN 1 3 5 7 9 11 13 15 17 19 21 23 25 GND GND nRST VCC GND PST2 PST0 DDATA2 DDATA0 GND VCC A12 A13 A14 A15 A16 A17 A18 A19 A20 VCC A21 A22 A23 GND D15 D14 D13 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 DSI DSO PST3 PST1 DDATA3 DDATA1 GND VCC SDO SDI ISPEN ISPMODE GND SCLK CLK nTEA 1 2 3 4 5 6 7 8 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 U6 74F543 J3 ISP CONN BKPT DSCLK 2 4 6 8 10 12 14 16 18 20 22 24 26 J1 / D EC000 CONN J1 / C EC000 CONN nOEAB16 GND nLE16_8 13 11 14 OEAB EAB LEAB AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 3 4 5 6 7 8 9 10 A0 A1 A2 A3 A4 A5 A6 A7 OEBA EBA LEBA 2 23 1 B0 B1 B2 B3 B4 B5 B6 B7 22 21 20 19 18 17 16 15 OEBA EBA LEBA 2 23 1 nOEBA16 GND nLE16_8 B0 B1 B2 B3 B4 B5 B6 B7 22 21 20 19 18 17 16 15 D8 D9 D10 D11 D12 D13 D14 D15 OEBA EBA LEBA 2 23 1 nOEBA8 GND nLE16_8 B0 B1 B2 B3 B4 B5 B6 B7 22 21 20 19 18 17 16 15 nOEBA16 GND nLE16_8 D0 D1 D2 D3 D4 D5 D6 D7 U7 74F543 U2 ISPLSI-1016 nAVEC nHALT AENORM AEIACK CLK VCC ISPEN SDI TT1 TT0 ATM FC2 FC1 FC0 nBR68K nBG68K GND SDO SIZ1 nBGCF nBDCF nLE16_8 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 I/O 28 I/O 29 I/O 30 I/O 31 Y0 VCC ISPEN/NC SDI/IN 0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 GND SDO/IN 1 I/O 8 I/O 9 I/O 10 I/O 11 I/O 27 I/O 26 I/O 25 I/O 24 IN 3 GND I/O 23 I/O 22 I/O 21 I/O 20 I/O 19 I/O 18 I/O 17 I/O 16 IN 2/MODE Y1/RESET VCC Y2/SCLK I/O 15 I/O 14 I/O 13 I/O 12 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 nTS nDTACK RNW SIZ0 MODE GND AD0 AEUPPER nDA0 nDA1 nAS ADLT LDS UDS ISPMODE nRST VCC SCLK nOEAB16 nOEBA16 nOEAB8 nOEBA8 nOEAB16 GND nLE16_8 13 11 14 OEAB EAB LEAB AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 3 4 5 6 7 8 9 10 A0 A1 A2 A3 A4 A5 A6 A7 U8 74F543 nOEAB8 GND nLE16_8 13 11 14 OEAB EAB LEAB AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 3 4 5 6 7 8 9 10 A0 A1 A2 A3 A4 A5 A6 A7 GATEWAY BOARD For More Information On This Product, Go to: www.freescale.com D0 D1 D2 D3 D4 D5 D6 D7 MOTOROLA Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and speciÞcally disclaims any and all liability, including without limitation consequential or incidental damages. ÒTypicalÓ parameters can and do vary in different applications. All operating parameters, including ÒTypicalsÓ must be validated for each customer application by customerÕs technical experts. Motorola does not convey any license under its patent rights nor the rights of others. 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MOTOROLA GATEWAY BOARD For More Information On This Product, Go to: www.freescale.com 19