ETC FC940L

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Description
Revised January 1999
FC940L
Low Voltage 1 to 18 Clock Distribution Device with
Selectable PECL or LVTTL Input
General Description
Features
The FC940L is a 1 to 18 low voltage clock fanout buffer.
The device allows for the selection of either differential
PECL or LVTTL/CMOS input levels. The 18 outputs are
compatible with LVCMOS or LVTTL technology and are
capable of driving 50Ω series or parallel terminated lines.
The device has a minimal propagation delay and features
low part-to-part and pin-to-pin skews. The outputs of the
device are designed to operate at either 2.5V or 3.3V VCC.
The output transistors have a 20Ω (30Ω) impedance at
3.3V (2.5V) VCC. The input and core circuitry operate at
3.3V.
■ Selectable Differential PECL or LVTTL/CMOS inputs
The FC940L is fabricated in a high performance BiCMOS
Process.
■ 2.5V/3.3V output VCC supply operation
■ Typical propagation delays 2.5 ns
■ Part-to-Part skew < 900 ps
■ Typical Pin-to-Pin skew 200 ps
■ Ability to drive 50Ω series or parallel terminated transmission lines
■ Latchup performance exceeds 300 mA
■ ESD performance:
Human body model > 2000V
Machine model > 200V
■ Pin compatible to MPC940L
■ 32 pin TQFP package
Ordering Code:
Order Number
FC940LVB
Package Number
VBE32A
Package Description
32-Lead Thin Quad Flat Package, JEDEC MO-136, 7mm Square
Device also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Assignment for TQFP
Pin Names
Description
Differential PECL Input
PECL_CLK, PECL_CLK
LVC_CLK
LVTTL/CMOS Clock Input
SEL
Input Selection Pin
O[0:17]
Low Voltage CMOS Outputs
Truth Table
Inputs
Outputs
O0–O17
PECL_CLK
LVC_CLK
SEL
L
X
L
L
H
X
L
H
X
L
H
L
X
H
H
H
H = High Voltage Level
L = Low Voltage Level
X = Immaterial
© 1999 Fairchild Semiconductor Corporation
DS500140.prf
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FC940L Low Voltage 1 to 18 Clock Distribution Device with Selectable PECL or LVTTL Input
August 1998
FC940L
Functional Description
The output buffers support the ability to be powered by
either a 2.5V or 3.3V VCC. The internal core voltage is
required to be a 3.3V.
The FC940L is a 1 to 18 Clock distribution fanout buffer.
The devices accept either a differential PECL or LVCMOS/
LVTTL input signal and generates 18 LVCMOS output signals. The SEL signal selects the differential PECL CLK
input signals when held at a logic “L” and selects the LVCMOS CLK input signal when held at a logic “H”. The complete functional operation is shown in the Truth Table.
The selectable input stage allows the device to be used in
combination with either LVTTL/LVCMOS or LVPECL clock
generation devices. The LVPECL inputs make this device
ideal for use in large clock distribution systems where there
are multiple levels of hierarchy.
Logic Diagram
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2
Supply Voltage (VCC)
−0.5V to +4.6V
Recommended Operating
Conditions
DC Input Voltage (VI)
−0.5V to +4.6V
Power Supply Voltage (VCC)
−0.5V to VCC + 0.5V
Output Voltage (VO) (Note 2)
VCC I
DC Input Diode Current (IIK)
VI < 0V
DC Output Diode Current (IOK)
VO < 0V
−50 mA
VO > VCC
+50 mA
0V to VCC
VCC O = 3.135V to 3.465V
±24 mA
±16 mA
0°C to +70°C
Free Air Operating Temperature
±100 mA
(ICC or Ground)
Input Edge Rate (∆t/∆V)
−65°C to + 150°C
VIN = 0.8V to 2.0V, VCC = 3.135V
0°C to + 70°C
Ambient Temperature Under Bias (TA)
Case Temperature Under Bias (TC)
0V to VCC
Output Voltage (VO)
VCC O = 2.375V to 2.625V
DC VCC or Ground Current per Supply Pin
Storage Temperature Range (TSTG)
2.375 to 3.465V
Input Voltage (VIN)
Output Current in IOH/IOL
±50 mA
DC Output Source/Sink Current (IO)
3.135V to 3.465V
VCC O(Note 3)
−50 mA
FC940L
Absolute Maximum Ratings(Note 1)
< 10 ns/V
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.
0°C to + 110°C
Note 2: Absolute Maximum Rating must be observed.
Note 3: VCCO ≤ VCC1
DC Electrical Characteristics (VCCI = 3.3 ± 0.165V, VCCO = 3.3 ± 0.165V)
Symbol
VIH
VIL
Parameter
High Level Input Voltage
Low Level Input Voltage
VCCI
Conditions
2.135
3.135–3.465 3.135–3.465
2.00
PECLK_CLK
3.135–3.465 3.135–3.465
1.49
OTHER
3.135–3.465 3.135–3.465
PECL_CLK
3.135–3.465 3.135–3.465
VCMR
Common Mode Range (Note 4)
High Level Output Voltage
IOH = −100 µA
IOH = −24 mA
IOL = 100 µA
Low Level Output Voltage
Quiescent Supply Current
(ICCI + ICCO)
Units
V
V
1.825
V
0.8
V
300
1000
mV
3.135–3.465 3.135–3.465
VCC−1.6
VCC−0.8
V
3.135–3.465 3.135–3.465
VCC−0.2
3.135
3.135
3.135–3.465 3.465
IOL = 24 mA
ICC
2.42
3.135–3.465 3.135–3.465
VOH
Input Current
Max
OTHER
Peak-to-Peak
Input Voltage
IIN
Min
PECLK_CLK
VPP
VOL
TA = 0°C to +70°C
VCCO
3.135
3.135
V
2.5
V
0.2
V
0.5
V
µA
PECL_CLK
3.135–3.465 3.135–3.465
100
LVC_CLK
3.135–3.465 3.135–3.465
100
µA
All Outputs Low
(ICCL)
3.465
3.465
240
mA
All Outputs High
(ICCH)
3.465
3.465
225
mA
Note 4: VCMR is the difference between VCCI and the most positive side of the differential Input signal. Normal operation is obtained when the “high” input is
within the VCMR Range and the inputs swing lies within the VPP specification. See figure 6.
3
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FC940L
DC Electrical Characteristics (VCCI = 3.3V ± 0.165V, VCCO = 2.5V ± 0.125V)
Symbol
VIH
VIL
Parameter
High Level Input Voltage
Low Level Input Voltage
Conditions
2.0
PECLK_CLK
3.135–3.465 2.375–2.625
1.49
OTHER
3.135–3.465 2.375–2.625
High Level Output Voltage
IOH = −100 µA
IOL = 100 µA
IOL = 16 mA
V
V
1.825
V
V
300
1000
mV
3.135–3.465 2.375–2.625
VCC−1.6
VCC−0.8
V
3.135–3.405 2.375–2.625
VCC−0.2
3.135
2.375
V
1.7
V
3.135–3.465 2.375–2.625
3.135
PECL_CLK
Units
0.8
3.135–3.465 2.375–2.625
IOH = −16 mA
Quiescent Supply Current
(ICCI + ICCO)
2.42
2.135
Common Mode Range (Note 4)
ICC
Max
3.135–3.465 2.375–2.625
VCMR
Input Current
Min
3.135–3.465 2.375–2.625
VOH
IIN
TA = 0°C to +70°C
OTHER
Peak-to-Peak Input Voltage
Low Level Output Voltage
VCCO
PECLK_CLK
VPP
VOL
VCCI
0.2
2.375
3.135–3.465 2.375–2.625
V
0.5
V
100
µA
100
µA
All Outputs Low
(ICCL)
3.465
2.625
240
mA
All Outputs High
(ICCH)
3.465
2.625
225
mA
LVC_CLK
3.135–3.465 2.375–2.625
AC Electrical Characteristics (VCCI = 3.3V ± 0.165V, TA = 0°C to +70°C)
(Note 5)
Symbol
Parameter
VCCO = 3.3V ± 0.165V
Min
Typ
VCCO = 2.5V ± 0.125V
Max
150
Min
Typ
Max
fmax
Clock Frequency
tPHL
Propagation Delay
tPLH
PECL_CLK to On
2.5
3.5
2.5
3.7
LVC_CLK to On
2.9
3.8
2.9
4.0
tPHL
Propagation Delay
tPLH
SEL to On
tr
Rise and Fall Time
tf
VCCO = 3.3V (0.8V to 2V)
150
MHz
5.3
5.5
600
Pin-to-Pin Output Skew
tOSHL
(Note 6)
tSK(PR)
Part-to-Part Skew (Note 7)
tpwo
Output Pulse Width (Note 8)
ns
ns
ps
VCCO = 2.5V (0.7V to 1.6V)
tOSLH
Units
600
200
200
ps
900
45
55
45
900
ps
55
%
Note 5: AC Specifications are measured into a 50Ω Parallel terminated line. See Figure 1. Measurements are made with an input rise time of 1 ns/V.
Note 6: Skew is defined as the absolute value of the difference between the actual propagation delay between any two outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH to LOW (tOSHL) or LOW to HIGH tOSLH).
Note 7: Part-to-Part Skew is defined as the variation in propagation delay between a specific output of device A and the same output of device B at the same
VCC, temperature, output loading and input signal conditions. This specification is valid where all outputs of the device are tied together. This specification is
guaranteed by design and statistical process distribution.
Note 8: This specification assumes an input waveform with 50% duty cycle. The worst case duty cycle degradation will typically occur at fMAX.
Capacitance
TA = +25°C
Symbol
Parameter
Conditions
Units
Typical
CIN
Input Capacitance
VCC = Open, VI = 0V or VCC
4
pF
CPD
Power Dissipation Capacitance
VI = 0V or VCC, f= 10 MHz, VCC = 3.3V
8
pF
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4
FC940L
AC Loading and Waveforms
FIGURE 1. AC Test Circuit
FIGURE 2. Waveform for Non-Inverting Output Signal
FIGURE 3. Waveform for Pin-to-Pin Output Skew
FIGURE 4. Duty Cycle Distortion
dpwh=(tpwho-tpwhi); dpwl=(tpwlo-tpwli)
FIGURE 5. Output Pulse Width High/Low
FIGURE 6. Differential Input Signals
VMO
VMI
Symbol
VCCI == 3.3V ± 0.165V
VCCO = 3.3V ± 0.165V
PECL_CLK
50% of Swing
1.5V
VCC/2
LVC_CLK
1.5V
1.5V
VCC/2
5
VCCO = 2.5V ± 0.125V
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FC940L Low Voltage 1 to 18 Clock Distribution Device with Selectable PECL or LVTTL Input
Physical Dimensions inches (millimeters) unless otherwise noted
32-Lead Thin Quad Flat Package, JEDEC, M0-136, 7mm Square
Package Number VBE32A
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
1. Life support devices or systems are devices or systems
device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the
sonably expected to cause the failure of the life support
body, or (b) support or sustain life, and (c) whose failure
device or system, or to affect its safety or effectiveness.
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
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user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.