SEMICONDUCTOR TECHNICAL DATA " ! The MPC941 is a 1:27 low voltage clock distribution chip. The device features the capability to select either a differential LVPECL or an LVTTL/ LVCMOS compatible input. The 27 outputs are LVCMOS or LVTTL compatible and feature the drive strength to drive 50Ω series or parallel terminated transmission lines. With output–to–output skews of 250ps, the MPC941 is ideal as a clock distribution chip for the most demanding of synchronous systems. For a similar product with a smaller number of outputs, please consult the MPC940 data sheet. • • • • • • • LOW VOLTAGE 1:27 CLOCK DISTRIBUTION CHIP LVPECL or LVCMOS/LVTTL Clock Input 250ps Maximum Targeted Output–to–Output Skew Drives Up to 54 Independent Clock Lines Maximum Output Frequency of 250MHz High Impedance Output Enable 52–Lead TQFP Packaging 3.3V VCC Supply Voltage FA SUFFIX With a low output impedance, in both the HIGH and LOW logic states, 52–LEAD TQFP PACKAGE the output buffers of the MPC941 are ideal for driving series terminated CASE 848D–03 transmission lines. More specifically, each of the 27 MPC941 outputs can drive two series terminated 50Ω transmission lines. With this capability, the MPC941 has an effective fanout of 1:54 in applications where each line drives a single load. With this level of fanout, the MPC941 provides enough copies of low skew clocks for most high performance synchronous systems. The differential LVPECL inputs of the MPC941 allow the device to interface directly with a LVPECL fanout buffer like the MC100EP111 to build very wide clock fanout trees or to couple to a high frequency clock source. The LVCMOS/LVTTL input provides a more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies. In addition, the two clock sources can be used to provide for a test clock interface as well as the primary system clock. A logic HIGH on the LVCMOS_CLK_Sel pin will select the TTL level clock input. The MPC941 is fully 3.3V compatible. The 52–lead TQFP package was chosen to optimize performance, board space and cost of the device. The 52–lead TQFP has a 10x10mm body size with a conservative 0.65mm pin spacing. This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. 2/97 Motorola, Inc. 1997 1 REV 0.1 MPC941 LOGIC DIAGRAM PECL_CLK PECL_CLK 0 LVCMOS_CLK 1 Q0 25 LVCMOS_CLK_Sel Q1–Q25 Q26 39 38 37 36 VCCO VCCO Q15 Q14 Q13 GNDO Q12 Q11 VCCO Q10 Q9 Q8 GNDO Pinout: 52–Lead TQFP (Top View) 35 34 33 32 31 30 29 28 27 VCCO 40 26 GNDO VCCO 41 25 GNDO Q7 42 24 Q16 Q6 43 23 Q17 Q5 44 22 Q18 GNDO 45 21 VCCO Q4 46 20 Q19 Q3 47 19 Q20 VCCO 48 18 GNDO Q2 49 17 Q21 Q1 50 16 Q22 Q0 51 15 Q23 GNDO 52 14 VCCO 7 LVCMOS_CLKSEL PECL_CLK PECL_CLK VCCI VCCO 8 9 10 11 12 13 GNDO 6 Q24 5 Q25 4 Q26 3 VCCO 2 GNDI GNDO 1 LVCMOS_CLK MPC941 FUNCTION TABLE LVCMOS_CLK_Sel 0 1 MOTOROLA Input PECL_CLK LVCMOS_CLK 2 TIMING SOLUTIONS BR1333 — Rev 6 MPC941 ABSOLUTE MAXIMUM RATINGS* Symbol Parameter Min Max Unit VCC Supply Voltage –0.3 3.6 V VI Input Voltage –0.3 VDD + 0.3 V IIN Input Current ±20 mA TStor Storage Temperature Range 125 °C –40 * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not implied. DC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±5%) Symbol Characteristic Min Typ Max Unit VIH Input HIGH Voltage PECL_CLK Other V VIL Input LOW Voltage PECL_CLK Other V VPP Peak–to–Peak Input Voltage PECL_CLK mV VCMR Common Mode Range PECL_CLK V VOH Output HIGH Voltage VOL IIN Condition V Note NO TAG Output LOW Voltage V Note NO TAG Input Current µA CIN Input Capacitance pF Cpd Power Dissipation Capacitance pF ICC Maximum Quiescent Supply Current mA 1. The MPC941 outputs can drive series or parallel terminated 50Ω (or 50Ω to VCC/2) transmission lines on the incident edge. AC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±5%) Symbol Characteristic Fmax Maximum Input Frequency tpd Propagation Delay tsk(o) Output–to–Output Skew tsk(pr) Part–to–Part Skew tpwo Output Pulse Width Min PECL_CLK to Q TTL_CLK to Q PECL_CLK to Q TTL_CLK to Q tr, tf Output Rise/Fall Time 2. Driving 50Ω transmission lines. 3. Part–to–part skew at a given temperature and voltage. 0.20 TIMING SOLUTIONS BR1333 — Rev 6 3 Typ Max Unit Condition 250 MHz Note NO TAG 3.0 3.0 ns Note NO TAG 250 ps Note NO TAG 650 650 ps Note NO TAG tCYCLE/2 ±500 ps Note NO TAG, Measured at VCC/2 ns 0.8V to 2.0V 1.0 MOTOROLA MPC941 OUTLINE DIMENSIONS FA SUFFIX PLASTIC TQFP PACKAGE CASE 848D–03 ISSUE C 4X 4X TIPS 0.20 (0.008) H L–M N –X– X=L, M, N 0.20 (0.008) T L–M N 52 CL 40 1 AB 39 3X VIEW Y AB –L– –M– B B1 13 VIEW Y V V1 J 26 –N– A1 BASE METAL F PLATING 27 14 ÇÇÇÇ ÉÉÉÉ ÉÉÉÉ ÇÇÇÇ 0.13 (0.005) S1 M D T L–M U S N S SECTION AB–AB ROTATED 90_ CLOCKWISE A S 4X C θ2 0.10 (0.004) T –H– –T– SEATING PLANE 4X θ3 VIEW AA 0.05 (0.002) S W θ1 2XR R1 0.25 (0.010) C2 θ GAGE PLANE K C1 E Z VIEW AA MOTOROLA G 4 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS –L–, –M– AND –N– TO BE DETERMINED AT DATUM PLANE –H–. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE –T–. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 (0.018). MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07 (0.003). DIM A A1 B B1 C C1 C2 D E F G J K R1 S S1 U V V1 W Z θ θ1 θ2 θ3 MILLIMETERS MIN MAX 10.00 BSC 5.00 BSC 10.00 BSC 5.00 BSC ––– 1.70 0.05 0.20 1.30 1.50 0.20 0.40 0.45 0.75 0.22 0.35 0.65 BSC 0.07 0.20 0.50 REF 0.08 0.20 12.00 BSC 6.00 BSC 0.09 0.16 12.00 BSC 6.00 BSC 0.20 REF 1.00 REF 0_ 7_ ––– 0_ 12 _ REF 5_ 13 _ INCHES MIN MAX 0.394 BSC 0.197 BSC 0.394 BSC 0.197 BSC ––– 0.067 0.002 0.008 0.051 0.059 0.008 0.016 0.018 0.030 0.009 0.014 0.026 BSC 0.003 0.008 0.020 REF 0.003 0.008 0.472 BSC 0.236 BSC 0.004 0.006 0.472 BSC 0.236 BSC 0.008 REF 0.039 REF 0_ 7_ ––– 0_ 12 _ REF 13 _ 5_ TIMING SOLUTIONS BR1333 — Rev 6 MPC941 Motorola reserves the right to make changes without further notice to any products herein. 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How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405; Denver, Colorado 80217. 303–675–2140 or 1–800–441–2447 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 81–3–3521–8315 Mfax: [email protected] – TOUCHTONE 602–244–6609 INTERNET: http://www.mot.com/sps/ ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 TIMING SOLUTIONS BR1333 — Rev 6 ◊ 5 MPC941/D MOTOROLA