Programmable Digital Vibration Sensor ADIS16220 Preliminary Technical Data FEATURES GENERAL DESCRIPTION Digital ±70 g accelerometer/vibration sensing 22 kHz sensor resonance 100.2 kSPS sample rate SPI-compatible serial interface Programmable data capture function: 3 channels, 1024 samples each 1 accelerometer/2 auxiliary ADCs (AIN1, AIN2) Manual trigger for user initiation Automatic trigger for periodic data capture Conditional trigger for condition-driven capture Digital temperature sensor output Digitally controlled sample rate Digitally controlled frequency response 2 auxiliary digital I/Os Digitally activated self-test Digitally activated low power mode Serial number and device ID Single-supply operation: 3.15 V to 3.6 V Operating temperature range: −40°C to +125°C 9.2 mm × 9.2 mm 16-terminal LGA The ADIS16220 iSensor® is a digital vibration sensor that combines industry-leading iMEMS® sensing technology with a signal processor. It provides a buffer memory for high speed data capture, along with a convenient serial interface for data collection and configuration. The 22 kHz sensor resonance and 100.2 kSPS sample rate provide adequate response for most machine-health applications. The averaging/decimating filter provides optimization for lower bandwidth applications. An internal clock drives the data sampling system, which fills the buffer memory for user access. The data capture function has three different trigger modes. The automatic data collection allows for periodic wake-up and capture, based on a programmable duty cycle. The manual data capture mode allows the user to initiate a data capture, providing power and read-rate optimization. The event capture mode continuously updates the buffers and monitors them for a preset trigger condition. This mode captures pre-event data and post-event data and produces an alarm indicator for driving an interrupt. The serial peripheral interface (SPI) and data buffer structure provide convenient access to wide-bandwidth sensor data. The ADIS16220 also offers a digital temperature sensor, digital power supply measurements, and peak output capture. APPLICATIONS Vibration analysis Shock detection and event capture Condition monitoring Machine health Instrumentation, diagnostics Safety, shut-off sensing Security sensing, tamper detection The ADIS16220 comes in a 9.2 mm × 9.2 mm × 3.9 mm LGA package that meets the Pb-free solder reflow profile requirements per JEDEC J-STD-020 and has an extended operating temperature range of −40°C to +125°C. FUNCTION BLOCK DIAGRAM DIO1 SELF-TEST DIO2 RST VDD I/O ALARMS MEMS SENSOR CONTROLLER TEMP SENSOR CLOCK AIN1 AIN2 POWER MANAGEMENT USER CONTROL REGISTERS CAPTURE BUFFER OUTPUT DATA REGISTERS SCLK DIN DOUT 07980-001 ADIS16220 CS SPI PORT FILTER GND VREF Figure 1. Rev. PrE Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. ADIS16220 Preliminary Technical Data TABLE OF CONTENTS Features .............................................................................................. 1 SPI Write Commands ...................................................................9 Applications ....................................................................................... 1 SPI Read Commands ....................................................................9 General Description ......................................................................... 1 Reading Data from the Capture Buffer ................................... 11 Function Block Diagram ................................................................. 1 Capture Mode Configuration ................................................... 11 Specifications..................................................................................... 3 Global Commands ..................................................................... 12 Timing Specifications .................................................................. 5 Filtering........................................................................................ 13 Timing Diagrams.......................................................................... 5 Offset Adjustment ...................................................................... 13 Absolute Maximum Ratings............................................................ 6 Input/Output Functions ............................................................ 13 ESD Caution .................................................................................. 6 Diagnostics .................................................................................. 14 Pin Configuration and Function Descriptions ............................. 7 Serialization................................................................................. 14 Recommended Pad Layout ......................................................... 7 Applications Information .............................................................. 15 Theory of Operation ........................................................................ 8 Assembly...................................................................................... 15 Sensing Element ........................................................................... 8 Interface Board ........................................................................... 15 Data Sampling and Processing ................................................... 8 Outline Dimensions ....................................................................... 16 User Interface ................................................................................ 8 Ordering Guide .......................................................................... 16 Basic Operation................................................................................. 9 Rev. PrE | Page 2 of 16 Preliminary Technical Data ADIS16220 SPECIFICATIONS TA = −40°C to +125°C, VDD = 3.3 V, ±1 g, unless otherwise noted. Table 1. Parameter ACCELEROMETER Measurement range Sensitivity Sensitivity Error Sensitivity Temperature Coefficient Nonlinearity Cross-Axis Sensitivity Alignment Error Offset Error Offset Temperature Coefficient Output Noise Output Noise Density Sensor Resonant Frequency Self-Test Response AUXILIARY INPUTS (AIN1, AIN2) Resolution1 Sensitivity Integral Nonlinearity Differential Nonlinearity Offset Offset Error Input Range Input Capacitance ON-CHIP VOLTAGE REFEERENCE Output Level Accuracy Temperature Coefficient Output Impedance LOGIC INPUTS2 Input High Voltage, VINH Input Low Voltage, VINL Logic 1 Input Current, IINH Logic 0 Input Current, IINL All Except RST RST Input Capacitance, CIN DIGITAL OUTPUTS2 Output High Voltage, VOH Output Low Voltage, VOL FLASH MEMORY Endurance3 Data Retention4 START-UP TIME5 Initial Startup Reset Recovery (RST) Sleep Mode Recovery Conditions Min TA = 25°C TA = 25°C TA = 25°C −70 19.073 ±5 ±310 ±0.2 ±2 ±1 With respect to full scale With respect to package TA = 25°C Typ −19.1 TA = 25°C, AVG_CNT = 0x0000 TA = 25°C, 10 Hz to 1 kHz 917 Max Unit +70 g mg/LSB % ppm/°C % % Degree g mg/°C mg rms mg/√Hz kHz LSB ±2 +19.1 ±5 507 4 22 1310 1703 12 305.18 2.4 4 VDD/2 ±20.4 20 Bits μV/LSB LSB LSB V LSB V pF 2.5 ±5 ±40 70 V mV ppm/°C Ω 0 VDD 2.0 VIH = 3.3 V VIL = 0 V ±0.2 −40 −1 10 ISOURCE = 1.6 mA ISINK = 1.6 mA 0.8 ±1 −60 2.4 0.4 10,000 10 TJ = 85°C RST or software (GLOB_CMD) Rev. PrE | Page 3 of 16 V V μA μA mA pF V V Cycles Years 160 23 2.3 ms ms ms ADIS16220 Parameter CONVERSION RATE Clock Accuracy POWER SUPPLY Power Supply Current Preliminary Technical Data Conditions AVG_CNT = 0x0000 Min Operating voltage range, VDD Capture mode, TA = 25°C Sleep mode, TA = 25°C Sleep mode, TA = 85°C Sleep mode, TA = 125°C 3.15 1 Typ 100.2 3 3.3 38 230 250 600 Max 3.6 46 400 1000 Unit kSPS % V mA μA μA μA A 12-bit analog-to-digital converter is used to create a 14-bit digital scale for the AIN1 and AIN2 inputs. The digital I/O signals are 5 V tolerant. 3 Endurance is qualified as per JEDEC Standard 22, Method A117, and measured at −40°C, +25°C, +85°C, and +125°C. 3 Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22, Method A117. Retention lifetime decreases with junction temperature. 5 The start-up times presented do not include the data capture time, which is dependent on the AVG_CNT register settings. 2 Rev. PrE | Page 4 of 16 Preliminary Technical Data ADIS16220 TIMING SPECIFICATIONS TA = 25°C, VDD = 3.3 V, unless otherwise noted. Table 2. Parameter fSCLK tSTALL tCS tDAV tDSU tDHD tSCLKR, tSCLKF tSR tSF tDF, tDR tSFS 1 Min1 0.01 15.4 48.8 Description SCLK frequency Stall period between data, between 16th and 17th SCLK Chip select to SCLK edge DOUT valid after SCLK edge DIN setup time before SCLK rising edge DIN hold time after SCLK rising edge SCLK rise/fall times SCLK high pulse width SCLK low pulse width DOUT rise/fall times CS high after SCLK edge Typ Max 2.25 Unit MHz μs ns ns ns ns ns ns ns ns ns 100 24.4 48.8 5 12.5 12.5 12.5 12.5 5 5 Guaranteed by design, not tested. TIMING DIAGRAMS tSR CS tSF tCS tSFS 1 2 3 4 5 6 15 16 SCLK tDAV MSB DB14 DB13 tDSU DIN W/R A6 DB12 DB11 A4 A3 DB10 DB2 DB1 LSB tDHD A5 A2 D2 D1 07980-002 DOUT LSB Figure 2. SPI Timing and Sequence tSTALL 07980-003 CS SCLK Figure 3. DIN Bit Sequence Rev. PrE | Page 5 of 16 ADIS16220 Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS Table 4. Package Characteristics Table 3. Parameter Acceleration Any Axis, Unpowered Any Axis, Powered VDD to GND Digital Input Voltage to GND Digital Output Voltage to GND Analog Inputs to GND Operating Temperature Range Storage Temperature Range Rating Package Type 16-Terminal LGA 2000 g 2000 g −0.3 V to +6.0 V −0.3 V to +5.3 V −0.3 V to VDD + 0.3 V −0.3 V to +3.6 V −40°C to +125°C −65°C to +125°C ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. PrE | Page 6 of 16 θJA 250°C/W θJC 25°C/W Device Weight 0.6 g Preliminary Technical Data ADIS16220 12 13 AIN2 11 VDD 14 NC 10 AIN1 15 NC 9 VREF 16 1 SCLK GND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS RST DIN 3 CS 4 DOUT 2 PIN 1 INDICATOR ADIS16220 TOP LOOK THROUGH VIEW (Not to Scale) 6 7 8 DIO2 NC NC NOTES 1. NC = NO CONNECT. 2. THIS IS NOT AN ACTUAL TOP VIEW, BECAUSE THE PINS ARE NOT VISIBLE FROM THE TOP. THIS IS A LAYOUT VIEW THAT REPRESENTS THE PIN CONFIGURATION IF THE PACKAGE IS LOOKED THROUGH FROM THE TOP. THIS CONFIGURATION IS PROVIDED FOR PCB LAYOUT PURPOSES. 07980-005 5 DIO1 A Figure 4. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 3 4 5, 6 7, 8, 10, 11 9 12 13 14 15 16 1 2 Type1 I O2 I I I/O N/A I I S I O S Mnemonic SCLK DOUT DIN CS DIO1, DIO2 NC RST AIN2 VDD AIN1 VREF GND Description SPI, Serial Clock. SPI, Data Output. SPI, Data Input. SPI, Chip Select. Digital Input/Output Pins. No Connect. Reset, Active Low. Analog Input Channel 2. Power Supply, 3.3 V. Analog Input Channel 1. Voltage Reference for AIN1 and AIN2. Ground. S = supply; O = output; I = input; I/O = input/output. DOUT is an output when CS is low. When CS is high, DOUT is in a three-state, high impedance mode. RECOMMENDED PAD LAYOUT 2.6955 8× 4.1865 8× 0.670 12× 8.373 2× 5.391 4× 9.2mm × 9.2mm STACKED LGA PACKAGE Figure 5. Recommended of a Pad Layout Rev. PrE | Page 7 of 16 07980-006 0.500 16× 1.127 16× ADIS16220 Preliminary Technical Data THEORY OF OPERATION ANCHOR MOVABLE FRAME UNIT SENSING CELL UNIT FORCING CELL ANCHOR AIN SIGNALS SPI SIGNALS CONTROL REGISTERS CLOCK Figure 7. Simplified Sensor Signal Processing Diagram USER INTERFACE SPI Interface Data collection and configuration commands both use the SPI, which consists of four wires. The chip select (CS) signal activates the SPI interface and the serial clock (SCLK) synchronizes the serial data lines. The serial input data clocks into DIN on the SCLK rising edge, and the serial output data clocks out of the DOUT on the SCLK falling edge. Many digital processor platforms support this interface with dedicated serial ports and simple instruction sets. Figure 6. MEMS Sensor Diagram DATA SAMPLING AND PROCESSING The ADIS16220 runs autonomously, based on the configuration in the user control registers. The analog acceleration signal feeds into an analog-to-digital (ADC) converter stage, which passes digitized data into the controller for data processing and capture. Processing options include offset adjustment, filtering, and checking for preset alarm conditions. The user registers provide addressing for all input/output operations on the SPI interface. Each 16-bit register has its own unique bit assignment and has two addresses: one for its upper byte and one for its lower byte. Table 8 provides a memory map for each register, along with their function. The control registers use a dual memory structure. The SRAM controls operation while the part is on, and facilitates all user configuration inputs. The flash memory provides nonvolatile storage for control registers that have flash backup (see Table 8). Storing configuration data in the flash memory requires a separate command (GLOB_ CMD[12] = 1, DIN = 0xBF10). When the device powers on or resets, the flash memory contents load into the SRAM, and then the device starts producing data according to the configuration in the control registers. MANUAL FLASH BACKUP NONVOLATILE FLASH MEMORY VOLATILE SRAM (NO SPI ACCESS) SPI ACCESS START-UP RESET Figure 8. SRAM and Flash Memory Diagram Rev. PrE | Page 8 of 16 07980-109 FIXED PLATES MOVING PLATE CONTROLLER User Registers 07980-004 ACCELERATION PLATE CAPACITORS ADC 07980-007 Digital vibration sensing in the ADIS16220 starts with a widebandwidth MEMS accelerometer core that provides a linear motion-to-electrical transducer function. Figure 6 provides a basic physical diagram of the sensing element and its response to linear acceleration. It uses a fixed frame and a moving frame to form a differential capacitance network that responds to linear acceleration. Tiny springs tether the moving frame to the fixed frame and govern the relationship between acceleration and physical displacement. A modulation signal on the moving plate feeds through each capacitive path into the fixed frame plates and into a demodulation circuit, which produces the electrical signal that is proportional to the acceleration acting on the device. TEMP SENSOR OUTPUT REGISTERS SPI PORT SENSING ELEMENT CAPTURE BUFFER MEMS SENSOR SPI PORT The ADIS16220 is a wide-bandwidth, digital acceleration sensor for vibration analysis applications. This sensing system collects data autonomously and makes it available to any processor system that supports a 4-wire serial peripheral interface (SPI). Preliminary Technical Data ADIS16220 BASIC OPERATION The ADIS16220 requires only power, ground, and the four SPI signals to produce data and make it available to a processor. Figure 9 provides a schematic for connecting to a SPI-compatible processor, and includes the two configurable digital I/O lines. DIO1’s factory default configuration is a busy indicator that goes high when the devices is capturing data and goes low when finished. VDD User registers govern all data collection and configuration. Table 8 provides a memory map that includes all user registers, with references to bit assignment tables that follow the generic assignments in Figure 10. 13 12 SCLK 3 DIN MISO 2 DOUT IRQ1 5 DIO1 IRQ2 6 DIO2 16 Figure 9. Electrical Hook-Up Diagram Table 6. Generic Master Processor Pin Names and Functions Pin Name SS IRQ1, IRQ2 MOSI MISO SCLK 6 5 4 3 2 1 0 LOWER BYTE CS Function Slave select Interrupt request inputs Master output, slave input Master input, slave output Serial clock SCLK DIN Figure 11. SPI Sequence for Manual Capture Start (DIN = 0xBF08) SPI READ COMMANDS Reading data through the SPI requires two consecutive 16-bit sequences. The first sequence transmits the read command and address on DIN, and the second receives the resulting data from DOUT. The 7-bit register address (A6:A0) can represent either the upper or lower byte address for the target register. For example, DIN can be either 0x0A00 or 0x0B00 when reading the CAPT_SUPPLY register. The ADIS16220 SPI interface supports full duplex serial communication (simultaneous transmit and receive) and uses the bit sequence shown in Figure 13. Processor platforms typically support SPI communication with general-purpose serial ports that require some configuration in their control registers. Table 7 provides a list of the most common settings that require attention to initialize a processor’s serial port for communication with the ADIS16220. Figure 12 provides a full-duplex mode example of reading the CAPT_SUPPLY register. Also, the second SPI segment sets the device up to read CAPT_TEMP on the following SPI segment (not shown). Table 7. Generic Master Processor SPI Settings Processor Setting Master SCLK Rate ≤ 2.25 MHz SPI Mode 3 (1, 1) MSB-First 16-Bit 7 07980-112 1 MOSI 07980-010 SCLK 8 Master processors write to the control registers, one byte at a time, using the bit assignments in Figure 13. Some configurations require writing both bytes to a register, which takes two separate 16-bit sequences, whereas others require only one byte. The programmable registers in Table 8 provide controls for optimizing sensor operation and for starting various automated functions. For example, set GLOB_CMD[11] = 1 by writing 0xBF08 to the master processor’s SPI transmit register, which feeds the DIN line, to start a manual capture sequence. The manual capture starts immediately after the last bit clocks into DIN (16th SCLK rising edge). SPI SLAVE CS 9 SPI WRITE COMMANDS 13 4 10 Figure 10. Generic Register Bit Definitions ADIS16220 SS 11 UPPER BYTE VDD SYSTEM PROCESSOR SPI MASTER CS 14 07980-110 15 Description ADIS16220 operates as a slave Bit rate setting Clock polarity/phase (CPOL = 1, CPHA = 1) Bit sequence Shift register/data length SPI SEGMENT 1 SPI SEGMENT 2 SCLK 0 0 0 0 1 0 1 0 1 0 0 0 1 1 1 1 DOUT DIN = 0x0A00 PRODUCES CAPT_SUPPLY CONTENTS ON DOUT DURING THE NEXT SPI SEGMENT DOUT = 0x0A8F, CAPT_SUPPLY = +3.3V Figure 12. Example SPI Read Sequence Rev. PrE | Page 9 of 16 07980-013 DIN ADIS16220 Preliminary Technical Data Note that all registers in Table 8 consist of two bytes. All unused memory locations are reserved for future use. Table 8. User Register Memory Map Name FLASH_CNT ACCL_NULL AIN1_NULL AIN2_NULL Access Read only Read/write Read/write Read/write Flash Backup Yes Yes Yes Yes CAPT_SUPPLY CAPT_TEMP CAPT_PEAKA CAPT_PEAK1 CAPT_PEAK2 CAPT_BUFA CAPT_BUF1 CAPT_BUF2 CAPT_PNTR CAPT_CTRL CAPT_PRD ALM_MAGA ALM_MAG1 ALM_MAG2 ALM_MAGS ALM_CTRL Read only Read only Read only Read only Read only Read only Read only Read only Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Yes Yes Yes Yes Yes No No No No Yes Yes Yes Yes Yes Yes Yes GPIO_CTRL MSC_CTRL DIO_CTRL AVG_CNT Read/write Read/write Read/write Read/write Yes Yes Yes Yes DIAG_STAT GLOB_CMD ST_DELTA Read only Write only Read only Yes No Yes LOT_ID1 LOT_ID2 PROD_ID SERIAL_NUM Read only Read only Read only Read only Yes Yes Yes Yes Default N/A 0x0000 0x0000 0x0000 Bit Assignments Table 30 Table 23 Table 24 Table 24 Function Flash memory write count Acceleration offset adjustment control AIN1 offset adjustment control AIN2 offset adjustment control Reserved Output, power supply during capture Output, temperature during capture Output, peak acceleration during capture Output, peak AIN1 level during capture Output, peak AIN2 level during capture Output, capture buffer for acceleration Output, capture buffer for AIN1 Output, capture buffer for AIN2 Operation, capture buffer address pointer Operation, capture control register Operation, capture period (automatic mode) Alarm A, acceleration peak threshold Alarm 1, AIN1 peak threshold Alarm 2, AIN2 peak threshold Alarm S, temperature/power supply threshold Alarm, control register Reserved Operation, general I/O configuration Operation, self-test control, AIN configuration Operation, digital I/O configuration Operation, filter configuration Reserved Diagnostics, system status Operation, system commands Self-test response Reserved Date code identification Date code identification Product identifier; convert to decimal = 16220 Serial number 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x0020 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x000F 0x0000 0x0000 N/A N/A N/A N/A 0x3F5C N/A Table 10 Table 10 Table 10 Table 10 Table 10 Table 10 Table 10 Table 10 Table 9 Table 13 Table 14 Table 17 Table 18 Table 18 Table 19 Table 16 Table 26 Table 28 Table 25 Table 22 Table 27 Table 21 Table 29 Table 31 Table 32 N/A Table 33 Each register contains two bytes. The address of the lower byte is displayed. The address of the upper byte is equal to the address of the lower byte, plus 1. CS SCLK DIN DOUT R/W DB15 A6 A5 A4 A3 A2 A1 DB14 DB13 DB12 DB11 DB10 DB9 A0 D7 D6 D5 D4 D3 D2 D1 D0 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 NOTES 1. DOUT BITS ARE BASED ON THE PREVIOUS 16-BIT SEQUENCE (R/W = 0). Figure 13. SPI Communication Bit Sequence Rev. PrE | Page 10 of 16 R/W DB15 A6 A5 DB14 DB13 07980-111 1 Address1 0x00 0x02 0x04 0x06 0x08 to 0x09 0x0A 0x0C 0x0E 0x10 0x12 0x14 0x16 0x18 0x1A 0x1C 0x1E 0x20 0x22 0x24 0x26 0x28 0x2A to 0x31 0x32 0x34 0x36 0x38 0x3A to 0x3B 0x3C 0x3E 0x40 0x42 to 0x51 0x52 0x54 0x56 0x58 Preliminary Technical Data ADIS16220 READING DATA FROM THE CAPTURE BUFFER Initiate a manual capture command by setting GLOB_CMD[11] = 1 (DIN = 0xBF08). Wait for DIO1 to go high and then low before using the SPI port. When the capture is complete, the first data samples load into the CAPT_BUFx registers and 0x0000 loads into the index pointer (CAPT_PNTR). The index pointer determines which data samples load into the CAPT_BUFx registers. For example, writing 0x0138 to the CAPT_PNTR register (DIN = 0x9A38, DIN = 0x9B01) causes the 313th sample in the buffer memory to load into the CAPT_BUFx registers. CAPT_BUFA ACCELERATION CAPTURE BUFFER CAPT_PNTR 1023 07980-014 0 Output (Binary) 0000 1110 0101 0001 0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 1111 0001 1010 1101 LSB +3670 +1 0 −1 −3670 Acceleration +70 g +0.019073 g 0 −0.019073 g −70 g Table 12. Analog Input Data Format Output (Binary) 0000 1100 1100 1101 0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 1111 0011 0011 0010 Hex 0x0CCD 0x0001 0x0000 0xFFFF 0xF332 LSB +3277 +1 0 −1 -3277 Level (mV) VDD/2 + 1000 VDD/2 + 0.305 VDD/2 VDD/2 − 0.305 VDD/2 − 1000 VS = (CAPT_SUPPLY) × 0.001221 V/LSB = +3.3 V where CAPT_SUPPLY = 2703 LSB. Table 9. CAPT_PNTR Bits Descriptions Temperature Equation Description (Default = 0x0000) Not used Data bits Temperature = (1278 − CAPT_TEMP) × 0.47°C/LSB + 25°C. For example, when CAPT_TEMP = 1331, the result is 0.1°C. The index pointer automatically increments with a CAPT_BUFA, CAPT_BUF1, or CAPT_BUF2 read command. In the master processor firmware, the loop may appear similar to the following: Data(0) = spi_reg_read(0x14) For n = 0 to 1023 Data(n) = spi_reg_read(0x14); CAPTURE MODE CONFIGURATION The CAPT_CTRL register provides three different options for triggering a data capture: manual, automatic, and event. It also offers an option for placing the device in a low power, shutdown mode in between capture events. This setting adds approximately 2.3 ms to the total capture time relationship: n = n + 1; 1 1024 2 AVG _ CNT (no flash) 97,184 1 TC 0.516 1024 2 AVG _ CNT (with flash) 97,184 TC 0.014 end Output Data Format The CAPT_BUFA and CAPT_PEAKA registers use a 14-bit, twos complement format to accommodate acceleration in both directions (positive and negative). In addition to the acceleration data, a capture event also produces analog input data (CAPT_BUF1, CAPT_BUF2), power supply data (CAPT_SUPPLY), temperature data (CAPT_TEMP), the peak acceleration level (CAPT_PEAKA) and the peak analog input levels (CAPT_PEAK1, CAPT_PEAK2) in the captured data. Table 13. CAPT_CTRL Bit Descriptions Bit [15:7] [6] [5:4] Table 10. Capture Output Register Formats Register CAPT_SUPPLY CAPT_TEMP CAPT_BUFA, CAPT_PEAKA CAPT_BUF1, CAPT_BUF2, CAPT_PEAK1, CAPT_PEAK2 Hex 0x0E56 0x0001 0x0000 0xFFFF 0xF1AA Power Supply Voltage (VS) Equation Figure 14. Acceleration Capture Buffer Structure and Operation; CAPT_BUF1 (AIN1) and CAPT_BUF2 (AIN2) Use Similar Structures Bit [15:10] [9:0] Table 11. Acceleration Data Format Bits 12 12 16 Format Binary, 0 V = 0 LSB Binary, 25°C = 1278 LSB Twos complement Scale 1.22 mV −0.47°C 19.073 mg 16 Twos complement 305.18 μV [3:2] [1] [0] Rev. PrE | Page 11 of 16 Description (Default = 0x0020) Not used Automatically store capture buffers to flash upon alarm trigger (1 = enabled) Pre-event capture length 00 = 64 samples 01 = 128 samples 10 = 256 samples 11 = 512 samples Capture mode 00 = manual: use GLOB_CMD[11] to start capture 01 = automatic: use CAPT_PRD[9:0] to set capture period 10 = event: continuously monitor data for the conditions set in ALM_CTRL, ALM_MAGA, ALM_MAG1, and ALM_MAG2. 11 = not used Power-down between capture events 1 = enabled, which requires CS toggle to wake up Not used ADIS16220 Preliminary Technical Data Table 17. ALM_MAGA Bit Descriptions Manual Capture Mode This is the factory-default mode, where the sensor waits for a user-driven trigger to execute a data capture. Set GLOB_CMD[11] = 1 (DIN = 0xBF08) to execute a data capture in this mode. Set CAPT_CTRL[7:0] = 0x02 to place the device in manual mode and enable the control bit that shuts the device down while it waits for the data capture command. Automatic Capture Mode In automatic mode, the device executes data captures without user input, on a periodic basis. Configuring the device for this mode requires three steps: program the capture period using CAPT_PRD, set the device in automatic mode using CAPT_CTRL[3:2], and start the capture process/clock using CLOB_CMD[11]. See Table 15 for an example of setting up automatic mode. Table 14. CAPT_PRD Register Bit Descriptions Bit [15:10] [9:8] [7:0] Description Set time scale to hours Set the time between captures to 24 hours Set the device for trigger mode and enable shutdown Start: device executes a capture and shuts down Event Capture Mode The event capture mode triggers a data capture when the data meets the preset conditions in the alarm registers (ALM_xxxx). The ALM_CTRL register provides trigger source selection and configuration controls, while the ALM_MAGx registers provide threshold level controls. Table 18. ALM_MAG1 and ALM_MAG2 Bit Descriptions Bit [15:0] [4] [3] [2] [1] [0] Description (Default = 0x0000) Not used System alarm comparison polarity 1 = trigger when less than ALM_MAGS[11:0] 0 = trigger when greater than ALM_MAGS[11:0] System alarm trigger source 1 = temperature, 0 = power supply System alarm enable (ALM_MAGS) 1 = enabled, 0 = disabled AIN2 alarm enable (ALM_MAG2) 1 = enabled, 0 = disabled AIN1 alarm enable (ALM_MAG1) 1 = enabled, 0 = disabled Acceleration alarm enable (ALM_MAGA) 1 = enabled, 0 = disabled Description (Default = 0x0000) Data bits for AIN1, AIN2 signal threshold setting; twos complement, 305.18 μV/LSB. Range = +8191/−8192 LSBs Table 19. ALM_MAGS Bit Descriptions Bit [15:12] [11:0] Description (Default = 0x0000) Not used. Data bits for temperature or supply threshold setting. Binary format matches CAPT_TEMP or CAPT_SUPPLY format, depending on the ALM_CTRL[4] setting. Table 20. Example Event Mode Configuration Sequence DIN 0xA00C, 0xA102 0xA634, 0xA700 0xA839 0xB61F 0x9C5A Table 16. ALM_CTRL Bit Descriptions Bit [15:6] [5] Description (Default = 0x0000) Data bits for acceleration threshold setting; twos complement, 19.073 mg/LSB. Range = +8191/−8192 LSBs Configuring the device in the event capture mode requires four steps: select which data channels to enable (ALM_CTRL), set each threshold (ALM_MAGx), select event capture mode (CAPT_CTRL) and start the capture mode operation (set GLOB_CMD[11]). Each ALM_MAGx register has a corresponding error flag in the DIAG_STAT register for software monitoring of alarm conditions. Note that the system alarm has an error flag in DIAG_STAT[11] but cannot trigger a data capture. Description (Default = 0x0000) Not used Scale 00 = 1 second/LSB 01 = 1 minute/LSB 10 = 1 hour/LSB Data bits, binary format Table 15. Example Event Mode Configuration Sequence DIN 0x9F02, 0x9E18 0x9C06 0xBF08 Bit [15:0] 0xBF08 Description Set acceleration trigger point at >+10 g and <−10 g by setting ALM_MAGA = 0x020C. Set temperature error flag level at +60°C by setting ALM_MAGS = 0x00C4. Set the system alarm as a greater-than-temperature configuration and enable both acceleration and system alarms by setting ALM_CTRL[7:0] = 0x39. Keep DIO1 as a busy indicator and set DIO2 as a positive alarm indicator by setting DIO_CTRL[7:0] = 0x1F. Set capture into event mode, enable automatic capture store to flash, enable power-down between captures, and set pre-event capture length to 128 samples by setting CAPT_CTRL[7:0] = 0x5A. Start the event capture mode by setting GLOB_CMD[11] = 1 GLOBAL COMMANDS The GLOB_CMD register provides an array of single-write commands for convenience. Setting the assigned bit in Table 21 to 1 activates each function. When the function completes, the bit restores itself to 0. For example, clear the capture buffers using a single DIN write sequence, DIN = 0xBF01. All of the commands in the GLOB_CMD register require the power supply to be within normal limits for the execution times listed in Table 21. The execution times reflect the factory default configuration where applicable and describe the time required to return to normal operation. Rev. PrE | Page 12 of 16 Preliminary Technical Data ADIS16220 Table 23. ACCL_NULL Bit Descriptions Table 21. GLOB_CMD Bit Descriptions Bit [15:14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] 1 Description Not used Restore capture data and settings from flash memory Copy capture data and settings to flash memory Capture mode start/stop Set CAPT_PNTR = 0x0000 Not used Clear capture buffers Software reset Not used Flash test, compare sum of flash memory with the sum of SRAM Clear DIAG_STAT register Factory setting restore Self-test Power-down, requires toggling CS low to wake up Autonull Execution Time1 N/A 0.88 ms (no capture) 6.91 ms (with capture) 350 ms (no capture) 502 (with capture) N/A 0.037 ms N/A 0.84 ms 22.7 ms N/A 10.5 ms 0.035 ms 335 ms 12 ms N/A 678 ms This indicates the typical duration of time between the command write and the device returning to normal operation. FILTERING The ADIS16220 provides an averaging/decimation filter for lower bandwidth applications that may value finer frequency resolution using the 1024-sample capture buffer. MEMS SENSOR ADC AVERAGING FILTER N + ÷N TO CAPTURE MEMORY AND OUTPUT REGISTERS 07980-009 OFFSET NULL REGISTER Figure 15. Simplified Signal Processing Flowchart AVG_CNT[3:0] controls the averaging/decimating filter structure in binomial steps, starting with 1 and ending with 1024. For example, set AVG_CNT[7:0] = 0x08 (DIN = 0xB608) to select 256 averages and a decimation rate of 1/256. Note that the decrease in sample time impacts the total capture time (TC): Bit [15:0] Table 24. AIN1_NULL, AIN2_NULL Bit Descriptions Bit [15:0] DIO1 and DIO2 are configurable as I/O lines that serve multiple purposes. The following register priority governs their operation: DIO_CTRL, then GPIO_CTRL. The DIO_CTRL register has four application-specific configuration options for each signal. The capture trigger input option works in conjunction with the manual capture mode and provides a hardware option for driving a data capture event. When enabled, this function searches for a positive pulse and the capture starts on the falling edge of this pulse. The busy indicator output is active during capture events and can help prevent undesirable interruptions. For example, set DIO_CTRL[5:0] = 101111 (DIN = 0xB62F) to establish DIO2 as a capture trigger input and keep DIO1 as a positive polarity, busy indicator output. Using the busy indicator as an interrupt driver enables the master processor to gather capture data as soon as it is available, without having to poll inputs or estimate execution times. The alarm indicator output is active when the trigger set by ALM_CTRL and ALM_MAGx activates. When configured as general-purpose lines, the GPIO_CTRL register configures DIO1 and DIO2. For example, set GPIO_CTRL = 0x0103 (DIN = 0xB203, then 0xB301) to set DIO1 and DIO2 as outputs, with DIO1 in a 1 state and DIO2 in a 0 state. Table 25. DIO_CTRL Bit Descriptions Bit [15:6] [5:4] Table 22. AVG_CNT Bit Descriptions Description (Default = 0x0000) Not used Power-of-two setting for number of averages, binary [3:2] OFFSET ADJUSTMENT The ACCL_NULL, AIN1_NULL and AIN2_NULL registers provide a bias adjustment function. For example, setting ACCL_NULL = 0x009C (DIN = 0x829C) increases the acceleration bias by 156 LSB (3 g). Set GLOB_CMD[0] = 1 (DIN = 0x3E01) to execute the autonull function, which loads the offset registers with a value derived from a 678 ms average of the acceleration data. Description (Default = 0x0000) Data bits, twos complement, 305.18 μV/LSB sensitivity. Signal path is similar to Figure 15. Range = +8191/−8192 LSBs INPUT/OUTPUT FUNCTIONS AVG_CNT[7:0] = 0x08 = 8, N = 28 = 256 averages Bit [15:4] [3:0] Description (Default = 0x0000) Data bits, twos complement, 19.073 mg/LSB sensitivity. See Figure 15 for impact on output. Range = +8191/−8192 LSBs [1] [0] Rev. PrE | Page 13 of 16 Description (Default = 0x000F) Not used DIO2 function selection 00 = general-purpose I/O (use GPIO_CTRL) 01 = alarm indicator output (per ALM_CTRL) 10 = capture trigger inputs 11 = busy indicator output DIO1 function selection 00 = general-purpose I/O (use GPIO_CTRL) 01 = alarm indicator output (per ALM_CTRL) 10 = capture trigger inputs 11 = busy indicator output DIO2 line polarity, If [5:4] = 00, see GPIO_CTRL 1 = active high 0 = active low DIO1 line polarity, If [3:2] = 00, see GPIO_CTRL 1 = active high 0 = active low ADIS16220 Preliminary Technical Data Self-Test Table 26. GPIO_CTRL Bit Descriptions Bit [15:10] [9] [8] [7:2] [1] [0] The internal MEMS sensing element has an electrostatic selftest function that simulates the physical displacement associated with an acceleration event. There are two options for using this feature to verify the integrity of the entire sensor signal chain. Set GLOB_CMD[2] = 1 to execute an automatic self-test sequence, which exercises the sensing element, observes the change in output, records it into ST_DELTA, compares it with the acceptable self-test response range in Table 1, and reports the pass/fail result in DIAG_STAT[5]. Description (Default = 0x0000) Not used General-Purpose I/O Line 2 data level General-Purpose I/O Line 1 data level Not used General-Purpose I/O Line 2, data direction control 1 = output, 0 = input General-Purpose I/O Line 1, data direction control 1 = output, 0 = input DIAGNOSTICS In all of the error flags in DIAG_STAT, a 1 identifies an error condition while a 0 signals normal operation. All of the flags remain until the next capture or reset command (GLOB_CMD[4] = 1). DIAG_STAT[1:0] return to 1 after the next sample (or capture) if the error conditions still exist. DIAG_STAT[14:12] provide flags to check the source of an event capture, prior to reading the entire capture buffer. DIAG_STAT[10:8] offers flags that check the peak values in the capture against the conditions in the ALM_CTRL and ALM_MAGx registers. The flash test produces an error flag in DIAG_STAT[6] to check if the sum of the internal operating memory matches the sum of the same flash memory locations. The capture period violation flag (DIAG_STAT[4]) rises to 1 when the user attempts to use the SPI while a capture sequence is in progress. Using the DIO1 line in the factory default configuration as a busy indicator can help prevent this violation. The SPI communication flag in DIAG_STAT[3] raises to a Logic 1 when the total number of SCLK clocks is not a multiple of 16 during a SPI transfer. Another option is to set MSC_CTRL[8] = 1 to manually activate the sensing element. Then execute a manual capture, which reflects the response associated with the self-test setting. Table 28. MSC_CTRL Bit Descriptions Bit [15:9] [8] [7:2] [1] [0] Description (Default = 0x0003) Not used Self-test enable, set to 1 to activate, (returns to 0 when complete) Not used Power supply compensation, AIN1 1 = enable, 0 = disable Power supply compensation, AIN2 1 = enable, 0 = disable MSC_CTRL[1:0] provides an option for reducing the sensitivity dependence on power supply for ratiometric sensors, such as the ADXL001. Table 29. ST_DELTA Bit Descriptions Bit [15:0] Description Acceleration data, twos complement, 19.073 mg/LSB Table 27. DIAG_STAT Bit Descriptions Table 30. FLASH_CNT Bit Descriptions Bit [15] [14] [13] [12] [11] Bit [15:0] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] Description (Default = 0x0000) Not used AIN2 sample > ALM_MAG2 AIN1 sample > ALM_MAG1 Acceleration sample > ALM_MAGA Error condition programmed into ALM_MAGS[11:0] and ALM_CTRL[5:4] is true Peak value in AIN2 data capture > ALM_MAG2 Peak value in AIN1 data capture > ALM_MAG1 Peak value in acceleration data capture > ALM_MAGA Data ready, capture complete Flash test, checksum flag Self-test diagnostic error flag Capture period violation/interruption SPI communications failure Flash update failure Power supply above 3.625 V Power supply below 3.15 V Description Binary counter for writing to flash memory SERIALIZATION LOT_ID1 and LOT_ID2 combine to provide a unique lot code that is 24 bits in length. SERIAL_NUM provides a unique serial number for each device within a given lot. Table 31. LOT_ID1 Bit Descriptions Bit [15:8] [7:0] Description Lot identification code, least significant byte Reserved for internal use, do not use Table 32. LOT_ID2 Bit Descriptions Bit [15:0] Description Lot identification code, most significant bytes Table 33. SERIAL_NUM Bit Descriptions Bit [15:0] Rev. PrE | Page 14 of 16 Description Serial number, lot-specific Preliminary Technical Data ADIS16220 APPLICATIONS INFORMATION ASSEMBLY INTERFACE BOARD The ADIS16220 is a system-in-package (SIP) that integrates multiple components together in a land grid array (LGA). This configuration offers the convenience of solder-reflow installation on printed circuit boards (PCBs). In developing a process flow for installing ADIS16220 devices on PCBs, refer to the following industry standards: JEDEC J-STD-020 for solder reflow temperature profiles and JEDEC J-STD-033 for moisture sensitivity (MSL) handling requirements. The MSL rating for these devices are clearly marked on the antistatic bags, which protect these devices from ESD during shipping and handling. Prior to assembly, review the process flow for opportunity to introduce shock levels that exceed the ADIS16220’s absolute maximum ratings. PCB separation (score and snap) and ultrasonic cleaning are two common areas that can introduce high levels of shock to these devices. The ADIS16220/PCBZ provides the ADIS16220 function on a 1.2 inch × 1.3 inch printed circuit board (PCB), which simplifies the connection to an existing processor system. The four mounting holes accommodate either M2 (2mm) or Type 2-56 machine screws. These boards are made of IS410 material and are 0.063 inches thick. The second level assembly uses a SAC305-compatible solder composition (Pb-free), which has a presolder reflow thickness of approximately 0.005 inches. The pad pattern on the ADIS16220/PCBZ matches that shown in Figure 5. J1 and J2 are dual-row, 2 mm (pitch) connectors that work with a number of ribbon cable systems, including 3M Part Number 152212-0100-GB (ribbon-crimp connector) and 3M Part Number 3625/12 (ribbon cable). J1/J2 PIN NUMBERS 1 2 J1 3 4 1 5 6 2 7 8 3 9 10 4 11 12 6 10 ADIS16220CCCZ 9 1 4 2 3 13 11 12 AIN1 SCLK AIN2 CS DIO2 DOUT DIN VDD 16 GND 1.050 a J2 U1 iSensor 4 × Ø0.087 M2×0.4 C1 2 × 0.000 Figure 17. PCB Assembly View and Dimensions 07980-017 2 × 0.900 0.150 0.865 5 7 10 8 11 3 11 12 5 7 9 2 15 10 07980-016 1.100 Figure 16. Electrical Schematic 0.035 2 × 0.000 6 1 8 9 0.200 VREF 12 6 5 Rev. PrE | Page 15 of 16 NC 14 4 8 J1 NC NC 7 2 × 0.673 DIO1 NC C1 2 × 0.925 J2 RST ADIS16220 Preliminary Technical Data OUTLINE DIMENSIONS 5.391 BSC (4×) 2.6955 BSC (8×) 9.35 9.20 SQ 9.05 13 PIN 1 INDICATOR 1.000 BSC (16×) 16 12 1 8.373 BSC (2×) 0.797 BSC (12×) 9 4 8 0.200 MIN (ALL SIDES) TOP VIEW 5 BOTTOM VIEW 0.373 BSC (16×) 5.00 TYP 052609-C 3.90 MAX SIDE VIEW Figure 18. 16-Terminal Stacked Land Grid Array [LGA] (CC-16-2) Dimensions shown in millimeters ORDERING GUIDE Model ADIS16220CCCZ1 ADIS16220/PCBZ1 1 Temperature Range −40°C to +125°C Package Description 16-Terminal Stacked Land Grid Array [LGA] Evaluation Board Z = RoHS Compliant Part. ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07980-0-7/09(PrE) Rev. PrE | Page 16 of 16 Package Option CC-16-2