Precision Four Degrees of Freedom Sensor ADIS16305 Digital gyroscope with range scaling ±75°/sec, ±150°/sec, ±300°/sec settings Triaxis digital accelerometer: ±3 g Wide sensor bandwidth: 330 Hz Autonomous operation and data collection No external configuration commands required Start-up time: 180 ms Sleep mode recovery time: 4 ms Factory-calibrated sensitivity, bias, and alignment Calibration temperature range: −40°C to +85°C SPI-compatible serial interface Embedded temperature sensor Programmable operation and control Automatic and manual bias correction controls Bartlett window FIR filter length, number of taps Digital I/O: data-ready, alarm indicator, general-purpose Alarms for condition monitoring Sleep mode for power management DAC output voltage Enable external sample clock input: up to 1.2 kHz Single-command self-test Single-supply operation: 4.75 V to 5.25 V 2000 g shock survivability Operating temperature range: −40°C to +85°C FUNCTIONAL BLOCK DIAGRAM AUX_ ADC AUX_ DAC TEMPERATURE SENSOR CS MEMS ANGULAR RATE SENSOR TRIAXIS MEMS ACCELERATION SENSOR SCLK SIGNAL CONDITIONING AND CONVERSION CALIBRATION AND DIGITAL PROCESSING OUTPUT REGISTERS AND SPI INTERFACE DIN DOUT ALARMS SELF-TEST DIGITAL CONTROL POWER MANAGEMENT VCC GND ADIS16305 RST DIO1 DIO2 DIO3 DIO4 09020-001 FEATURES Figure 1. APPLICATIONS Medical instrumentation Robotics Platform controls Navigation GENERAL DESCRIPTION The iSensor® ADIS16305 is a complete inertial system that includes a gyroscope and triaxis accelerometer. Each sensor in the ADIS16305 combines industry-leading iMEMS® technology with signal conditioning that optimizes dynamic performance. The factory calibration characterizes each sensor for sensitivity, bias, alignment, and linear acceleration (gyro bias). As a result, each sensor has its own dynamic compensation formulas that provide accurate sensor measurements over a variety of conditions. The ADIS16305 provides a simple, cost-effective method for integrating accurate, multiaxis, inertial sensing into industrial systems, especially when compared with the complexity and investment associated with discrete designs. All necessary motion testing and calibration are part of the production process at the factory, greatly reducing system integration time. Tight orthogonal alignment simplifies inertial frame alignment in navigation systems. An improved SPI interface and register structure provide faster data collection and configuration control. The ADIS16305 uses a pinout that is compatible with the ADIS1635x, ADIS1636x, and ADIS1640x families, when used with an interface flex connector. This compact module is approximately 23 mm × 31 mm × 8 mm and provides a standard connector interface, which enables horizontal or vertical mounting. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved. ADIS16305 TABLE OF CONTENTS Features .............................................................................................. 1 Memory Map .............................................................................. 10 Applications ....................................................................................... 1 Burst Read Data Collection ...................................................... 11 Functional Block Diagram .............................................................. 1 Output Data Registers ............................................................... 11 General Description ......................................................................... 1 Orientation Angles ..................................................................... 12 Revision History ............................................................................... 2 Calibration................................................................................... 13 Specifications..................................................................................... 3 Operational Control................................................................... 13 Timing Specifications .................................................................. 5 Input/Output Functions ............................................................ 15 Absolute Maximum Ratings............................................................ 6 Diagnostics .................................................................................. 16 ESD Caution .................................................................................. 6 Product Identification................................................................ 17 Pin Configuration and Function Descriptions ............................. 7 Applications Information .............................................................. 18 Typical Performance Characteristics ............................................. 8 Interface Printed Circuit Board (PCB) .................................... 18 Theory of Operation ........................................................................ 9 Gyroscope Bias Optimization ................................................... 18 Basic Operation ............................................................................ 9 Outline Dimensions ....................................................................... 19 Reading Sensor Data .................................................................... 9 Ordering Guide .......................................................................... 19 Device Configuration .................................................................. 9 REVISION HISTORY 7/10—Revision 0: Initial Version Rev. 0 | Page 2 of 20 ADIS16305 SPECIFICATIONS TA = 25°C, VCC = 5.0 V, angular rate = 0°/sec, dynamic range = ±300°/sec ± 1 g, unless otherwise noted. Table 1. Parameter GYROSCOPE Dynamic Range Initial Sensitivity Sensitivity Temperature Coefficient Misalignment Nonlinearity Initial Bias Error In-Run Bias Stability Angular Random Walk Bias Temperature Coefficient Linear Acceleration Effect on Bias Voltage Sensitivity Output Noise Rate Noise Density 3 dB Bandwidth Sensor Resonant Frequency Self-Test Change in Output Response ACCELEROMETERS Dynamic Range Initial Sensitivity Sensitivity Temperature Coefficient Misalignment Nonlinearity Initial Bias Error In-Run Bias Stability Velocity Random Walk Bias Temperature Coefficient Output Noise Noise Density 3 dB Bandwidth Sensor Resonant Frequency Self-Test Change in Output Response ADC INPUT Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Input Range Input Capacitance Test Conditions TA = 25°C, dynamic range = ±300°/sec TA = 25°C, dynamic range = ±150°/sec TA = 25°C, dynamic range = ±75°/sec −40°C ≤ TA ≤ +85°C Reference to z-axis accelerometer, TA = 25°C Best-fit straight line TA = 25°C, ±1 σ TA = 25°C, 1 σ, SMPL_PRD = 0x01 TA = 25°C, 1 σ, SMPL_PRD = 0x01 −40°C ≤ TA ≤ +85°C Any axis, 1 σ (MSC_CTRL Bit[7] = 1) VCC = 4.75 V to 5.25 V TA = 25°C, ±300°/sec range, no filtering TA = 25°C, f = 25 Hz, ±300°/sec, no filtering ±300°/sec range setting Each axis 25°C −40°C ≤ TA ≤ +85°C Axis-to-axis, TA = 25°C, Δ = 90° ideal Axis-to-frame (package), TA = 25°C Best-fit straight line TA = 25°C, ±1 σ TA = 25°C, 1 σ, SMPL_PRD = 0x01 TA = 25°C, 1 σ, X axis and Y axis TA = 25°C, 1 σ, Z axis −40°C ≤ TA ≤ +85°C TA = 25°C, no filtering, X axis and Y axis TA = 25°C, no filtering, Z axis TA = 25°C, no filtering, X axis and Y axis TA = 25°C, no filtering, Z axis X axis and Y axis Z axis Min Typ ±300 0.0495 ±350 0.05 0.025 0.0125 20 ±0.1 0.1 ±3 0.006 1.85 0.006 0.02 0.32 0.73 0.04 330 14.5 ±1400 ±696 ±3 0.594 500 90 ±3.6 0.6 25 ±0.1 ±0.5 ±0.3 ±60 0.037 0.1 0.16 0.3 4.25 6.5 225 340 330 5.5 1100 450 Max 0.0505 ±2449 0.606 1700 860 12 ±2 ±1 ±4 ±2 0 During acquisition Rev. 0 | Page 3 of 20 3.3 20 Unit °/sec °/sec/LSB °/sec/LSB °/sec/LSB ppm/°C Degrees % of FS °/sec °/sec °/√hr °/sec/°C °/sec/g °/sec/V °/sec rms °/sec/√Hz rms Hz kHz LSB g mg/LSB ppm/°C Degrees Degrees % of FS mg mg m/sec/√hr m/sec/√hr mg/°C mg rms mg rms μg/√Hz rms μg/√Hz rms Hz kHz LSB LSB Bits LSB LSB LSB LSB V pF ADIS16305 Parameter DAC OUTPUT Resolution Relative Accuracy Differential Nonlinearity Offset Error Gain Error Output Range Output Impedance Output Settling Time LOGIC INPUTS 1 Input High Voltage, VINH Input Low Voltage, VINL Test Conditions 5 kΩ/100 pF to GND Min Typ 12 ±4 ±1 ±5 ±0.5 For Code 101 to Code 4095 0 3.3 2 10 2.0 0.8 0.55 CS signal to wake up from sleep mode CS Wake-Up Pulse Width Logic 1 Input Current, IINH Logic 0 Input Current, IINL All Pins Except RST RST Pin Input Capacitance, CIN DIGITAL OUTPUTS1 Output High Voltage, VOH Output Low Voltage, VOL FLASH MEMORY Data Retention 3 FUNCTIONAL TIMES 4 Power-On Start-Up Time Reset Recovery Time Sleep Mode Recovery Time Flash Memory Test Time Automatic Self-Test Time CONVERSION RATE Clock Accuracy Sync Input Clock POWER SUPPLY Power Supply Current Max 20 VIH = 3.3 V VIL = 0 V ISOURCE = 1.6 mA ISINK = 1.6 mA Endurance 2 TJ = 85°C Time until data is available Normal mode, SMPL_PRD ≤ 0x09 Low power mode, SMPL_PRD ≥ 0x0A Normal mode, SMPL_PRD ≤ 0x09 Low power mode, SMPL_PRD ≥ 0x0A ±10 −40 −1 10 −60 2.4 0.4 10,000 20 180 250 55 120 4 20 90 12 Normal mode, SMPL_PRD ≤ 0x09 Low power mode, SMPL_PRD ≥ 0x0A SMPL_PRD = 0x01 to 0xFF 0.413 Operating voltage range, VCC Low power mode at 25°C Normal mode at 25°C Sleep mode at 25°C 4.75 1 ±0.2 5.0 18 42 500 819.2 ±3 1.2 5.25 Unit Bits LSB LSB mV % V Ω μs V V V μs μA μA mA pF V V Cycles Years ms ms ms ms ms ms ms ms SPS % kHz V mA mA μA The digital I/O signals are driven by an internal 3.3 V supply, and the inputs are 5 V tolerant. Endurance is qualified as per JEDEC Standard 22, Method A117, and measured at −40°C, +25°C, +85°C, and +125°C. 3 The retention lifetime equivalent is at a junction temperature (TJ) of 85°C as per JEDEC Standard 22, Method A117. Retention lifetime decreases with junction temperature. 4 These times do not include thermal settling and internal filter response times (330 Hz bandwidth), which may impact overall accuracy. 2 Rev. 0 | Page 4 of 20 ADIS16305 TIMING SPECIFICATIONS TA = 25°C, VCC = 5 V, unless otherwise noted. Table 2. Normal Mode (SMPL_PRD ≤ 0x09) Min 1 Typ Max 0.01 2.0 9 40 48.8 Parameter fSCLK tSTALL tREADRATE tCS Description Serial clock Stall period between data Read rate Chip select to clock edge tDAV tDSU tDHD tSCLKR, tSCLKF tDR, tDF tSFS t1 tx t2 t3 DOUT valid after SCLK edge DIN setup time before SCLK rising edge DIN hold time after SCLK rising edge SCLK rise/fall times (not shown in figures) DOUT rise/fall times (not shown in figures) CS high after SCLK edge Input sync positive pulse width Input sync low time Input sync to data-ready output Input sync period 1 Low Power Mode (SMPL_PRD ≥ 0x0A) Min1 Typ Max 0.01 0.3 75 100 48.8 100 Burst Read Min1 Typ Max 0.01 1.0 1/fSCLK 48.8 100 24.4 48.8 100 24.4 48.8 5 5 12.5 12.5 24.4 48.8 5 5 5 5 100 12.5 12.5 5 5 5 12.5 12.5 5 5 100 600 600 833 833 Guaranteed by design and characterization, but not tested in production. Timing Diagrams CS tCS tSFS 1 2 3 4 5 6 15 16 SCLK tDAV MSB DB14 DB13 tDSU DIN R/W A6 DB12 DB11 A4 A3 DB10 DB2 DB1 LSB tDHD A5 D2 A2 D1 09020-002 DOUT LSB Figure 2. SPI Timing and Sequence tREADRATE tSTALL 09020-003 CS SCLK Figure 3. Stall Time and Data Rate t3 t2 t1 tX 09020-004 SYNC CLOCK (DIO4) DATA READY Figure 4. Input Clock Timing Diagram Rev. 0 | Page 5 of 20 Unit MHz μs μs ns ns ns ns ns ns ns μs μs μs μs ADIS16305 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Acceleration Any Axis, Unpowered Any Axis, Powered VCC to GND Digital Input Voltage to GND Digital Output Voltage to GND Analog Input to GND Operating Temperature Range Storage Temperature Range Rating 2000 g 2000 g −0.3 V to +6.0 V −0.3 V to +5.3 V −0.3 V to VCC + 0.3 V −0.3 V to +3.6 V −40°C to +85°C −65°C to +125°C 1, 2 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 4. Package Characteristics Package Type 24-Lead Module 1 Extended exposure to temperatures outside the specified temperature range of −40°C to +85°C can adversely affect the accuracy of the factory calibration. For best accuracy, store the parts within the specified operating range of −40°C to +85°C. 2 Although the device is capable of withstanding short-term exposure to 150°C, long-term exposure threatens internal mechanical integrity. ESD CAUTION Rev. 0 | Page 6 of 20 θJA 39.8°C/W θJC 14.2°C/W Device Weight 6.1 grams (max) ADIS16305 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DIO3 SCLK DIN DIO1 DIO2 VCC GND GND DNC DNC AUX_ADC DNC 1 3 5 7 9 11 13 15 17 19 21 23 2 4 6 8 10 12 14 16 18 20 22 24 DIO4/CLKIN DOUT CS RST VCC VCC GND DNC DNC AUX_DAC DNC DNC TOP VIEW (Not to Scale) NOTES 1. MATING CONNECTOR: SAMTEC FTSH-112-03 OR EQUIVALENT. 2. DNC = DO NOT CONNECT. 09020-005 ADIS16305 Figure 5. ADIS16305 Pin Configuration Z-AXIS aZ gZ Y-AXIS X-AXIS aY NOTES 1. THE ARROW DIRECTION ASSOCIATED WITH aZ, aY, AND gZ INDICATES THE DIRECTION OF MOTION THAT PRODUCES A POSITIVE RESPONSE IN EACH ACCELEROMETER AND GYROSCOPE OUTPUT REGISTER. 09020-006 aX Figure 6. Axial Orientation Table 5. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7, 9 8 10, 11, 12 13, 14, 15 16, 17, 18, 19, 22, 23, 24 20 21 1 Mnemonic DIO3 DIO4/CLKIN SCLK DOUT DIN CS DIO1, DIO2 RST VCC GND DNC AUX_DAC AUX_ADC Type 1 I/O I/O I O I I I/O I S S N/A O I Description Configurable Digital Input/Output. Configurable Digital Input/Output or Sync Clock Input. SPI Serial Clock. SPI Data Output. Clocks output on SCLK falling edge. SPI Data Input. Clocks input on SCLK rising edge. SPI Chip Select. Configurable Digital Input/Output. Reset. Power Supply. Power Ground. Do Not Connect. Auxiliary, 12-Bit DAC Output. Auxiliary, 12-Bit ADC Input. I/O is input/output, I is input, O is output, S is supply, and N/A is not applicable. Rev. 0 | Page 7 of 20 ADIS16305 TYPICAL PERFORMANCE CHARACTERISTICS 0.01 ROOT ALLAN VARIANCE (g) 0.1 +1σ 0.01 MEAN 0.001 Z-AXIS 0.0001 X- AND YAXES 0.001 0.1 1 10 100 Tau (sec) 1k 10k Figure 7. Gyroscope Allan Variance 0.00001 0.1 1 10 100 1k Tau (sec) Figure 8. Accelerometer Allan Variance Rev. 0 | Page 8 of 20 10k 09020-008 –1σ 09020-007 ROOT ALLAN VARIANCE (°/sec) 1 ADIS16305 THEORY OF OPERATION BASIC OPERATION The ADIS16305 is an autonomous sensor system that starts up after it has a valid power supply voltage and begins producing inertial measurement data. After each sample cycle, the sensor data is loaded into the output registers, and DIO1 pulses high, which provides a new data-ready control signal for driving system-level interrupt service routines. In a typical system, a master processor accesses the output data registers through the SPI interface, using the connection diagram shown in Figure 9. Table 6 provides a generic functional description for each pin on the master processor. Table 7 describes the typical master processor settings for communicating with the ADIS16305. 15 6 CS SCLK 3 SCLK MOSI 5 DIN MISO 4 DOUT IRQ 7 DIO1 12 SPI SLAVE 7 6 5 4 3 2 Function Slave select Interrupt request Master output, slave input Master input, slave output Serial clock Description ADIS16305 is a slave Normal mode, SMPL_PRD[7:0] ≤ 0x09 CPOL = 1 (polarity), CHPA = 1 (phase) Bit sequence Shift register/data length LOWER BYTE For burst read, SCLK rate ≤ 1 MHz. For low power mode, SCLK rate ≤ 300 kHz. CS DOUT D15 A6 A5 A4 A3 A2 A1 A0 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NOTES 1. DOUT BITS ARE PRODUCED ONLY WHEN THE PREVIOUS 16-BIT DIN SEQUENCE STARTS WITH R/W = 0. Figure 11. SPI Communication Bit Sequence Rev. 0 | Page 9 of 20 R/W D15 A6 A5 D14 D13 09020-011 SCLK R/W 0 The master processor initiates the backup function by setting GLOB_CMD[3] = 1 (DIN = 0xBE04). This command copies the user registers into their assigned flash memory locations and requires the power supply to stay within its normal operating range for the entire 50 ms process. The FLASH_CNT register provides a running count of these events for monitoring the long-term reliability of the flash memory. Table 7. Generic Master Processor SPI Settings DIN 1 The user register memory map (see Table 8) identifies configuration registers with either a W or R/W. Configuration commands also use the bit sequence shown in Figure 11. If the MSB = 1, the last eight bits (DC7 to DC0) in the DIN sequence are loaded into the memory address associated with the address bits (A6 to A0). For example, if DIN = 0xA11F, 0x1F is loaded into Address 0x21 (XACCL_OFF, upper byte) at the conclusion of the data frame. 15 09020-009 14 Table 6. Generic Master Processor Pin Names and Functions 1 8 DEVICE CONFIGURATION Figure 9. Electrical Connection Diagram Processor Setting Master SCLK Rate ≤ 2 MHz1 SPI Mode 3 MSB First Mode 16-Bit Mode 9 The SPI operates in full-duplex mode, which means that the master processor can read the output data from DOUT while using the same SCLK pulses to transmit the next target address on DIN. 13 Pin Name SS IRQ MOSI MISO SCLK 10 Although the ADIS16305 produces data independently, it operates as an SPI slave device that communicates with system (master) processors using the 16-bit segments displayed in Figure 11. Individual register reads require two of these 16-bit sequences. The first 16-bit sequence provides the read command bit (R/W = 0) and the target register address (A6 to A0). The second sequence transmits the register contents (D15 to D0) on the DOUT line. For example, if DIN = 0x0A00, the contents of XACCL_OUT are shifted out on the DOUT line during the next 16-bit sequence. ADIS16305 SS 11 READING SENSOR DATA 5V 11 12 Figure 10. Generic Register Bit Assignments VDD 10 13 UPPER BYTE I/O LINES ARE COMPATIBLE WITH 3.3V OR 5V LOGIC LEVELS SYSTEM PROCESSOR SPI MASTER 14 09020-010 The user registers provide addressing for all input/output operations on the SPI interface. Each 16-bit register has two 7-bit addresses: one for its upper byte and one for its lower byte. Table 8 lists the lower byte address for each register, and Figure 10 shows the generic bit assignments. ADIS16305 MEMORY MAP Table 8. User Register Memory Map Name FLASH_CNT SUPPLY_OUT GYRO_OUT Reserved Reserved XACCL_OUT YACCL_OUT ZACCL_OUT TEMP_OUT PITCH_OUT ROLL_OUT AUX_ADC Reserved GYRO_OFF PITCH_OFF ROLL_OFF XACCL_OFF YACCL_OFF ZACCL_OFF ALM_MAG1 ALM_MAG2 ALM_SMPL1 ALM_SMPL2 ALM_CTRL AUX_DAC GPIO_CTRL MSC_CTRL SMPL_PRD SENS_AVG SLP_CNT DIAG_STAT GLOB_CMD Reserved LOT_ID1 LOT_ID2 PROD_ID SERIAL_NUM 1 2 R/W R R R N/A2 N/A2 R R R R R R R N/A2 R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W R W N/A2 R R R R Flash Backup Yes No No N/A2 N/A2 No No No No No No No N/A2 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No Yes Yes Yes No No N/A2 N/A2 Yes Yes Yes Yes Address 1 0x00 0x02 0x04 0x06 0x08 0x0A 0x0C 0x0E 0x10 0x12 0x14 0x16 0x18 0x1A 0x1C 0x1E 0x20 0x22 0x24 0x26 0x28 0x2A 0x2C 0x2E 0x30 0x32 0x34 0x36 0x38 0x3A 0x3C 0x3E 0x40 to 0x51 0x52 0x54 0x56 0x58 Default N/A 2 N/A2 N/A2 N/A2 N/A2 N/A2 N/A2 N/A2 N/A2 N/A2 N/A2 N/A2 N/A2 0x0000 N/A2 N/A2 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0006 0x0001 0x0402 0x0000 0x0000 0x0000 N/A2 N/A2 N/A2 0x3FB1 N/A2 Register Description Flash memory write count Power supply measurement Gyroscope output Reserved Reserved X-axis accelerometer output Y-axis accelerometer output Z-axis accelerometer output Gyroscope temperature measurement Pitch angle output (x-axis) Roll angle output (y-axis) Auxiliary ADC output Reserved Gyroscope bias offset factor Pitch angle offset factor Roll angle offset factor X-axis acceleration bias offset factor Y-axis acceleration bias offset factor Z-axis acceleration bias offset factor Alarm 1 amplitude threshold Alarm 2 amplitude threshold Alarm 1 sample size Alarm 2 sample size Alarm control Auxiliary DAC data Auxiliary digital input/output control Miscellaneous control: data-ready, self-test Internal sample period (rate) control Dynamic range and digital filter control Sleep mode control System status System command Reserved Lot Identification Code 1 Lot Identification Code 2 Product identification Serial number Bit Function See Table 28 See Table 9 See Table 9 N/A2 N/A2 See Table 9 See Table 9 See Table 9 See Table 9 See Table 9 See Table 9 See Table 9 N/A2 See Table 16 See Table 18 See Table 18 See Table 17 See Table 17 See Table 17 See Table 30 See Table 30 See Table 31 See Table 31 See Table 32 See Table 25 See Table 23 See Table 24 See Table 20 See Table 22 See Table 21 See Table 29 See Table 19 N/A2 See Table 35 See Table 35 See Table 35 See Table 35 Each register contains two bytes. The address of the lower byte is displayed. The address of the upper byte is equal to the address of the lower byte plus 1. N/A stands for not applicable. Rev. 0 | Page 10 of 20 ADIS16305 BURST READ DATA COLLECTION Gyroscopes Burst read data collection is a process-efficient method for collecting data from the ADIS16305. In burst read, all output registers are clocked out on DOUT, 16 bits at a time, in sequential data cycles (each separated by one SCLK period). To start a burst read sequence, set DIN = 0x3E00. The contents of each output register are then shifted out on DOUT, starting with SUPPLY_OUT and ending with AUX_ADC (see Figure 13). The addressing sequence shown in Table 8 determines the order of the outputs in burst read. The gyroscope output register, GYRO_OUT, uses a 14-bit, twos complement digital format. When using the factory-default range of ±300°/sec, each LSB translates into 0.05°/sec. Table 10 offers some examples for translating the digital data into rotation rate measurements. When the dynamic rage is set to ±150°/sec, divide the rotation rate numbers in Table 10 by a factor of two. When the dynamic rage is set to ±75°/sec, divide the rotation rate numbers in Table 10 by a factor of four. OUTPUT DATA REGISTERS Table 10. Rotation Rate, Twos Complement Format Each output data register uses the format in Figure 12 and Table 9. Figure 6 shows the positive direction for each inertial sensor. The ND bit is equal to 1 when the register contains unread data. The EA bit is high when any error/alarm flag in the DIAG_STAT register is equal to 1. Rotation Rate +300°/sec +0.1°/sec +0.05°/sec 0°/sec −0.05°/sec −0.1°/sec −300°/sec MSB FOR 14-BIT OUTPUT 09020-012 ND EA MSB FOR 12-BIT OUTPUT Figure 12. Output Register Bit Assignments 1 2 Address 0x02 0x04 0x0A 0x0C 0x0E 0x10 0x12 0x14 0x16 Scale Power supply Gyroscope Acceleration (x) Acceleration (y) Acceleration (z) Temperature Pitch angle Roll angle ADC measurement Hex 0x1770 0x0002 0x0001 0x0000 0x3FFF 0x3FFE 0x2890 Binary XX01 0111 0111 0000 XX00 0000 0000 0010 XX00 0000 0000 0001 XX00 0000 0000 0000 XX11 1111 1111 1111 XX11 1111 1111 1110 XX10 1000 1001 0000 Accelerometers Table 9. Output Data Register Formats Name SUPPLY_OUT GYRO_OUT1 XACCL_OUT YACCL_OUT ZACCL_OUT TEMP_OUT2 PITCH_OUT ROLL_OUT AUX_ADC Decimal +6000 LSB +2 LSB +1 LSB 0 LSB −1 LSB −2 LSB −6000 LSB The accelerometer output registers, XACCL_OUT, YACCL_OUT, and ZACCL_OUT, use a 14-bit, twos complement digital format. Table 11 offers some examples for translating the digital data into linear acceleration measurements Reference Table 13 Table 10 Table 11 Table 11 Table 11 Table 14 Table 12 Table 12 Table 15 Table 11. Acceleration, Twos Complement Format Acceleration +3.3 g +1.2 mg +0.6 mg 0g −0.6 mg −1.2 mg −3.3 g Assumes that the scaling is set to ±300°/sec. This factor scales with the range. 0x0000 = 25°C (±5°C). Decimal +5500 LSB +2 LSB +1 LSB 0 LSB −1 LSB −2 LSB −5500 LSB Hex 0x157C 0x0002 0x0001 0x0000 0x3FFF 0x3FFE 0x2A84 Binary XX01 0101 0111 1100 XX00 0000 0000 0010 XX00 0000 0000 0001 XX00 0000 0000 0000 XX11 1111 1111 1111 XX11 1111 1111 1110 XX10 1010 1000 0100 Note that the codes in Table 10, Table 11, Table 12, Table 13, Table 14, and Table 15 assume typical sensitivity values. CS 1 2 3 4 5 9 GYRO_OUT XACCL_OUT YACCL_OUT ROLL_OUT 10 SCLK DOUT 0x3E00 PREVIOUS DON’T CARE SUPPLY_OUT Figure 13. Burst Read Sequence Rev. 0 | Page 11 of 20 AUX_ADC 09020-013 DIN ADIS16305 ORIENTATION ANGLES Table 13. Power Supply, Offset Binary Format The ROLL_OUT and PITCH_OUT registers provide a tilt angle calculation based on the accelerometer measurements. The zero reference is the point at which the z-axis faces gravity for a north-east-down (NED) configuration. Table 12 displays a number of examples for the 13-bit, twos complement digital format in both of these registers. Figure 14 provides the physical references and formulas that produce these orientation angles. Supply Voltage 5.25 V 5.002418 V 5V 4.997582 V 4.75 V Decimal 2171 LSB 2069 LSB 2068 LSB 2067 LSB 1964 LSB Hex 0x87B 0x815 0x814 0x813 0x7AC Binary XXXX 1000 0111 1011 XXXX 1000 0001 0101 XXXX 1000 0001 0100 XXXX 1000 0001 0011 XXXX 0111 1010 1100 Internal Temperature Table 12. Orientation Angles, Twos Complement Format Angle +180° +90 +0.088° +0.044° 0° −0.044° −0.088° −90° −179.96° Decimal +4091 +2045 +2 LSB +1 LSB 0 LSB −1 −2 −2045 −4090 Hex 0x0FFB 0x07FD 0x0002 0x0001 0x0000 0x1FFF 0x1FFE 0x1803 0x1006 The TEMP_OUT register provides an internal measurement for temperature and uses 12-bit, twos complement for its digital format. Table 14 provides several numerical examples of this format. This is an internal temperature measurement, which can vary from ambient conditions outside of the package. Binary XXX0 1111 1111 1011 XXX0 0111 1111 1101 XXX0 0000 0000 0010 XXX0 0000 0000 0001 XXX0 0000 0000 0000 XXX1 1111 1111 1111 XXX1 1111 1111 1110 XXX1 1000 0000 0011 XXX1 0000 0000 0110 Table 14. Temperature, Twos Complement Format Temperature +105°C +85°C +25.272°C +25.136°C +25°C +24.864°C +24.728°C −40°C Z-AXIS aZ aY Hex 0x24C 0x1B9 0x002 0x001 0x000 0xFFF 0xFFE 0xE22 Binary XXXX 0010 0100 1100 XXXX 0001 1011 1001 XXXX 0000 0000 0010 XXXX 0000 0000 0001 XXXX 0000 0000 0000 XXXX 1111 1111 1111 XXXX 1111 1111 1110 XXXX 1110 0010 0010 Analog Input (ADC) φROLL The AUX_ADC register provides access to the auxiliary ADC input channel measurements and uses 12-bit, offset binary as its digital format. The ADC is a 12-bit successive approximation converter that has an input circuit equivalent to the one shown in Figure 15. The maximum input is 3.3 V. The ESD protection diodes can handle 10 mA without causing irreversible damage. The on resistance (R1) of the switch has a typical value of 100 Ω. The sampling capacitor, C2, has a typical value of 16 pF. FRONT VIEW Y-AXIS φROLL = ROLL_OUT = a TAN Decimal +588 LSB +441 LSB +2 LSB +1 LSB 0 LSB −1 LSB −2 LSB −478 LSB aY aZ Z-AXIS aZ VCC D φPITCH R1 C2 aX X-AXIS Figure 15. Equivalent Analog Input Circuit (Conversion Phase: Switch Open, Track Phase: Switch Closed) 09020-014 φPITCH = PITCH_OUT = a TAN –aX aY × SIN (ΦROLL) + aZ COS (ΦROLL) D 09020-015 C1 SIDE VIEW Figure 14. Orientation for PITCH_OUT and ROLL_OUT Angles Power Supply Table 15. ADC Measurement, Offset Binary Format The SUPPLY_OUT register provides an internal measurement for the power supply voltage and uses a 12-bit, offset binary digital format. Table 13 provides several numerical examples of this format. Input Voltage 3.3 V 1V 1.6118 mV 805.9 μV 0V Rev. 0 | Page 12 of 20 Decimal 4095 LSB 1241 LSB 2 LSB 1 LSB 0 LSB Hex 0xFFF 0x4D9 0x002 0x001 0x000 Binary XXXX 1111 1111 1111 XXXX 0100 1101 1001 XXXX 0000 0000 0010 XXXX 0000 0000 0001 XXXX 0000 0000 0000 ADIS16305 CALIBRATION Linear Acceleration Bias Compensation (Gyroscope) Manual Bias Calibration Set MSC_CTRL[7] = 1 (DIN = 0xB486) to enable correction for low frequency acceleration influences on gyroscope bias. Note that the DIN sequence also preserves the factory default condition for the data-ready function (see Table 24). The bias offset registers in Table 16 and Table 17 provide a manual adjustment function for the output of each sensor. For example, if GYRO_OFF = 0x1FF6 (DIN = 0x9B1F, 0x9AF6), the GYRO_OUT offset shifts by −10 LSBs, or −0.125°/sec. OPERATIONAL CONTROL Table 16. GYRO_OFF Bit Descriptions Global Commands Bits [15:13] [12:0] The GLOB_CMD register provides trigger bits for several useful functions. Setting the assigned bit to 1 starts each operation, which returns the bit to 0 after completion. For example, set GLOB_CMD[7] = 1 (DIN = 0xBE80) to execute a software reset, which stops the sensor operation and runs the device through its start-up sequence. This sequence includes loading the control registers with their respective flash memory locations prior to producing new data. Reading the GLOB_CMD register (DIN = 0x3E00) starts the burst read sequence. Description (Default = 0x0000) Not used. Data bits. Twos complement, 0.0125°/sec per LSB. Typical adjustment range = ±50°/sec. Table 17. XACCL_OFF, YACCL_OFF, ZACCL_OFF Bit Descriptions Bits [15:12] [11:0] Description (Default = 0x0000) Not used. Data bits. Twos complement, 0.6 mg/LSB. Typical adjustment range = ±1.22 g. Table 19. GLOB_CMD Bit Descriptions Frame Alignment The PITCH_OFF and ROLL_OFF registers (see Table 18) provide the angular orientation difference between the inertial frame (internal) and the external frame (package). They follow the same orientation as PITCH_OUT and ROLL_OUT, as shown in Figure 14. Table 18. PITCH_OFF, ROLL_OFF Bit Descriptions Bits [15:10] [9:0] Description Not used. Data bits. Twos complement, 0.014°/LSB. Bit(s) [15:8] [7] [6:5] [4] [3] [2] [1] [0] Description Not used Software reset command Not used Precision autonull command Flash update command Auxiliary DAC data latch Factory calibration restore command Autonull command Internal Sample Rate Gyroscope Automatic Bias Null Calibration Set GLOB_CMD[0] = 1 (DIN = 0xBE01) to execute the automatic bias null calibration function. This function measures the gyroscope output register and then loads the gyroscope offset register with the opposite value to provide a quick bias calibration. All sensor data is then reset to 0, and the flash memory is updated automatically within 50 ms (see Table 19). Gyroscope Precision Automatic Bias Null Calibration Set GLOB_CMD[4] = 1 (DIN = 0xBE10) to execute the precision automatic bias null calibration function. This function takes the sensor offline for 30 sec while it collects a set of data and calculates more accurate bias correction factors for each gyroscope. After this function is executed, the newly calculated correction factor is loaded into the gyroscope offset registers, all sensor data is reset to 0, and the flash memory is updated automatically within 50 ms (see Table 19). Restoring Factory Calibration Set GLOB_CMD[1] = 1 (DIN = 0xBE02) to execute the factory calibration restore function. This function resets each user calibration register to 0x0000 (see Table 16 and Table 17), resets all sensor data to 0, and automatically updates the flash memory within 50 ms (see Table 19). The SMPL_PRD register provides discrete sample rate settings using the bit assignments in Table 20 and the following equation: tS = tB × (NS + 1) For example, when SMPL_PRD[7:0] = 0x0A, the sample rate is 149 SPS. Table 20. SMPL_PRD Bit Descriptions Bit(s) [15:8] [7] [6:0] Description (Default = 0x0001) Not used Time base (tB) 0 = 0.61035 ms, 1 = 18.921 ms Increment setting (NS) Internal sample period = tS = tB × (NS + 1) The default sample rate setting of 819.2 SPS provides optimal performance. For systems that value slower sample rates, keep the internal sample rate at 819.2 SPS. Use the programmable filter (SENS_AVG) to reduce the bandwidth, which helps to prevent aliasing. The data-ready function (MSC_CTRL) can drive an interrupt routine that uses a counter to help ensure data coherence at reduced rates. Rev. 0 | Page 13 of 20 ADIS16305 0 Power Management –20 –40 MAGNITUDE (dB) The SENS_AVG[10:8] bits provide three dynamic range settings for this gyroscope. The lower dynamic range settings (±75°/sec and ±150°/sec) limit the minimum filter tap sizes to maintain resolution. For example, set SENS_AVG[10:8] = 010 (DIN = 0xB902) for a measurement range of ±150°/sec. Because this setting can influence the filter settings, program SENS_AVG[10:8] and then SENS_AVG[2:0] if more filtering is required. Table 22. SENS_AVG Bit Descriptions N LPF 757Hz N 1 Dynamic Range Bit(s) [15:11] [10:8] N LPF 330Hz N = 2m m = SENS_AVG[2:0] 09020-016 FROM ACCELERATION SENSOR 0.1 Figure 17. Bartlett Window, FIR Filter Frequency Response (Phase Delay = N Samples) The signal chain for each MEMS sensor has several filter stages, which shape their frequency response. Figure 16 provides a block diagram for both gyroscope and accelerometer signal paths. Table 22 provides additional information for digital filter configuration. N 0.01 FREQUENCY (Ratio) Sensor Bandwidth LPF 404Hz N=2 N=4 N = 16 N = 64 –120 –140 0.001 Description Not used Indefinite sleep mode; set to 1 Programmable sleep time bits, 0.5 sec/LSB FROM GYROSCOPE SENSOR –80 –100 Table 21. SLP_CNT Bit Descriptions Bit(s) [15:9] [8] [7:0] –60 09020-017 Setting SMPL_PRD ≥ 0x0A also sets the sensor to low power mode. For systems that require lower power dissipation, insystem characterization helps users to quantify the associated performance trade-offs. In addition to sensor performance, this mode affects SPI data rates (see Table 2). Set SLP_CNT[8] = 1 (DIN = 0xBB01) to start the indefinite sleep mode, which requires a CS assertion (high to low), reset, or power cycle to wake up. Use SLP_CNT[7:0] to put the device into sleep mode for a specified period. For example, SLP_CNT[7:0] = 0x64 (DIN = 0xBA64) puts the ADIS16305 to sleep for 50 sec. Figure 16. MEMS Analog and Digital Filters Digital Filtering The N blocks in Figure 16 are part of the programmable lowpass filter, which provides additional noise reduction on the inertial sensor outputs. This filter contains two cascaded averaging filters that provide a Bartlett window, FIR filter response (see Figure 17). For example, set SENS_AVG[2:0] = 100 (DIN = 0xB804) to set each stage to 16 taps. When used with the default sample rate of 819.2 SPS, this value reduces the sensor bandwidth to approximately 16 Hz. [7:3] [2:0] Rev. 0 | Page 14 of 20 Description Not used Measurement range (sensitivity) selection 100 = ±300°/sec (default condition) 010 = ±150°/sec, filter taps ≥ 4 (Bits[2:0] ≥ 0x02) 001 = ±75°/sec, filter taps ≥ 16 (Bits[2:0] ≥ 0x04) Not used Number of taps in each stage, N = 2M; maximum setting = 6 (110), N = 26 = 64 taps/stage ADIS16305 INPUT/OUTPUT FUNCTIONS Table 24. MSC_CTRL Bit Descriptions General-Purpose I/O Bit(s) [15:12] [11] DIO1, DIO2, DIO3, and DIO4 are configurable, general-purpose I/O lines that serve multiple purposes according to the following control register priority: MSC_CTRL, ALM_CTRL, and GPIO_CTRL. For example, set GPIO_CTRL = 0x080C (DIN = 0xB20C, and then 0xB308) to configure DIO1 and DIO2 as inputs and DIO3 and DIO4 as outputs, with DIO3 set low and DIO4 set high. [10] [9] [8] In this configuration, read GPIO_CTRL (DIN = 0x3200) to monitor the digital state of DIO1 and DIO2. [7] Table 23. GPIO_CTRL Bit Descriptions Bit(s) [15:12] [11] [10] [9] [8] [7:4] [3] [2] [1] [0] [6] Description Not used General-Purpose I/O Line 4 (DIO4) data level General-Purpose I/O Line 3 (DIO3) data level General-Purpose I/O Line 2 (DIO2) data level General-Purpose I/O Line 1 (DIO1) data level Not used General-Purpose I/O Line 4 (DIO4) direction control (1 = output, 0 = input) General-Purpose I/O Line 3 (DIO3) direction control (1 = output, 0 = input) General-Purpose I/O Line 2 (DIO2) direction control (1 = output, 0 = input) General-Purpose I/O Line 1 (DIO1) direction control (1 = output, 0 = input) [5:3] [2] [1] [0] Description Not used Memory test (cleared upon completion) (1 = enabled, 0 = disabled) Internal self-test enable (cleared upon completion) (1 = enabled, 0 = disabled) Manual self-test, negative stimulus (1 = enabled, 0 = disabled) Manual self-test, positive stimulus (1 = enabled, 0 = disabled) Linear acceleration bias compensation for gyroscopes (1 = enabled, 0 = disabled) Point of percussion alignment, accelerometer (1 = enabled, 0 = disabled) Not used Data ready enable (1 = enabled, 0 = disabled) Data ready polarity (1 = active high, 0 = active low) Data ready line select (1 = DIO2, 0 = DIO1) Auxiliary DAC Input Clock Configuration The input clock function allows for external control oversampling in the ADIS16305. Set SMPL_PRD[7:0] = 0x00 (DIN = 0xB600) to enable this function. See Table 2 and Figure 4 for timing information. Data-Ready I/O Indicator The factory default sets DIO1 as a positive data-ready indicator signal. The MSC_CTRL[2:0] bits provide configuration options for changing the default. For example, set MSC_CTRL[2:0] = 100 (DIN = 0xB404) to change the polarity of the data-ready signal on DIO1 for interrupt inputs that require negative logic inputs for activation. The pulse width is between 100 μs and 200 μs over all conditions. The 12-bit AUX_DAC line can drive its output to within 5 mV of the ground reference when it is not sinking current. As the output approaches 0 V, the linearity begins to degrade (~100 LSB beginning point). As the sink current increases, the nonlinear range increases. The DAC latch command moves the values of the AUX_DAC register into the DAC input register, enabling both bytes to take effect at the same time. Table 25. AUX_DAC Bit Descriptions Bits [15:12] [11:0] Description Not used Data bits, scale factor = 0.8059 mV/LSB Offset binary format, 0 V = 0 LSB Table 26. Setting AUX_DAC = 1 V DIN 0xB0D9 0xB104 0xBE04 Rev. 0 | Page 15 of 20 Description AUX_DAC[7:0] = 0xD9 (217 LSB). AUX_DAC[15:8] = 0x04 (1024 LSB). GLOB_CMD[2] = 1. Move values into the DAC input register, resulting in a 1 V output level. ADIS16305 DIAGNOSTICS Table 28. FLASH_CNT Bit Descriptions Self-Test Bits [15:0] Description Binary counter for writing to flash memory 600 RETENTION (Years) 450 300 150 0 0x0400 0xB502 0x0400 0xB501 0x0400 0xB500 While the self-test still functions when the device is in motion, zero motion typically produces the most reliable results. The settings in Table 27 are flexible and allow for optimization around speed and noise influence. For example, using fewer filtering taps decreases delay times but increases the possibility of noise influence. The FLASH_CNT register (see Table 28) provides a tool for managing the flash memory’s endurance. The FLASH_CNT register increments every time there is a write to the flash memory. Figure 18 quantifies the relationship between data retention and junction temperature. 55 70 85 100 125 135 150 Figure 18. Flash/EE Memory Data Retention Description SMPL_PRD[7:0] = 0x01, sample rate = 819.2 SPS SENS_AVG[15:8] = 0x04, gyro range = ±300°/sec SENS_AVG[7:0] = 0x02, four-tap averaging filter Delay = 50 ms Read GYRO_OUT MSC_CTRL[9] = 1, gyroscope negative self-test Delay = 50 ms Read GYRO_OUT Determine whether the bias in the gyroscope output changed according to the self-test response specified in Table 1 MSC_CTRL[9:8] = 01, gyroscope/accelerometer positive self-test Delay = 50 ms Read GYRO_OUT Determine whether the bias in the gyroscope output changed according to the self-test response specified in Table 1 MSC_CTRL[15:8] = 0x00 Flash Memory Management 40 JUNCTION TEMPERATURE (°C) Table 27. Manual Self-Test Example Sequence DIN 0xB601 0xB904 0xB802 30 09020-018 The self-test function allows the user to verify the mechanical integrity of each MEMS sensor. It applies an electrostatic force to each sensor element, which results in mechanical displacement that simulates a response to actual motion. Table 1 lists the expected response for each sensor, which provides pass/fail criteria. Set MSC_CTRL[10] = 1 (DIN = 0xB504) to run the internal self-test routine, which exercises all inertial sensors, measures each response, makes pass/fail decisions, and reports them to error flags in the DIAG_STAT register. This process takes 35 ms to complete and report the results to DIAG_STAT[5], DIAG_STAT[10], and DIAG_STAT[15:13]. MSC_CTRL[10] resets itself to 0 after completing the routine. The MSC_CTRL[9:8] bits provide manual control over the self-test function for investigation of potential failures. Table 27 outlines an example test flow for using this option to verify the gyroscope function. Checksum Test Set MSC_CTRL[11] = 1 (DIN = 0x9D08) to verify the flash memory integrity against the factory check sum and read DIAG_STAT[6] to check the results 20 ms after the command. Status The error flags provide indicator functions for common system level issues. All of the flags are cleared (set to 0) after each DIAG_STAT register read cycle. If an error condition remains, the error flag returns to 1 during the next sample cycle. The DIAG_STAT[1:0] bits do not require a read of this register to return to 0. If the power supply voltage goes back into range, these two flags are cleared automatically. Table 29. DIAG_STAT Bit Descriptions Bit(s) [15] [14] [13] [12:11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] 1 Description Z-axis accelerometer self-test failure (1 = fail, 0 = pass) Y-axis accelerometer self-test failure (1 = fail, 0 = pass) X-axis accelerometer self-test failure (1 = fail, 0 = pass) Not used Gyroscope self-test failure (1 = fail, 0 = pass) Alarm 2 status (1 = active, 0 = inactive) Alarm 1 status (1 = active, 0 = inactive) Not used Flash test, checksum flag (1 = fail, 0 = pass) Self-test diagnostic error flag (1 = fail, 0 = pass) Sensor overrange (1 = fail, 0 = pass) SPI communication failure (1 = fail, 0 = pass)1 Flash update failure (1 = fail, 0 = pass) Power supply > 5.25 V (1 = power supply > 5.25 V, 0 = power supply ≤ 5.25 V) Power supply < 4.75 V (1 = power supply < 4.75 V, 0 = power supply ≥ 4.75 V) The SPI error flag in DIAG_STAT[3] goes to 1 when the number of SCLKs is not equal to an integer multiple of 16. Rev. 0 | Page 16 of 20 ADIS16305 Alarm Registers The alarm function provides monitoring for two independent conditions. The ALM_CTRL register provides control inputs for trigger source, data filtering (prior to comparison), static comparison, dynamic rate-of-change comparison, and output indicator configurations. The ALM_MAGx registers establish the trigger threshold and polarity configurations. Table 33 gives an example of how to configure a static alarm. The ALM_SMPLx registers provide the number of samples to use in the dynamic rate-of-change configuration. The period equals the number in the ALM_SMPLx register multiplied by the sample period time, which is established by the SMPL_PRD register. See Table 34 for an example of how to configure the sensor for this type of function. Table 30. ALM_MAG1, ALM_MAG2 Bit Descriptions Bit(s) [15] [14] [13:0] Description Comparison polarity (1 = greater than, 0 = less than) Not used Data, matches the format of the trigger source Table 33. Alarm Configuration Example 1 DIN 0xAF55, 0xAE17 0xA783, 0xA641 0xA93C, 0xA8BF Table 34. Alarm Configuration Example 2 DIN 0xAF76, 0xAEC7 Table 31. ALM_SMPL1, ALM_SMPL2 Bit Descriptions 0xB601 Bits [15:8] [7:0] 0xAA08 Description Not used Data bits: number of samples (both 0x00 and 0x01 = 1) 0xAC50 Table 32. ALM_CTRL Bit Designations Bits [15:12] Value 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 [11:8] [7] [6] [5] [4] [3] [2] [1] [0] 1 Description Alarm 2 trigger source selection Disable Power supply output Gyroscope output Not used Not used X-axis accelerometer output Y-axis accelerometer output Z-axis accelerometer output Temperature output Pitch angle output Roll angle output Auxiliary ADC measurement Alarm 1 trigger source selection (see Bits[15:12]) Rate of change (ROC) enable for Alarm 2 1 = rate of change, 0 = static level Rate of change (ROC) enable for Alarm 1 1 = rate of change, 0 = static level Not used Comparison data filter setting1 1 = filtered data, 0 = unfiltered data Not used Alarm output enable (1 = enable, 0 = disable) Alarm output polarity (1 = high, 0 = low) Alarm output line select (1 = DIO2, 0 = DIO1) Description ALM_CTRL = 0x5517 Alarm 1 input = XACCL_OUT Alarm 2 input = XACCL_OUT Static level comparison, filtered data DIO2 output indicator, positive polarity ALM_MAG1 = 0x8341 Alarm 1 is true if XACCL_OUT > +0.5 g ALM_MAG2 = 0x3CBF Alarm 2 is true if XACCL_OUT < −0.5 g 0xA783, 0xA641 0xA93C, 0xA8BF Description ALM_CTRL = 0x76C7 Alarm 1 input = YACCL_OUT Alarm 2 input = ZACCL_OUT Rate-of-change comparison, unfiltered data DIO2 output indicator, positive polarity SMPL_PRD = 0x0001 Sample rate = 819.2 SPS ALM_SMPL1 = 0x0008 Alarm 1 rate-of-change period = 9.77 ms ALM_SMPL2 = 0x0050 Alarm 2 rate-of-change period = 97.7 ms ALM_MAG1 = 0x8341 Alarm 1 is true when Δ XACCL_OUT > 0.5 g over a period of 9.77 ms ALM_MAG2 = 0x3CBF Alarm 1 is true when Δ XACCL_OUT < −0.5 g over a period of 97.7 ms PRODUCT IDENTIFICATION Table 35 provides a summary of the registers that identify the product: PROD_ID, which identifies the product type; LOT_ID1 and LOT_ID2, the 32-bit lot identification code; and SERIAL_NUM, which displays the 12-bit serial number. All four registers are two bytes in length. When using the SERIAL_NUM value to calculate the serial number, mask off the upper four bits and convert the remaining 12 bits to a decimal number. Table 35. Identification Registers Register Name LOT_ID1 LOT_ID2 PROD_ID SERIAL_NUM Incline outputs (pitch, roll) always use filtered data in this comparison. Rev. 0 | Page 17 of 20 Address 0x52 0x54 0x56 0x58 Description Lot Identification Code 1 Lot Identification Code 2 ADIS16305: 0x3FB1 (16,305) Serial number, 0 to 4095 ADIS16305 APPLICATIONS INFORMATION INTERFACE PRINTED CIRCUIT BOARD (PCB) GYROSCOPE BIAS OPTIMIZATION The ADIS16305/PCBZ includes one ADIS16305ALMZ, one interface PCB, and one interface flex. This combination simplifies the process of prototype connections of the ADIS16305AMLZ with an existing processor system. The factory calibration addresses initial bias errors along with temperature-dependent bias behaviors. Installation and certain environmental conditions can introduce modest bias errors. The precision autonull command provides a simple predeployment method for correcting these errors to an accuracy of approximately 0.008°/sec, using an average of 30 sec. Set GLOB_CMD[4] = 1 (DIN = BE10) to start this operation. Averaging the sensor output data for 100 sec can provide incremental performance gains, as well. Controlling device rotation, power supply, and temperature during these averaging times helps to ensure optimal accuracy during this process. Refer to the AN-1041 Application Note for more information about optimizing performance. J1 and J2 are dual-row, 2 mm (pitch) connectors that work with a number of ribbon cable systems, including 3M Part Number 152212-0100-GB (ribbon crimp connector) and 3M Part Number 3625/12 (ribbon cable). Figure 19 provides a hole pattern design for installing the ADIS16305/PCBZ so that the flex fits well in between the ADIS16305AMLZ and the interface PCB. Figure 20 provides the pin assignments for each connector, and the pin descriptions match those listed in Table 5. The ADIS16305 does not require external capacitors for normal operation; therefore, the interface PCB does not use the C1/C2 pads (not shown in Figure 19). 33.77 23.75 3.30 × 4 2.20 × 2 27.00 12 11 2 1 J1 12 11 2 1 J2 15.05 30.10 09020-019 13.50 ADIS16305AMLZ SCF-140379-01 INTERFACE PCB Figure 19. Physical Diagram for Mounting the ADIS16305/PCBZ J1 1 2 SCLK AUX_ADC 1 2 GND CS 3 4 DOUT AUX_DAC 3 4 DIO3 DNC 5 6 DIN GND 5 6 DIO4 GND 7 8 GND DNC 7 8 DNC GND 9 10 VCC DNC 9 10 DNC VCC 11 12 VCC DIO2 11 12 DIO1 09020-020 J2 RST Figure 20. J1/J2 Pin Assignments for Interface PCB Rev. 0 | Page 18 of 20 ADIS16305 OUTLINE DIMENSIONS 31.25 31.00 30.75 13.60 13.50 13.40 13.60 13.50 13.40 2.20 THRU HOLE (2 PLACES) 23.25 23.00 22.75 9.13 8.88 8.63 15.24 TOP VIEW DETAIL A 13.97 7.82 6.55 6.30 6.05 8.00 MAX 1.27 3.05 0.64 2.55 2.30 2.05 END VIEW 1.27 BSC CONNECTOR PITCH 04-06-2010-A DETAIL A Figure 21. 24-Lead Module with Connector Interface (ML-24-4) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADIS16305AMLZ ADIS16305/PCBZ 1 Temperature Range −40°C to +85°C Package Description 24-Lead Module with Connector Interface Interface Board Z = RoHS Compliant Part. Rev. 0 | Page 19 of 20 Package Option ML-24-4 ADIS16305 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09020-0-7/10(0) Rev. 0 | Page 20 of 20