FEATURES Dual-mode inclinometer system Dual–axis, inclinometer configuration, ±30° Single-axis, vertical operation, ±180° High accuracy, 0.1° 14-bit digital inclination data, 0.025° resolution 14-bit digital acceleration data, 0.244 mg resolution ±1.7 g accelerometer measurement range 12-bit digital temperature sensor output Digitally controlled sensitivity and bias calibration Digitally controlled sample rate Digitally controlled frequency response Dual alarm settings with rate/threshold limits Auxiliary digital I/O Digitally activated self test Digitally activated low power mode SPI-compatible serial interfaceAuxiliary 12-bit ADC input and DAC output Single-supply operation: +3.0 V to +3.6 V 3500 g powered shock survivability FUNCTIONAL BLOCK DIAGRAM AUX ADC AUX DAC VREF ADIS16209 TEMPERATURE SENSOR DUAL-AXIS ACCELEROMETER SIGNAL CONDITIONING AND CONVERSION CALIBRATION AND DIGITAL PROCESSING DIGITAL CONTROL SELF-TEST CS SPI PORT SCLK DIN DOUT VDD POWER MANAGEMENT ALARMS AUXILIARY I/O GND RST DIO1 DIO2 07096-001 Preliminary Technical Data High-Accuracy, Dual-Axis Digital Inclinometer and Accelerometer ADIS16209 Figure 1. APPLICATIONS Platform control, stabilization, and alignment Tilt sensing, inclinometers, leveling Motion/position measurement Monitor/alarm devices (security, medical, safety) Navigation GENERAL DESCRIPTION The ADIS16209 is a high-accuracy, digital inclinometer, that accommodates both single axis (±180°) and dual-axis (±30°) operation. The standard supply voltage (+3.3 V) and SPI® serial interface enable simple integration into most industrial system designs. A simple internal register structure handles all output data and configuration features. This includes access to the following output data: • • Programmable alarm conditions Configurable operating parameters include • Sample rate • Power management • Digital filtering • Auxiliary analog and digital output Calibrated acceleration • Offset/null adjustment Self-test, for sensor’s mechanical structure • Accurate incline angles • • Power supply • Internal temperature • Auxiliary analog and digital input signals • Diagnostic error flags The ADIS16209 is available in a 9.2 mm × 9.2 mm × 3.9mm LGA package that operates over a temperature range of −40°C to +125°C. It is capable of being attached using standard RoHScompliant solder reflow processes. Rev. PrA Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. ADIS16209 Preliminary Technical Data TABLE OF CONTENTS Features .............................................................................................. 1 Recommended Pad Geometry ....................................................7 Applications ....................................................................................... 1 Typical Performance Characteristics ..............................................8 Functional Block Diagram .............................................................. 1 Theory of Operation ...................................................................... 10 General Description ......................................................................... 1 Basic Operation .............................................................................. 11 Specifications..................................................................................... 3 Output Data Registers ............................................................... 12 Timing Specifications .................................................................. 5 Operation Control Registers ..................................................... 12 Timing Diagrams.......................................................................... 5 Calibration Registers .................................................................. 14 Absolute Maximum Ratings............................................................ 6 ALARM Registers....................................................................... 14 ESD Caution .................................................................................. 6 Outline Dimensions ....................................................................... 15 Pin Configuration and Function Descriptions ............................. 7 Ordering Guide .......................................................................... 15 Rev. PrA | Page 2 of 16 Preliminary Technical Data ADIS16209 SPECIFICATIONS TA = +25°C, VDD = 3.3 V, tilt = 0°, unless otherwise noted. Table 1. Parameter HORIZONTAL INCLINE Input Range Relative Accuracy Sensitivity Offset VERTICAL ROTATION Input Range Relative Accuracy Sensitivity Offset ACCELEROMETER Input Range1 Nonlinearity1 Alignment Error Cross Axis Sensitivity Sensitivity Offset ACCELEROMETER NOISE PERFORMANCE Output Noise Noise Density ACCELEROMETER FREQUENCY RESPONSE Sensor Bandwidth Sensor Resonant Frequency ACCELEROMETER SELF-TEST STATE2 Output Change When Active TEMPERATURE SENSOR Output at 25°C Scale Factor ADC INPUT Resolution Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Offset Error Gain Error Input Range Input Capacitance Conditions Each axis Operable to ~±90 degrees ±30 degrees, AVG_CNT = 0x08 Min ±30 degrees, 25°C ±30 degrees, −40°C to +85°C 0 degrees, +25°C 0 degrees, −40°C to +85°C Sensor within ±30 degrees of vertical 0.02492 Typ ±70 ±0.1 0.0250 0.02492 TBD TBD 0.0250 Unit Degrees Degrees 0.02508 °/LSB °/LSB Degrees Degrees +180 Degrees Degrees Degrees °/LSB °/LSB Degrees Degrees TBD TBD −180 −40°C to +85°C ±30 degrees ±30 degrees, −40°C to +85°C 0 degrees 0 degrees, −40°C to +85°C Each axis 25°C % of full scale X sensor to Y sensor Max 0.02508 TBD TBD −40°C to +85°C 0g 0 g, −40°C to +85°C TBD TBD g % Degrees % mg/LSB ppm/°C mg mg AVG_CNT = 0x00 AVG_CNT = 0x00 1.7 0.17 mg rms mg/√Hz rms 50 5.5 Hz kHz ±1.7 TBD At 25°C 706 ±0.1 ±0.2 ±2 0.244 1343 1973 LSB LSB LSB/°C 12 ±2 ±1 ±4 ±2 Bits LSB LSB LSB LSB V pF 2.5 20 Rev. PrA | Page 3 of 16 TBD 1278 −2.13 0 During acquisition ±0.5 ADIS16209 Parameter ON-CHIP VOLTAGE REFERENCE Accuracy Reference Temperature Coefficient Output Impedance DAC OUTPUT Resolution Relative Accuracy Differential Nonlinearity Offset Error Gain Error Preliminary Technical Data Conditions Min At 25°C −10 2 12 4 1 ±5 ±0.5 0 to 2.5 2 10 For Code 101 to Code 4095 For CS signal when used to wake up from sleep mode VIH = 3.3 V VIL = 0 V ISOURCE = 1.6 mA ISINK = 1.6 mA V Ω μs 0.8 0.55 V V V ±0.2 ±10 μA −40 −1 10 −60 μA mA pF 2.4 0.5 0.4 V V 128 Seconds 130 2.5 ms ms 20,000 20 TJ = 85°C Cycles Years 4096 2.066 3.0 Normal mode, SMPL_PRD ≥ 0x08, 25°C Fast mode, SMPL_PRD ≤ 0x07, 25°C Sleep mode, at 25°C 3.3 11 36 500 SPS SPS 3.6 14 42 750 V mA mA μA Guaranteed by iMEMS® packaged part testing, design, and/or characterization. Self-test response changes as the square of VDD. The RST pin has an internal pull-up. 4 Guaranteed by design. Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at −40°C, +25°C, +85°C, and +125°C. 6 Bits LSB LSB mV % 2.0 3 5 +10 Unit V mV ppm/oC Ω 5 kΩ/100 pF to GND Output Impedance Output Settling Time LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL 1 Max ±40 70 Output Range Logic 1 Input High Current, IINH Logic 0 Input Low Current, IINL All except RST RST3 Input Capacitance, CIN DIGITAL OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL SLEEP TIMER Timeout Period4 START-UP TIME Initial Sleep Mode Recovery FLASH MEMORY Endurance5 Data Retention6 CONVERSION RATE Maximum Throughput Rate Minimum Throughput Rate POWER SUPPLY Operating Voltage Range Power Supply Current Typ 2.5 Retention lifetime equivalent at junction temperature (TJ) 55°C as per JEDEC Standard 22 Method A117. Retention lifetime decreases with junction temperature. Rev. PrA | Page 4 of 16 Preliminary Technical Data ADIS16209 TIMING SPECIFICATIONS TA = 25°C, VDD = 3.3 V, tilt = 0°, unless otherwise noted. Table 2. Parameter fSCLK Description Fast mode, SMPL_PRD ≤ 0x07 (fs ≥ 1024 Hz) Normal mode, SMPL_PRD ≥ 0x08 (fs ≤ 910 Hz) Chip select period, fast mode, SMPL_PRD ≤ 0x07 (fs ≥ 1024 Hz) Chip select period, normal mode, SMPL_PRD ≥ 0x08 (fs ≤ 910 Hz) Chip select to clock edge Data output valid after SCLK edge Data input setup time before SCLK rising edge Data input hold time after SCLK rising edge Data output fall time Data output rise time CS high after SCLK edge tDATARATE tDATARATE tCS tDAV tDSU tDHD tDF tDR tSFS 1 Min1 0.01 0.01 40 100 48.8 Typ Max 2.5 1.0 Unit MHz MHz μs μs ns ns ns ns ns ns ns 100 24.4 48.8 5 5 12.5 12.5 5 Guaranteed by design, not tested. TIMING DIAGRAMS tDATARATE tSTALL CS 07096-002 SCLK tSTALL = tDATA RATE – 16/fSCLK Figure 2. SPI Chip Select Timing CS tCS tSFS 1 SCLK 2 3 4 5 6 15 16 tDAV MSB DB13 DB14 tDSU DIN DB12 DB11 A4 A3 DB10 DB2 DB1 LSB tDHD W/R A5 A2 D2 D1 LSB Figure 3. SPI Timing (Utilizing SPI Settings Typically Identified as Phase = 1, Polarity = 1) DATA FRAME CS SCLK W/R WRITE = 1 READ = 0 A5 A4 A3 A2 A1 REGISTER ADDRESS A0 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DATA FOR WRITE COMMANDS DON’T CARE FOR READ COMMANDS Figure 4. DIN Bit Sequence Rev. PrA | Page 5 of 16 DC0 07096-004 DIN 07096-003 DOUT ADIS16209 Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Acceleration (Any Axis, Unpowered) Acceleration (Any Axis, Powered) VDD to GND Digital Input/Output Voltage to GND Analog Inputs to GND Analog Inputs to GND Operating Temperature Range Storage Temperature Range Table 4. Package Characteristics Rating 3500 g 3500 g −0.3 V to +7.0 V −0.3 V to +5.5 V −0.3 to VDD + 0.3 V −0.3 to VDD + 0.3 V −40°C to +125°C −65°C to +150°C Package Type 16-Terminal LGA ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. PrA | Page 6 of 16 θJA 250°C/W θJC 25°C/W Device Weight 0.6 grams Preliminary Technical Data ADIS16209 AUX ADC VDD 16 VREF GND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 15 14 13 12 ADIS16209 11 NC TOP LOOK THROUGH VIEW (Not to Scale) 10 NC 9 RST 1 AUX DAC 2 AX 6 7 8 NOTES 1. NC = NO CONNECT 2. THIS IS NOT AN ACTUAL “TOP VIEW,” AS THE PINS ARE NOT VISIBLE FROM THE TOP. THIS IS A LAYOUT VIEW, WHICH REPRESENTS THE PIN CONFIGURATION, IF THE PACKAGE IS LOOKED THROUGH FROM THE TOP. THIS CONFIGURATION IS PROVIDED FOR PCB LAYOUT PURPOSES. 07096-005 DIO1 5 NC CS NC DIN 4 DOUT PIN 1 INDICATOR DIO2 SCLK 3 AY Figure 5. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 3 4 5, 6 7, 8, 10, 11 9 12 13 14 15 16 1 Type1 I O I I I/O – I O S I O S Mnemonic SCLK DOUT DIN CS DIO1, DIO2 NC RST AUX DAC VDD AUX ADC VREF GND Description SPI, Serial Clock. SPI, Data Output. SPI, Data Input. SPI, Chip Select. Digital Input/Output Pins. No Connect. Reset, Active Low. Auxiliary DAC Output. Power Supply, +3.3 V. Auxiliary ADC Input. Precision Reference. Ground. S = supply; O = output; I = input. RECOMMENDED PAD GEOMETRY 2.6955 8× 4.1865 8× 0.670 12× 8.373 2× 5.391 4× 9.2mm × 9.2mm STACKED LGA PACKAGE Figure 6. Example of a Pad Layout Rev. PrA | Page 7 of 16 07096-006 0.500 16× 1.127 16× ADIS16209 Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS Figure 7. Figure 10. Figure 8. Figure 11. Figure 9. Figure 12. Rev. PrA | Page 8 of 16 Preliminary Technical Data ADIS16209 Figure 13. Figure 16. Figure 14. Figure 17. Figure 15. Figure 18. Rev. PrA | Page 9 of 16 ADIS16209 Preliminary Technical Data THEORY OF OPERATION Figure 19 and Figure 20 illustrate how the accelerometer responds to gravity, according to its orientation, with respect to gravity. Figure 19 displays the configuration for the incline angle outputs and Figure 20 displays the configuration used for the rotational angle position. This configuration provides greater measurement range than a single-axis. The ADIS16209 incorporates the signal processing circuit that converts acceleration into an incline angle, and corrects for several known error sources that would otherwise degrade the accuracy level. Rev. PrA | Page 10 of 16 θx GRAVITY = 1g θx HORIZON 07096-007 ax Figure 19. Single-Axis Tilt Theory Diagram ay θx GRAVITY = 1g ax θx HORIZON 07096-008 The ADIS16209 tilt sensing system uses gravity as its only stimulus, and a MEMS accelerometer as its sensing element. MEMS accelerometers typically employ a tiny, spring-loaded structure that is interlaced with a fixed pick-off finger structure. The spring constant of the floating structure determines how far it moves when subjected to a force. This structure responds to both dynamic forces associated with acceleration and static forces, such as gravity. Figure 20. Dual-Axis Tilt Theory Diagram Preliminary Technical Data ADIS16209 BASIC OPERATION ADIS16209 CS SCLK EMBEDDED PROCESSOR/ DSP/FPGA PF SCK DIN MOSI DOUT MISO 07096-009 The ADIS16209 requires only power/ground and SPI connections. The SPI is simple to hook up and is supported by many common digital hardware platforms. Figure 21 provides a simple hook-up diagram, while Table 2, Figure 2, Figure 3 provide timing and bit assignments. Figure 4 provides the bit sequence for accessing the register memory structure. Each function within the ADIS16209 has its own register, which has a unique, 6-bit address. Note that all 16 SCLK cycles are required for the DIN bit sequence to configure the output for the next data frame. The ADIS16209 supports full duplex mode operation. Table 6 provides the entire user register map for the ADIS16209. For each register, the lower byte’s address is given. For those registers that have two bytes, the upper byte’s address is simply the lower byte’s address, incremented by 0x01. Figure 21. Typical SPI Hook-up Many of the configuration registers have also been assigned mirror locations in the flash memory, which effectively provides them with a backup storage function. To assure the backup of these registers, the COMMAND register provides an initiation bit for manual flash updates. The ENDURANCE register provides a running count of these events. Table 6. User Register Map Name ENDURANCE SUPPLY_OUT XACCL_OUT YACCL_OUT AUX_ADC TEMP_OUT XINCL_OUT YINCL_OUT ROT_OUT XACCL_NULL YACCL_NULL XINCL_NULL YINCL_NULL ROT_NULL R/W R R R R R R R R R R/W R/W R/W R/W R/W Flash Backup Yes No No No No No No No No Yes Yes Yes Yes Yes ALM_MAG1 ALM_MAG2 ALM_SMPL1 ALM_SMPL2 ALM_CTRL R/W R/W R/W R/W R/W AUX_DAC GPIO_CTRL MSC_CTRL SMPL_PRD AVG_CNT SLP_CNT STATUS COMMAND R/W R/W R/W R/W R/W W R W Yes Yes Yes Yes Yes No No No No Yes Yes Yes No No Address 0x00 0x02 0x04 0x06 0x08 0x0A 0x0C 0x0E 0x10 0x12 0x14 0x16 0x18 0x1A 0x1C to 0x1F 0x20 0x22 0x24 0x26 0x28 0x2A to 0x2F 0x30 0x32 0x34 0x36 0x38 0x3A 0x3C 0x3E Size (Bytes) 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4 2 2 2 2 2 6 2 2 2 2 2 2 2 2 Function Diagnostics, flash write counter (16-bit binary) Output, power supply Output, X-axis acceleration Output, Y-axis acceleration Output, auxiliary ADC Output, temperature Output, ±90° X-axis inclination Output, ±90° Y-axis inclination Output, ±180° vertical rotational position Calibration, X-Axis acceleration offset null Calibration, Y-axis acceleration offset null Calibration, X-axis inclination offset null Calibration, Y-axis inclination offset null Calibration, vertical rotation offset null Reserved, do not write to these locations Alarm 1, amplitude threshold Alarm 2, amplitude threshold Alarm 1, sample period Alarm 2, sample period Alarm, source control register Reserved Auxiliary DAC data Operation, digital I/O configuration and data Operation, data-ready and self-test control Operation, sample rate configuration Operation, filter configuration Operation, sleep mode control Diagnostics, system status register Operation, system command register Rev. PrA | Page 11 of 16 Reference Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 16 Table 16 Table 17 Table 17 Table 17 Table 18 Table 18 Table 19 Table 19 Table 20 Table 14 Table 13 Table 12 Table 8 Table 10 Table 9 Table 21 Table 15 ADIS16209 Preliminary Technical Data OUTPUT DATA REGISTERS Table 7 provides the data configuration for each output data register in the ADIS16209. Starting with the MSB of the upper byte, each output data register has the following bit sequence: new data (ND) flag, error/alarm (EA) flag, followed by 14 data bits. The data bits are LSB-justified and in the case of the 12-bit data formats, the remaining 2 bits are not used. The ND flag indicates that unread data resides in the output data registers. This flag clears and returns to 0 during an output register read sequence. It returns to 1 after the next internal sample update cycle completes. The EA flag indicates an error condition. The STATUS register contains all of the error flags and provides the ability to investigate root cause. Table 7. Output Data Register Formats Register SUPPLY_OUT XACCL_OUT YACCL_OUT AUX_ADC TEMP_OUT XINCL_OUT2 YINCL_OUT2 ROT_OUT3 Bits 12 14 14 12 12 14 14 14 Format Binary, +3.3 V = 0x0ABE Twos complement Twos complement Binary, +2 V = 0x0CCC Binary, +25°C = 0x04FE Twos complement Twos complement Twos complement Scale1 1.22 mV 0.244 mg 0.244 mg 0.6105 mV −0.47°C 0.025° 0.025° 0.025° 68%. The two different modes of operation offer a system-level trade-off between performance (sample rate, serial transfer rate) and power dissipation. Power Management In addition to offering two different performance modes for power optimization, the ADIS16209 offers a programmable shutdown period, which the SLP_CNT register controls. Table 9. SLP_CNT Bit Descriptions Bit 15:8 7:0 Scale denotes quantity per LSB. 2 Range = −90° to +90°. 3 Range = −180° to +179.975°. OPERATION CONTROL REGISTERS Digital Filtering The AVG_CNT register controls the moving average digital filter, which determines the size of the moving average filter, in eight power-of-two step sizes (that is, 2M = 1, 2, 4, 16, 32, 64, 128, and 256). Filter setup requires one simple step: write the appropriate M factor to the assigned bits in the AVG_CNT register. Table 10. AVG_CNT Bit Descriptions Description (Default = 0x0004) Not used Power-of-two step size, maximum binary value = 1000 The following equation offers a frequency response relationship for this filter: Internal Sample Rate The SMPL_PRD register controls the ADIS16209 internal sample rate and has two parts: a selectable time base and a multiplier. The following relationship produces the sample rate: HA( f ) = sin(π × N × f × t S ) N × sin(π × f × t S ) 20 TS = TB × (NS + 1) N=4 0 Table 8. SMPL_PRD Bit Descriptions 6:0 Description Not used Time base (TB) 0 = 244.14 μs, 1 = 7.568 ms Increment setting (NS) (Default = 0x0001) N = 128 MAGNITUDE (dB) Bit 15:8 7 (Default = 0x00) For example, writing 0x08 to the SLP_CNT register places the ADIS16209 into sleep mode for 4 seconds. The only way to stop this process is to remove power or reset the device. Bit 15:4 3:0 1 Description Not used Data bits, 0.5 seconds/code N = 16 –20 –40 –60 An example calculation of the default sample period follows: B7 = 0 → TB = 122.07 μs, B6…B0 = 000000001 → NS = 1 –100 0.001 TS = TB × (NS + 1) = 122.07 μs × (1 + 1) = 244.14 μs 0.01 0.1 f/fS fS = 1∕TS = 4096 SPS Figure 22. Frequency Response—Moving Average Filter The sample rate setting has a direct impact on the SPI data rate capability. For sample rates ≥1024 SPS, the SPI SCLK can run at a rate up to 2.5 MHz. For sample rates <1024 SPS, the SPI SCLK can run at a rate up to 1 MHz. The sample rate setting also affects the power dissipation. When the sample rate is set <1024 SPS, the power dissipation typically reduces by a factor of Digital I/O Lines The ADIS16209 provides two, general purpose, digital input/output lines that have several configuration options. Rev. PrA | Page 12 of 16 07096-010 –80 SMPL_PRD = 0x01, B7 − B0 = 00000001 Preliminary Technical Data ADIS16209 Table 11. Digital I/O Line Configuration Registers Function [Priority] Data-Ready I/O indicator [1] Alarm Indicator [2] General-Purpose I/O Configuration [3] General-Purpose I/O Line Communication Register MSC_CTRL ALM_CTRL GPIO_DIR GPIO_DAT Data-Ready I/O Indicator The MSC_CTRL register provides controls for a data-ready function. For example, writing 0x05 to this register enables this function, and establishes DIO2 as an active-low, data-ready line. The duty cycle is 20% (±10% tolerance). Table 14. AUX_DAC Bit Descriptions Table 12. MSC_CTRL Bit Descriptions Bit 15:11 10 9 8 7:3 2 1 0 Description (Default = 0x0000) Not used Self-test at power-on: 1 = disabled, 0 = enabled Not used Self-test enable (temporary, bit is volatile) 1 = enabled, 0 = disabled Not used Data-ready enable: 1 = enabled, 0 = disabled Data-ready polarity: 1 = active high, 0 = active low Data-ready line select: 1 = DIO2, 0 = DIO1 Self-Test Self-test exercises the sensor’s mechanical structure and provides a simple method for verifying the operation of the entire sensor signal conditioning circuit. There are two different self-test options: startup and manual. If either of these self-tests results in a failure, the self-test error flag, located in the STATUS register, sets to 1. See Table 12 for the appropriate MSC_CTRL bit designations. General Purpose I/O The GPIO_CTRL controls the direction and data of the general-purpose digital lines, DIO1 and DIO2. For example, writing a 0x02 to the GPIO_DIR register sets DIO2 as an output line and DIO1 as an input line. Reading the data bits in GPIO_CTRL reveals the line’s logic level. Table 13. GPIO_CTRL Bit Descriptions Bit 15:10 9 8 7:2 1 DAC function, which is useful for systems that require analog level controls. It offers a rail-to-rail buffered output that has a range of 0 V to 2.5 V. The DAC can drive its output to within 5 mV of the ground reference when it is not sinking current. As the output approaches ground, the linearity begins to degrade (100 LSB beginning point). As the sink current increases, the nonlinear range increases. The DAC output latch function, contained in the COMMAND register provides continuous operation while writing to each byte of this register. The contents of this register are volatile, which means that the desired output level must be set after every reset and power cycle event. Description (Default = 0x0000) Not used General-purpose I/O Line 2 data General-purpose I/O Line 1 data Not used General-purpose I/O Line 2, data direction control 1 = output, 0 = input General-purpose I/O Line 1, data direction control 1 = output, 0 = input Bit 15:12 11:0 Description (Default = 0x0000) Not used Data bits, scale factor = 0.6105 mV/code Offset binary format, 0 V = 0 codes Global Commands The COMMAND register provides initiation bits for several commands, which simplify many common operations. Writing a 1 to the assigned COMMAND bit exercises its function. Table 15. COMMAND Bit Descriptions Bit 15:8 7 6:5 4 3 2 1 0 Description (Default = 0x0000) Not used Software reset Not used Clear status register (reset all bits to 0) Flash update; backs up all registers, per Table 6 DAC data latch Factory calibration restore Autonull The software reset command restarts the internal processor, which loads all registers with the contents in their flash memory locations. The flash update copies the contents of all the flash backup registers into their assigned, nonvolatile, flash memory locations. This process takes approximately 50 ms and requires a power supply that is within the specified operating range. After waiting the appropriate time for the flash update to complete, verify successful completion by reading the STATUS register (if successful, the flash update error is zero). If the flash update was not successful, reading this error bit accomplishes two things: (1) alert system processor to try again, and (2) clear the error flag, which is required for flash memory access. Auxiliary DAC The DAC data latch command loads the contents of AUX_DAC into the DAC latches. Because the AUX_DAC contents must be updated one byte at a time, this command ensures a stable DAC output voltage during updates. The auxiliary DAC provides a 12-bit level adjustment function. The AUX_DAC register controls the operation of the auxiliary The autonull command provides a simple method for removing offset from the sensor outputs. This command takes the 0 Rev. PrA | Page 13 of 16 ADIS16209 Preliminary Technical Data contents of the output data registers and loads the equal but opposite number into the offset calibration registers. The accuracy of this operation depends on zero force, zero motion, and optimal noise management during the measurement (see the Digital Filtering section). The factory calibration restore sets the offset null registers (XACCL_NULL, for example) back to their default values. CALIBRATION REGISTERS The ADIS16209 incorporates an extensive factory calibration and provides precision acceleration, incline, and rotational position data. For systems that require on-site calibration, user-programmable offset adjustment registers are available. Table 16 provides the bit assignments for the following userprogrammable calibration registers: XACCL_NULL and YACCL_NULL. Table 17 provides the bit assignments for the following user-programmable calibration registers: XINCL_NULL, YINCL_NULL, and ROT_NULL. Table 16. Acceleration Offset Register Bit Designations Bit 15:12 11:0 Description (Default = 0x0000) Not used Data bits, twos complement, sensitivity = 0.244 mg/LSB Table 17. Incline/Rotation Offset Register Bit Designations Bit 15:14 13:0 Description (Default = 0x0000) Not used Data bits, twos complement, sensitivity = 0.025°/LSB ALARM REGISTERS The alarm function provides monitoring for two independent conditions. The ALM_CTRL register provides control inputs for data source, data filtering (prior to comparison), static/ dynamic, and output indicator configurations. The ALM_MAGx registers establish the trigger threshold and polarity configurations. The ALM_SMPLx registers provide the numbers of samples to use in the dynamic, rate-of-change configuration. The rate-of-change calculation is YC = N DS 1 N DS ∑ Table 19. ALM_SMPL1/ALM_SMPL2 Bit Designations Bit 15:8 7:0 Table 20. ALM_CTRL Bit Descriptions Bit 15 14:12 n =1 11 10:8 7:6 5 4 3 2 1 0 The STATUS register provides a series of error flags, which provide indicator functions for common system-level issues. All of the flags clear (set to 0) after each STATUS register read cycle. If an error condition remains, then the error flag returns to 1 during the next sample cycle. Table 21. STATUS Bit Descriptions Bit 15:10 9 4 3 2 Table 18. ALM_MAG1/ALM_MAG2 Bit Designations Bit 15 14 13:0 Description (Default = 0x0000) Comparison polarity: 1 = greater than, 0 = less than Not used Data bits, matches format of trigger source selection Description (Default = 0x0000) Alarm 2 rate of change control: 1 = enabled Trigger source, Alarm 2 Disabled Power supply X-acceleration Y-acceleration Temperature sensor X-axis incline angle Y-axis incline angle Rotational position Alarm 1: rate-of-change control, 1 = enabled Trigger source, Alarm 1, same as bits 14:12 Not used Alarm 2 filter: 1 = filtered data, 0 = no filter Alarm 1 filter: 1 = filtered data, 0 = no filter Not used Alarm indicator, using DIO1/DIO2: 1 = enabled Alarm indicator polarity: 1 = active high Alarm indicator line select: 1 = DIO2, 0 = DIO1 Status 7:6 5 where: NDS is the number of samples in ALM_SMPLx. y(n) is the sampled output data. MC is the magnitude for comparison in ALM_MAGx. > or < is determined by the MSB in ALM_MAGx. Value 000 001 010 011 100 101 110 111 8 y (n + 1) − y (n) ⇒ Alarm ⇒ is YC > or < M C ? Description (Default = 0x0001) Not used Data bits: number of samples (both 0x00 and 0x01 = 1) 1 0 Rev. PrA | Page 14 of 16 Description (Default = 0x0000) Not used Alarm 2 status 1 = active, 0 = inactive Alarm 1 status 1 = active, 0 = inactive Not used Self-test diagnostic error flag 1 = error condition, 0 = normal operation Not used SPI communications failure 1 = error condition, 0 = normal operation Flash update failed 1 = error condition, 0 = normal operation Power supply above 3.625 V 1 = >3.625 V, 0 = <2.975 V (normal) Power supply below 2.975 V 1 = <2.975 V, 0 = >2.975 V (normal) Preliminary Technical Data ADIS16209 OUTLINE DIMENSIONS 5.391 BSC (4×) 2.6955 BSC (8×) 9.35 MAX 13 PIN 1 INDICATOR 12 9.20 TYP 1.000 BSC (16×) 16 1 8.373 BSC (2×) 0.797 BSC (12×) 9 4 8 0.200 MIN (ALL SIDES) TOP VIEW 5.00 TYP 5 BOTTOM VIEW 0.373 BSC (16×) 022007-B 3.90 MAX SIDE VIEW Figure 23. 16-Terminal Land Grid Array [LGA] (CC-16-2) Dimensions shown in millimeters ORDERING GUIDE Model ADIS16209CCCZ1 ADIS16209/PCBZ1 1 Temperature Range −40°C to +125°C Package Description 16-Terminal Land Grid Array [LGA] Evaluation Board Z = RoHS Compliant Part. Rev. PrA | Page 15 of 16 Package Option CC-16-2 ADIS16209 Preliminary Technical Data NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR07096-0-10/07(PrA) Rev. PrA | Page 16 of 16