ETC LA6513A

Ordering number:EN2367B
CMOS IC
LC6512A, LC6513A
Single-Chip 4-Bit Microcomputer
for Control-Oriented Applications
(Low-Threshold Input, On-Chip FLT Driver)
Package Dimensions
unit:mm
3025B-D42SIC
[LC6512A]
42
22
0.25
The LC6512A, 6513A are microcomputers that are dentical
with FLT driver-contained microcomputers LC6502D,
6505D in instruction set but are further enhanced in performance, such as shorter cycle time, more stack levels, increased FLT drive capacity, and are partially changed in
specifications for standby function. Since the LC6512A,
6513A are also pin-compatible with the LC6502D, 6505D,
they can be used as similar replacements for the LC6502D,
6505D. The LC6512A, 6513A can replace the LC6502B/
6502D, 6505B/6505D to enhance performances of equipment in which these microcomputers have been applied so
far.
(3) The standby function is the same as for the LC6514B
and its using method is different from that of the
LC6502D, 6505D, etc.
15.24
13.8
General Description
Features
1
21
0.48
0.95
1.78
1.15
SANYO : DIP42S
unit:mm
3052A-QIP48A
[LC6513A]
20.0
14.0
1.5
1.0
0.15
25
1.5
3.0
3.0
1.5
0.35
36
24
1.0
20.0
0.35
37
14.0
48
13
1
12
16.6
2.45max
1.5
• Low power dissipation CMOS single-chip microcomputer.
• Instruction set with 79 instructions common to the
LC6502C, 6502B, 6502D/LC6505C, 6505B, 6505D.
• 2-source, 2-level interrupt function (external interrupt/
internal timer interrupt)
• 8-level stack
• 4-bit prescaler-contained 8-bit programmable timer
• FLT driver-contained output ports and low-threshold input ports
(1) Digits driving output ports: 10 pins
(2) Segments driving output ports: 8 pins
(3) Normal voltage input ports: 8 pins (4 pins: Lowthreshold input port)
(4) Normal voltage input/output ports: 8-pins
• ROM, RAM
(1) LC6512A ROM: 2048bytes, RAM: 128 × 4bits
(2) LC6513A ROM: 1024 bytes, RAM: 64 × 4bits
• Cycle time 1.33µs min.
400kHz, 800kHz, 1MHz, 3MHz ceramic resonator OSC.
• Power-down by 2 standby modes
(1) HALT mode: Power dissipation saving by program
standby during normal operation
(2) HOLD mode: Power supply backup during power
failure
0.51min 4.25
3.8 5.1max
37.9
1.7
2.15
SANYO : QIP48A
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges,or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
O1001TN (KT)/7129YT/7227KI/5317KI/N256KI,TS No.2367–1/24
LC6512A, LC6513A
• Differences among LC6512D, 6513D,and LC6512A, 6513A
The LC6512D, 6513D and LC6512A, 6513A are different in the OSC circuit only and are the same in the basic
features. The differences are shown below.
Item
LC6512A, 6513A
LC6512D. 6513D
OSC circuit
configuration
1-stage inverter
5-stage inverter
OSC mode
Ceramic resonator OSC
Ceramic resonator OSC, CR OSC, application of external clock
OSC waveform
Sine wave
Rectangular wave
Operating
frequency
Ceramic resonator OSC: 500kHz, 800kHz,1MHz, 3MHz
Ceramic resonator OSC: 400kHz, 800kHz, 1 MHz
CR OSC: 400kHz typ. 800kHz typ
External clock: 222kHz to 1290kHz
Technical Data
The LC6512A, 6513A are members of our LC6500 series of CMOS microcomputers. For their internal functions, refer to
the LC6500 SERIES USFR′S MANUAL. Those which differ from the description in the USER′S MANUAL are described in this catalog. Carefully study features and Appendix 4 Standby Function in this catalog before using the LC6512A,
6513A.
Pin Assignments
Pin Name
OSC1, OSC2
INT
RES
HOLD
PAO-3
PBO-3
PCO-3
PDO-3
PEO-3
PFO-3
PGO-3
PHO-3
PI0, 1
TEST
: Ceramic resonator for OSC
: Interrupt
: Reset
: Hold
: Input port
: Input port
: Input/output common port
: Input/output common port
: Output port (High-voltage port)
: Output port (High-voltage port)
: Output port (High-voltage port)
: Output port (High-voltage port)
: Output port (High-voltage port)
: Test
A0–3
B0–3
C0–3
D0–3
E0–3
F0–3
G0–3
H0–3
I0, 1
DIP42S
(Note) Nothing must be connected to NC
pins internally or externally.
When mounting the QIP version on the
board, do not dip it in solder.
QIP48A
No.2367–2/24
LC6512A, LC6513A
System Block Diagram
Note*:High-voltage port
RAM
F
WR
AC
ALU
DP
E
CTL
OSC
TM
: Data memory
: Flag
: Working register
: Accumulator
: Arithmetic and logic unit
: Data pointer
: E register
: Control register
: Oscillation circuit
: Timer
STS
ROM
PC
INT
IR
I.DEC
CF, CSF
ZF, ZSF
EXTF
TMF
: Status register
: Program memory
: Program counter
: Interrupt control
: lnstruction register
: lnstruction decoder
: Carry flag, carry save flag
: Zero flag, zero save flag
: External interrupt request flag
: Internal interrupt request flag
Pin Description
Pin Name
Input/Output
Function
INT
Input
Interrupt request input pin
HOLD
Input
HOLD mode request input pin (The LC6502, 6505 differ in function.)
Capable of being used as a general-purpose single-bit input port unless the standby mode is used.
RES
Input
Reset input pin
PA0-3
Input
Input port A0 to A3 (Normal voltage, low-threshold input)
Capable of 4-bit input and single-bit decision for branch
Use also for HALT mode release request input
Continued on next page.
No.2367–3/24
LC6512A, LC6513A
Continued from preceding page.
Input/Output
Pin Name
Function
Input port B0 to B3 (Normal voltage)
Capable of 4-bit input and single-bit decision for branch
PB0-3
Input
PC0-3
Input/Output
Input/output common port C0 to C3 (Normal voltage)
Capable of 4-bit input and single-bit decision for branch during input
Capable of 4-bit output and single-bit set/reset during output
PD0-3
Input/Output
Input/output common port D0 to D3 (Normal voltage)
Capable of 4-bit input and single-bit decision for branch during input
Capable of 4-bit output and single-bit set/reset during output
PE0-3
Output
Output port E0 to E3 (Digit driver output)
Capable of 4-bit output and single-bit set/reset
Capable of 4-bit input of output latch contents and single-bit decision of output latch for branch
PF0-3
Output
Output port F0 to F3 (Digit driver output)
Capable of 4-bit output and single-bit set/reset
Capable of 4-bit input of output latch contents and single-bit decision of output latch for branch
PG0-3
Output
Output port G0 to G3 (Segment driver output)
Capable of 4-bit output and single-bit set/reset
Capable of 4-bit input of output latch contents and single-bit decision of output latch for branch
PH0-3
Output
Output port H0 to H3 (Segment driver output)
Capable of 4-bit output and single-bit set/reset
Capable of 4-bit input of output latch contents and single-bit decision of output latch for branch
Pl0, 1
Output
Output port I0, I1 (Digit driver output)
Capable of 2-bit output and single-bit set/reset
Capable of 2-bit input of output latch contents and single-bit decision of output latch for branch
0SC1
Input
0SC2
Output
VDD
Input
VSS
A ceramic resonator is connected to this pin and pin OSC2 in the internal clock mode.
Pin for externally connecting a resonance circuit for the internal clock mode
Power supply pin
Normally connected to +5V
Connected to 0V power supply
TEST
Input
IC test pin
Normally connected to VSS(0V)
Specifications
Absolute Maximum Ratings at Ta = 25˚C, VSS=0V
Parameter
Maximum supply voltage
Input voltage
Output voltage
Peak output current
Allowable power dissipation
Symbol
Conditions
VDD max
VIN
VOUT(1)
VOUT(2)
lnput pins other than OSC1
Ports C,D OSC2
Ports E,F,G,H,I
Ratings
Unit
–0.3 to +7.0
V
–0.3 to VDD+0.3 (Note1)
–0.3 to VDD+0.3
V
V
VDD–45 to VDD+0.3
–2.0 to +2.0
mA
V
IO(1)
Ports C,D:Each pin
IO(2)
IO(3)
Ports E,F,I:Each pin
–15 to 0
mA
Ports G, H:Each pin
–10 to 0
mA
IO(4)
Pd max(1)
All pins of ports C to I
Pd max(2)
Ta=–30 to +70°C (DIP)
Ta=–30 to +70°C (Flat package)
–90 to +16
mA
350
mW
600
mW
Operating temperature
Topr
–30 to +70
˚C
Storage temperature
Tstg
–55 to +125
˚C
(Note1) For pin OSCl, up to oscillation amplitude generated when internally oscillated under the recommended
oscillation conditions in Fig. 2 is allowable.
[Note] When mounting the QIP package version on the board, do not dip it in solder.
No.2367–4/24
LC6512A, LC6513A
Allowable Operating Conditions at Ta = –30 to +70°C, VDD = 5V±10%, VSS = 0V,
Parameter
Symbol
Ratings
Conditions
min
typ
VDD(1)
5.5
V
Power-down supply voltage
VDD(2)
HOLD mode: HOLD=VIL(3)
1.8
5.5
V
VIH(1)
Port A
1.9
VDD
V
VDD
V
Input low-level voltage
External capacitance for ceramic resonator
O SC
VIH(2)
Ports B, C, D
0.7VDD
VIH(3)
lNT, RES, HOLD and OSC1
0.8VDD
VDD
V
VIL(1)
Ports B, C, D
VSS
0.3VDD
V
VIL(2)
lNT, RES, OSC1
VSS
0.2VDD
V
VIL(3)
HOLD,TEST: VDD=1.8 to 5.5V
VSS
0.2VDD
V
VIL(4)
Port A
VSS
0.5
V
C1
See Fig. 2.
C2
See Fig. 2.
tDH
See Figs. 3-3, 3-4 in Appendix 3.
(N-2)
Xtcyc*
(N-2)
Xtcyc*
Allowable delay in key scan circuit
tDL
Standby timing
5.0
Unit
Operating supply voltage
Input high-level voltage
4.5
max
µs
µs
tVDDF
VDD=1.8 to 5.5V, See Fig. 1.
0
µs
tVDDR
VDD=1.8 to 5.5V, See Fig. 1.
0
µs
(Note)* tcyc: Cycle time at microcomputer running mode
[Note]
No chattering shall be applied to the HOLD
pin and PA0 to 3 pins during the HALT
instruction execution cycle.
Fig. 1 Standby mode timing
No.2367–5/24
LC6512A, LC6513A
Electrical Characteristics at Ta = –30 to +70°C, VDD = 5.0V±10%, VSS = 0V
Parameter
Symbol
Conditions
Input high-level current
IIH
Each input pin: VIN=VDD
Input low-level current
IIL
Each input pin: VIN=VSS
Output high-level voltage
Output low-level voltage
Output OFF leak current
Clock OSC frequency for ceramic
resonator OSC
Output capacitance
typ
max
1.0
Unit
µA
–1.0
µA
VOH(1)
Ports C, D: IOH=–1mA
VDD–2.0
V
VOH(2)
Ports C, D: IOH=–100µA
VDD–0.5
V
VOH(3)
Ports E, F, I: IOH=–10mA
VDD–1.8
V
VOH(4)
Ports E, F, I: IOH=–2mA
VDD–1.0
V
VOH(5)
Ports E, F, I: IOH=–1mA
(Each port IOH=Less than –1mA)
VDD–0.5
V
VOH(6)
Ports G, H: IOH=–2mA
VDD–1.0
V
VOH(7)
PortsG, H: IOH=–1mA (Each port IOH=Less than –1mA)
VDD–0.5
V
VOH(8)
OSC2: IOH=–100µA
VDD–0.5
VOL(1)
Ports C, D: IOL=1mA
0.4
V
VOL(2)
OSC2: IOL=100µA
0.4
V
IOFF(1)
Ports C, D: VOUT=VDD, HOLD mode
1.0
µA
IOFF(2)
Ports C, D: VOUT=VSS, HOLD mode
IOFF(3)
Ports E, F, G, H, I: VOUT=VDD
IOFF(4)
Ports E, F, G, H, I: VOUT=VDD–40V
–30
OSC circuit in Fig. 2:
392
Note 2
784
980
2940
V
–1.0
µA
30
µA
408
kHz
Note 2
816
kHz
Note 2
1020
kHz
Note 2
3060
kHz
Ceramic resonator OSC;f=400, 800, 1000kHz
1.0
2.0
mA
IDD(1)
Operating mode f=3MHz.
Recommended conditions for ceramic resonator OSC,
output pin open, input pin VIN=VSS
2.7
4.0
mA
IDD(2)
HALT mode: VDD=5V±10%, Test circuit in Fig. 3
10
µA
IDD(3)
HOLD mode: VDD=1.8 to 5.5V, Test circuit in Fig. 4
Each input pin: Measure at f=1MHz.
Pins not being measured: VSS
Ports E, F,G, H, l: Measure at f=1MHz
Pins not being measured: VSS
Ports C, D.. Measure at f=1MHz,
Pins not being measured: VSS
INT, RES, HOLD
10
µA
fCFOSC
Current drain
Input capacitance
Ratings
min
CIN
COUT
Input/output capacitance
CIO
Hysteresis voltage
VH
Recommended conditions for ceramic resonator OSC
µA
5
pF
10
pF
10
pF
0.1VDD
V
No.2367–6/24
LC6512A, LC6513A
Center frequency
3MHz
1MHz
800kHz
400kHz
Ceramic resonator
C1 (pF)
CF: Ceramic resonator
CSA3.00MG (Murata)
KBR3.0MS (Kyocera)
CSB1000K, D (Murata)
KBR1000H (Kyocera)
CSB800K, D (Murata)
KBR800H (Kyocera)
CSB400P (Murata)
KBR400B (Kyocera)
C2 (pF)
CSA3.00MG (Murata)
33±10%
KBR3.0MS (Kyocera)
22±10%
CSB1000K, D (Murata)
180±10%
KBR1000H (Kyocera)
180±10%
CSB800K, D (Murata)
180±10%
KBR800H (Kyocera)
180±10%
CSB400P (Murata)
330±10%
KBR400B (Kyocera)
330±10%
Fig. 2 Recommended OSC circuit, constants
for ceramic resonator OSC
Note 2) There is a tolerance of approximately 1% between the center frequency at the ceramic resonator mode and the
nominal value presented by the ceramic resonator supplier. For details, refer to the specification for the ceramic
resonator.
The min., max. values of OSC frequency represent the oscillatable frequency range.
Note 3) When using the piggyback microcomputer, evaluation chip for evaluation, connect a feedback resistor (approximately lMΩ).
Input/output common ports C, D: Output inhibit
HALT instruction is executed to provide HALT mode.
Fig. 3 IDD(2) test circuit
Fig. 4 IDD(3) test circuit
τVDD: Power supply rise time constant
τRES: RES pin rise time constant
Fix C. R so that τVDD <
= 10ms. is obtained.
= τRES, tOSC >
t
:
OSC
stabilized
time
OSC
Fig. 5 lnitial reset timing
No.2367–7/24
LC6512A, LC6513A
Appendix 1. Support System
For application development of the LC6512A, 6513A, the support system for the LC6512A, 6513A is used.
1-1. Software support
The support system provides source editor, cross assembler. For cross assembler on CP/M, the "LC6502.COM",
"LC6505.COM" are used, and on MS-DOS, the ''LC6512.COM", ''LC6513.COM" are used.
1-2. Hardware support
(1) Evaluation chip
Evaluation chip LC6597 is used. Level converters, drivers are connected to high-voltage ports (PE0 to 3, PF0 to 3,
PG0 to 3, PH0 to 3, PI0, 1) externally.
(A dedicated adaptor is available.)
Evaluation chip
General-purpose input
General-purpose input/output
External memory for program
FLT driver output
Fig. 1-1 Basic evaluation system using evaluation chip
(2) Simulation chip
Piggyback LC65PG12/13 and adaptor (EVA-97-12D/13D) for the LC6512A, 6513A are used jointly.
LC65PG12/13
EVA-97-12D/13D
A driver shown in fig. 1-3 is contained.
Conversion board TB42S
To user’s application aquipment
Fig. 1-2 How to use piggyback
No.2367–8/24
LC6512A, LC6513A
(3) Evaluation kit
The EVA-410 and EVA-TB2 are used. For connecting with user's application equipment, adaptor (EVA-97-12D/
13D) is used.
(4) Adaptor (EVA-97-12D/13D)
This is used when evaluating the LC6512A, 6513A with the aid of the evaluation chip and piggyback. This
contains drivers for FLT. (See Figs. 1-3, 1-4.)
42-pin IC socket
•Evaluation kit
•Piggyback
-Vpp input
• Power supply for adaptor-contained
driver(LB1294)-Vpp for FLT is applied.
No external driver is required for
mass-produced microcomputers.
Conversion board TB42S
User’s application board
(42-pin IC pin)
Fig. 1-3 Adaptor (EVA-97-12D/13D) for LC6512A, 6513A
CN3
Conversion board
42-pin IC pin
CN2
Connector for
cable connection
NFP-50A-0112
(Yamaichi Electric-made)
CN1
Surface 42-pin socket
(Yamaichi Electric-made)
IC1 to 3 (16pin)
LB1294 10pin : NC
IC4 (14pin)
LA6339
Fig. 1-4 EVA-97-12D/13D
No.2367–9/24
LC6512A, LC6513A
Appendix 2. lnternal Architecture of LC6512A, 6513A
The LC6512A, 6513A are identical with the LC6502C, 6505C in the internal architecture and instruction set except that
output ports are of high-voltage type and port A is of low-threshold input type and the standby function is the same as for
the LC6514B. For details, refer to ''LC6500 SERIES USER'S MANUAL''; and for the standby function, refer to Appendix
4 ''Standby Function''.
2-1. PC
For the LC6512A, 6513A, this is organized with an 11-bit, 10-bit binary counter, respectively, which specifies the
ROM address of an instruction to be executed next. The high-order 3(2) bits specify a page and the low-order 8 bits
specify an address in the page. The page is updated automatically. ( ) is for the LC6513A.
2-2. ROM
This is used to store user programs. For the LC6512A, 6513A,this is organized with 2048x 8 bits, 1024 x 8 bits,
respectively. By using the ROM table read instruction, the whole area can be accessed and the display pattern can be
programmed.
2-3. Stack
This is used to save the contents of the PC at the subroutine call or interrupt mode. This allows subroutine nesting up
to 8 levels.
2-4. DP
This is a register organized with 4-bit DPL and 3-bit, 2-bit DPH for the LC6512A, 6513A, respectively. When accessing the data RAM, the DPL, DPH specify a column address, row address, respectively. When accessing input/output
ports, the DPL specifies port A to port l. The DPL also specifies internal pseudo port O.
2-5. RAM
This is a static RAM used to store data. For the LC6512A, 6513A, this is organized with 128 x 4 bits, 64 x 4 bits,
respectively. Row address 7H(3H) is allocated for 16 flags and 8 working registers which can be manipulated without
being addressed by the DP. ( ) is for the LC6513A.
2-6. AC, E
The AC is a 4-bit register which stores data to be processed by instructions. The E register is an auxiliary register to be
back up the AC and is used as a temporary register or general-purpose register at the instruction execution mode.
2-7. ALU
This is a circuit which performs arithmetic and logic operations specified by individual instructions. This outputs not
only data of operation results but also the status of carry (C), zero (Z).
2-8. Status register
This is a 4-bit register which stores the status of carry, zero and the external interrupt, timer interrupt request.
The contents of the status register can be tested by the branch instructions.
2-9. Timer
This consists of a 4-bit fixed prescaler and an 8-bit programmable timer. This counts the system clock and requests a
timer interrupt when an overflow occurs.
2-10. Control register
This is a 4-bit register, 2-bits of which control input/output of input/output common ports C, D and 2-bits of which
enable/disable external interrupt, internal timer interrupt.
2-1 1. Input/output ports
There are 9 ports/34 pins from port A to I. Each port is addressed by the DPL. Ports A, B are of normal-voltage input
type, ports C, D are of normal-voltage input/output common type, and ports E, F, G, H, I contain FLT drivers. Port A
is of low-threshold input type.
No.2367–10/24
LC6512A, LC6513A
(1) Ports A0 to 3, B0 to 3
DSB---Input inhibit at HOLD mode
Ports A,B
Internal bus
Functions • 4-bit input (IP instruction)
• Single-bit test (BP, BNP instructions)
• Port A: Low-threshold input
• Port B: Normal-threshold input
(2) Ports C0 to 3, D0 to 3
DSB---Input output inhibit at HOLD mode
Output: High impedance
Ports C,D
Internal bus
Output
inhibit
DSB---Output control (Control register)
Functions 1. Input mode (Output inhibit)
• 4-bit input (IP instruction)
• Single-bit test (BP, BNP instructions)
2. Output mode
• 4-bit output (OP instruction)
• Single-bit set, reset (SPB, RPB instructions)
(3) Ports E0 to 3, F0 to 3, G0 to 3, H0 to 3, I0 to 1 (High-voltage ports)
DSB=Output inhibit at HOLD mode (Output transistor OFF)
Internal bus
Ports E to I
Functions • 4-bit (2-bit for port I) output (OP instruction)
• 4-bit (2-bit for port I) input of output latch contents (IP instruction)
• Single-bit set, reset (SPB, RPB instructions)
Set: The output represents a 1. ----- Output transistor ON
Reset: The output represents a 0. ----- Output transistor OFF
• Single-bit test of output latch contents (BP, BNP instructions)
• PortsE, F, I: FLT digits drive
• Ports G, H: FLT segments drive
No.2367–11/24
LC6512A, LC6513A
2-12. External interrupt
The trailing edge of the signal on the INT pin is detected and the interrupt request flag in the status register is set. The
occurrence of an interrupt is controlled by the enable/disable flag in the control register.
2-13. Reset
The system is initialized by setting the RES pin to L-level. The contents to be initialized are as follows:
• PC
Address 000H
• Control register 0000 → Interrupt disable, Ports C, D: Output inhibit
• Status register Timer, external interrupt flag → Reset
• Output port
Output latch (0H) → Output transistor OFF
Appendix 3. Proper Cares in Using IC
3-1. Low-threshold input port A0 to 3 provides the input characteristic shown in Fig. 3-1.
VDD
High-level input
1.9V
0.5V
VSS
Low-level input
Fig. 3-1
3-2. FLT driver output
Ports E0 to 3, F0 to 3, I0 to 1 (10 pins) are for high-current digits driver output; and ports G0 to 3, H0 to 3 (8 pins) are for
intermediate-current segments driver outputs. Of course, digits driver outputs can be used as segments driver outputs.
Fig. 3-2 shows a sample application.
Key scan
Digits
Ports E,F,I
-Vpp
Ports G, H
-Vpp
Segments
LC6512A, 6513A
Fig. 3-2 FLT display application
No.2367–12/24
LC6512A, LC6513A
Digit drive signal-used key scan
When key-scanning with the FLT digit drive signal in Fig. 3-3 and inputting the return signal to port A, the following must
be observed.
(a) Estimate voltage drop (VON) in the output transistor using the current flowing in an FLT used and the V-I
characteristic of the output port of the LC6512A, 6513A.
(b) Estimate voltage drop (VSW)in the switch circuit.
(c) Check to see that VON + VSW meets the VIH/VIL requirement of the input port in Fig. 3-1.
tDL tDH (External circuit delay time)
Fig. 3-3 Sample key scan application
For the key scan application in Fig. 3-3, make the program considering the delay in the external circuit and the input delay
shown below.
Fig. 3-4
When the IP instruction is used to input the return signal as shown above, the input delay must be considered and two
instructions are placed between the IP instruction and the crossing of input port waveform and VIL(4), VIH(1), respectively.
Some instructions must be placed additionally according to the length of delay (tDL, tDH) in the external circuit after the
digit drive signal is delivered with the execution of the OP instruction (point a and point c).
N: Number of instruction cycles existing between instruction (OP, SPB, RPB) used to output data to output port and
instruction (IP, BP, BNP) used to input data from input port.
(Number of instruction cycles to be programmed according to the length of tDL, tDH)
tDL, tDH: Delay in external circuit from output port to input port.
No.2367–13/24
LC6512A, LC6513A
Appendix 4. Standby Function
Two standby modes – HALT mode and HOLD mode – are available to minimize the power dissipation when the program
is in the wait state or a power failure is backed up. Both modes are set with the execution of the HALT instruction. All the
operations including the system clock generator are stopped at the standby mode. (For other models LC6502/05 of the
LC6500 series, the HOLD mode is hardware-set with the HOLD pin = "L". Be careful of the difference in the mode setting
method.)
The HALT mode and HOLD mode are used properly depending on the purposes. They are different in the mode setting
conditions, I/O port state during standby operation, mode releasing method. The HALT mode is entered by executing the
HALT instruction when the HOLD pin is at H-Level. The HALT mode is used to save the power dissipation when the
program is in the wait state. The HOLD mode is entered by executing the HALT instruction when the HOLD pin is at LLevel. At the HOLD mode all I/O ports are disabled and there is no power dissipation in the interfaces with external
circuits, permitting capacitor or battery-used power supply backup during power failure.
4-1. HALT mode setting
The HALT mode is entered by executing the HALT instruction when the HOLD pin is at H-Level and all pins for port
A0 to A3 are at L-Level. When even one of pins for port A0 to A3 is at H-Level, the HALT instruction is disregarded
and becomes equal to the NOP instruction.
The HALT mode causes individual blocks to be placed in the following states.
(1) Operation is stopped
• All the operations including the system clock generator are stopped.
(2) I/O port
• The state immediately before setting the HALT mode is held.
(3) Blocks to be cleared/reset
• Timer............State where all bits are set to "1"(max.time).
• Status flag.....The EXTF, TMF are reset (interrupt disable). The CF, ZF contents are held. An interrupt request at the
HALT mode is disregarded.
(4) Blocks to be held
• For the registers, data RAM, port output latch, PC (except those in (3), the contents immediately before setting the
HALT mode are held.
4-2. HOLD mode setting
The HOLD mode is entered by executing the HALT instruction when the HOLD pin is at L-Level. ln this case, the
contents of port A0 to A3 remain unaffected.
The state in the HOLD mode is the same as that in the HALT mode, except the state of I/O port. The HOLD mode
permits the undermentioned power-down mode to be entered.
I/O port
• lnput ports A, B:
lnput inhibit
• Input/output port C, D: Input inhibit, output high impedance
• Output ports E to I:
Output Pch transistor OFF
• INT, RES pins:
Input inhibit
For the output latch of the output port, the contents immediately before setting the HOLD mode are held.
No.2367–14/24
LC6512A, LC6513A
4-3. HOLD power-down mode setting
The HOLD mode permits the supply voltage to be lowered and also the power dissipation to be reduced after mode
setting. The HOLD mode can be used in the capacitor or battery-used backup operation during power failure.
Fig. 4-1 HOLD mode and power-down
¡ A failure of the main power supply is detected and a standby request is made. This is hardware-controlled by the
external circuit.
™ The HOLD pin is software-polled or the same signal is applied to the INT pin to test the standby request by
interrupt. Then, the HALT instruction is executed and the HOLD mode is entered. (Note)
£ After the HOLD mode is entered, power-down can be attained by lowering VDD.
¢ After VDD returns to the prescribed voltage, the HOLD pin is set to H-Level and the normal operation returns.
(Note) The HOLD pin input signal is transferred to pseudo input port PO 0 (DPL = 0EH, 20 bit). Therefore, when
polling the HOLD pin, the BP0 or BNP0 instruction is used at DPL = 0EH. (The IP instruction cannot be
used.)
When the BP0 instruction is used for testing, a branch occurs when the input voltage is at high level in the
same manner as for normal input ports.
4-4. HALT mode release
Release by reset
When L-Level is applied to the RES pin, the HALT mode is released and the system reset state is entered.
When the RES pin is set to H-Level again, the normal operation starts. Since the ceremic resonator mode is used for
system clock generation, the release by reset must be performed.
–Notes–
• Since the ceramic resonator mode is used for system clock generation, L-Level must be applied to the RES pin for 5
to 10 ms (oscillation stabilizing time).
Mode change from HALT mode to HOLD Mode
The HALT mode is entered with the execution of the HALT instruction when the HOLD pin is at H-Level.
The HALT mode is changed to the HOLD mode automatically by setting the HOLD pin to L-Level.
Fig. 4-2 Mode change from HALT modeto HOLD mode
No.2367–15/24
LC6512A, LC6513A
4-5. HOLD mode release
Release by reset
The HOLD mode is released by setting the HOLD pin to H-Level while applying L-Level to the RES pin. When the
RES pin is set to H-Level again, the normal operation starts. The contents of the memories remain unaffected except
the PC, I/O ports, registers which are initialized by the reset operation.
Since the ceramic resonator mode is used, the reset state must be held until oscillation is fully stabilized (10 ms after
oscillation start) after the HOLD mode is released.
Fig. 4-3 HOLD mode release by reset
Note: With L-Level applied to the HOLD pin as shown above, the CPU is not reset even when the RES pin is set to LLevel. This is because the HOLD pin is given priority lest the CPU is reset unnecessarily when the capacitor or
battery-used backup mode causes the CPU peripherals to operate unstably and the RES pin is set to L-Level. Be
careful of the level of the HOLD pin and RES pin also at the initial reset mode when power is applied. When the
HOLD pin is at L-Level, no reset occurs.
4-6. Proper cares in using standby function
When using the HOLD mode, an application circuit and program must be designed with the following in mind.
(1) The supply voltage at the standby state must not be less than specified.
(2) Input timing of each control signal (HOLD, RES, port A, INT, etc.) at the standby initiate/release state.
(3) Release operation must not be overlapped at the time of execution of the HALT instruction.
4-7. Sample application where the standby function is used for power failure backup
Power failure backup is an application where power failure of the main power source is detected by the HOLD pin,
etc. to cause the HOLD mode to be entered so that the current drain is minimized and a backup capacitor is used to
retain the contents of the internal registers even during power failure.
4-7-1. Sample application circuit (ceramic resonator OSC)
Fig. 4-4 shows a ceramic resonator OSC-applied circuit where the standby function is used for power failure backup.
100V
AC
Power
Supply
Unit(resistance:Ω, capacitance:F)
Fig. 4-4 Sample Application Circuit
No.2367–16/24
LC6512A, LC6513A
4-7-2. Operating waveform
The operating waveform in the sample application circuit in Fig. 4-4 is shown below. The mode is roughly divided as
follows:
⁄ Initial application of power
¤ Instantaneous break-(2)
¤ Instantaneous break-(3)
‹ Return from backup voltage
4-7-3. Operation of sample application circuit
¡ At the time of initial application of power
A reset occurs and the execution of the program starts at address 000H of the program counter (PC).
™ At the time of instantaneous break
(1) At the time of very short instantaneous break
The execution of the program continues.
(2) At the time of instantaneous break being a little longer than (1) (When the RES input voltage meets VIL and the
HOLD input voltage does not meet VIL).
A reset occurs during the execution of the program and the execution of the program starts at address 000H of
the program counter (PC).
Since the HOLD request signal is not applied to the HOLD pin, the HOLD mode is not entered.
(3) At the time of long instantaneous break (When both of the RES input voltage and HOLD input voltage meet
VIL).
The HOLD request signal is applied to the HOLD pin and the HOLD mode is entered.
When V+ rises after instantaneous break, a reset occurs to release the HOLD mode and the execution of the
program starts at address 000H of the program counter (PC).
£ At the time of return from backup voltage
A reset occurs and the execution of the program starts at address 000H of the program counter (PC).
No.2367–17/24
LC6512A, LC6513A
4-7-4. Notes for circuit design
¡ How to fix C3, R6, C2, R2
Fix closed loop (A) discharge time constants C3, R6 and HOLD pin charge time constants C2, R2 so that closed
loop (A) fully discharges before the HOLD input voltage gets lower than VIL at the time of instantaneous break and
the RES input voltage is sure to get lower than VIL (a reset occurs) when V+ rises after instantaneous break where
the HOLD input voltage gets lower than VIL.
™ How to fix C3, R7
Fix RES pin charge time constants C3, R7 so that when power is applied initially or the HOLD mode is released the
ceramic resonator OSC oscillates normally and the RES input voltage exceeds VIH and the program starts running.
£ How to fix R4, R5
Fix Tr bias constants R4, R5 so that when V+ rises after instantaneous break the RES input voltage gets lower than
VIL (brought to L-Level) before the HOLD input voltage exceeds VIH (brought to H- Level).
¢ How to fix C2, R3
Fix HOLD pin charge time constants C2, R3 so that when the HOLD mode is released from the backup mode the
HOLD input voltage does not exceed VOH (not brought to H-Level) until the RES input voltage gets lower than VIL
(brought to L-Level).
Fix C3, R7 and C2, R3 so that the time interval from the moment the HOLD input voltage exceeds VIH until the
moment the RES input voltage exceeds VIH is longer than the ceremic resonator OSC stabilizing time.
∞ When the load is heavy or the polling interval is long
Since Cl discharges largely, increase the capacity of C1 or separate (B) detection from V+ and use a power supply
or signal that rises faster than V+.
4-7-5. Notes for software design
When the HOLD request signal is detected, the HALT instruction is executed immediately. A concrete example is
shown below.
(1) An interrupt is inhibited before polling the HOLD request pin (HOLD pin).
(2) Polling of the HOLD pin and the HALT instruction are programmed consecutively.
…
[ Concrete example ]
…
RCTL
BP0
HALT
3
AAA
;EXTEN, TMEN ← 0 (External, timer interrupt inhibit)
;Polling of the HOLD pin (If H-Level, a branch occurs to AAA.)
;The HOLD mode is entered.
AAA:
No.2367–18/24
LC6512A, LC6513A
Appendix LC6500 Series Instruction Set (by Function)
Cycles
D7D6D5D4 D3D2D1D0
Bytes
Instruction
Accumulator manipulation instructions
Memory manipulation
instructions
Instruction code
Mnemonic
< <
Status
flag
affected
Description
Function
1100
0000
1
1
AC ← 0
The AC contents are cleared.
Clear CF
1110
0001
1
1
CF ← 0
The CF is reset.
STC
Set CF
1111
0001
1
1
CF ← 1
The CF is set.
CMA
Complement AC
1110
1011
1
1
AC ← (AC)
The AC contents are complemented
(zero bits become 1,one bits become 0)
ZF
INC
Increment AC
0000
1110
1
1
AC ← (AC)+1
The AC contents are incremented +1.
ZF CF
DEC
0000
1111
1
1
AC ← (AC)–1
The AC contents are decremented –1.
ZF CF
RAL
Decrement AC
Rotate AC left through
CF
0000
0001
1
1
AC0←(CF).ACn+1←
(ACn). CF←(AC3)
The AC contents are shifted left through the
CF.
ZF CF
TAE
Tranfer AC to E
0000
0011
1
1
Exchange AC with E
0000
1101
1
1
E←(AC)
(AC)→
←(E)
The AC contents are transferred to the E.
XAE
INM
lncrement M
0010
1110
1
1
M(DP)←[M(DP)]+1
The M(DP) contents are incrementcd +1.
ZF CF
DEM
Decrement M
0010
1111
1
1
M(DP)←[M(DP)]–1
ZF CF
SMB bit Set M data bit
0000
1
1
M(DP. B1B0)–1
RMB bit Reset M data bit
0010
10B1B0
10B1B0
1
1
M(DP. B1B0)←0
AD
Add M to AC
0110
0000
1
1
AC ←(AC)+[M(DP)]
ADC
Add M to AC with CF
0010
0000
1
1
AC←(AC)+[M(DP)]
+(CF)
The M (DP) contents are decremented –1.
A single bit of the M(DP)specified by B1 B0
is set.
A single bit of the M(DP) specified by B1 B0
is reset.
The AC contents and the M(DP) contents
are binary-added and the result is placed in
the AC.
The AC,CF, M(DP) contents are binaryadded and the result is placed in the AC.
DAA
Decimal adjust AC in
addition
Decimal adjust AC in
Subtraction
1110
0110
1
1
AC←(AC)+6
6 is added and to the AC contens.
ZF
1110
1010
1
1
AC←(AC)+10
10 is added to the AC contents.
ZF
The AC contents and the M(DP) contents
are exelusive-ORed and the result is placed
in the AC.
The AC contents and the M(DP) contents
are ANDed and the result is placed in the
AC.
The AC contents and the M(DP) contents
are ORed and the result is placed in the AC.
ZF
The AC contents and the M(DP) contents
are compared and the CF and ZF are
set/reset.
ZF CF
Exclusive or M to AC
1111
0101
1
1
AC←(AC)
[M(DP)]
AND
And M to AC
1110
0111
1
1
AC←(AC)
[M(DP)]
OR
Or M to AC
1110
0101
1
1
AC←(AC)
[M(DP)]
CM
Compare AC with M
1111
1011
1
1
[M(DP)]+(AC)+1
Comparison result
[M(DP)] >(AC)
[M(DP)] =(AC)
[M(DP)] <(AC)
0010
0100
1100
I3I2I1I0
2
2
ZF
CF
CF
The AC contents and the E contents are
exchanged.
EXL
Compare AC with
immediate data
I3 I2 I1 l0+(AC)+1
CF
0
1
1
CF
0
1
1
2
2
(DPL)
1
1
AC←I3 I2 I1 l0
The DPL contents and immediate data
I3 I2 I1 I0 are compared.
Immediate data I3 I2 I1 I0 in loaded in the
AC.
0000
S
1100
I3 I2 I1 l0
ZF CF
ZF
ZF
ZF CF
ZF
0
1
0
1100
I3I2I1I0
I3I2I1I0
0010
0101
ZF
ZF CF
ZF
0
1
0
The AC contents and immediate data
I3 I2 I1 I0 are compared and the ZF and CF
are set/reset.
Comparison result
I3I2l1l0 >(AC)
I3I2l1l0 =(AC)
I3I2l1l0 <(AC)
CLI data Compare DPL with
immediate data
LI data Load AC with
immediate data
Remarks
∗1
Clear AC
CLC
CI data
ZF
ZF
∗1
0010
1
1
M(DP) ←(AC)
The AC contents are stored in the M(DP).
Load AC from M
XM data Exchange AC with
M.then modify DPH
with immediate data
0010
0001
1
1
The M(DP) contents are loaded in the AC.
ZF
1010
0M2M1M0
1
2
The AC contents and the M(DP) contents
are exchanged.Then, the DPH contents are
modified with the contens of(DPH)
0M2M1M0.
ZF
The ZF is set/
reset accoding to
the result of (DPH)
0M2M1M0.
X
Exchange AC with M
1010
0000
1
2
AC←[M(DP)]
(AC) ← [M(DP)]
DPH ←(DPH)
• 0M2M1M0
(AC) ← [M(DP)]
The AC contents and the M(DP) contents
are exchanged.
ZF
The ZF is set/reset
accoding to the
DPH contents at
the time of instruction execution.
XI
Exchange AC with M.
then increment DPL
1111
1110
1
2
(AC) ← [M(DP)]
DPL ←(DPL)+1
←
The AC contents and the M(DP) contents
are exchanged.Then, the DPL contents are
incremented +1.
ZF
The ZF is set/reset
accoding to the
result of (DPL +1).
XD
Exchange AC wIth M.
then decrement DPL
1111
1111
1
2
(AC) ← [M(DP)]
DPL ←(DPL)–1
←
ZF
The ZF is set/reset
accoding to the
result of (DPL–1).
RTBL
Read table data from
program ROM
0110
0011
1
2
AC. E←ROM
(PCh.E. AC)
The AC contents and the M(DP) contents
are exchanged.Then, the DPL contents are
decremented –1.
The contents of ROM addressed by the PC
whose low-order 8 bits are replaced with the E
and AC contents are loaded in the AC and E.
←
←
Store AC to M
L
Load/store instructions
( ),[ ]: Contents
← : Transfer and direction
+:
Addition
–:
Subtraction
:
AND
:
OR
:
Exclusive OR
CLA
DAS
Operation/comparison instructions
M:
Memory
M(DP):
Memory addressed by DP
P(DPL): Input/output port addressed by DPL
PC:
Program counter
STACK: Stack register
TM :
Timer
TMF :
Timer (internal) interrupt request flag
At, Ha, La: Working register
ZF:
Zero flag
<
Symbols
Meaning
AC :
Accumulator
ACt:
Accumulator bit t
CF:
Carry flag
CTL:
Control register
DP:
Data pointer
E:
E register
EXTF: External interrupt request flag
Fn:
Flag bit n
No.2367–19/24
Bytes
Cycles
1
1
DPH←0
DPL←I3I2I1I0
The DPH and DPL are loaded with 0 and
immediate data I3I2I1I0 respectively.
LHI data Load DPH with
immediate data
0100
I3 I2 I1 I0
1
1
DPH←I3I2I1I0
lND
Increment DPL
1110
1110
1
1
DPL←(DPL)+1
DED
Decrement DPL
1110
1111
1
1
DPL←(DPL)–1
TAL
Transfer AC to DPL
1111
0111
1
1
DPL←(AC)
TLA
Transfer DPL to AC
1110
1001
1
1
AC←(DPL)
XAH
Exchange AC with
DPH
Exchange AC with
working register At
0010
0011
1
1
(AC)← (DPH)
The DPH is loaded with immediate
data I3I2I1I0.
The DPL contents are incremented
+1.
The DPL contents are decremented
–1.
The AC contents are transferred to
the DPL.
The DPL contents are transferred to
the AC.
The AC contents and the DPH
contents are exchanged.
1
1
1
1
1
1
1
1
(AC)← (A0)
(AC)← (A1)
(AC)← (A2)
(AC)← (A3)
1
1
1
1
(DPH)← (H0)
(DPH)← (H1)
1
1
1
1
(DPL) ← (L0)
(DPL)← (L1)
The DPH contents and the contents
of working register H0 or H1 specified
by a are exchanged.
The DPL contents and the contents of
working register L0 or L1 specified by
a are exchanged.
XAt
XA0
XA1
XA2
XA3
XHa
XH0
XH1
XLa
XL0
XL1
Exchange DPH with
working register Ha
Exchange DPL with
working register La
SFB flag Set flag bit
1110
1110
1110
1110
1111
1111
t1 t0
0000
0100
1000
1100
a
1000
1100
a
0000
0100
Description
1111
1111
0101
B3B2B1B0
1
1
Fn←1
A flag specified by B3B2B1B0 is set.
0001
B3B2B1B0
1
1
Fn←0
A flag specified by B3B2B1B0 is
reset.
0 1 1 0 1 P10P9P8
P7P6P5P4 P3P2P1P0
2
2
PC←PC11(orPC11) A jump to an address specified by the
PC11(or PC11)and immediate data
P10P9P8P7P6P5
P10 to P0 occurs.
P4P3P2P1P0
jump to an address specified by the
PC7 to 0 ←(E, AC) A
contents of the PC whose low-order 8
bits are replaced with the E and AC
contents occurs.
Reset flag bit
JMP
addr
Jump in the current
bank
JPEA
Jump in the current
page modified by E
and AC
1111
1010
1
1
CZP
addr
Call subroutine in the
Zero Page
1011
P3P2P1P0
1
1
STACK←(PC)+1
PC11 to 6.PC1 to 0←0
PC5 to 2←P3P2P1P0
A subroutine in page 0 of bank 0 is
called.
CAL
addr
Call subroutine in the
zero bank
1 0 1 0 1 P10P9P8
P7P6P5P4 P3P2P1P0
2
2
STACK←(PC)+2
PC11* to 0←OP10P9
P8P7P6P5P4P3P2P1P0
A subroutine in bank 0 is called.
RT
Return from
subroutine
Returnn from interrupt
routine
1
1
PC←(STACK)
A return from a subroutine occurs.
1
1
PC←(STACK)
CF ZF←CSF.ZSF
A return from an lnterrupt servicing
routine occurs.
0110
0010
0010
0010
Status
flag
affected
Remarks
ZF
ZF
ZF
The AC contents and the contents of
working register A0, A1, A2, or A3
specified by t1 t0 are exchanged.
RFB
flag
RTI
Branch instructions
Load DPH With Zero and
DPL with immediate data
respectively
←
←
Working register manipulation
instructions
I3 I2 I1 I0
LDZ
date
←
←
Flag manipulation instructions
1000
D7D6D5D4 D3D2D1D0
Function
←
←
←
←
Jump/subroutine instructions
Instruction code
Mnemonic
←
Data pointer manipulation instructions
Instruction
LC6512A, LC6513A
The flags are
divided into 4
groups of F0 to
F3,F4 to F7,F8 to
F11,F12 to F15.
The ZF is set/reset
according to the 4
bits including a
single bit specified
bit specified by
immediate data
B3B2B1B0.
ZF
ZF CF
BAt
addr
Branch on AC bit
0111
0 0 t1 t0
P7P6P5P4 P3P2P1P0
2
2
PC7 to 0←P7P6P5P4 If a single bit of the AC specified by
immediate data t1 t0 is 1,a branch to an
P3P2P1P0
address specified by immediate data P7
If ACt=1
to P0 within the current page occurs.
Mnemonic is
BA0 to BA3
according to
the value of t.
BNAt
addr
Branch on no AC bit
0 0 t1 t0
0011
P7P6P5P4 P3P2P1P0
2
2
PC7 to 0←P7P6P5P4 If a single bit of the AC specified by
immediate data t1t0 is 0,a branch to an
P3P2P1P0
address specified by immediate data P7
If ACt=0
to P0 within the current page occurs.
Mnemonic is
BNA0 to BNA3
according to
the value of t.
BMt
addr
Branch on M bit
0111
0 1 t1 t0
P7P6P5P4 P3P2P1P0
2
2
PC7 to 0←P7P6P5P4 If a single bit of the M(DP) specified by
immediate data t1t0 is 1,a branch to an
P3P2P1P0
address specified by immediate data P7
If [M(DP.t1t0)]=1
to P0 within the current page occurs.
Mnemonic is
BM0 to BM3
according to
the value of t.
BNMt
addr
Branch on no M bit
0011
0 1 t1 t0
P7P6P5P4 P3P2P1P0
2
2
PC7 to 0←P7P6P5P4 If a single bit of the M(DP) specified by
immediate data t1t0 is 0,a branch to an
P3P2P1P0
address specified by immediate data P7
If [M(DP.t1t0)]=0
to P0 within the current page occurs.
BPt
addr
Branch on Port bit
1 0 t1 t0
0111
P7P6P5P4 P3P2P1P0
2
2
PC7 to 0←P7P6P5P4 If a single bit of port P(DPL) specified by
immediate data t1 t0 is 1,a branch to an
P3P2P1P0
address specified by immediate data P7
If [P(DPL.t1t0)]=1
toP0 within the current page occurs.
Mnemonic is
BNM0 to
BNM3
according to
the value of t.
Mnemonic is
BP0 to BP3
according to
the value of t.
BNPt
addr
Branch on no Port bit
0011
1 0 t1 t0
P7P6P5P4 P3P2P1P0
2
2
PC7 to 0←P7P6P5P4 If a single bit of port P(DPL) specified by
immediate data t1 t0 is 0,a branch to an
P3P2P1P0
address specified by immediate data P7
If [P(DPL.t1t0)]=0
to P0 within the current page occurs.
BTTM
addr
Branch on timer
2
2
PC7 to 0←P7P6P5P4
P3P2P1P0
If TMF=1
then TMF←0
0111
1100
P7P6P5P4 P3P2P1P0
If theTMF is 1,a branch to an address
specified by immediate data P7 to P0
within the current page occurs.The TMF
is reset.
Mnemonic is
BNP0 to BNP3
according to
the value of t.
TMF
No.2367–20/24
D7D6D5D4 D3D2D1D0
BNTM
addr
Branch on no timer
BI addr
Branch on interrupt
0011
1100
Cycles
Instruction code
Mnemonic
Bytes
Instruction
LC6512A, LC6513A
2
2
PC7 to 0←P7P6P5P4
P3P2P1P0
If TMF=0
then TMF←0
2
2
PC7 to 0←P7P6P5P4
P3P2P1P0
If EXTF=1
then EXTF←0
2
2
PC7 to 0←P7P6P5P4
P3P2P1P0
If EXTF=0
then EXTF←0
2
2
2
2
2
2
2
2
2
2
PC7 to 0←P7P6P5P4
P3P2P1P0
If CF=1
PC7 to 0←P7P6P5P4
P3P2P1P0
If CF=0
PC7 to 0←P7P6P5P4
P3P2P1P0
If ZF=1
PC7 to 0←P7P6P5P4
P3P2P1P0
If ZF=0
PC7 to 0←P7P6P5P4 If a fiag bit of the 16 flags specified by
P3P2P1P0 immediate data n3n2n1n0 is 1,a branch to
an address specified by immediate data P7
If Fn=1
2
2
PC7 to 0←P7P6P5P4 If a fiag bit of the 16 flags specified by
P3P2P1P0 immediate data n3n2n1n0 is 1,a branch to
an address specified by immediate data P7
If Fn=0
P7P6P5P4 P3P2P1P0
0111
1101
P7P6P5P4 P3P2P1P0
Branch instructions
BNI
addr
Branch on no lnterrupt
0011
1101
P7P6P5P4 P3P2P1P0
BC addr Branch on CF
0111
1111
P7P6P5P4 P3P2P1P0
BNC
addr
Branch on no CF
001l
1111
P7P6P5P4 P3P2P1P0
BZ addr Branch on ZF
011l
1110
P7P6P5P4 P3P2P1P0
Function
Description
Branch on no ZF
BFn
addr
Branch on flag bit
BNFn
addr
Branch on no flag bit
IP
Input port to AC
0000
1100
1
1
AC←[P(DPL)]
OP
Output AC to port
0110
0001
1
1
P(DPL)←(AC)
0000
0 1 B1B0
1
2
P(DPL B1B0)←1
Immediate data B1B0- specified one
bit in port p(DPL)is set.
Immediate data B1B0- specified one
bit in port p(DPL)is reset.
00ll
1110
1 1 0 1 n3n2n1n0
P7P6P5P4 P3P2P1P0
Remarks
If the TMF is 0, a branch to an
TMF
address specified by immediate data
P7 to P0 within the current page
occurs. The TMF is reset.
If the EXTF is 1, a branch to an
EXTF
address specified by immediate data
P7 to P0 within the current page
occurs. The EXTF is reset.
If the EXTF is 0, a brance to an
EXTF
address specified by immediate data
P7 to P0 within the current page
occurs. The EXTF is reset.
If the CF is 1, a branch to an address
specified by immediate data P7 to P0
within the current page occurs.
If the CF is 0, a branch to an address
specified by immediate data P7 to P0
within the current page occurs.
If the ZF is 1, a branch to an address
specified by immediate data P7 to P0
within the current page occurs.
If the ZF is 0, a branch to an address
specified by immediate data P7 to P0
within the current page occurs.
BNZ
addr
P7P6P5P4 P3P2P1P0
Status
flag
affected
Mnemonic is
BFO to BF15
according to
the value of n.
Other instructions
Input/Output instructions.
to P0 within the current page occurs.
SPB bit Set port bit
1001
n3n2n1n0
P7P6P5P4 P3P2P1P0
to P0 within the current page occurs.
The contents of port P(DPL) are inputted to
the AC.
The AC contents are outputted to port
P(DPL)
RPB bit
Reset port bit
0010
0 1 B1B0
1
2
P(DPL B1B0)←0
SCTL
bit
Set control register
bit(S)
0010
1000
1100
B3B2B1B0
2
2
CTL←(CTL)
Immediate data B3B2B1B0-specified
B3B2B1B0 bits in the control register are set.
RCTL
bit
Reset control register
bit(S)
0010
1001
1100
B3B2B1B0
2
2
CTL←(CTL)
Immediate data B3B2B1B0-specified
B3B2B1B0 bits in the control register are reset.
WTTM
Write timer
1111
1001
1
1
TM←(E).(AC)
TMF ←0
The E and AC contents are loaded in
the timer. The TMF reset.
HALT
Halt
1111
0110
1
1
Halt
All operations stop.
NOP
No operation
0000
0000
1
1
No operation
No operation is performed, but 1
machine cycle is consumed.
Mnemonic is
BNFO to
BNF15
according to
the value of n.
ZF
Mnemonic is
BNFO to BNF15
according to the
value of n.
ZF
When this instruction is executed,the
E register contents
are destroyed.
ZF
TMF
*1 lf the LI instruction or CLA instruction is used consecutively in such a manner as LI, LI, LI……,or CLA,
CLA, CLA, ……, the first LI instruction or CLA instruction only is effective and the following LI instructions or CLA instructions are changed to the NOP instructions.
No.2367–21/24
LC6512A, LC6513A
LC6500 Series Instruction Map
No.2367–22/24
Note
(1) The Branch instructions include the following instructions, and only when the branch
conditions are met immediate data of ROM is loaded in the PC.
BAt BPt BI BZ
BNAt BNPt BNI BNZ
BMt BTM BC BFn
BNMt BNTM BNC BNFn
(2)ACZ,C-----Suffix Z, C represent that the ZF, CF flags of the status register are affected.
LC6512A, LC6513A
LC6500 Series Programming Model
No.2367–23/24
LC6512A, LC6513A
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer's
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer's products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products(including technical data,services) described or
contained herein are controlled under any of applicable local export control laws and regulations,
such products must not be expor ted without obtaining the expor t license from the authorities
concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification"
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
This catalog provides information as of October, 2001. Specifications and information herein are subject
to change without notice.
PS No.2367–24/24