CMOS LSI LC66E2316 No. 5486 Four-Bit Single-Chip Microcontroller with 16 KB of On-Chip EPROM Preliminary Overview Package Dimensions The LC66E2316 is an on-chip EPROM version of the LC6623XX Series CMOS 4-bit single-chip microcontrollers. The LC66E2316 provides the same functions as the LC662316A, and is pin compatible with that product. Since the LC66E2316 is provided in a window package, it can be reprogrammed repeatedly and is thus optimal for program development. unit: mm 3127-DIC42S [LC66E2316] 0.25 37.32 1 21 14.99 22 0.46 3.4min 1.27 6.5max Features and Functions 1.778 SANYO: DIC42S unit: mm 3157-QFC48 [LC66E2316] 20.0 1.5 0.35 3.0 14.0 3.0 1.0 0.35 0.15 36 25 1.0 24 13 48 1.5 20.0 37 14.0 • On-chip EPROM capacity of 16 kilobytes, and an onchip RAM capacity of 512 × 4 bits. • Fully supports the LC66000 Series common instruction set (128 instructions). • I/O ports: 36 pins • DTMF generator This microcontroller incorporates a circuit that can generate two sine wave outputs, DTMF output, or a melody output for software applications. • 8-bit serial interface: one circuit • Instruction cycle time: 0.95 to 10 µs (at 4.5 to 5.5 V) • Powerful timer functions and prescalers — Time limit timer, event counter, pulse width measurement, and square wave output using a 12-bit timer. — Time limit timer, event counter, PWM output, and square wave output using an 8-bit timer. — Time base function using a 12-bit prescaler. • Powerful interrupt system with 10 interrupt factors and 7 interrupt vector locations. — External interrupts: 3 factors/3 vector locations — Internal interrupts: 4 factors/4 vector locations (Waveform output internal interrupts: 3 factors and 1 vector; shared with external expansion interrupts) • Flexible I/O functions Selectable options include 20-mA drive outputs, inverter circuits, pull-up and open-drain circuits. • Optional runaway detection function (watchdog timer) • 8-bit I/O functions • Power saving functions using halt and hold modes. • Packages: DIC42S (window), QFC48 (window) • Evaluation LSIs: LC66599 (evaluation chip) + EVA800/850 - TB662YXX2 15.24 0.8 42 1 12 2.2 4.2 4.77max SANYO: QFC48 SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 22897HA (OT) No. 5486-1/26 LC66E2316 Series Organization Type No. No. of pins ROM capacity RAM capacity Package LC66304A/306A/308A 42 4 K/6 K/8 KB 512 W DIP42S QFP48E LC66404A/406A/408A 42 4 K/6 K/8 KB 512 W DIP42S QFP48E LC66506B/508B/512B/516B 64 6 K/8 K/12 K/16 KB 512 W DIP64S QFP64A LC66354A/356A/358A 42 4 K/6 K/8 KB 512 W DIP42S QFP48E LC66354S/356S/358S 42 4 K/6 K/8 KB 512 W QFP44M Features Normal versions 4.0 to 6.0 V/0.92 µs Low-voltage versions 2.2 to 5.5 V/3.92 µs LC66556A/558A/562A/566A 64 6 K/8 K/12 K/16 KB 512 W DIP64S QFP64E LC66354B/356B/358B 42 4 K/6 K/8 KB 512 W DIP42S QFP48E LC66556B/558B/562B/566B 64 6 K/8 K/12 K/16 KB 512 W DIP64S QFP64E Low-voltage high-speed versions 3.0 to 5.5 V/0.92 µs LC66354C/356C/358C 42 4 K/6 K/8 KB 512 W DIP42S QFP48E 2.5 to 5.5 V/0.92 µs LC662104A/06A/08A 30 4 K/6 K/8 KB 384 W DIP30SD MFP30S LC662304A/06A/08A/12A/16A 42 4 K/6 K/8 K/12 K/16 KB 512 W DIP42S QFP48E LC662508A/12A/16A 64 8 K/12 K/16 KB 512 W DIP64S QFP64E LC665304A/06A/08A/12A/16A 48 4 K/6 K/8 K/12 K/16 KB 512 W DIP48S QFP48E LC66E308 42 EPROM 8 KB 512 W DIC42S with window QFC48 with window LC66P308 42 OTPROM 8 KB 512 W DIP42S QFP48E DIC42S with window QFC48 with window LC66E408 42 EPROM 8 KB 512 W LC66P408 42 OTPROM 8 KB 512 W DIP42S QFP48E QFC64 with window LC66E516 64 EPROM 16 KB 512 W DIC64S with window LC66P516 64 OTPROM 16 KB 512 W DIP64S QFP64E LC66E2108* 30 EPROM 8 KB 384 W LC66E2316 42 EPROM 16 KB 512 W DIC42S with window QFC48 with window LC66E2516 64 EPROM 16 KB 512 W DIC64S with window QFC64 with window LC66E5316 52/48 EPROM 16 KB 512 W DIC52S with window QFC48 with window LC66P2108* 30 OTPROM 8 KB 384 W DIP30SD MFP30S LC66P2316* 42 OTPROM 16 KB 512 W DIP42S QFP48E LC66P2516 64 OTPROM 16 KB 512 W DIP64S QFP64E LC66P5316 48 OTPROM 16 KB 512 W DIP48S QFP48E On-chip DTMF generator versions 3.0 to 5.5 V/0.95 µs Dual oscillator support 3.0 to 5.5 V/0.95 µs Window and OTP evaluation versions 4.5 to 5.5 V/0.92 µs Window evaluation versions 4.5 to 5.5 V/0.92 µs OTP 4.0 to 5.5 V/0.95 µs Note: * Under development No. 5486-2/26 LC66E2316 Pin Assignments DIC42S P20/SI0/A0 P21/SO0/A1 P22/SCK0/A2 P23/INT0/A3 P30/INT1/A4 P31/POUT0/A5 P32/POUT1/A6 VSS OSC1 OSC2 VDD RES/VPP/OE PE0 PE1 TEST/EPMOD P33/HOLD P40/INV0I/A7 P41/INV0O/A8 P42/INV1I/A9 P43/INV1O/A10 P50/A11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 LC66E2316 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P13/D7 P12/D6 P11/D5 P10/D4 P03/D3 P02/D2 P01/D1 P00/D0 PD3/INV3O PD2/INV3I PD1/INV2O PD0/INV2I PC3/DASEC PC2/CE P63/PIN1 P62/DT P61 P60/ML P53/TA P52/A13 P51/A12 P02/D2 P01/D1 P00/D0 PD3/INV3O PD2/INV3I PD1/INV2O NC PD0/INV2I PC3/DASEC PC2/CE P63/PIN P62/DT QFC48 36 35 34 33 32 31 30 29 28 27 26 25 37 24 38 23 39 22 40 21 LC66E2316 41 20 42 19 43 18 44 17 45 16 46 15 47 14 48 13 1 2 3 4 5 6 7 8 9 10 11 12 P31/POUT0/A5 P32/POUT1/A6 VSS OSC1 OSC2 NC VDD RES/VPP/OE PE0 PE1 TEST/EPMOD P33/HOLD P03/D3 P10/D4 P11/D5 P12/D6 P13/D7 NC NC P20/SI0/A0 P21/SO0/A1 P22/SCK0/A2 P23/INT0/A3 P30/INT1/A4 P61 P60/ML P53/INT2/TA P52/A13 P51/A12 NC NC P50/A11 P43/INV1O/A10 P42/INV1I/A9 P41/INV0O/A8 P40/INV0I/A7 Top view No. 5486-3/26 LC66E2316 Usage Notes The LC66E2316 was created for program development, product evaluation, and prototype development for products based on the LC6623XX Series microcontrollers. Keep the following points in mind when using this product. 1. After a reset The RES pin must be held low for an additional 3 instruction cycles after the oscillator stabilization period has elapsed. Also, the port output circuit types are set up during the 9 instruction cycles immediately after RES is set high. Only then is the program counter set to 0 and program execution started from that location. (The port output circuits all revert to the open-drain type during periods when RES is low.) VDDmin VDD OSC At least 10 ms Oscillator stabilization RES At least 3 instruction Location Location 0 1 Program execution (PC) Open drain Port output type Option switching Option specification period 9 instruction cycles 2. Notes on LC6623XX evaluation The high end of the EPROM area (locations 3FF0H to 3FFFH) are the option specification area. Option specification data must be programmed for and loaded into this area. The Sanyo specified cross assembler for this product is the program LC66S.EXE. Also, insert JMP instructions so that user programs do not attempt to execute addresses that exceed the capacity of the mask ROM, and write zeros (00H) to areas (other than 3FF0H to 3FFFH) that exceed the actual capacity of the mask ROM. 3. Always apply an opaque seal to the window on the LC66E2316 package when actually using the device. Main differences between the LC66E2316, LC66P2316, and LC6623XX Series Item LC6623XX Series (mask version) LC66E2316 LC66P2316 Differences in the main characteristics • Operating temperature range –30 to +70°C +10 to +40°C –30 to +70°C • Operating supply voltage/operating frequency (cycle time) 3.5 to 5.5 V/0.95 to 10 µs 4.5 to 5.5 V/0.95 to 10 µs 4.0 to 5.5 V/0.95 to 10 µs • Input high-level current (RES) Maximum: 1 µA Typical: 10 µA (normal operation and halt mode) Hold mode: 1 µA maximum Typical: 10 µA (normal operation and halt mode) Hold mode: 1 µA maximum • Input low-level current (RES) Maximum: 1 µA Typical: 100 µA Typical: 100 µA Larger than that for the mask versions Typical: 10 nA, maximum: 10 µA* Larger than that for the mask versions Typical: 10 nA, maximum: 10 µA* • Current drain (Operating at 4 MHz) (Halt mode at 4 MHz) (Hold mode) Typical: 10 nA, maximum: 10 µA Port output types at reset The output type specified in the options Open-drain outputs Open-drain outputs Package • DIP42S • QFP48E • DIC42S window package • QFC48 window package • DIP42S • QFP48E Note: * Although the microcontroller will remain in hold mode if the RES pin is set low while it is in hold mode, always use the reset start sequence (after switching HOLD from low to high, switch RES from low to high) when clearing hold mode. Also not that a current of about 100 µA flows from the RES pin when it is low. This increases the hold mode current drain by about 100 µA. See the data sheets for the individual products for details on other differences. No. 5486-4/26 LC66E2316 System Block Diagram RAM STACK (512W) RES TEST OSC1 E DD DD SP M P P P P R HL XY OSC2 HOLD DT C FLAG SYSTEM CONTROL ML EPROM 16KB DTMF GEN. PE PD A0 to A13 D0 to D7 Z E ALU A MPX PRESCALER EPROM control CE DASEC Vpp/OE EPMOD TA PC TIMER0 SERIAL I/O 0 POUT0 SI0 SO0 SCK0 INT0 MPX INT1. INT2 INTERRUPT CONTROL MPX TIMER1 PIN1. POUT1 PC INVxO INVxI (x=0 to 3) P0 P1 P2 P3 P4 P5 P6 Pin Function Overview Pin P00/D0 P01/D1 P02/D2 P03/D3 P10/D4 P11/D5 P12/D6 P13/D7 P20/SI0/A0 P21/SO0/A1 P22/SCK0/ A2 P23/INT0/A3 I/O I/O I/O I/O Overview Output driver type Options I/O ports P00 to P03 • Input or output in 4-bit or 1-bit units • P00 to P03 support the halt mode control function (This function can be specified in bit units.) • Used as data pins in EPROM mode • Pch: Pull-up MOS type • Nch: Intermediate sink current type • Pull-up MOS or Nch OD output • Output level on reset I/O ports P10 to P13 • Input or output in 4-bit or 1-bit units • Used as data pins in EPROM mode • Pch: Pull-up MOS type • Nch: Intermediate sink current type • Pull-up MOS or Nch OD output • Output level on reset I/O ports P20 to P23 • Input or output in 4-bit or 1-bit units • P20 is also used as the serial input SI0 pin. • P21 is also used as the serial output SO0 pin. • P22 is also used as the serial clock SCK0 pin. • P23 is also used as the INT0 interrupt request pin, and also as the timer 0 event counting and pulse width measurement input. • Used as address pins in EPROM mode State after a Standby mode reset operation Hold mode: Output off High or low (option) Halt mode: Output retained Hold mode: Output off High or low (option) Halt mode: Output retained Hold mode: Output off • Pch: CMOS type • Nch: Intermediate sink current type CMOS or Nch OD output H Hold mode: Output off Continued on next page. No. 5486-5/26 LC66E2316 Continued from preceding page. Pin P30/INT1/A4 P31/POUT0/ A5 P32/POUT1/ A6 P33/HOLD P40/INV0I/ A7 P41/INV0O/ A8 P42/INV1I/ A9 P43/INV1O/ A10 P50/A11 P51/A12 P52/A13 P53/INT2/TA P60/ML P61 P62/DT P63/PIN1 I/O Overview I/O I/O ports P30 to P32 • Input or output in 3-bit or 1-bit units • P30 is also used as the INT1 interrupt request. • P31 is also used for the square wave output from timer 0. • P32 is also used for the square wave and PWM output from timer 1. • P31 and P32 also support 3-state outputs. • Used as address pins in EPROM mode I Hold mode control input • Hold mode is set up by the HOLD instruction when HOLD is low. • In hold mode, the CPU is restarted by setting HOLD to the high level. • This pin can be used as input port P33 along with P30 to P32. • When the P33/HOLD pin is at the low level, the CPU will not be reset by a low level on the RES pin. Therefore, applications must not set P33/HOLD low when power is first applied. I/O I/O ports P40 to P43 • Input or output in 4-bit or 1-bit units • Input or output in 8-bit units when used in conjunction with P50 to P53. • Can be used for output of 8-bit ROM data when used in conjunction with P50 to P53. • Dedicated inverter circuit (option) • Used as address pins in EPROM mode I/O I/O I/O ports P50 to P53 • Input or output in 4-bit or 1-bit units • Input or output in 8-bit units when used in conjunction with P40 to P43. • Can be used for output of 8-bit ROM data when used in conjunction with P40 to P43. • P53 is also used as the INT2 interrupt request. • Used as address pins in EPROM mode I/O ports P60 to P63 • Input or output in 4-bit or 1-bit units • P60 is also used as the melody output ML pin. • P62 is also used as the tone output DT pin. • P63 is also used for the event count input to timer 1. Output driver type Options State after a Standby mode reset operation Hold mode: Output off • Pch: CMOS type • Nch: Intermediate sink current type CMOS or Nch OD output H Halt mode: Output retained • Pch: Pull-up MOS type • CMOS type when the inverter circuit option is selected • Nch: Intermediate sink current type • Pull-up MOS or Nch OD output • Output level on reset • Inverter circuit • High or low (option) • Inverter I/O is set to the output off state. Hold mode: Port output off, inverter output off Halt mode: Port output retained, inverter output continues Hold mode: Output off • Pch: Pull-up MOS type • Nch: Intermediate sink current type • Pull-up MOS or Nch OD output • Output level on reset High or low (option) Halt mode: Output retained Hold mode: Output off • Pch: CMOS type • Nch: Intermediate sink current type CMOS or Nch OD output H Halt mode: Output retained Continued on next page. No. 5486-6/26 LC66E2316 Continued from preceding page. Pin PC2/CE PC3/DASEC PD0/INV2I PD1/INV2O PD2/INV3I PD3/INV3O I/O Overview I I/O ports PC2 to PC3 • Output in 2-bit or 1-bit units • PC3 is also used as the control CE and DASEC pin in EPROM mode. • Pch: CMOS type • Nch: Intermediate sink current type Dedicated input ports PD0 to PD3 Dedicated inverter circuits (option) • When the inverter circuit option is selected. • Pch: CMOS type • Nch: Intermediate sink current type I I OSC1 I System clock oscillator connections O When an external clock is used, leave OSC2 open and connect the clock signal to OSC1. I System reset input • When the P33/HOLD pin is at the high level, a low level input to the RES pin will initialize the CPU. • This pin is also used as the VPP/OE pin in EPROM mode. I CPU test pin This pin must be connected to VSS during normal operation. Setting this pin to +12 V switches the LC66E2316 to EPROM mode. RES/VPP/ OE TEST/ EPMOD VDD VSS Options CMOS or Nch OD output Inverter circuits State after a Standby mode reset operation Hold mode: Port output off H Halt mode: Port output retained Normal input Inverter I/O goes to the output off state. Hold mode: Inverter Output off Halt mode: Inverter output continues Hold mode: input disabled PE0 PE1 OSC2 Output driver type Dedicated input ports Halt mode: inputs accepted Ceramic oscillator or external clock selection Option selection Hold mode: oscillator stops Halt mode: oscillator continues Power supply pins Note: Pull-up MOS type: The output circuit includes a MOS transistor that pulls the pin up to VDD. CMOS output: Complementary output. OD output: Open-drain output. No. 5486-7/26 LC66E2316 User Options 1. Port 0, 1, 4, and 5 output level at reset option The output levels at reset for I/O ports 0, 1, 4, and 5, in independent 4-bit groups, can be selected from the following two options. Option Conditions and notes 1. Output high at reset The four bits of ports 0, 1, 4, or 5 are set in a group 2. Output low at reset The four bits of ports 0, 1, 4, or 5 are set in a group 2. Oscillator circuit options • Main clock Option Circuit OSC1 1. External clock 2. Ceramic oscillator Conditions and notes The input has Schmitt characteristics C1 OSC1 Ceramic oscillator C2 OSC2 Note: There is no RC oscillator option. 3. Watchdog timer option A runaway detection function (watchdog timer) can be selected as an option. 4. Port output type options • The output type of each bit (pin) in ports P0, P1, P2, P3 (except for the P33/HOLD pin), P4, P5, P6, and PC can be selected individually from the following two options. Option Circuit Conditions and notes Output data 1. Open-drain output Input data The port P2, P3, P5, and P6 inputs have Schmitt characteristics. DSB Output data 2. Output with built-in pull-up resistor Input data The port P2, P3, P5, and P6 inputs have Schmitt characteristics. The CMOS outputs (ports P2, P3, P6, and PC) and the pull-up MOS outputs (P0, P1, P4, and P5) are distinguished by the drive capacity of the p-channel transistor. DSB No. 5486-8/26 LC66E2316 5. Inverter array circuit option One of the following options can be selected for each of the following port sets: P40/P41, P42/P43, PD0/PD1, and PD2/PD3. Option Circuit Conditions and notes Output data Input data When the open-drain output type is selected DSB 1. Normal port I/O circuit Output data When the built-in pull-up resistor output type is selected Input data DSB Input Output data high Input data DSB 2. Inverter I/O circuit Output Output data high If this option is selected, the I/O circuit is disabled by the DSB signal. Also note that the open-drain port output type option and the high level at reset option must be selected. Input data DSB No. 5486-9/26 LC66E2316 LC662316 Series Option Data Area and Definitions ROM area 3FF0H Bit P5 6 P4 Unused Oscillator option 0 = external clock, 1 = ceramic oscillator 3 Unused This bit must be set to 0. 2 P1 1 P0 This bit must be set to 0. Output level at reset Watchdog timer option 7 P13 6 P12 5 P11 4 P10 3 P03 2 P02 1 P01 7 3FF3H 0 = high level, 1 = low level 4 0 3FF2H Output level at reset Option/data relationship 5 0 3FF1H Option specified 7 0 = low level, 1 = high level 0 = none, 1 = yes (present) Output type 0 = OD, 1 = PU Output type 0 = OD, 1 = PU P00 Unused 6 P32 5 P31 4 P30 3 P23 2 P22 1 P21 0 P20 7 P53 6 P52 5 P51 4 P50 3 P43 2 P42 1 P41 0 P40 This bit must be set to 0. Output type 0 = OD, 1 = PU Output type 0 = OD, 1 = PU Output type 0 = OD, 1 = PU Output type 0 = OD, 1 = PU 7 6 5 3FF4H Unused This bit must be set to 0. 4 3 P63 2 P62 1 P61 0 P60 Output type 0 = OD, 1 = PU 7 6 5 3FF5H Unused This bit must be set to 0. Unused This bit must be set to 0. Unused This bit must be set to 0. Unused This bit must be set to 0. 4 3 2 1 0 7 6 5 3FF6H 4 3 2 1 0 Continued on next page. LC66E2316 Continued from preceding page. ROM area Bit Option specified Option/data relationship 7 6 5 3FF7H This bit must be set to 0. 4 3 PC3 2 PC2 1 0 3FF8H Unused Output type Unused 0 = OD, 1 = PU This bit must be set to 0. 7 ML disabled option 0 = disabled, 1 = enabled 6 Unused This bit must be set to 1. 5 Unused This bit must be set to 1. 4 PD3 3 PD1 2 Inverter output Unused 1 P43 0 P41 0 = inverter output, 1 = none This bit must be set to 1. Inverter output 0 = inverter output, 1 = none 7 6 5 3FF9H Unused This bit must be set to 0. Unused This bit must be set to 0. Unused This bit must be set to 0. Unused This bit must be set to 0. Unused This bit must be set to 0. Unused This bit must be set to 0. Unused This bit must be set to 0. Unused This bit must be set to 0. Reserved. Must be set to predefined data values. This data is generated by the assembler. If the assembler is not used, set this data to ‘00’. 4 3 2 1 0 7 6 5 3FFAH 4 3 2 1 0 7 6 5 3FFBH 4 3 2 1 0 7 6 5 3FFCH 4 3 2 1 0 7 6 5 3FFDH 4 3 2 1 0 Continued on next page. No. 5486-11/26 LC66E2316 Continued from preceding page. ROM area Bit Option specified Option/data relationship 7 6 5 4 3FFEH 3 Reserved. Must be set to predefined data values. This data is generated by the assembler. If the assembler is not used, set this data to ‘00’. Reserved. Must be set to predefined data values. This data is generated by the assembler. If the assembler is not used, set this data to ‘00’. 2 1 0 7 6 5 4 3FFFH 3 2 1 0 Usage Notes 1. Option specification When using a Sanyo cross assembler with the LC66E2316, use the version called “LC66S.EXE” and specify the actual microcontroller to be evaluated with the CPU pseudo instruction in the source file. The port options must be specified in the source file. The cross assembler will create an option code list in the option specification area (locations 3FF0H to 3FFFH). It is also possible to directly set up data in the option specification area. If this is done, the options must be specified according to the option code creation table shown on the following page. 2. Writing the EPROM Use a special-purpose writing conversion board (the W66EP5316D for the DIP package, and the W66EP2316Q for the QFP package) to allow the EPROM programmers listed below to be used when writing the data created by the cross assembler to the LC66E2316. • The EPROM programmers listed below can be used. Manufacturer Models that can be used Advantest R4945, R4944A, R4943, or equivalent products Ando AF9704 AVAL Minato Electronics — MODEL1890A • The “27512 (VPP 12.5 V) Intel high-speed write” technique must be used to write the EPROM. Set the address range to location 0 to 3FFFH. The DASEC jumper must be off. 3. Using the data security function The data security function sets up the microcontroller in advance so that data that was written to the microcontroller EPROM cannot be read out. Use the following procedure to enable the LC66E2316 data security function. • Set the write conversion board DASEC jumper to the on position. • Write the data to the EPROM once again. At this time, since this function will operate, the EPROM programmer will issue an error. However, this error does not indicate that there was a problem in either the programmer or the LSI. Notes: 1. If the data at all addresses was “FF” at step 2, the data security function will not be activated. Notes: 2. The data security function will not be activated at step 2 if the “blank → program → verify” operation sequence is used. Notes: 3. Always return the jumper to the off position after the data security function has been activated. No. 5486-12/26 LC66E2316 4. Erase procedure Use a general-purpose EPROM eraser to erase data written to the EPROM. LC66E2316 (DIC) LC66E2316 (QFC) Cut corner Pin 1 SW DASEC Pin 1 Aligned to the top SW DASEC Pin 1 O Write board (W66EP5316D) Write board (W66EP2316Q) Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Maximum supply voltage Input voltage Symbol VDD max VIN1 VIN2 Output voltage Output current per pin Total pin current Allowable power dissipation Conditions VDD P2, P3 (except for the P33/HOLD pin), P61, and P63 All other inputs VOUT1 P2, P3 (except for the P33/HOLD pin), P61, and P63 VOUT2 All other inputs Ratings Unit Note –0.3 to +7.0 V –0.3 to +12.0 V 1 –0.3 to VDD + 0.3 V 2 –0.3 to +12.0 V 1 –0.3 to VDD + 0.3 V 2 mA 3 ION1 P0, P1, P2, P3 (except for the P33/HOLD pin), P4, P5, P6, PC 20 20 mA 3 2 mA 4 ION2 P41, P43, PC3, PD1, PD3 –IOP1 P0, P1, P4, P5 –IOP2 P2, P3 (except for the P33/HOLD pin), P6,and PC 4 mA 4 Σ ION1 P0, P1, P2, P3 (except for the P33/HOLD pin), PD 75 mA 3 Σ ION2 P4, P5, P6, PC 75 mA 3 Σ IOP1 P0, P1, P2, P3 (except for the P33/HOLD pin), PD 25 mA 4 Σ IOP2 P4, P5, P6, PC Pd max Ta = +10 to +40°C: DIC42S (QFC48) 25 mA 4 600 (430) mW 5 Operating temperature Topr –30 to +70 °C Storage temperature Tstg –55 to +125 °C Note: 1. Applies to pins with open-drain output specifications. For pins with other than open-drain output specifications, the ratings in the pin column for that pin apply. 2. For the oscillator input and output pins, levels up to the free-running oscillation level are allowed. 3. Sink current (Applies to PD when the inverter array specifications have been selected.) 4. Source current (Applies to all pins except PD for which the pull-up output specifications, the CMOS output specifications, or the inverter array specifications have been selected. Applies to P8 pins for which the inverter array specifications have been selected.) Contact your Sanyo representative for the electrical characteristics when the inverter array or buffer array options are specified. No. 5486-13/26 LC66E2316 Allowable Operating Ranges at Ta = +10 to +40°C, VSS = 0 V, VDD = 4.5 to 5.5 V, unless otherwise specified. Parameter Operating supply voltage Memory retention supply voltage Input high-level voltage Input low-level voltage Operating frequency (instruction cycle time) Symbol VDD Conditions min typ max Unit Note VDD 4.5 5.5 V VDDH VDD: During hold mode 1.8 5.5 V VIH1 P2, P3 (except for the P33/HOLD pin), P61, and P63: N-channel output transistor off 0.8 VDD 10.0 V VIH2 P33/HOLD, RES, OSC1: N-channel output transistor off 0.8 VDD VDD V VIH3 P0, P1, P4, P5, PC, PD, PE: N-channel output transistor off 0.8 VDD VDD V 2 VIL1 P2, P3 (except for the P33/HOLD pin), P6, RES, and OSC1: N-channel output transistor off VSS 0.2 VDD V 1 VIL2 P33/HOLD: VDD = 1.8 to 5.5 V VSS 0.2 VDD V VIL3 P0, P1, P4, P5, PC, PD, PE, TEST: N-channel output transistor off VSS 0.2 VDD V 0.4 (10) 4.20 (0.95) MHz (µs) 0.4 4.20 MHz 100 fop (Tcyc) 1 2 [External clock input conditions] Frequency fext OSC1: Defined by Figure 1. Input the clock signal to OSC1 and leave OSC2 open. (External clock input must be selected as the oscillator circuit option.) Pulse width textH, textL OSC1: Defined by Figure 1. Input the clock signal to OSC1 and leave OSC2 open. (External clock input must be selected as the oscillator circuit option.) Rise and fall times textR, textF OSC1: Defined by Figure 1. Input the clock signal to OSC1 and leave OSC2 open. (External clock input must be selected as the oscillator circuit option.) ns 30 ns Note: 1. Applies to pins with open-drain specifications. However, VIH2 applies to the P33/HOLD pin. When ports P2, P3, and P6 have CMOS output specifications they cannot be used as input pins. 2. PC port pins with CMOS output specifications cannot be used as input pins. Contact your Sanyo representative for the allowable operating ranges for P4 and PD when the inverter array is used. No. 5486-14/26 LC66E2316 Electrical Characteristics at Ta = +10 to +40°C, VSS = 0 V, VDD = 4.5 to 5.5 V unless otherwise specified. Parameter Symbol Input high-level current Input low-level current Unit Note 5.0 µA 1 P0, P1, P4, P5, PC, OSC1, and P33/HOLD (Does not apply to PD, PE, PC2, and PC3): VIN = VDD, with the output Nch transistor off 1.0 µA 1 IIH3 PD, PE, PC2, PC3: VIN = VDD, with the output Nch transistor off 1.0 µA 1 IIH4 RES: VIN = VDD, operating, halt mode µA 1 IIH5 RES: VIN = VDD, hold mode 1.0 µA 1 IIL1 Input ports other than PD, PE, PC2, and PC3: VIN = VSS, with the output Nch transistor off –1.0 µA 2 IIL2 PC2, PC3, PD, PE: VIN = VSS, with the output Nch transistor off –1.0 µA 2 IIL3 RES: VIN = VSS µA 1 V 3 IIH1 IIH2 VOH1 Output high-level voltage Value of the output pull-up resistor min typ max 10 100 P2, P3 (except for the P33/HOLD pin), P6, and PC: IOH = –1 mA VDD – 1.0 P2, P3 (except for the P33/HOLD pin), P6, and PC: IOH = –0.1 mA VDD – 0.5 RPO P0, P1, P4, P5 150 kΩ VOL1 P0, P1, P2, P3, P4, P5, P6, and PC (except for the P33/HOLD pin): IOL = 1.6 mA 0.4 V VOL2 P0, P1, P2, P3, P4, P5, P6, and PC (except for the P33/HOLD pin): IOL = 10 mA 1.5 V IOFF1 P2, P3, P61, P63: VIN = VDD 5.0 µA 5 IOFF2 Does not apply to P2, P3, P61, and P63: VIN = VDD 1.0 µA 5 Output low-level voltage Output off leakage current Conditions P2, P3 (except for the P33/HOLD pin), P61, and P63: VIN = 10.0 V, with the output Nch transistor off 30 100 4 [Schmitt characteristics] Hysteresis voltage VHYS High-level threshold voltage VtH Low-level threshold voltage VtL 0.1 VDD P2, P3, P5, P6, OSC1 (EXT), RES V 0.5 VDD 0.8 VDD V 0.2 VDD 0.5 VDD V [Ceramic oscillator] Oscillator frequency fCF OSC1, OSC2: Figure 2, 4 MHz Oscillator stabilization time fCFS Figure 3, 4 MHz 4.0 MHz 10.0 ms [Serial clock] Cycle time Input Output Low-level and high-level Input pulse widths Output Rise an fall times Output tCKCY tCKL SCK0: With the timing of Figure 4 and the test load of Figure 5. tCKH 0.9 µs 2.0 Tcyc 0.4 µs 1.0 Tcyc tCKR, tCKF 0.1 µs [Serial input] Data setup time tICK Data hold time tCKI SI0: With the timing of Figure 4. Stipulated with respect to the rising edge (↑) of SCK0. 0.3 µs 0.3 µs [Serial output] Output delay time tCKO SO0: With the timing of Figure 4 and the test load of Figure 5. Stipulated with respect to the falling edge (↓) of SCK0. 0.3 µs Continued on next page. No. 5486-15/26 LC66E2316 Continued from preceding page. Parameter Symbol Conditions min typ max Unit tIOH, tIOL INT0: Figure 6, conditions under which the INT0 interrupt can be accepted, conditions under which the timer 0 event counter or pulse width measurement input can be accepted 2 Tcyc tIIH, tIIL INT1, INT2: Figure 6, conditions under which the corresponding interrupt can be accepted 2 Tcyc PIN1 high and low-level pulse widths tPINH, tPINL PIN1: Figure 6, conditions under which the timer 1 event counter input can be accepted 2 Tcyc RES high and low-level pulse widths tRSH, tRSL RES: Figure 6, conditions under which reset can be applied. 3 Tcyc Operating current drain IDD OP Halt mode current drain IDDHALT Note [Pulse conditions] INT0 high and low-level High and low-level pulse widths for interrupt inputs other than INT0 Hold mode current drain IDDHOLD VDD: 4-MHz ceramic oscillator 6.0 12 mA VDD: 4-MHz external clock 6.0 12 mA VDD: 4-MHz ceramic oscillator 4.0 8.0 mA VDD: 4-MHz external clock 4.0 8.0 mA 0.01 10 µA VDD: VDD = 1.8 to 5.5 V 6 Note: 1. With the output Nch transistor off in shared I/O ports with the open-drain output specifications. These pins cannot be used as input pins if the CMOS output specifications are selected.When the port option is selected for PE. 2. With the output Nch transistor off in shared I/O ports with the open-drain output specifications. The rating for the pull-up output specification pins is stipulated in terms of the output pull-up current IPO. These pins cannot be used as input pins if the CMOS output specifications are selected. 3. With the output Nch transistor off for CMOS output specification pins. 4. With the output Nch transistor off for pull-up output specification pins. 5. With the output Nch transistor off for open-drain output specification pins. 6. Reset state Tone (DTMF) Output Characteristics DC Characteristics at Ta = +10 to +40°C, VSS = 0 V Parameter Symbol Conditions min typ max Unit Tone output voltage (p-p) VT1 DT: Dual tones, VDD = 4.5 to 5.5 V 0.9 1.3 2.0 V Row/column tone output voltage ratio DBCR1 DT: Dual tones, VDD = 4.5 to 5.5 V 1.0 2.0 3.0 dB Tone distortion THD1 DT: Single tone, VDD = 4.5 to 5.5 V 2 7 % VDD 0.8VDD OSC1 0.2VDD (OSC2) VSS textL External clock OPEN textF textH textR 1/fext Figure 1 External Clock Input Waveform No. 5486-16/26 LC66E2316 VDD OSC1 C1 0V OSC OSC2 Ceramic oscillator Operating VDD minimum value Stable oscillation C2 Oscillator unstable period tCFS Figure 3 Oscillator Stabilization Period Figure 2 Ceramic Oscillator Circuit Table 1 Guaranteed Ceramic Oscillator Constants External capacitor type External capacitor type 4 MHz (Murata Mfg. Co., Ltd.) CSA4.00MG C1 = 33 pF ± 10% 4 MHz (Kyocera Corporation) KBR4.0MS C1 = 33 pF ± 10% Built-in capacitor type 4 MHz (Murata Mfg. Co., Ltd.) CST4.00MG C2 = 33 pF ± 10% 4 MHz (Kyocera Corporation) KBR4.0MES C2 = 33 pF ± 10% tCKCY tCKL SCK0 SCK1 0.2VDD (input) 0.4VDD (output) tCKR tCKF tCKH 0.8VDD (input) VDD-1 (output) tICK tCKI SI0 0.8VDD 0.2VDD SI1 R=1kΩ tCK0 SO0 SO1 TEST point VDD-1 0.4VDD Figure 4 Serial I/O Timing C=50pF Figure 5 Timing Load tI0H tI1H tPINH tRSH 0.8VDD 0.2VDD tI0L tI1L tPINL tRSL Figure 6 Input Timing for the INT0, INT1, INT2, PIN1, and RES pins P60/ML P62/DT R=10 kΩ Figure 7 Tone Output Pin Load No. 5486-17/26 LC66E2316 LC66XXXX Series Instruction Table (by function) Abbreviations: AC: Accumulator E: E register CF: Carry flag ZF: Zero flag HL: Data pointer DPH, DPL XY: Data pointer DPX, DPY M: Data memory M (HL): Data memory pointed to by the DPH, DPL data pointer M (XY): Data memory pointed to by the DPX, DPY auxiliary data pointer M2 (HL): Two words of data memory (starting on an even address) pointed to by the DPH, DPL data pointer SP: Stack pointer M2 (SP): Two words of data memory pointed to by the stack pointer M4 (SP): Four words of data memory pointed to by the stack pointer in: n bits of immediate data t2: Bit specification PCh: PCm: PCl: Fn: TIMER0: TIMER1: SIO: P: P (i4): INT: ( ), [ ]: ←: : : : +: –: —: t2 11 10 01 00 Bit 23 22 21 20 Bits 8 to 11 in the PC Bits 4 to 7 in the PC Bits 0 to 3 in the PC User flag, n = 0 to 15 Timer 0 Timer 1 Serial register Port Port indicated by 4 bits of immediate data Interrupt enable flag Indicates the contents of a location Transfer direction, result Exclusive or Logical and Logical or Addition Subtraction Taking the one's complement No. 5486-18/26 Instruction code Mnemonic D 7 D6 D5 D4 D3 D2 D1 D0 Number of bytes Number of cycles LC66E2316 Operation Description Affected status bits Note [Accumulator manipulation instructions] CLA Clear AC 1 0 0 0 0 0 0 0 1 1 AC ← 0 Clear AC to 0. (Equivalent to LAI 0.) ZF DAA Decimal adjust AC in addition 1 1 0 0 0 0 1 0 1 1 1 1 0 1 1 0 2 2 AC ← (AC) + 6 Add six to AC. (Equivalent to ADI 6.) ZF DAS Decimal adjust AC in subtraction 1 1 0 0 0 0 1 0 1 1 1 1 1 0 1 0 2 2 AC ← (AC) + 10 (Equivalent to ADI 0AH.) Add 10 to AC. ZF CLC Clear CF 0 0 0 1 1 1 1 0 1 1 CF ← 0 Clear CF to 0. CF STC Set CF 0 0 0 1 1 1 1 1 1 1 CF ← 1 Set CF to 1. CF ZF Has a vertical skip function. CMA Complement AC 0 0 0 1 1 0 0 0 1 1 AC ← (AC) Take the one’s complement of AC. IA Increment AC 0 0 0 1 0 1 0 0 1 1 AC ← (AC) + 1 Increment AC. ZF, CF DA Decrement AC 0 0 1 0 0 1 0 0 1 1 AC ← (AC) – 1 Decrement AC. ZF, CF Shift AC (including CF) right. CF CF, ZF RAR Rotate AC right through CF 0 0 0 1 0 0 0 0 1 1 AC3 ← (CF), ACn ← (ACn + 1), CF ← (AC0) RAL Rotate AC left through CF 0 0 0 0 0 0 0 1 1 1 AC0 ← (CF), ACn + 1 ← (ACn), CF ← (AC3) Shift AC (including CF) left. TAE Transfer AC to E 0 1 0 0 0 1 0 1 1 1 E ← (AC) Transfer the contents of AC to E. TEA Transfer E to AC 0 1 0 0 0 1 1 0 1 1 AC ← (E) Transfer the contents of E to AC. ZF XAE Exchange AC with E 0 1 0 0 0 1 0 0 1 1 (AC) ↔ (E) Exchange the contents of AC and E. [Memory manipulation instructions] IM Increment M 0 0 0 1 0 0 1 0 1 1 M (HL) ← [M (HL)] + 1 Increment M (HL). ZF, CF DM Decrement M 0 0 1 0 0 0 1 0 1 1 M (HL) ← [M (HL)] – 1 Decrement M (HL). ZF, CF IMDR i8 Increment M direct 1 1 0 0 I7 I6 I5 I4 0 1 1 1 I3 I2 I1 I0 2 2 M (i8) ← [M (i8)] + 1 Increment M (i8). ZF, CF DMDR i8 Decrement M direct 1 1 0 0 I7 I6 I5 I4 0 0 1 1 I3 I2 I1 I0 2 2 M (i8) ← [M (i8)] – 1 Decrement M (i8). ZF, CF SMB t2 Set M data bit 0 0 0 0 1 1 t1 t0 1 1 [M (HL), t2] ← 1 Set the bit in M (HL) specified by t0 and t1 to 1. RMB t2 Reset M data bit 0 0 1 0 1 1 t1 t0 1 1 [M (HL), t2] ← 0 Clear the bit in M (HL) specified by t0 and t1 to 0. ZF 0 0 0 0 0 1 1 0 1 1 AC ← (AC) + [M (HL)] Add the contents of AC and M (HL) as two’s complement values and store the result in AC. ZF, CF 1 1 0 0 I7 I6 I5 I4 1 0 0 1 I3 I2 I1 I0 2 Add the contents of AC and M (i8) as two’s complement AC ← (AC) + [M (i8)] values and store the result in AC. Add the contents of AC, M (HL) and C as two’s complement values and store the result in AC. ZF, CF [Arithmetic, logic and comparison instructions] AD Add M to AC ADDR i8 Add M direct to AC 2 ZF, CF ADC Add M to AC with CF 0 0 0 0 0 0 1 0 1 1 AC ← (AC) + [M (HL)] + (CF) ADI i4 Add immediate data to AC 1 1 0 0 0 0 1 0 1 1 1 1 I3 I2 I1 I0 2 2 AC ← (AC) + I3, I2, I1, I0 Add the contents of AC and the immediate data as two’s complement values and store the result in AC. ZF SUBC Subtract AC from M with CF 0 0 0 1 0 1 1 1 1 1 AC ← [M (HL)] – (AC) – (CF) Subtract the contents of AC and CF from M (HL) as two’s complement values and store the result in AC. ZF, CF ANDA And M with AC then store AC 0 0 0 0 0 1 1 1 1 1 AC ← (AC) [M (HL)] Take the logical and of AC and M (HL) and store the result in AC. ZF ORA Or M with AC then store AC 0 0 0 0 0 1 0 1 1 1 AC ← (AC) [M (HL)] Take the logical or of AC and M (HL) and store the result in AC. ZF CF will be zero if there was a borrow and one otherwise. Continued on next page. No. 5486-19/26 LC66E2316 Instruction code Mnemonic D 7 D6 D5 D4 D3 D2 D1 D0 Number of bytes Number of cycles Continued from preceding page. Operation Affected status bits Description Note [Arithmetic, logic and comparison instructions] EXL Exclusive or M with AC then store AC 0 0 0 1 0 1 0 1 1 1 AC ← (AC) [M (HL)] Take the logical exclusive or of AC and M (HL) and store the result in AC. ZF ANDM And M with AC then store M 0 0 0 0 0 0 1 1 1 1 M (HL) ← (AC) [M (HL)] Take the logical and of AC and M (HL) and store the result in M (HL). ZF ORM Or M with AC then store M 0 0 0 0 0 1 0 0 1 1 M (HL) ← (AC) [M (HL)] Take the logical or of AC and M (HL) and store the result in M (HL). ZF Compare the contents of AC and M (HL) and set or clear CF and ZF according to the result. CM Compare AC with M 0 0 0 1 0 1 1 0 1 1 [M (HL)] + (AC) + 1 Magnitude comparison [M (HL)] > (AC) [M (HL)] = (AC) [M (HL)] < (AC) CF ZF 0 1 1 ZF, CF 0 1 0 Compare the contents of AC and the immediate data I3 I2 I1 I0 and set or clear CF and ZF according to the result. CI i4 Compare AC with immediate data 1 1 0 0 1 0 1 0 1 1 1 1 I3 I2 I1 I0 2 2 I3 I2 I1 I0 + (AC) + 1 Magnitude comparison I3 I2 I1 I0 > AC I3 I2 I1 I0 = AC I3 I2 I1 I0 < AC CLI i4 CMB t2 Compare DPL with immediate data Compare AC bit with M data bit 1 1 0 0 1 0 1 1 1 1 1 1 I3 I2 I1 I0 2 CF ZF 0 1 1 ZF, CF 0 1 0 2 ZF ← 1 if (DPL) = I3 I2 I1 I0 ZF ← 0 if (DPL) ≠ I3 I2 I1 I0 Compare the contents of DPL with the immediate data. Set ZF if identical and clear ZF if not. ZF Compare the corresponding bits specified by t0 and t1 in AC and M (HL). Set ZF if identical and clear ZF if not. ZF 1 1 0 0 1 1 0 1 1 1 1 1 0 0 t1 t0 2 2 ZF ← 1 if (AC, t2) = [M (HL), t2] ZF← 0 if (AC, t2) ≠ [M (HL), t2] [Load and store instructions] LAE Load AC and E from M2 (HL) 0 1 0 1 1 1 0 0 1 1 AC ← M (HL), E ← M (HL + 1) Load the contents of M2 (HL) into AC, E. LAI i4 Load AC with immediate data 1 0 0 0 I3 I2 I1 I0 1 1 AC ← I3 I2 I1 I0 Load the immediate data into AC. ZF LADR i8 Load AC from M direct 1 1 0 0 I7 I6 I5 I4 0 0 0 1 I3 I2 I1 I0 2 2 AC ← [M (i8)] Load the contents of M (i8) into AC. ZF S Store AC to M 0 1 0 0 0 1 1 1 1 1 M (HL) ← (AC) Store the contents of AC into M (HL). SAE Store AC and E to M2 (HL) 0 1 0 1 1 1 1 0 1 1 M (HL) ← (AC) M (HL + 1) ← (E) Store the contents of AC, E into M2 (HL). LA reg Load AC from M (reg) 0 1 0 0 1 0 t0 0 1 1 AC ← [M (reg)] Has a vertical skip function Load the contents of M (reg) into AC. The reg is either HL or XY depending on t0. ZF reg T0 HL XY 0 1 Continued on next page. No. 5486-20/26 LC66E2316 Instruction code Mnemonic D 7 D6 D5 D4 D3 D2 D1 D0 Number of bytes Number of cycles Continued from preceding page. Operation Description Affected status bits Note [Load and store instructions] LA reg, I Load AC from M (reg) 0 1 0 0 then increment reg Load AC from M (reg) LA reg, D 0 1 0 1 then decrement reg XA reg Exchange AC with M (reg) Exchange AC with XA reg, I M (reg) then increment reg 0 1 0 0 0 1 0 0 1 0 t0 1 1 0 t0 1 1 1 t0 0 1 1 t0 1 1 1 1 1 2 2 1 2 AC ← [M (reg)] DPL ← (DPL) + 1 or DPY ← (DPY) + 1 Load the contents of M (reg) into AC. (The reg is either HL or XY.) Then increment the contents of either DPL or DPY. ZF The relationship between t0 and reg is the same as that for the LA reg instruction. ZF is set according to the result of incrementing DPL or DPY. AC ← [M (reg)] DPL ← (DPL) – 1 or DPY ← (DPY) – 1 Load the contents of M (reg) into AC. (The reg is either HL or XY.) Then decrement the contents of either DPL or DPY. ZF The relationship between t0 and reg is the same as that for the LA reg instruction. ZF is set according to the result of decrementing DPL or DPY. (AC) ↔ [M (reg)] Exchange the contents of M (reg) and AC. The reg is either HL or XY depending on t0. reg T0 HL XY 0 1 (AC) ↔ [M (reg)] DPL ← (DPL) + 1 or DPY ← (DPY) + 1 Exchange the contents of M (reg) and AC. (The reg is either HL or XY.) Then increment the contents of either DPL or DPY. The relationship between t0 and reg is the same as that for the XA reg instruction. Exchange the contents of M (reg) and AC. (The reg is either HL or XY.) Then decrement the contents of either DPL or DPY. The relationship between t0 and reg is the same as that for the XA reg instruction. Exchange AC with XA reg, D M (reg) then decrement reg 0 1 0 1 1 1 t0 1 1 2 (AC) ↔ [M (reg)] DPL ← (DPL) – 1 or DPY ← (DPY) – 1 XADR i8 Exchange AC with M direct 1 1 0 0 I7 I6 I5 I4 1 0 0 0 I3 I2 I1 I0 2 2 (AC) ↔ [M (i8)] Exchange the contents of AC and M (i8). LEAI i8 Load E & AC with immediate data 1 1 0 0 I7 I6 I5 I4 0 1 1 0 I3 I2 I1 I0 2 2 E ← I7 I6 I5 I4 AC ← I3 I2 I1 I0 Load the immediate data i8 into E, AC. RTBL Read table data from 0 1 0 1 program ROM 2 E, AC ← [ROM (PCh, E, AC)] Load into E, AC the ROM data at the location determined by replacing the lower 8 bits of the PC with E, AC. RTBLP Read table data from program ROM then 0 1 0 1 output to P4, 5 Output from ports 4 and 5 the ROM data at the location determined by replacing the lower 8 bits of the PC with E, AC. 1 0 1 0 1 1 0 0 0 1 2 Port 4, 5 ← [ROM (PCh, E, AC)] ZF ZF is set according to the result of incrementing DPL or DPY. ZF ZF is set according to the result of decrementing DPL or DPY. [Data pointer manipulation instructions] LDZ i4 Load DPH with zero and DPL with immediate data respectively 0 1 1 0 I3 I2 I1 I0 1 1 DPH ← 0 DPL ← I3 I2 I1 I0 Load zero into DPH and the immediate data i4 into DPL. LHI i4 Load DPH with immediate data 1 1 0 0 0 0 0 0 1 1 1 1 I3 I2 I1 I0 2 2 DPH ← I3 I2 I1 I0 Load the immediate data i4 into DPH. LLI i4 Load DPL with immediate data 1 1 0 0 0 0 0 1 1 1 1 1 I3 I2 I1 I0 2 2 DPL ← I3 I2 I1 I0 Load the immediate data i4 into DPL. LHLI i8 Load DPH, DPL with immediate data 1 1 0 0 I7 I6 I5 I4 0 0 0 0 I3 I2 I1 I0 2 2 DPH ← I7 I6 I5 I4 DPL ← I3 I2 I1 I0 Load the immediate data into DLH, DPL. LXYI i8 Load DPX, DPY with immediate data 1 1 0 0 I7 I6 I5 I4 0 0 0 0 I3 I2 I1 I0 2 2 DPX ← I7 I6 I5 I4 DPY ← I3 I2 I1 I0 Load the immediate data into DLX, DPY. Continued on next page. No. 5486-21/26 LC66E2316 Instruction code Mnemonic D 7 D6 D5 D4 D3 D2 D1 D0 Number of bytes Number of cycles Continued from preceding page. Operation Description Affected status bits Note [Data pointer manipulation instructions] IL Increment DPL 0 0 0 1 0 0 0 1 1 1 DPL ← (DPL) + 1 Increment the contents of DPL. ZF DL Decrement DPL 0 0 1 0 0 0 0 1 1 1 DPL ← (DPL) – 1 Decrement the contents of DPL. ZF IY Increment DPY 0 0 0 1 0 0 1 1 1 1 DPY ← (DPY) + 1 Increment the contents of DPY. ZF DY Decrement DPY 0 0 1 0 0 0 1 1 1 1 DPY ← (DPY) – 1 Decrement the contents of DPY. ZF TAH Transfer AC to DPH 1 1 0 0 1 1 1 1 1 1 1 1 0 0 0 0 2 2 DPH ← (AC) Transfer the contents of AC to DPH. THA Transfer DPH to AC 1 1 0 0 1 1 1 0 1 1 1 1 0 0 0 0 2 2 AC ← (DPH) Transfer the contents of DPH to AC. XAH Exchange AC with DPH 0 1 0 0 0 0 0 0 1 1 (AC) ↔ (DPH) Exchange the contents of AC and DPH. TAL Transfer AC to DPL 1 1 0 0 1 1 1 1 1 1 1 1 0 0 0 1 2 2 DPL ← (AC) Transfer the contents of AC to DPL. TLA Transfer DPL to AC 1 1 0 0 1 1 1 0 1 1 1 1 0 0 0 1 2 2 AC ← (DPL) Transfer the contents of DPL to AC. XAL Exchange AC with DPL 0 1 0 0 0 0 0 1 1 1 (AC) ↔ (DPL) Exchange the contents of AC and DPL. TAX Transfer AC to DPX 1 1 0 0 1 1 1 1 1 1 1 1 0 0 1 0 2 2 DPX ← (AC) Transfer the contents of AC to DPX. TXA Transfer DPX to AC 1 1 0 0 1 1 1 0 1 1 1 1 0 0 1 0 2 2 AC ← (DPX) Transfer the contents of DPX to AC. XAX Exchange AC with DPX 0 1 0 0 0 0 1 0 1 1 (AC) ↔ (DPX) Exchange the contents of AC and DPX. TAY Transfer AC to DPY 1 1 0 0 1 1 1 1 1 1 1 1 0 0 1 1 2 2 DPY ← (AC) Transfer the contents of AC to DPY. TYA Transfer DPY to AC 1 1 0 0 1 1 1 0 1 1 1 1 0 0 1 1 2 2 AC ← (DPY) Transfer the contents of DPY to AC. XAY Exchange AC with DPY 0 1 0 0 0 0 1 1 1 1 (AC) ↔ (DPY) Exchange the contents of AC and DPY. ZF ZF ZF ZF [Flag manipulation instructions] SFB n4 Set flag bit 0 1 1 1 n 3 n2 n1 n0 1 1 Fn ← 1 Set the flag specified by n4 to 1. RFB n4 Reset flag bit 0 0 1 1 n 3 n2 n1 n0 1 1 Fn ← 0 Reset the flag specified by n4 to 0. Jump to the location in the same bank specified by the immediate data P12. ZF [Jump and subroutine instructions] JMP addr Jump in the current bank 1 1 1 0 P11P10P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 2 2 PC13, 12 ← PC13, 12 PC11 to 0 ← P11 to P8 JPEA Jump to the address stored at E and AC in the current page 0 0 1 0 1 1 PC13 to 8 ← PC13 to 8, PC7 to 4 ← (E), PC3 to 0 ← (AC) Jump to the location determined by replacing the lower 8 bits of the PC by E, AC. 2 PC13 to 11 ← 0, PC10 to 0 ← P10 to P0, M4 (SP) ← (CF, ZF, PC13 to 0), SP ← (SP)-4 Call a subroutine. PC13 to 6, PC10 ← 0, PC5 to 2 ← P3 to P0, Call a subroutine on page 0 M4 (SP) ← in bank 0. (CF, ZF, PC12 to 0), SP ← SP-4 CAL addr Call subroutine 0 1 1 1 0 1 0 1 0 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 2 CZP addr Call subroutine in the 1 0 1 0 zero page P3 P2 P1 P0 1 2 BANK Change bank 1 0 1 1 1 1 0 0 0 1 This becomes PC12 + (PC12) immediately following a BANK instruction. Change the memory bank and register bank. Continued on next page. No. 5486-22/26 LC66E2316 Instruction code Mnemonic D 7 D6 D5 D4 D3 D2 D1 D0 Number of bytes Number of cycles Continued from preceding page. Operation Affected status bits Description Note [Jump and subroutine instructions] Store the contents of reg in M2 (SP). Subtract 2 from SP after the store. PUSH reg Push reg on M2 (SP) 1 1 0 0 1 1 1 1 1 1 1 1 1 i 1 i0 0 2 2 M2 (SP) ← (reg) SP ← (SP) – 2 reg i1 i0 HL XY AE Illegal value 0 0 1 1 0 1 0 1 POP reg Pop reg off M2 (SP) 1 1 0 0 1 1 1 0 1 1 1 1 1 i 1 i0 0 2 2 SP ← (SP) + 2 reg ← [M2 (SP)] Add 2 to SP and then load the contents of M2(SP) into reg. The relation between i1i0 and reg is the same as that for the PUSH reg instruction. RT Return from subroutine 0 0 0 1 1 1 0 0 1 2 SP ← (SP) + 4 PC ← [M4 (SP)] Return from a subroutine or interrupt handling routine. ZF and CF are not restored. RTI Return from interrupt routine 0 0 0 1 1 1 0 1 1 2 SP ← (SP) + 4 PC ← [M4 (SP)] CF, ZF ← [M4 (SP)] Return from a subroutine or interrupt handling routine. ZF and CF are restored. 2 PC7 to 0 ← P7 P6 P5 P4 P3 P2 P1 P0 if (AC, t2) = 1 Branch to the location in the same page specified by P7 to P0 if the bit in AC specified by the immediate data t1 t0 is one. 2 PC7 to 0 ← P7 P6 P5 P4 P3 P2 P1 P0 if (AC, t2) = 0 Branch to the location in the same page specified by P7 to P0 if the bit in AC specified by the immediate data t1 t0 is zero. 2 PC7 to 0 ← P7 P6 P5 P4 P3 P2 P1 P0 if [M (HL),t2] =1 Branch to the location in the same page specified by P7 to P0 if the bit in M (HL) specified by the immediate data t1 t0 is one. 2 PC7 to 0 ← P7 P6 P5 P4 P3 P2 P1 P0 if [M (HL),t2] =0 Branch to the location in the same page specified by P7 to P0 if the bit in M (HL) specified by the immediate data t1 t0 is zero. ZF, CF [Branch instructions] BAt2 addr BNAt2 addr BMt2 addr BNMt2 addr BPt2 addr BNPt2 addr Branch on AC bit 1 1 0 1 0 0 t1 t0 P7 P6 P5 P4 P3 P2 P1 P0 Branch on no AC bit 1 0 0 1 0 0 t1 t0 P7 P6 P5 P4 P3 P2 P1 P0 Branch on M bit 1 1 0 1 0 1 t1 t0 P7 P6 P5 P4 P3 P2 P1 P0 Branch on no M bit 1 0 0 1 0 1 t1 t0 P7 P6 P5 P4 P3 P2 P1 P0 Branch on Port bit 1 1 0 1 1 0 t1 t0 P7 P6 P5 P4 P3 P2 P1 P0 1 0 0 1 1 0 t1 t0 Branch on no Port bit P7 P6 P5 P4 P3 P2 P1 P0 2 2 2 2 2 2 2 2 PC7 to 0 ← P7 P6 P5 P4 P3 P2 P1 P0 if [P (DPL), t2] =1 PC7 to 0 ← P7 P6 P5 P4 P3 P2 P1 P0 if [P (DPL), t2] =0 Branch to the location in the same page specified by P7 to P0 if the bit in port (DPL) specified by the immediate data t1 t0 is one. Internal control registers can also be tested by executing this instruction immediately after a BANK instruction. However, this is limited to registers that can be read out. Branch to the location in the same page specified by P7 to P0 if the bit in port (DPL) specified by the immediate data t1 t0 is zero. Internal control registers can also be tested by executing this instruction immediately after a BANK instruction. However, this is limited to registers that can be read out. Continued on next page. No. 5486-23/26 LC66E2316 Instruction code Mnemonic D 7 D6 D5 D4 D3 D2 D1 D0 Number of bytes Number of cycles Continued from preceding page. Operation Description Affected status bits Note [Branch instructions] 2 PC7 to 0 ← P7 P6 P5 P4 P3 P2 P1 P0 if (CF) = 1 Branch to the location in the same page specified by P7 to P0 if CF is one. BC addr Branch on CF 1 1 0 1 1 1 0 0 P7 P6 P5 P4 P3 P2 P1 P0 BNC addr Branch on no CF 1 0 0 1 1 1 0 0 P7 P6 P5 P4 P3 P2 P1 P0 2 2 PC7 to 0 ← P7 P6 P5 P4 P3 P2 P1 P0 if (CF) = 0 Branch to the location in the same page specified by P7 to P0 if CF is zero. BZ addr Branch on ZF 1 1 0 1 1 1 0 1 P7 P6 P5 P4 P3 P2 P1 P0 2 2 PC7 to 0 ← P7 P6 P5 P4 P3 P2 P1 P0 if (ZF) = 1 Branch to the location in the same page specified by P7 to P0 if ZF is one. Branch on no ZF 1 0 0 1 1 1 0 1 P7 P6 P5 P4 P3 P2 P1 P0 2 PC7 to 0 ← P7 P6 P5 P4 P3 P2 P1 P0 if (ZF) = 0 Branch to the location in the same page specified by P7 to P0 if ZF is zero. 2 PC7 to 0 ← P7 P6 P5 P4 P3 P2 P1 P0 if (Fn) = 1 Branch to the location in the same page specified by P0 to P7 if the flag (of the 16 user flags) specified by n3 n2 n1 n0 is one. Branch to the location in the same page specified by P0 to P7 if the flag (of the 16 user flags) specified by n3 n2 n1 n0 is zero. BNZ addr BFn4 addr BNFn4 addr Branch on flag bit Branch on no flag bit 1 1 1 1 n 3 n2 n1 n0 P7 P6 P5 P4 P3 P2 P1 P0 2 2 2 1 0 1 1 n 3 n2 n1 n0 P7 P6 P5 P4 P3 P2 P1 P0 2 2 PC7 to 0 ← P7 P6 P5 P4 P3 P2 P1 P0 if (Fn) = 0 [I/O instructions] IP0 Input port 0 to AC 0 0 1 0 0 0 0 0 1 1 AC ← (P0) Input the contents of port 0 to AC. ZF IP Input port to AC 0 0 1 0 0 1 1 0 1 1 AC ← [P (DPL)] Input the contents of port P (DPL) to AC. ZF IPM Input port to M 0 0 0 1 1 0 0 1 1 1 M (HL) ← [P (DPL)] Input the contents of port P (DPL) to M (HL). IPDR i4 Input port to AC direct 1 1 0 0 0 1 1 0 1 1 1 1 I3 I2 I1 I0 2 2 AC ← [P (i4)] Input the contents of P (i4) to AC. IP45 Input port 4, 5 to E, AC respectively 1 1 0 0 1 1 0 1 1 1 1 1 0 1 0 0 2 2 E ← [P (4)] AC ← [P (5)] Input the contents of ports P (4) and P (5) to E and AC respectively. OP Output AC to port 0 0 1 0 0 1 0 1 1 1 P (DPL) ← (AC) Output the contents of AC to port P (DPL). OPM Output M to port 0 0 0 1 1 0 1 0 1 1 P (DPL) ← [M (HL)] Output the contents of M (HL) to port P (DPL). OPDR i4 Output AC to port direct 1 1 0 0 0 1 1 1 1 1 1 1 I3 I2 I1 I0 2 2 P (i4) ← (AC) Output the contents of AC to P (i4). OP45 Output E, AC to port 4, 5 respectively 1 1 0 0 1 1 0 1 1 1 1 1 0 1 0 1 2 2 P (4) ← (E) P (5) ← (AC) Output the contents of E and AC to ports P (4) and P (5) respectively. SPB t2 Set port bit 0 0 0 0 1 0 t1 t0 1 1 [P (DPL), t2] ← 1 Set to one the bit in port P (DPL) specified by the immediate data t1 t0. RPB t2 Reset port bit 0 0 1 0 1 0 t1 t0 1 1 [P (DPL), t2] ← 0 Clear to zero the bit in port P (DPL) specified by the immediate data t1 t0. And port with ANDPDR immediate data then i4, p4 output 1 1 0 0 0 1 0 1 I3 I2 I1 I0 P3 P2 P1 P0 2 2 P (P3 to P0) ← [P (P3 to P0)] I3 to I0 Take the logical AND of P (P3 to P0) and the immediate data ZF I3 I2 I1 I0 and output the result to P (P3 to P0). Or port with immediate data then output 1 1 0 0 0 1 0 0 I3 I2 I1 I0 P3 P2 P1 P0 2 2 P (P3 to P0) ← [P (P3 to P0)] I3 to I0 Take the logical OR of P (P3 to P0) and the immediate data ZF I3 I2 I1 I0 and output the result to P (P3 to P0). ORPDR i4, p4 ZF ZF Continued on next page. No. 5486-24/26 LC66E2316 Instruction code Mnemonic D 7 D6 D5 D4 D3 D2 D1 D0 Number of bytes Number of cycles Continued from preceding page. Operation Description Affected status bits Note [Timer control instructions] WTTM0 Write timer 0 1 1 0 0 1 0 1 0 1 2 Write the contents of M2 (HL), TIMER0 ← [M2 (HL)], AC into the timer 0 reload (AC) register. WTTM1 Write timer 1 1 1 0 0 1 1 1 1 1 1 1 1 0 1 0 0 2 2 Write the contents of E, AC TIMER1 ← (E), (AC) into the timer 1 reload register A. RTIM0 Read timer 0 1 1 0 0 1 0 1 1 1 2 M2 (HL), AC ← (TIMER0) Read out the contents of the timer 0 counter into M2 (HL), AC. RTIM1 Read timer 1 1 1 0 0 1 1 1 1 1 1 1 1 0 1 0 1 2 2 E, AC ← (TIMER1) Read out the contents of the timer 1 counter into E, AC. START0 Start timer 0 1 1 0 0 1 1 1 0 1 1 1 1 0 1 1 0 2 2 Start timer 0 counter Start the timer 0 counter. START1 Start timer 1 1 1 0 0 1 1 1 0 1 1 1 1 0 1 1 1 2 2 Start timer 1 counter Start the timer 1 counter. STOP0 Stop timer 0 1 1 0 0 1 1 1 1 1 1 1 1 0 1 1 0 2 2 Stop timer 0 counter Stop the timer 0 counter. STOP1 Stop timer 1 1 1 0 0 1 1 1 1 1 1 1 1 0 1 1 1 2 2 Stop timer 1 counter Stop the timer 1 counter. [Interrupt control instructions] MSET Set interrupt master enable flag 1 1 0 0 0 1 0 1 1 1 0 1 0 0 0 0 2 2 MSE ← 1 Set the interrupt master enable flag to one. MRESET Reset interrupt master enable flag 1 1 0 0 1 0 0 1 1 1 0 1 0 0 0 0 2 2 MSE ← 0 Clear the interrupt master enable flag to zero. EIH i4 Enable interrupt high 1 1 0 0 0 1 0 1 1 1 0 1 I3 I2 I1 I0 2 2 EDIH ← (EDIH) EIL i4 Enable interrupt low 1 1 0 0 0 1 0 0 1 1 0 1 I3 I2 I1 I0 2 2 EDIL ← (EDIL) DIH i4 Disable interrupt high 1 1 0 0 1 0 0 1 1 1 0 1 I3 I2 I1 I0 2 2 EDIH ← (EDIH) DIL i4 Disable interrupt low 1 1 0 0 1 0 0 0 1 1 0 1 I3 I2 I1 I0 2 2 EDIL ← (EDIL) WTSP Write SP 1 1 0 0 1 1 0 1 1 1 1 1 1 0 1 0 2 2 SP ← (E), (AC) Transfer the contents of E, AC to SP. RSP Read SP 1 1 0 0 1 1 0 1 1 1 1 1 1 0 1 1 2 2 E, AC ← (SP) Transfer the contents of SP to E, AC. i4 i4 i4 i4 Set the interrupt enable flag to one. Set the interrupt enable flag to one. Clear the interrupt enable flag to zero. ZF Clear the interrupt enable flag to zero. ZF [Standby control instructions] HALT HALT 1 1 0 0 1 1 0 1 1 1 1 1 1 1 1 0 2 2 HALT Enter halt mode. HOLD HOLD 1 1 0 0 1 1 0 1 1 1 1 1 1 1 1 1 2 2 HOLD Enter hold mode. STARTS Start serial I O 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 0 2 2 START SI O Start SIO operation. WTSIO Write serial I O 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 1 2 2 SIO ← (E), (AC) Write the contents of E, AC to SIO. RSIO Read serial I O 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 2 2 E, AC ← (SIO) Read out the contents of SIO into E, AC. [Serial I/O control instructions] [Other instructions] NOP No operation 0 0 0 0 0 0 0 0 1 1 No operation Consume one machine cycle without performing any operation. SB i2 Select bank 1 1 0 0 1 1 0 0 1 1 1 1 0 0 I1 I0 2 2 PC13, PC12 ← I1 I0 Specify the memory bank. No. 5486-25/26 LC66E2316 ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of February, 1997. Specifications and information herein are subject to change without notice. No. 5486-26/26