AD ADP2302ARDZ-3.3-R7

2 A/3 A, 20 V, 700 kHz,
Nonsynchronous Step-Down Regulators
ADP2302/ADP2303
FEATURES
Intermediate power rail conversion
DC-to-DC point of load applications
Communications and networking
Industrial and instrumentation
Healthcare and medical
Consumer
VIN
BST
ADP2302/
ADP2303
PGOOD
SW
EN
FB
VOUT
08833-001
ON
OFF
GND
Figure 1. Typical Application Circuit
100
90
80
70
60
VOUT = 3.3V
50
INDUCTOR: VLF10040T -4R7N5R4
DIODE: SSB43L
40
0
0.5
1.0
1.5
VOUT = 5.0V
2.0
2.5
OUTPUT CURRENT (A)
3.0
08833-002
APPLICATIONS
TYPICAL APPLICATIONS CIRCUIT
VIN
EFFICIENCY (%)
Wide input voltage range: 3.0 V to 20 V
Maximum load current
2 A for ADP2302
3 A for ADP2303
±1.5% output accuracy over temperature
Output voltage down to 0.8 V
700 kHz switching frequency
Current-mode control architecture
Automatic PFM/PWM mode
Precision enable pin with hysteresis
Integrated high-side MOSFET
Integrated bootstrap diode
Internal compensation and soft start
Power-good output
Undervoltage lockout (UVLO)
Overcurrent protection (OCP)
Thermal shutdown (TSD)
8-lead SOIC package with exposed paddle
Figure 2. ADP2303 Efficiency vs. Output Current at VIN = 12 V
GENERAL DESCRIPTION
The ADP2302/ADP2303 are fixed frequency, current-mode
control, step-down, dc-to-dc regulators with an integrated
power MOSFET. The ADP2302/ADP2303 can run from an
input voltage of 3.0 V to 20 V, which makes them suitable for a
wide range of applications. The output voltage of the ADP2302/
ADP2303 can be down to 0.8 V for the adjustable version, while
the fixed output version is available in preset output voltage
options of 5.0 V, 3.3 V, and 2.5 V. The 700 kHz operating
frequency allows small inductor and ceramic capacitors to be
used, providing a compact solution. Current mode control
provides fast and stable line and load transient performance.
The ADP2302/ADP2303 have integrated soft start circuitry to
prevent a large inrush current at power-up. The power-good
signal can be used to sequence devices that have an enable input.
The precision enable threshold voltage allows the part to be
easily sequenced from other input/output supplies. Other key
features include undervoltage lockout (UVLO), overvoltage
protection (OVP), thermal shutdown (TSD), and overcurrent
protection (OCP).
The ADP2302/ADP2303 devices are available in the 8-lead,
SOIC package with exposed paddle and are rated for the −40oC
to +125oC junction temperature range.
Rev. 0
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
ADP2302/ADP2303
TABLE OF CONTENTS
Features .............................................................................................. 1 Overvoltage Protection (OVP)................................................. 15 Applications....................................................................................... 1 Power Good ................................................................................ 15 Typical Applications Circuit............................................................ 1 Control Loop............................................................................... 15 General Description ......................................................................... 1 Applications Information .............................................................. 16 Revision History ............................................................................... 2 Programming Output Voltage .................................................. 16 Specifications..................................................................................... 3 Voltage Conversion Limitations............................................... 16 Absolute Maximum Ratings............................................................ 4 Low Input Voltage Considerations .......................................... 17 Thermal Resistance ...................................................................... 4 Programming the Precision Enable ......................................... 17 ESD Caution.................................................................................. 4 Inductor ....................................................................................... 17 Pin Configuration and Function Descriptions............................. 5 Catch Diode ................................................................................ 18 Typical Performance Characteristics ............................................. 6 Input Capacitor........................................................................... 19 Functional Block Diagram ............................................................ 13 Output Capacitor........................................................................ 19 Theory of Operation ...................................................................... 14 Thermal Consideration ............................................................. 19 Basic Operation .......................................................................... 14 Design Example .............................................................................. 20 PWM Mode................................................................................. 14 Catch Diode Selection ............................................................... 20 Power Saving Mode.................................................................... 14 Inductor Selection ...................................................................... 20 Bootstrap Circuitry .................................................................... 14 Output Capacitor Selection....................................................... 20 Precision Enable ......................................................................... 14 Resistive Voltage Divider Selection.......................................... 20 Integrated Soft Start ................................................................... 14 Circuit Board Layout Recommendations ................................... 22 Current Limit .............................................................................. 14 Typical Application Circuits ......................................................... 23 Short-Circuit Protection............................................................ 14 Outline Dimensions ....................................................................... 26 Undervoltage Lockout (UVLO) ............................................... 15 Ordering Guide .......................................................................... 26 Thermal Shutdown (TSD)......................................................... 15 REVISION HISTORY
7/10—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
ADP2302/ADP2303
SPECIFICATIONS
VIN = 3.3 V, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.
Table 1.
Parameters
VIN
Voltage Range
Supply Current
Shutdown Current
Undervoltage Lockout Threshold
FB
Regulation Voltage
Bias Current
SW
On Resistance 1
Peak Current Limit
Leakage Current
Minimum On Time
Minimum Off Time
OSCILLATOR FREQUENCY
SOFT START TIME
EN
Input Threshold
Input Hysteresis
Pull-Down Current
BOOTSTRAP VOLTAGE
PGOOD
PGOOD Rising Threshold
PGOOD Hysteresis
PGOOD Deglitch Time 2
PGOOD Output Low Voltage
PGOOD Leakage Current
THERMAL SHUTDOWN
Threshold
Hysteresis
1
2
Symbol
VIN
IVIN
ISHDN
UVLO
VFB
IFB
Test Conditions
Min
3.0
No switching, VIN = 12 V
VEN = 0 V, VIN = 12 V
VIN rising
VIN falling
2.2
720
24
2.7
2.4
Max
Unit
20
950
45
2.9
V
μA
μA
V
V
ADP230xARDZ (adjustable)
ADP230xARDZ-2.5
ADP230xARDZ-3.3
ADP230xARDZ-5.0
ADP230xARDZ (adjustable)
0.788
2.463
3.25
4.925
0.8
2.5
3.3
5.0
0.01
0.812
2.538
3.35
5.075
0.1
V
V
V
V
μA
VBST − VSW = 5 V, ISW = 200 mA
ADP2302, VBST − VSW = 5 V
ADP2303, VBST − VSW = 5 V
VEN = VSW = 0 V, VIN = 12 V
80
2.7
4.6
120
3.5
5.5
0.1
126
210
700
2048
160
4.4
6.4
5
170
280
805
mΩ
A
A
μA
ns
ns
kHz
Clock cycles
1.2
100
1.2
5.0
1.28
V
mV
μA
V
87.5
2.5
32
150
0.1
92.5
fSW
595
VEN
1.12
VBOOT
Typ
VIN = 12 V
4.7
82.5
VPGOOD = 5 V
Rising temperature
Pin-to-Pin measurements.
Guaranteed by design.
Rev. 0 | Page 3 of 28
150
15
5.3
300
1
%
%
Clock cycles
mV
μA
°C
°C
ADP2302/ADP2303
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
Parameter
VIN, EN, PGOOD
SW
BST to SW
FB, NC
Operating Junction Temperature Range
Storage Temperature Range
Soldering Conditions
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
MAX Rating
−0.3 V to +24 V
−1.0 V to +24 V
−0.6 V to +6 V
−0.3 V to +6 V
−40°C to +125°C
−65°C to +150°C
JEDEC J-STD-020
Table 3. Thermal Resistance1
Package Type
8-Lead SOIC_N_EP
1
θJA
58.5
Unit
°C/W
θJA is measured using natural convection on JEDEC 4-layer board.
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified, all voltages are
referenced to GND.
Rev. 0 | Page 4 of 28
ADP2302/ADP2303
BST 1
VIN 2
EN 3
ADP2302
ADP2303
TOP VIEW
PGOOD 4 (Not to Scale)
8
SW
7
GND
6
NC
5
FB
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD SHOULD BE SOLDERED
TO AN EXTERNAL GROUND PLANE UNDERNEATH
THE IC FOR THERMAL DISSIPATION.
08833-003
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration (Top View)
Table 4. Pin Function Descriptions
Pin No.
1
Mnemonic
BST
2
VIN
3
EN
4
5
PGOOD
FB
6
7
8
9 (EPAD)
NC
GND
SW
Exposed Pad
Description
Bootstrap Supply for the High-Side MOSFET Driver. A 0.1 μF capacitor is connected between SW and BST to
provide a floating driver voltage for the power switch.
Power Input. Connect to the input power source with a ceramic bypass capacitor to GND directly from this
pin.
Output Enable. Pull this pin high to enable the output. Pull this pin low to disable the output. This pin can
also be used as a programmable UVLO input. This pin has an internal 1.2 μA pull-down current to GND.
Power-Good Open-Drain Output.
Feedback Voltage Sense Input. For the adjustable version, connect this pin to a resistive divider from VOUT. For
the fixed output version, connect this pin to VOUT directly.
Used for internal testing. Connect to GND or leave this pin floating to ensure proper operation.
Ground. Connect this pin to the ground plane.
Switch Node Output. Connect an inductor to VOUT and a catch diode to GND from this pin.
The exposed pad should be soldered to an external ground plane underneath the IC for thermal dissipation.
Rev. 0 | Page 5 of 28
ADP2302/ADP2303
TYPICAL PERFORMANCE CHARACTERISTICS
100
90
90
80
80
60
50
0.5
1.0
1.5
60
50
INDUCTOR: VLF10040T-6R8N4R5
DIODE: SSB43L
0
VOUT = 1.5V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
VOUT = 5.0V
2.0
2.5
3.0
OUTPUT CURRENT (A)
40
INDUCTOR: VLF10040T-4R7N5R4
DIODE: SSB43L
0
90
80
80
EFFICIENCY (%)
90
70
VOUT = 1.2V
VOUT = 1.5V
VOUT = 1.8V
VOUT = 2.5V
60
40
40
1.0
1.5
2.0
2.5
3.0
OUTPUT CURRENT (A)
0
0.5
1.0
1.5
2.0
OUTPUT CURRENT (A)
Figure 8. ADP2302 Efficiency, VIN = 18 V
100
90
90
80
80
EFFICIENCY (%)
100
70
VOUT = 1.5V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
VOUT = 5.0V
50
70
VOUT = 1.2V
VOUT = 1.5V
VOUT = 1.8V
VOUT = 2.5V
60
50
INDUCTOR: VLF10040T-6R8N4R5
DIODE: SSB43L
INDUCTOR: VLF10040T-3R3N6R2
DIODE: SSB43L
40
0
0.5
1.0
OUTPUT CURRENT (A)
1.5
2.0
08833-006
EFFICIENCY (%)
3.0
INDUCTOR: VLF10040T-6R8N4R5
DIODE: SSB43L
Figure 5. ADP2303 Efficiency, VIN = 5 V
60
2.5
VOUT = 2.5V
VOUT = 3.3V
VOUT = 5.0V
50
INDUCTOR: VLF10040T-2R2N7R1
DIODE: SSB43L
0.5
2.0
70
08833-005
EFFICIENCY (%)
100
0
1.5
Figure 7. ADP2303 Efficiency, VIN = 12 V
100
50
1.0
OUTPUT CURRENT (A)
Figure 4. ADP2303 Efficiency, VIN = 18 V
60
0.5
40
0
0.5
1.0
OUTPUT CURRENT (A)
1.5
Figure 9. ADP2302 Efficiency, VIN = 5 V
Figure 6. ADP2302 Efficiency, VIN = 12 V
Rev. 0 | Page 6 of 28
2.0
08833-009
40
70
08833-007
VOUT = 2.5V
VOUT = 3.3V
VOUT = 5.0V
08833-008
70
EFFICIENCY (%)
100
08833-004
EFFICIENCY (%)
VIN = 3.3 V, TA = 25°C, unless otherwise noted.
0.20
0.20
0.15
0.15
0.10
0.10
LOAD REGULATION (%)
0.05
0
–0.05
–0.10
–0.15
–0.05
–0.10
11
14
17
20
–0.20
VIN (V)
0
Figure 10. ADP2302 Line Regulation, VOUT = 3.3 V, IOUT = 2 A
0.5
1.0
OUTPUT CURRENT (A)
1.5
2.0
08833-013
8
08833-010
5
Figure 13. ADP2302 Load Regulation, VOUT = 3.3V, VIN = 12 V
0.20
0.20
0.15
0.15
0.10
0.10
LOAD REGULATION (%)
0.05
0
–0.05
–0.10
–0.15
0.05
0
–0.05
–0.10
–0.15
5
8
11
14
17
08833-011
–0.20
20
VIN (V)
–0.20
0
0.5
1.0
1.5
2.0
2.5
3.0
OUTPUT CURRENT (A)
08833-014
LINE REGULATION (%)
0
–0.15
–0.20
Figure 14. ADP2303 Load Regulation, VOUT = 3.3 V, VIN = 12 V
Figure 11. ADP2303 Line Regulation, VOUT = 3.3 V , IOUT = 3 A
900
50
45
850
QUIESCENT CURRENT (μA)
40
35
30
25
20
15
TJ = –40°C
TJ = +25°C
TJ = +125°C
10
5
800
750
700
650
TJ = –40°C
TJ = +25°C
TJ = +125°C
600
550
500
0
2
4
6
8
10
12
14
16
VIN (V)
18
20
08833-012
SHUTDOWN CURRENT (μA)
0.05
2
4
6
8
10
12
VIN (V)
14
16
Figure 15. Quiescent Current vs. VIN
Figure 12. Shutdown Current vs. VIN
Rev. 0 | Page 7 of 28
18
20
08833-015
LINE REGULATION (%)
ADP2302/ADP2303
ADP2302/ADP2303
812
790
810
770
808
FEEDBACK VOLTAGE (mV)
810
730
710
690
670
650
630
804
802
800
798
796
794
792
610
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
788
–40
4.4
6.4
4.2
6.2
4.0
6.0
PEAK CURRENT LIMIT (A)
40
60
80
100
120
3.8
3.6
3.4
3.2
3.0
5.8
5.6
5.4
5.2
5.0
4.8
0
20
40
60
80
100
120
TEMPERATURE (°C)
4.6
–40
08833-017
–20
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 17. ADP2302 Current-Limit Threshold vs. Temperature, VBST − VSW = 5 V
08833-020
PEAK CURRENT LIMIT (A)
20
Figure 19. 0.8 V Feedback Voltage vs. Temperature
2.8
Figure 20. ADP2303 Current-Limit Threshold vs. Temperature, VBST − VSW = 5 V
1.30
2.8
1.25
ENABLE THRESHOLD (V)
2.9
2.7
RISING
2.6
2.5
2.4
FALLING
RISING
1.20
1.15
FALLING
1.10
1.05
2.3
2.2
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
120
1.00
–40
08833-018
UVLO THRESHOLD (V)
0
TEMPERATURE (°C)
Figure 16. Frequency vs. Temperature
2.6
–40
–20
08833-019
790
08833-016
590
–40
806
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 18. UVLO Threshold vs. Temperature
Figure 21. Enable Threshold vs. Temperature
Rev. 0 | Page 8 of 28
120
08833-021
FREQUENCY (kHz)
750
ADP2302/ADP2303
270
150
265
145
260
140
MINIMUM ON TIME (ns)
MINIMUM OFF TIME (ns)
255
250
245
240
235
230
225
220
135
130
125
120
115
110
215
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
100
–40
08833-022
205
–40
–20
0
20
40
60
80
100
08833-025
105
210
120
TEMPERATURE (°C)
Figure 22. Minimum Off Time vs. Temperature
Figure 25. Minimum On Time vs. Temperature
180
VOUT (AC)
170
1
MOSFET RESISTOR (mΩ)
160
150
140
IL
130
120
SW
110
4
100
VGS = 3V
VGS = 4V
VGS = 5V
90
80
2
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
CH1 5.00mV
Figure 23. MOSFET RDSON vs. Temperature (Pin-to-Pin Measurement)
B
W
CH2 5.00V
M1.00µs
CH4 2.00A Ω T 30.00%
A CH2
7.50V
08833-026
60
–40
08833-023
70
Figure 26. Continuous Conduction Mode (CCM), VOUT = 3.3 V, VIN = 12 V
VOUT (AC)
1
VOUT (AC)
1
IL
4
IL
4
SW
SW
2
B
W
CH2 5.00V
M1.00µs
CH4 2.00A Ω T 30.00%
A CH2
7.50V
CH1 50.00mV
Figure 24. Discontinuous Conduction Mode (DCM), VOUT = 3.3 V, VIN = 12 V
Rev. 0 | Page 9 of 28
B
W
CH2 5.00V
CH4 2.00A Ω
M200µs
A CH2
T 30.00%
7.50V
Figure 27. Power Saving Mode, VOUT = 3.3 V, VIN = 12 V
08833-027
CH1 5.00mV
08833-024
2
ADP2302/ADP2303
VOUT
VOUT
1
1
IL
IL
4
4
EN
EN
SW
2
2
CH1 2.00V BW
CH3 10.0V BW
CH2 10.0V
M1.00ms
CH4 2.00A Ω T 20.20%
A CH3
6.20V
08833-028
3
CH1 2.00V BW
CH3 10.0V BW
Figure 28. Soft Start Without Load, VOUT = 3.3 V, VIN = 12 V
CH2 10.0V
M1.00ms
CH4 2.00A Ω T 20.20%
A CH3
3.60V
08833-031
SW
3
Figure 31. Soft Start with Full Load, VOUT = 3.3 V, VIN = 12 V
VOUT (AC)
VOUT (AC)
1
1
IO
IO
4
B
W
CH4 2.00A Ω
M200µs
T 20.00%
A CH4
1.20A
CH1 200mV
B
W
CH4 2.00A Ω
Figure 29. ADP2303 Load Transient, 0.5 A to 3.0 A, VOUT = 5.0 V, VIN = 12 V,
L = 4.7 μH, COUT = 47 μF
M200µs
T 20.00%
A CH4
1.88A
08833-032
CH1 500mV
08833-029
4
Figure 32. ADP2303 Load Transient, 0.5 A to 3.0 A, VOUT = 3.3 V, VIN = 12 V,
L = 4.7 μH, COUT = 2 × 47 μF
VOUT (AC)
VOUT (AC)
1
1
IO
IO
4
B
W
CH4 1.00A Ω
M200µs
T 20.00%
A CH4
1.20A
Figure 30. ADP2302 Load Transient, 0.5 A to 2.0 A, VOUT = 5.0 V, VIN = 12 V,
L = 6.8 μH, COUT = 2 × 22 μF
CH1 200mV
B
W
CH4 1.00A Ω
M200µs
T 20.00%
A CH4
1.20A
08833-033
CH1 200mV
08833-030
4
Figure 33. ADP2302 Load Transient, 0.5 A to 2.0 A, VOUT = 3.3 V, VIN = 12 V,
L = 6.8 μH, COUT = 2 × 22 μF
Rev. 0 | Page 10 of 28
ADP2302/ADP2303
VOUT
VOUT
1
1
IL
IL
SW
4
4
SW
B
W
CH2 10.0V
M40.0µs
CH4 5.00A Ω T 30.00%
A CH1
1.26V
CH1 1.00V
B
W
CH2 10.0V
M400µs
CH4 5.00A Ω T 30.00%
A CH1
1.26V
08833-037
2
CH1 1.00mV
08833-034
2
Figure 37. Output Short Recovery, VOUT = 3.3 V, VIN = 12 V,
L = 4.7 μH, COUT = 2 × 47 μF
Figure 34. Output Short, VOUT = 3.3 V, VIN = 12 V,
L = 4.7 μH, COUT = 2 × 47 μF
VOUT
VOUT
1
VIN
VIN
1
SW
2
M1.00ms A CH3
T 23.40%
11.0V
CH1 20.0mV BW CH2 10.0V BW M1.00ms
CH3 5.00V BW
T 23.40%
A CH3
11.0V
80
180
80
180
64
144
64
144
48
108
48
108
32
72
32
72
16
36
16
36
0
0
0
0
–72
–48
–108
–64
–144
–80
CROSS FREQUENCY = 36kHz
PHASE MARGIN = 60°
–180
1k
10k
100k
FREQUENCY (Hz)
1M
–16
–36
–32
–72
–108
–48
–80
Figure 36. ADP2302 Bode Plot, VOUT = 2.5 V, VIN = 12 V,
L = 4.7 μH, COUT =3 × 22 μF
–144
CROSS FREQUENCY = 42kHz
PHASE MARGIN = 56°
–64
08833-036
–36
–32
PHASE (Degrees)
–16
–180
1k
10k
100k
FREQUENCY (Hz)
1M
Figure 39. ADP2302 Bode Plot, VOUT = 3.3 V, VIN = 12 V,
L = 6.8 μH, COUT = 2 × 22 μF
Rev. 0 | Page 11 of 28
PHASE (Degrees)
Figure 38. ADP2302 Line Transient, 7 V to 15 V, VOUT = 3.3 V, IOUT = 2 A,
L = 6.8 μH, COUT = 2 × 22 μF
MAGNITUDE (dB)
Figure 35. ADP2303 Line Transient, 7 V to 15 V, VOUT = 3.3 V, IOUT = 3 A,
L = 4.7 μH, COUT = 2 × 47 μF
08833-039
2
08833-038
3
08833-035
3
CH1 20.0mV BW CH2 10.0V BW
CH3 5.00V BW
MAGNITUDE (dB)
SW
80
180
64
144
64
144
48
108
48
108
32
72
32
72
16
36
16
36
0
0
0
0
–36
–32
–72
–48
–108
–144
–64
–180
1k
10k
100k
FREQUENCY (Hz)
1M
–32
–72
–48
–108
–80
–180
1k
Figure 40. ADP2302 Bode Plot, VOUT = 5 V, VIN = 12 V,
L = 6.8 μH, COUT = 2 × 22 μF
10k
100k
FREQUENCY (Hz)
1M
Figure 42. ADP2303 Bode Plot, VOUT = 2.5 V, VIN = 12 V,
L = 3.3 μH, COUT = 2 × 47 μF
180
80
180
64
144
64
144
48
108
48
108
32
72
32
72
16
36
16
36
0
0
0
0
PHASE (Degrees)
MAGNITUDE (B/A) (dB)
80
–16
–36
–32
–72
–48
–108
–144
–64
CROSS FREQUENCY = 19kHz
PHASE MARGIN = 59°
–64
–80
–180
1k
10k
100k
FREQUENCY (Hz)
1M
08833-041
MAGNITUDE (dB)
–144
CROSS FREQUENCY = 26kHz
PHASE MARGIN = 65°
–16
–36
–32
–72
–48
–108
–80
Figure 41. ADP2303 Bode Plot, VOUT = 3.3 V, VIN = 12 V,
L = 4.7 μH, COUT = 2 × 47 μF
–144
CROSS FREQUENCY = 28kHz
PHASE MARGIN = 65°
–180
1k
10k
100k
FREQUENCY (Hz)
1M
Figure 43. ADP2303 Bode Plot, VOUT = 5 V, VIN = 12 V,
L = 4.7 μH, COUT = 47 μF
Rev. 0 | Page 12 of 28
PHASE (B–A) (Degeres)
–80
–36
08833-143
CROSS FREQUENCY = 32kHz
PHASE MARGIN = 59°
–64
–16
08833-142
PHASE (Degrees)
–16
PHASE (B–A) (Degeres)
180
MAGNITUDE (B/A) (dB)
80
08833-040
MAGNITUDE (dB)
ADP2302/ADP2303
ADP2302/ADP2303
FUNCTIONAL BLOCK DIAGRAM
VIN
VIN
2
THERMAL
SHUTDOWN
SHUTDOWN
LOGIC
UVLO
SHUTDOWN IC
1.20V
ON
CURRENT
SENSE AMPLIFIER
OCP
EN 3
1.2µA
OVP
0.880V
BOOT
REGULATOR
CURRENT
LIMIT
THRESHOLD
R
1
BST
Q
S
VBIAS = 1.1V
PGOOD 4
0.680V
8
RAMP
GENERATOR
SW
VOUT
CLK
GENERATOR
FREQUENCY FOLDBACK
(⅛ fSW, ¼ fSW, ½ fSW, fSW)
NC 6
gm
5
0.8V VOLTAGE
REFERENCE
FB
ADP2302/ADP2303
7
GND
Figure 44. Functional Block Diagram
Rev. 0 | Page 13 of 28
08833-042
OFF
ADP2302/ADP2303
THEORY OF OPERATION
The ADP2302/ADP2303 are nonsynchronous, step-down,
dc-to-dc regulators, each with an integrated high-side power
MOSFET. The high switching frequency and 8-lead SOIC
package provide a small, step-down, dc-to-dc regulator
solution.
The ADP2302/ADP2303 can operate with an input voltage from
3.0 V to 20 V while regulating an output voltage down to 0.8 V.
The ADP2302 can provide 2 A maximum continuous output
current, and the ADP2303 can provide 3 A maximum
continuous output current.
BASIC OPERATION
The ADP2302/ADP2303 use the fixed-frequency, peak currentmode PWM control architecture from medium to high loads,
but shift to a pulse-skip mode control scheme at light loads to
reduce the switching power losses and improve efficiency. When
these devices operate in fixed-frequency PWM mode, output
regulation is achieved by controlling the duty cycle of the integrated
MOSFET. While the devices are operating in pulse-skip mode at
light loads, the output voltage is controlled in a hysteretic
manner with higher output ripple. In this mode of operation, the
regulator periodically stops switching for a few cycles, thus
keeping the conversion losses minimal to improve efficiency.
PWM MODE
In PWM mode, the ADP2302/ADP2303 operate at a fixed
frequency, set by an internal oscillator. At the start of each
oscillator cycle, the MOSFET switch is turned on, providing a
positive voltage across the inductor. The inductor current
increases until the current-sense signal crosses the peak
inductor current threshold that turns off the MOSFET switch;
this threshold is set by the error amplifier output. During the
MOSFET off time, the inductor current declines through the
external diode until the next oscillator clock pulse comes and a
new cycle starts.
POWER SAVING MODE
To achieve higher efficiency, the ADP2302/ADP2303 smoothly
transition to the pulse-skip mode when the output load decreases
below the pulse-skip current threshold. When the output voltage dips below the regulation, the ADP2302/ADP2303 enter
PWM mode for a few oscillator cycles until the voltage increases
to regulation range. During the idle time between bursts, the
MOSFET switch is turned off, and the output capacitor supplies
all the output current.
Because the pulse-skip mode comparator monitors the internal
compensation node, which represents the peak inductor current
information, the average pulse-skip load current threshold
depends on the input voltage (VIN), the output voltage (VOUT),
the inductor, and the output capacitor.
Because the output voltage occasionally dips below regulation
and then recovers, the output voltage ripple in the power saving
mode is larger than the ripple in the PWM mode of operation.
BOOTSTRAP CIRCUITRY
The ADP2302/ADP2303 each have an integrated boot regulator,
which requires that a 0.1 μF ceramic capacitor (X5R or X7R) be
placed between the BST and SW pins to provide the gate drive
voltage for the high-side MOSFET. There is at least a 1.2 V
difference between the BST and SW pins to turn on the high-side
MOSFET. This voltage should not exceed 5.5 V in case the BST
pin is supplied with the external voltage source through a diode.
The ADP2302/ADP2303 generate a typical 5.0 V bootstrap voltage
for the gate drive circuit by differentially sensing and regulating
the voltage between the BST and SW pins. There is a diode
integrated on the chip that blocks the reverse voltage between the
VIN and BST pins when the MOSFET switch is turned on.
PRECISION ENABLE
The ADP2302/ADP2303 provide a precision enable circuit that
has 1.2 V reference threshold with 100 mV hysteresis. When the
voltage at the EN pin is greater than 1.2 V (typical), the part is
enabled. If the EN voltage falls below 1.1 V (typical), the chip
is disabled. The precision enable threshold voltage allows the
ADP2302/ADP2303 to be easily sequenced from other input/
output supplies. It also can be used as a programmable UVLO
input by using a resistive divider. An internal 1.2 μA pull-down
current prevents errors if the EN pin is left floating.
INTEGRATED SOFT START
The ADP2302/ADP2303 have an internal digital soft start
circuitry to limit the output voltage rise time and reduce
the inrush current at power up. The soft start time is fixed at
2048 clock cycles.
CURRENT LIMIT
The ADP2302/ADP2303 include current-limit protection circuitry
to limit the amount of positive current flowing through the highside MOSFET switch. The positive current limit on the power
switch limits the amount of current that can flow from the input
to the output.
SHORT-CIRCUIT PROTECTION
The ADP2302/ADP2303 include frequency foldback to prevent
output current runaway when there is a hard short on the output.
The switching frequency is reduced when the voltage at the FB pin
drops below a certain value, which allows more time for the
inductor current to decline, but increases the ripple current while
regulating the peak current. This results in a reduction in average
output current and prevents output current runaway. The correlation between the switching frequency and the FB pin voltage
is shown in Table 5.
Rev. 0 | Page 14 of 28
ADP2302/ADP2303
Table 5. Correlation Between fSW and VFB
OVERVOLTAGE PROTECTION (OVP)
FB Pin Voltage
VFB ≥ 0.6 V
0.4 V < VFB < 0.6 V
0.2 V < VFB ≤ 0.4 V
VFB ≤ 0.2 V
The ADP2302/ADP2303 provide an overvoltage protection
feature to protect the system against an output short to a higher
voltage supply. If the feedback voltage is above 0.880 V, the
internal high-side MOSFET is turned off, until the voltage at FB
decreases to 0.850 V. At that time, the ADP2302/ADP2303
resume normal operation.
Switching Frequency
fSW
1/2 fSW
1/4 fSW
1/8 fSW
When a hard short (VFB ≤ 0.2 V) is removed, a soft start cycle
is initiated to regulate the output back to its level during normal
operation, which helps to limit the inrush current and prevent
possible overshoot on the output voltage.
UNDERVOLTAGE LOCKOUT (UVLO)
The ADP2302/ADP2303 have fixed, internally set undervoltage
lockout circuitry (UVLO). If the input voltage drops below
2.4 V, the ADP2302/ADP2303 shut down and the MOSFET
switch turns off. After the voltage rises above 2.7 V, the soft
start period is initiated, and the part is enabled.
THERMAL SHUTDOWN (TSD)
If the ADP2302/ADP2303 junction temperature rises above 150°C,
the thermal shutdown circuit disables the chip. Extreme junction
temperature can be the result of high current operation, poor
circuit board design, or high ambient temperature. A 15°C
hysteresis is included so that when thermal shutdown occurs,
the ADP2302/ADP2303 do not return to operation until the onchip temperature drops below 135°C. When the devices recover
from thermal shutdown, a soft start is initiated.
POWER GOOD
The PGOOD pin is an active high, open-drain output and
requires a resistor to pull it up to a voltage (<20.0 V). A high
indicates that the voltage on the FB pin (and therefore the
output voltage) is above 87.5% of the reference voltage. A low
indicates that the voltage on the FB pin is below 85% of the
reference voltage. There is a 32-cycle waiting period after FB is
detected as being in or out of bounds.
CONTROL LOOP
The ADP2302/ADP2303 are internally compensated to minimize
external component count and cost. In addition, the built-in
slope compensation helps to prevent subharmonic oscillations
when the ADP2302/ADP2303 operate at a duty cycle greater
than or close to 50%.
Rev. 0 | Page 15 of 28
ADP2302/ADP2303
APPLICATIONS INFORMATION
PROGRAMMING OUTPUT VOLTAGE
ADP2302/ADP2303 have an adjustable version where the output
voltage is programmed through an external resistive divider, as
shown in Figure 45. Suggested resistor values for the typical
output voltage setting are listed in Table 6. The output voltages
are calculated using the following equation:
⎛ R
VOUT = 0.800 V × ⎜⎜1 + TOP
⎝ R BOT
where:
VOUT is the output voltage.
RTOP is the feedback resistor from VOUT to FB.
RBOT is the feedback resistor from FB to GND.
VOUT
RTOP
08833-043
FB
RBOT
VOUT(max) = tMIN-OFF × fSW(max) × (VIN(min) + VD) − VD
where:
VIN(min) is the minimum input voltage.
fSW(max) is the maximum switching frequency for the worst case.
VD is the diode forward drop.
tMIN-OFF is the minimum controllable off time.
⎞
⎟
⎟
⎠
ADP2302/
ADP2303
The upper limit of the output voltage is constrained by the minimum controllable off time, which can be as high as 280 ns in
ADP2302/ADP2303 for the worst case. By considering the
variation of both the switching frequency and the input voltage,
the equation for the upper limit of the output voltage is
Figure 45. Programming the Output Voltage Using a Resistive Voltage Divider
In addition, the bootstrap circuit limits the minimum input voltage
for the desired output due to the internal dropout voltage. To
attain stable operation at light loads and ensure proper startup for
the prebiased condition, the ADP2302/ADP2303 require the
voltage difference between the input voltage and the regulated
output voltage (or between the input voltage and the prebias
voltage) to be greater than 2.1 V for the worst case. If the voltage
difference is smaller, the bootstrap circuit relies on some minimum
load current to charge the boost capacitor for startup. Figure 46
shows the typical required minimum input voltage vs. load current
for the 3.3 V output voltage.
5.3
Table 6. Suggested Values for Resistive Voltage Divider
FOR START UP
5.1
RBOT (kΩ), ±1%
20
11.3
10.2
10.2
10.2
10
4.9
4.7
4.5
4.3
4.1
VOLTAGE CONVERSION LIMITATIONS
3.9
There are both lower and upper output voltage limitations for a
given input voltage due to the minimum on time, the minimum
off time, and the bootstrap dropout voltage.
3.7
The lower limit of the output voltage is constrained by the
controllable minimum on time, which can be as high as 170 ns
for the worst case. By considering the variation of both the switching frequency and the input voltage, the equation for the lower
limit of the output voltage is
WHILE IN
OPERATION
3.5
1
10
100
1000
OUPTUT CURRENT (mA)
08833-146
RTOP (kΩ), ±1%
10
10
12.7
21.5
31.6
52.3
VIN (V)
VOUT (V)
1.2
1.5
1.8
2.5
3.3
5.0
Figure 46. Minimum Input Voltage vs. Load Current
Based on three conversion limitations (the minimum on time,
the minimum off time, and the bootstrap dropout voltage),
Figure 47 shows the voltage conversion limitations.
VOUT(min) = tMIN-ON × fSW(max) × (VIN(max) + VD) − VD
where:
VIN(max) is the maximum input voltage.
fSW(max) is the maximum switching frequency for the worst case.
tMIN-ON is the minimum controllable on time.
VD is the diode forward drop.
Rev. 0 | Page 16 of 28
ADP2302/ADP2303
22
VIN
VIN
20
MAXIMUM INPUT VOLTAGE
18
ADP2302/
ADP2303
REN1
16
EN
12
REN2
10
08833-047
VIN (V)
14
8
Figure 49. Precision Enable Used as a Programmable UVLO
6
The precision enable feature also allows the ADP2302/ADP2303 to
be sequenced precisely by using a resistive voltage divider from
another dc-to-dc power supply, as shown in Figure 50.
MINIMUM INPUT VOLTAGE
2
0
2
4
6
8
VOUT (V)
10
12
14
16
08833-147
4
Figure 47. Voltage Conversion Limitations
LOW INPUT VOLTAGE CONSIDERATIONS
ADP2302/
ADP2303
ANOTHER
DC/DC
SUPPLIER
With a 1.2 μA pull-down current on the EN pin, the equation for
the start-up voltage in Figure 49 and Figure 50 is
⎞
⎛ 1.2 V
VSTARTUP = ⎜⎜
+ 1.2 μA ⎟⎟ × R EN1 + 1.2 V
⎝ R EN2
⎠
BST
VIN
ADP2302/
ADP2303
5V BIAS VOLTAGE
where:
VSTARTUP is the start-up voltage to enable the chip.
REN1 is the resistor from the dc source to EN.
REN2 is the resistor from EN to GND.
SW
ON
FB
EN
08833-046
OFF
EN
REN2
Figure 50. Precision Enable Used as a Sequencing Control
from Another DC-to-DC Power Supply
SCHOTTKY
DIODE
3.0V ~ 5.0V
REN1
08833-048
For low input voltage between 3 V and 5 V, the internal boot
regulator cannot provide enough bootstrap voltage due to the
internal dropout voltage. As a result, the increased MOSFET
RDS(ON) reduces the available load current. To prevent this, add
an external small-signal Schottky diode from a 5.0 V external
bootstrap bias voltage. Because the absolute maximum rating
between the BST and SW pins is 6.0 V, the bias voltage should
be less than 5.5 V. Figure 48 shows the application diagram for
the external bootstrap circuit.
GND
Figure 48. External Bootstrap Circuit for Low Input Voltage Application
PROGRAMMING THE PRECISION ENABLE
Generally, the EN pin can connect to the VIN pin so that the
device automatically starts up when the input power is applied.
However, the precision enabling feature allows the ADP2302/
ADP2303 to be used as a programmable UVLO by connecting
a resistive voltage divider to VIN, as shown in Figure 49. This
configuration prevents the start-up problems that can occur
when VIN ramps up slowly in soft start with a relatively high
load current.
INDUCTOR
The high switching frequency of the ADP2302/ADP2303 allows
the use of small inductors. For best performance, use inductor
values between 1 μH and 15 μH.
The peak-to-peak inductor ripple current is calculated using the
following equation:
ΔI RIPPLE =
(VIN − VOUT ) ⎛ VOUT + VD
× ⎜⎜
L × f sw
⎝ VIN + VD
⎞
⎟
⎟
⎠
where:
fSW is the switching frequency.
L is the inductor value.
VD is the diode forward drop.
VIN is the input voltage.
VOUT is the output voltage.
Inductors of smaller values are usually smaller in size but
increase the ripple current and the output ripple voltage. As a
guideline, the inductor peak-to-peak ripple current is typically
set to 30% of the maximum load current for optimal transient
Rev. 0 | Page 17 of 28
ADP2302/ADP2303
response and efficiency. Therefore, the inductor value is calculated
using the following equation:
L=
(VIN − VOUT )
0.3 × I LOAD (max) × f sw
⎛V
+ VD
× ⎜⎜ OUT
⎝ V IN + VD
⎞
⎟
⎟
⎠
CATCH DIODE
The catch diode conducts the inductor current during the off
time of the internal MOSFET. The average current of the diode
in normal operation is, therefore, dependent on the duty cycle
of the regulator as well as the output load current.
where ILOAD(max) is the maximum load current.
⎛ V
+ VD
I DIODE( AVG ) = ⎜⎜1 − OUT
V IN + V D
⎝
The inductor peak current is calculated using the following
equation:
I PEAK = I LOAD (max) +
⎞
⎟ × I LOAD(max)
⎟
⎠
where VD is the diode forward drop.
ΔI RIPPLE
2
The minimum current rating of the inductor must be greater
than the inductor peak current. For ferrite core inductors with a
quick saturation characteristic, the inductor saturation current
rating should be higher than the switch current limit threshold
to prevent the inductor from reaching its saturation point. Be
sure to validate the worst-case condition, in which there is a
shorted output, over the intended temperature range.
Inductor conduction loss is caused by the flow of current
through internal dc resistance (DCR). Larger sized inductors
have smaller DCR of the inductor and, therefore, may reduce
inductor conduction losses. Inductor core loss is related to the
core material and the ac flux swing, which are affected by the
peak-to-peak inductor ripple current. Because the ADP2302/
ADP2303 are high frequency switching regulators, shielded ferrite core materials are recommended for their low core losses
and low EMI. Some recommended inductors are shown in
Table 8.
The only reason to select a diode with a higher current rating
than necessary in normal operation is for the worst-case condition, in which there is a shorted output. In this case, the diode
current increases up to the typical peak current limit threshold.
Be sure to consult the diode data sheet to ensure that the diode
can operate well within the thermal and electrical limits.
The reverse breakdown voltage rating of the diode must be higher
than the highest input voltage and allow an appropriate margin
for the ringing that may be present on the SW node. A Schottky
diode is recommended for the best efficiency because it has a
low forward voltage drop and fast switching speed. Table 7
provides a list of recommended Schottky diodes.
Table 7. Recommended Schottky Diodes
Vendor
Vishay
ON Semiconductor
Diodes Inc.
Part No.
SSB43L
SSA33L
MBRS330T3
B330B
VRRM (V)
30
30
30
30
Table 8. Recommended Inductors
Vendor
Sumida
Coilcraft
Toko
TDK
Value (μH)
2.5
3.8
5.2
7
10
2.5
3.8
5.2
7
10
2.8
3.7
4.7
6.4
10
2.2
3.3
4.7
6.8
10
Part No.
CDRH104RNP-2R5N
CDRH104RNP-3R8N
CDRH104RNP-5R2N
CDRH104RNP-7R0N
CDRH104RNP-100N
MSS1038-252NL
MSS1038-382NL
MSS1038-522NL
MSS1038-702NL
MSS1038103NL
#919AS-2R8M
#919AS-3R7M
#919AS-4R7M
#919AS-6R4M
#919AS-100M
VLF10040T-2R2N7R1
VLF10040T-3R3N6R2
VLF10040T-4R7N5R4
VLF10040T-6R8N4R5
VLF10040T-100M3R8
DCR (mΩ)
7.8
9.6
16
20
26
10
13
22
27
35
10.7
14.2
16.2
22.9
26.5
7.9
10.5
12.7
19.8
28
Rev. 0 | Page 18 of 28
ISAT (A)
7.5
6
5.5
4.8
4.4
7.62
6.5
5.28
4.74
3.9
8.3
7
6.1
5.2
4.3
8.2
6.7
5.4
4.6
3.8
Dimensions L × W × H (mm)
10.5 × 10.3 × 3.8
10.5 × 10.3 × 3.8
10.5 × 10.3 × 3.8
10.5 × 10.3 × 3.8
10.5 × 10.3 × 3.8
10 × 10.2 × 3.8
10 × 10.2 × 3.8
10 × 10.2 × 3.8
10 × 10.2 × 3.8
10 × 10.2 × 3.8
10.3 × 10.3 × 4.5
10.3 × 10.3 × 4.5
10.3 × 10.3 × 4.5
10.3 × 10.3 × 4.5
10.3 × 10.3 × 4.5
10 × 9.7 × 4.0
10 × 9.7 × 4.0
10 × 9.7 × 4.0
10 × 9.7 × 4.0
10 × 9.7 × 4.0
IAVG (A)
4
3
3
3
ADP2302/ADP2303
INPUT CAPACITOR
The input capacitor must be able to support the maximum input
operating voltage and the maximum RMS input current. The
rms ripple current flowing through the input capacitor is, at
maximum, ILOAD(max)/2. Select an input capacitor capable of
withstanding the rms ripple current for an application’s maximum load current using the following equation:
I IN ( RMS) = I LOAD(max) × D × (1 − D )
VOUT + VD
V IN + VD
The recommended input capacitance is ceramic with X5R or X7R
dielectrics due to its low ESR and small temperature coefficients.
A capacitance of 10 μF should be adequate for most applications.
To minimize supply noise, place the input capacitor as close as
possible to the VIN pin of the ADP2302/ADP2303.
OUTPUT CAPACITOR
The output capacitor selection affects both the output voltage ripple
and the loop dynamics of the regulator. The ADP2302/ADP2303
are designed to operate with small ceramic capacitors that have
low ESR and equivalent series inductance (ESL) and are, therefore,
easily able to meet stringent output voltage ripple specifications.
When the regulator operates in continuous conduction mode,
the overall output voltage ripple is the sum of the voltage spike
caused by the output capacitor equivalent series resistance
(ESR) plus the voltage ripple caused by the charging and
discharging of the output capacitor
⎛
1
ΔV RIPPLE = ΔI RIPPLE × ⎜⎜
+ ESR COUT
⎝ 8 × f sw × C OUT
⎞
⎟
⎟
⎠
Capacitors with lower ESR are preferable to guarantee low
output voltage ripple, as shown in the following equation:
ESRCout
In general, most applications require a minimum output
capacitor value of 2 × 22 μF.
Some recommended output capacitors for VOUT ≤ 5.0 V are
provided in Table 9.
THERMAL CONSIDERATION
ADP2302/ADP2303 have an internal high-side MOSFET and
its drive circuit. Only a small amount of power dissipates inside
the ADP2302/ADP2303 package under typical load conditions,
which reduces thermal constraints.
where D is the duty cycle and is equal to
D=
coefficients. Y5V and Z5U dielectrics are not recommended
because of their poor temperature and dc bias characteristics.
However, in applications with maximum loads at high ambient
temperature and high duty cycle, the heat dissipated in the
package may cause the junction temperature of the die to
exceed the maximum junction temperature of 125°C. If the
junction temperature exceeds 150°C, the regulator goes into
thermal shutdown and recovers when the junction temperature
drops below 135°C.
The junction temperature of the die is the sum of the ambient
temperature and the temperature rise of the package due to
power dissipation, as indicated in the following equation:
TJ = TA + TR
where:
TJ is the junction temperature.
TA is the ambient temperature.
TR is the rising temperature of the package due to power
dissipation.
The rising temperature of the package is directly proportional
to the power dissipation in the package. The proportionality
constant for this relationship is the thermal resistance from the
junction of the die to the ambient temperature, as shown in the
following equation:
TR = θJA × PD
ΔVRIPPLE
≤
ΔI RIPPLE
Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over temperature and applied
voltage. X5R or X7R dielectrics are recommended for best
performance, due to their low ESR and small temperature
where:
TR is the rising temperature of the package.
θJA is the thermal resistance from the junction of the die to the
ambient temperature of the package.
PD is the power dissipation in the package.
Table 9. Recommended Capacitors for VOUT ≤ 5.0 V
Vendor
Murata
TDK
Value
22 μF, 6.3 V, X5R
47 μF, 6.3 V, X5R
22 μF, 6.3 V, X5R
33 μF, 6.3 V, X5R
47 μF, 6.3 V, X5R
Part No.
GRM31CR60J226KE19
GRM32ER60J476ME20
C3216X5R0J226MB
C3216X5R0J336MB
C3225X5R0J476MB
Rev. 0 | Page 19 of 28
Dimensions L × W × H (mm)
3.2 × 2.5 × 2.0
3.2 × 2.5 × 2.0
3.2 × 1.6 × 0.85
3.2 × 1.6 × 1.3
3.2 × 2.5 × 2.5
ADP2302/ADP2303
DESIGN EXAMPLE
This section provides the procedures to select the external components, based on the example specifications listed in Table 10.
The schematic for this design example is shown in Figure 51.
Because the output current is 3 A, the ADP2303 is chosen for
this application.
Table 10. Step-Down DC-to-DC Regulator Requirements
Parameter
Input Voltage, VIN
Output Voltage, VOUT
Programmable
UVLO Voltage
PGOOD
Specification
12.0 V ± 10%
3.3 V, 3 A, 1% VOUT ripple
at full load condition
VIN start-up voltage
approximately 7.8 V
Not used
Additional
Requirements
None
None
The inductor peak current is calculated using the following
equation:
I PEAK = I LOAD(max) +
where:
ILOAD(max) = 3 A.
ΔIRIPPLE = 0.7 A.
The calculated peak current for the inductor is 3.4 A. Therefore,
in this application, select VLF10040T-4R7N5R4 as the inductor.
OUTPUT CAPACITOR SELECTION
None
Select the output capacitor based on the minimum output
voltage ripple requirement, according to the following equation:
None
⎛
1
ΔV RIPPLE = ΔI RIPPLE × ⎜⎜
+ ESR COUT
⎝ 8 × f sw × C OUT
CATCH DIODE SELECTION
Select the catch diode. A Schottky diode is recommended for best
efficiency because it has a low forward voltage drop and faster
switching speed. The average current of the catch diode in
normal operation, with a typical Schottky diode forward
voltage, can be calculated using the following equation:
⎛ V
+ VD
I DIODE( AVG ) = ⎜⎜1 − OUT
V IN + V D
⎝
where:
ΔIRIPPLE = 0.7 A.
fSW = 700 kHz.
ΔVRIPPLE = 33 mV (1% of output voltage).
Because the output capacitor is one of two external components
that control the loop stability and according to the recommended
external components in Table 11, choose two 47 μF capacitor
with a 6.3 V voltage rating in this application.
RESISTIVE VOLTAGE DIVIDER SELECTION
The output feedback resistive voltage divider is
⎛ R
VOUT = 0.800 V × ⎜⎜1 + TOP
⎝ R BOT
Therefore, IDIODE(AVG) = 2.1 A.
In this case, selecting a SSB43L, 4.0 A, 30 V surface-mount
Schottky diode results in more reliable operation.
Select the inductor by using the following equation:
0.3 × I LOAD (max) × f sw
⎛V
+ VD
× ⎜⎜ OUT
V
+
⎝ IN V D
⎞
⎟
⎟
⎠
For the 3.3 V output voltage, choose RTOP = 31.6 kΩ and
RBOT = 10.2 kΩ as the feedback resistive voltage divider
according to the recommended values in Table 11.
INDUCTOR SELECTION
(V IN − VOUT )
⎞
⎟
⎟
⎠
If ESR of the ceramic capacitor is 3 mΩ, then COUT = 4 μF.
⎞
⎟ × I LOAD(max)
⎟
⎠
where:
VOUT = 3.3 V.
VIN = 12 V.
ILOAD(max) = 3 A.
VD = 0.4 V.
L=
ΔI RIPPLE
2
The resistive voltage divider for the programmable VIN start-up
voltage is
⎞
⎟
⎟
⎠
⎞
⎛ 1. 2 V
VSTARTUP = ⎜⎜
+ 1.2 μA ⎟⎟ × R EN1 + 1.2 V
R
⎠
⎝ EN2
where:
VOUT = 3.3 V.
VIN = 12 V.
ILOAD(max) = 3 A.
VD = 0.4 V.
fSW = 700 kHz.
If VSTARTUP = 7.8 V, choose REN2 = 10.2 kΩ, and then calculate
REN1, which, in this case, is 56 kΩ.
This results in L = 4.12 μH. The closest standard value is 4.7 μH;
therefore, ΔIRIPPLE = 0.7 A.
Rev. 0 | Page 20 of 28
ADP2302/ADP2303
VIN
CIN
10µF
25V
CBST
0.1µF
ADP2303
RPGOOD
100kΩ
REN1
56kΩ
1%
BST
SW
PGOOD
EN
REN2
10.2kΩ
1%
L
D
4.7µH
SSB43L
VOUT = 3.3V
3A
COUT1
47µF
6.3V
COUT2
47µF
6.3V
RTOP
31.6kΩ
1%
FB
RBOT
10.2kΩ
1%
GND
08833-049
VIN = 12V
Figure 51. Schematic for the Design Example
Table 11. Recommended External Components for Typical Applications at 2 A/3 A Output Load
Part Number
ADP2302
ADP2303
VIN (V)
18
18
12
12
12
12
12
5
5
5
18
18
12
12
12
12
12
5
5
5
VOUT (V)
3.3
5.0
1.5
1.8
2.5
3.3
5.0
1.5
1.8
2.5
3.3
5.0
1.5
1.8
2.5
3.3
5.0
1.5
1.8
2.5
ILOAD(max) (A)
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
L (μH)
6.8
10
4.7
4.7
4.7
6.8
6.8
3.3
3.3
3.3
4.7
6.8
2.5
3.3
3.3
4.7
4.7
2.2
2.2
2.2
COUT
2 × 22 μF
2 × 22 μF
2 × 47 μF
3 × 22 μF
3 × 22 μF
2 × 22 μF
2 × 22 μF
2 × 47 μF
2 × 47 μF
2 × 22 μF
2 × 47 μF
47 μF
3 × 47 μF
3 × 47 μF
2 × 47 μF
2 × 47 μF
47 μF
3 × 47 μF
3 × 47 μF
3 × 47 μF
Rev. 0 | Page 21 of 28
RTOP (kΩ), ±1%
31.6
52.3
10
12.7
21.5
31.6
52.3
10
12.7
21.5
31.6
52.3
10
12.7
21.5
31.6
52.3
10
12.7
21.5
RBOT (kΩ), ±1%
10.2
10
11.3
10.2
10.2
10.2
10
11.3
10.2
10.2
10.2
10
11.3
10.2
10.2
10.2
10
11.3
10.2
10.2
ADP2302/ADP2303
CIRCUIT BOARD LAYOUT RECOMMENDATIONS

Good circuit board layout is essential to obtaining the best
performance for ADP2302/ADP2303. Poor layout can affect the
regulation and stability, as well as the electromagnetic interface
(EMI) and electromagnetic compatibility (EMC) performance.
A PCB layout example is shown in Figure 53. Refer to the
following guidelines for a good PCB layout:


ADP2302/
ADP2303
Place the input capacitor, the inductor, catch diode, output
capacitor, and bootstrap capacitor close to the IC using
short traces.
Ensure that the high current loop traces are as short and
wide as possible. The high current path is shown Figure 52.
Maximize the size of ground metal on the component side
to improve thermal dissipation.
Use a ground plane with several vias connecting to the
component side ground to further reduce noise on
sensitive circuit nodes.
PGOOD
SW
EN
FB
GND
Figure 52. Typical Application Circuit with High Current Lines Shown in Blue
VOUT
INDUCTOR
OUTPUT
CAPACITORS
DIODE
GND
BST CAP
BST 1
INPUT
CAPACITOR
VIN 2
VIN
08833-050

BST
VIN
EXPOSED
PAD
8 SW
7 GND
EN 3
6 NC
PGOOD 4
5 FB
08833-051

Minimize the length of the FB trace connecting the top of
the feedback resistive voltage divider to the output. In
addition, keep these traces away from the high current
traces and the switch node to avoid noise pickup.
Figure 53. Recommended Layout for ADP2302/ADP2303
Rev. 0 | Page 22 of 28
ADP2302/ADP2303
TYPICAL APPLICATION CIRCUITS
VIN = 12V
BST
VIN
ADP2302ARDZ
EN
SW
RPGOOD
100kΩ
PGOOD
CBST
0.1µF
VOUT = 1.5V
2A
L
4.7µH
D
B330B
COUT1
47µF
6.3V
COUT2
47µF
6.3V
RTOP
10kΩ
1%
FB
RBOT
11.3kΩ
1%
GND
08833-052
CIN
10µF
25V
Figure 54. ADP2302 Typical Application, VIN = 12 V, VOUT = 1.5 V, 2 A
VIN = 12V
VIN
BST
CBST
0.1µF
ADP2302ARDZ
EN
SW
L
4.7µH
D
B330B
RPGOOD
100kΩ
PGOOD
VOUT = 1.8V
2A
COUT1
22µF
6.3V
COUT2
22µF
6.3V
COUT3
22µF
6.3V
RTOP
12.7kΩ
1%
FB
RBOT
10.2kΩ
1%
GND
08833-053
CIN
10µF
25V
Figure 55. ADP2302 Typical Application, VIN = 12 V, VOUT = 1.8 V, 2 A
VIN = 12V
VIN
CIN
10µF
25V
BST
CBST
0.1µF
ADP2302ARDZ-2.5
EN
SW
PGOOD
VOUT = 2.5V
2A
L
4.7µH
D
B330B
COUT1
22µF
6.3V
COUT2
22µF
6.3V
COUT3
22µF
6.3V
08833-054
FB
GND
Figure 56. ADP2302 Typical Application, VIN = 12 V, VOUT = 2.5 V, 2 A
VIN
VIN
RPGOOD
100kΩ
REN1
56kΩ
1%
BST
ADP2302ARDZ-3.3
SW
PGOOD
EN
REN2
10.2kΩ
1%
CBST
0.1µF
L
6.8µH
D
B330B
VOUT = 3.3V
2A
COUT1
22µF
6.3V
COUT2
22µF
6.3V
FB
GND
Figure 57. ADP2302 Typical Application, VIN = 12 V, VOUT = 3.3 V, 2 A, with Programmable 7.8 V UVLO
Rev. 0 | Page 23 of 28
08833-055
CIN
10µF
25V
ADP2302/ADP2303
VIN = 12V
BST
VIN
CIN
10µF
25V
ADP2302ARDZ-5.0
EN
SW
RPGOOD
100kΩ
PGOOD
CBST
0.1µF
VOUT = 5.0V
2A
L
6.8µH
D
B330B
COUT1
22µF
16V
COUT2
22µF
16V
08833-056
FB
GND
Figure 58. ADP2302 Typical Application, VIN = 12 V, VOUT = 5 V, 2 A
VIN = 12V
VIN
BST
CBST
0.1µF
ADP2303ARDZ
EN
SW
L
2.5µH
D
SSB43L
RPGOOD
100kΩ
PGOOD
VOUT = 1.5V
3A
COUT1
47µF
6.3V
COUT2
47µF
6.3V
COUT3
47µF
6.3V
RTOP
10kΩ
1%
FB
RBOT
11.3kΩ
1%
GND
08833-057
CIN
10µF
25V
Figure 59. ADP2303 Typical Application, VIN = 12 V, VOUT = 1.5 V, 3 A
VIN = 12V
VIN
BST
CBST
0.1µF
ADP2303ARDZ
EN
SW
L
3.3µH
D
SSB43L
RPGOOD
100kΩ
PGOOD
VOUT = 1.8V
3A
COUT1
47µF
6.3V
COUT2
47µF
6.3V
COUT3
47µF
6.3V
RTOP
12.7kΩ
1%
FB
RBOT
10.2kΩ
1%
GND
Figure 60. ADP2303 Typical Application, VIN = 12 V, VOUT = 1.8 V, 3 A
VIN = 12V
VIN
BST
ADP2303ARDZ
EN
SW
RPGOOD
100kΩ
PGOOD
CBST
0.1µF
L
3.3µH
D
SSB43L
VOUT = 2.5V
3A
COUT1
47µF
6.3V
COUT2
47µF
6.3V
RTOP
21.5kΩ
1%
FB
RBOT
10.2kΩ
1%
GND
Figure 61. ADP2303 Typical Application, VIN = 12 V, VOUT = 2.5 V, 3 A
Rev. 0 | Page 24 of 28
08833-059
CIN
10µF
25V
08833-058
CIN
10µF
25V
ADP2302/ADP2303
VIN = 12V
BST
VIN
CIN
10µF
25V
CBST
0.1µF
ADP2303ARDZ-5.0
EN
SW
L
4.7µH
D
SSB43L
RPGOOD
100kΩ
PGOOD
VOUT = 5V
3A
COUT1
47µF
6.3V
08833-060
FB
GND
Figure 62. ADP2303 Typical Application, VIN = 12 V, VOUT = 5 V, 3 A
VIN = 5V
BST
VIN
ADP2302ARDZ
EN
SW
RPGOOD
100kΩ
PGOOD
CBST
0.1µF
L
3.3µH
D
B330B
VOUT = 1.2V
2A
COUT1
47µF
6.3V
COUT2
47µF
6.3V
RTOP
10kΩ
1%
FB
RBOT
20kΩ
1%
GND
Figure 63. ADP2302 Typical Application, VIN = 5V, VOUT = 1.2 V, 2 A
Rev. 0 | Page 25 of 28
08833-061
CIN
10µF
25V
ADP2302/ADP2303
OUTLINE DIMENSIONS
5.00 (0.197)
4.90 (0.193)
4.80 (0.189)
4.00 (0.157)
3.90 (0.154)
3.80 (0.150)
8
5
TOP VIEW
1
4
2.29 (0.090)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
2.29 (0.090)
6.20 (0.244)
6.00 (0.236)
5.80 (0.228)
BOTTOM VIEW
1.27 (0.05)
BSC
(PINS UP)
1.75 (0.069)
1.35 (0.053)
1.65 (0.065)
1.25 (0.049)
0.10 (0.004)
MAX
COPLANARITY
0.10
SEATING
PLANE
0.51 (0.020)
0.31 (0.012)
0.50 (0.020)
0.25 (0.010)
0.25 (0.0098)
0.17 (0.0067)
8°
0°
45°
1.27 (0.050)
0.40 (0.016)
072808-A
COMPLIANT TO JEDEC STANDARDS MS-012-A A
CONTROLLING DIMENSIONS ARE IN MILLIMETER; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 64. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP]
Narrow Body
(RD-8-1)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1
ADP2302ARDZ-R7
ADP2302ARDZ-2.5-R7
ADP2302ARDZ-3.3-R7
ADP2302ARDZ-5.0-R7
ADP2302-EVALZ
ADP2303ARDZ-R7
ADP2303ARDZ-2.5-R7
ADP2303ARDZ-3.3-R7
ADP2303ARDZ-5.0-R7
ADP2303-EVALZ
1
Output Voltage
Adjustable
2.5 V
3.3 V
5.0 V
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Adjustable
2.5 V
3.3 V
5.0 V
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Z = RoHS Compliant Part.
Rev. 0 | Page 26 of 28
Package Description
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
Evaluation Board
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
Evaluation Board
Package Option
RD-8-1
RD-8-1
RD-8-1
RD-8-1
RD-8-1
RD-8-1
RD-8-1
RD-8-1
ADP2302/ADP2303
NOTES
Rev. 0 | Page 27 of 28
ADP2302/ADP2303
NOTES
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08833-0-7/10(0)
Rev. 0 | Page 28 of 28