SC284P Dual Channel 2.5MHz, 2.0A Synchronous Buck with Automatic Power Save POWER MANAGEMENT Features Description VIN Range — 2.75 – 5.5V VOUT Selectable — 1.0 - 3.3V Up to 2A Output Current for Each Channel Package with Ultra-Small Footprint : 3 x 3 x 0.6(mm) Switching Frequency — 2.5MHz Efficiency Up to 94% High Light-load Efficiency via Automatic PSAVE Mode Low Output Noise in CCM Excellent Transient Response Start Up into Pre-Biased Output 100% Duty-Cycle Low Dropout Operation Shutdown Current — <1µA Internal Soft-Start Input Under-Voltage Lockout Output Over-Voltage, Current Limit Protection Over-Temperature Protection VOUT Further Adjustable Using External Resistors PGOOD Feature Lead-free, Halogen-free, and RoHS/WEEE Compliant The SC284P is a dual channel 2A synchronous step-down regulator designed to operate with an input voltage range of 2.75 to 5.5 Volts. Each channel offers seven pre-determined output voltages via three control pins programmable from 1.0 to 3.3 Volts. The control pins allow for on-the-fly voltage changes, enabling system designers to implement dynamic power savings. The SC284P is also capable of adjusting the output voltage via an external resistor divider. The SC284P is optimized for maximum efficiency over a wide range of load currents. During full load operation, the device operates in PWM mode with fixed 2.5MHz oscillator frequency, allowing the use of small surface mount external components. As the load decreases, the regulator will transition into Power Save mode maintaining high efficiency. Connecting CTL0 — CTL2 to logic low forces the device into shutdown mode reducing the supply current to less than 1µA. Connecting any of the control pins to logic high enables the converter and sets the output voltage according to Table 1. Other features include undervoltage lockout, soft-start to limit inrush current, and over-temperature protection. Applications Wireless Access Point/Router/Modem Femtocell Set-Top Box Point-Of-Sale Projector Typical Application Circuit VINA CINA 10µF RAVINA 1Ω CAVINA 10nF VINB CINB 10µF RAVINB 1Ω CAVINB 10nF LA 2.2µH PVINA LXA VOUTA AVINA LB 2.2µH AGNDA PVINB SC284P PGOODA Revision 2.1 COUTB 22µF VOUTA VOUTB PGNDA AVINB AGNDB CTL0A CTL1A CTL2A LXB VOUTB COUTA 22µF CTL0A CTL1A CTL2A PGOODA PGNDB CTL0B CTL1B CTL2B PGOODB © 2014 Semtech Corporation CTL0B CTL1B CTL2B PGOODB SC284P Pin Configuration PVINA LXA PGNDA VOUTA CTL2B CTL1B Ordering Information 20 19 18 17 16 1 TOP VIEW 15 CTL0B 14 PGOODB AGNDA 2 AVINA 3 13 AVINB PGOODA 4 12 AGNDB CTL0A 5 11 PVINB 6 7 8 9 10 CTL1A CTL2A VOUTB PGNDB LXB T 3 x 3 x 0.6(mm) MLPQ-UT20 θJA= 40°C/W Marking Information Device Package SC284PULTRC(1)(2) 3 x 3 x 0.6(mm) MLPQ-UT20 SC284PEVB Evaluation Board Notes: (1) Available in tape and reel only. A reel contains 3,000 devices. (2) Available in lead-free package only. Device is fully WEEE and RoHS compliant and halogen-free. Table 1 – Output Voltage Settings CTL2[A/B] CTL1[A/B] CTL0[A/B] Output Voltage 0 0 0 Disabled 0 0 1 1.0V 0 1 0 1.1V 0 1 1 1.2V 1 0 0 1.5V 1 0 1 1.8V 1 1 0 2.5V 1 1 1 3.3V 284P = Part Number Code yyww = Date Code xxxx = Semtech Lot Number SC284P Absolute Maximum Ratings Recommended Operating Conditions AVINA, AVINB, PVINA, PVINB Supply (V) . . . . . -0.3 to +6.0 VINA and VINB Supply (V) . . . . . . . . . . . . . . . . . . . . . . . 2.75 to 5.5 LXA and LXB (V). . . . . . . . . -1 to VIN +1, -3 (20ns Max), 6 Max Maximum Output Current Each Channel (A) . . . . . . . . . . 2.0 VOUTA and VOUTB (V) . . . . . . . . . . . . . . . . . . -0.3 to (VIN +0.3) CTLXA/B pins (V). . . . . . . . . . . . . . . . . . . . -0.3 to (VIN + 0.3) Peak IR Reflow Temperature (°C). . . . . . . . . . . . . . . . . . . . . 260 ESD Protection Level(2) (kV) . . . . . . . . . . . . . . . . . . . . . . . . . 3kV Output Short Circuit to GND. . . . . . . . . . . . . . . .Continuous Thermal Information Thermal Resistance, Junction to Ambient (1) (°C/W). . . . 40 Maximum Junction Temperature (°C). . . . . . . . . . . . . . . +150 Storage Temperature Range (°C). . . . . . . . . . . . . . -65 to +150 Exceeding the absolute maximum ratings may result in permanent damage to the device and/or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not recommended. Notes: (1) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards. (2) Tested according to JEDEC standard JESD22-A114-B. Electrical Characteristics Unless specified: VINA= VINB= 5.0V, VOUTA= VOUTB= 1.5V, CINA= CINB=10µF, COUTA=COUTB= 22µF, L= 2.2µH, -40°C ≤ (TA = TJ )≤ +125 °C. Unless otherwise noted typical values are TA= +25 °C. Parameter Symbol Input Voltage Range VINA/B Under-Voltage Lockout UVLO Quiescent Current Shutdown Current Soft-Start Time Output Voltage Range Output Voltage Tolerance(1) Conditions Min Typ 2.75 Rising VINA ,VINB 2.55 2.65 Max Units 5.5 V 2.75 V Hysteresis 200 mV Channel A & B, PWM mode excluding IOUT, per channel 6 mA IOUT = 0mA, CTLX = VIN 60 µA ISHDN CTL0-2= GND, Per channel 1 tSS Channel A & B; IOUT= 2A, VOUT =90% of final value 1700 IQ VOUT ΔVOUT Channel A & B; IOUT=400mA, PWM Mode 10 µA µs 1.0 3.3 -2.0 +2.0 V % PSAVE Mode 1.75 CTL Settings Regulation ΔVCTL-REG Channel A & B; Relative to VOUT at CTL=100, IOUTA=400mA; IOUTB=400mA; PWM Mode ±1 % Line Regulation ΔVLINE-REG Channel A & B; VIN= 2.75 – 5.5V; PWM Mode ±0.2 %/V Load Regulation ΔVLOAD-REG Channel A & B; VIN = 5.0V; IOUT=1mA – 2A ±0.3 %/A SC284P Electrical Characteristics (continued) Parameter Symbol Conditions Min Typ Max Units Current Limit Threshold ILIMIT Channel A & B; Peak LX current 2.25 3.0 3.75 A Oscillator Frequency fOSC Channel A & B 2.0 2.5 3.0 MHz -1 ILK(LX) Channel A & B; VIN = 5.5V; LX = 0V; CTL0-2= GND -10 LX Leakage Current(2) µA Channel A & B; VIN = 5.5V; LX = 5.0V; CTL0-2= GND 1 Foldback Holding Current ICL_HOLD Average LX Current, VOUT =1.5V 600 High Side Switch Resistance(3) RDSON_P Channel A & B; ILX= 100mA, TJ= 25 °C 95 Low Side Switch Resistance RDSON_N Channel A & B; ILX= -100mA, TJ= 25 °C 65 ICTL_ Channel A & B; CTL0-2=VIN or GND -2.0 CTLx Input High Threshold VCTLx_HI Channel A & B 1.6 CTLx Input Low Threshold VCTLx_LO Channel A & B Impedence of PGOOD Low RPGOOD_LO CTLx Input Current(2) PGOOD Threshold VPG_TH PGOOD Delay VPG_DLY 10 mA mΩ 2.0 µA V 0.4 V 8 Ω VOUT rising 90 % Asserted 2 ms PGOOD= Low 20 μs VOUT Over Voltage Protection VOVP Channel A & B 115 % Thermal Shutdown Temperature(4) TSD Channel A & B 160 °C TSD_HYS Channel A & B 10 °C Thermal Shutdown Hysteresis(4) Notes: (1) The “Output Voltage Tolerance” includes output voltage accuracy, voltage drift over temperature. (2) A negative current means the current flows from the pin and a positive current means the current flows into the pin. (3) Measured from VINA/B to LXA/B. (4) Thermal shutdown protection is independent for each channel. SC284P Typical Characteristics Circuit Conditions: CIN= 10uF/6.3V; COUT= 22uF/6.3V, Unless otherwise noted, L= 2.2uH (TOKO: 1127AS-2R2M). Efficiency vs. Load Current Total Loss (Per Channel) vs. Load Current 100 1000 TA=25℃ VIN = 5V, VOUT = 3.3V 800 VIN = 3.3V, VOUT = 1.5V 80 Loss (mW) Efficiency (%) 90 VIN = 5V, VOUT = 1.5V 70 Vin=3.3V,Vo=1.5V 600 Vin=5V,Vo=3.3V 400 200 60 Vin=5V,Vo=1.5V 0 50 0.001 0.01 0.1 1 0 10 0.5 Load Current (A) Steady State (PSAVE) Operation ( IOUT=200mA) 2.0 IOUT 2A/div ILX 500mA/div ILX 1A/div VLX 2V/div VLX 2V/div VIN = 5V VOUT = 1.5V 500ns/div 500ns/div VIN = 5V VOUT = 1.5V UVLO Hysteresis UVLO Rising Threshold 200 195 UVLO Hysteresis (mV) 2.68 Input Voltage (V) 1.5 Steady State (PWM) Operation (IOUT=2A) IOUT 200mA/div 2.70 1.0 Load Current (A) 2.66 2.64 2.62 190 185 180 175 2.60 -50 -25 0 25 50 75 Ambient Temperature (0C) 100 125 150 170 -50 -25 0 25 50 75 100 125 150 Ambient Temperature (0C) SC284P Typical Characteristics Circuit Conditions: CIN= 10uF/6.3V; COUT= 22uF/6.3V, Unless otherwise noted, L= 2.2uH (TOKO: 1127AS-2R2M). Load Regulation, Vout=1.0V Load Regulation, Vout=1.2V 1.27 1.10 1.25 Output Voltage (V) Output Voltage (V) 1.05 1250C 250C 1.00 -400C 1.22 1250C 250C -400C 1.20 1.17 0.95 1.15 1.12 0.90 0.0 0.5 1.0 1.5 0.0 2.0 0.5 1.60 1.90 1.55 1.85 Output Voltage (V) Output Voltage (V) 1.5 2.0 Load Regulation, Vout=1.8V Load Regulation, Vout=1.5V 1250C 250C 1.50 -400C 1250C 1.80 250C -400C 1.75 1.45 1.70 1.40 0.0 0.5 1.0 1.5 0.0 2.0 0.5 1.0 1.5 2.0 Load Current (A) Load Current (A) Load Regulation, Vout=2.5V Load Regulation, Vout=3.3V 2.65 3.45 2.60 3.40 Output Voltage (V) Output Voltage (V) 1.0 Load Current (A) Load Current (A) 2.55 1250C 2.50 250C -400C 2.45 3.35 1250C 3.30 250C 3.25 -400C 3.20 2.40 3.15 2.35 0.0 0.5 1.0 Load Current (A) 1.5 2.0 0.0 0.5 1.0 1.5 2.0 Load Current (A) SC284P Typical Characteristics Circuit Conditions: CIN= 10uF/6.3V; COUT= 22uF/6.3V, Unless otherwise noted, L= 2.2uH (TOKO: 1127AS-2R2M). Line Regulation, Vout=1.0V, Iout=500mA Line Regulation, Vout=1.2V, Iout=500mA 1.05 1.26 1.04 1.24 1.02 1.01 1250C 1.00 250C 0.99 -400C Output Voltage (V) Output Voltage (V) 1.03 0.98 0.97 1.22 1250C 250C 1.20 -400C 1.18 1.16 0.96 0.95 2.5 3.0 3.5 4.0 4.5 5.0 1.14 5.5 2.5 Input Voltage (V) 3.5 4.0 4.5 5.0 5.5 Inout Voltage (V) Line Regulation, Vout=1.8V, Iout=500mA Line Regulation, Vout=1.5V, Iout=500mA 1.58 1.89 1.56 1.87 1.85 1.54 1.52 Output Voltage (V) Output Voltage (V) 3.0 1250C 1.50 250C 1.48 -400C 1.83 1250C 1.81 250C 1.79 -400C 1.77 1.75 1.46 1.73 1.44 2.5 3.0 3.5 4.0 4.5 5.0 1.71 5.5 2.5 Input Voltage (V) 3.0 3.5 4.0 4.5 5.0 5.5 Input Voltage (V) Line Regulation, Vout=2.5V, Iout=500mA Line Regulation, Vout=3.3V, Iout = 500mA 3.46 2.62 3.42 3.38 Output Voltage (V) Output Voltage (V) 2.58 2.54 2.50 1250C 2.46 250C -400C 3.34 3.30 1250C 3.26 250C -400C 3.22 2.42 3.18 3.14 2.38 2.5 3.0 3.5 4.0 Input Voltage (V) 4.5 5.0 5.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Input Voltage (V) SC284P Typical Waveforms Circuit Conditions: CIN= 10uF/6.3V; COUT= 22uF/6.3V, L= 2.2uH (TOKO: 1127AS-2R2M). Start Up (Enable) (VOUT=1.5V) Start Up (Power up VIN=VCTLx) (VOUT=1.5V) VIN 5V/div VIN 2V/div VCTL 2V/div VOUT 1V/div VOUT 1V/div VIN = 5V IOUT = 0.4A to 2A 50us/div VIN = 5V IOUT = 0.4A to 2A 50us/div Start Up (Enable) (VOUT=3.3V) Start Up (Power up VIN=VCTLx) (VOUT=3.3V) VIN 5V/div VIN 2V/div VCTL 2V/div VOUT 1V/div VOUT 1V/div VIN = 5V IOUT = 2A 200us/div VIN = 5V IOUT = 2A Shutdown (Disable)(VOUT=1.5V) 200us/div Shutdown (Disable)(VOUT=3.3V) VIN 5V/div VIN 5V/div VCTL 2V/div VCTL 2V/div VOUT 1V/div VOUT 1V/div VIN = 5V ROUT = 1.65Ω(2A) 50us/div SC284P Typical Characteristics Circuit Conditions: CIN= 10uF/6.3V; COUT= 22uF/6.3V, Unless otherwise noted, L= 2.2uH (TOKO: 1127AS-2R2M). Switching Frequency Vs Temperature, Vout=1.2V 2.575 2.575 2.57 2.57 Switching Frequency (MHz) Switching Frequency (MHz) Switching Frequency Vs Temperature, Vout=1.0V 2.565 2.56 2.555 2.55 2.545 2.565 2.56 2.555 2.55 2.545 2.54 2.54 2.535 -40 -15 10 35 60 85 110 2.535 135 -40 Ambient Temperature (0C) 35 60 85 110 135 Switching Frequency Vs Temperature, Vout=1.8V 2.575 2.575 2.57 2.57 Switching Frequency (MHz) Switching Frequency (MHz) 10 Ambient Temperature (0C) Switching Frequency Vs Temperature, Vout=1.5V 2.565 2.56 2.555 2.55 2.545 2.54 2.565 2.56 2.555 2.55 2.545 2.54 2.535 -40 -15 10 35 60 85 110 2.535 135 -40 Ambient Temperature (0C) -15 10 35 60 85 110 135 Ambient Temperature (0C) Switching Frequency Vs Temperature, Vout=2.5V Switching Frequency vs Temperature, Vout=3.3V 2.575 2.575 2.57 2.57 Switching Frequency (MHz) Switching Frequency (MHz) -15 2.565 2.56 2.555 2.55 2.545 2.565 2.56 2.555 2.55 2.545 2.54 2.54 2.535 2.535 -40 -15 10 35 60 Ambient Temperature 85 (0C) 110 135 -40 -15 10 35 60 85 110 135 Ambient Temperature (0C) SC284P Typical Characteristics Circuit Conditions: CIN= 10uF/6.3V; COUT= 22uF/6.3V, Unless otherwise noted, L= 2.2uH (TOKO: 1127AS-2R2M). Switching Frequency Vs Input Voltage, Vout=1.0V Switching Frequency Vs Input Voltage, Vout=1.2V 2.65 Switching Frequency (MHz) Switching Frequency (MHz) 2.65 2.6 2.55 2.5 2.45 2.5 3 3.5 4 4.5 5 2.6 2.55 2.5 2.45 5.5 2.5 Input Voltage (V) 4 4.5 5 5.5 Switching Frequency Vs Input Voltage, Vout=1.8V 2.65 2.65 Switching Frequency (MHz) Switching Frequency (MHz) 3.5 Input Voltage (V) Switching Frequency Vs Input Voltage, Vout=1.5V 2.6 2.55 2.5 2.45 2.5 3 3.5 4 4.5 5 2.6 2.55 2.5 2.45 5.5 2.5 Input Voltage (V) 3 3.5 4 4.5 5 5.5 Input Voltage (V) Switching Frequency Vs Input Voltage, Vout=2.5V Switching Frequency vs Input Voltage, Vout=3.3V 2.65 Switching Frequency (MHz) 2.65 Switching Frequency (MHz) 3 2.6 2.55 2.5 2.6 2.55 2.5 2.45 2.45 2.5 3 3.5 4 Input Voltage (V) 4.5 5 5.5 2.5 3 3.5 4 4.5 5 5.5 Input Voltage (V) 10 SC284P Typical Waveforms Circuit Conditions: CIN= 10uF/6.3V; COUT= 22uF/6.3V, L= 2.2uH (TOKO: 1127AS-2R2M). Transient Response (Vout=1.5V, Iout=0.1A to 0.4A) Transient Response (Vout=1.5V, Iout=0.4A to 2A) VOUT 100mV/div VOUT 50mV/div ILX 200mA/div ILX 1A/div IOUT 200mA/div IOUT 1A/div VIN = 5V IOUT = 0.1A to 0.4A VIN = 5V IOUT = 0.4A to 2A 20us/div Transient Response (Vout=1.5V, Iout=0.01A to 0.1A) VOUT 50mV/div 20us/div Transient Response (Vout=3.3V, Iout=0.4A to 2A) VOUT 100mV/div ILX 1A/div ILX 500mA/div IOUT 50mA/div IOUT 200mA/div VIN = 5V IOUT = 2A 200us/div VIN = 5V IOUT = 2A Output Hard Short (VOUT=1.5V) 200us/div Output Voltage Ripple (VOUT=1.5V) VOUT 1V/div VOUT 20mV/div ILX 1A/div VIN = 5V IOUT = 500mA 50us/div VIN = 5V IOUT = 500mA 1us/div 11 SC284P Pin Descriptions Pin # Pin Name Pin Function 1 PvinA Channel A — Input supply voltage for the converter power stage and internal circuitry. 2 AGNDA Ground connection for internal circuitry — connect directly to PGNDA. 3 AVINA Power supply for internal circuitry — must be connected to PVINA using an R-C filter of 1Ω and 10nF. 4 PGOODA Power Good indicator for channel A. When the output voltage reaches the PGOODA threshold, this pin will be open drain (after the PGOOD delay), otherwise it is pulled low internally. 5 CTL0A Channel A — Control bit 0, see Table 1 for decoding. This pin has a 1 MΩ internal pull-down resistor. This resistor is switched in circuit whenever the pin voltage is below the input high threshold, or when the part is in under-voltage lockout. 6 CTL1A Channel A — Control bit 1, see Table 1 for decoding. This pin has a 1 MΩ internal pull-down resistor. This resistor is switched in circuit whenever the pin voltage is below the input high threshold, or when the part is in under-voltage lockout. 7 CTL2A Channel A — Control bit 2, see Table 1 for decoding. This pin has a 1 MΩ internal pull-down resistor. This resistor is switched in circuit whenever the pin voltage is below the input high threshold, or when the part is in under-voltage lockout. 8 VOUTB Output voltage sense pin of Channel B 9 PGNDB Channel B — Ground connection for converter power stage and internal circuitry. 10 LXB 11 PvinB Channel B — Input supply voltage for the converter power stage and internal circuitry. 12 AGNDB Ground connection for internal circuitry — connect directly to PGNDB. 13 AVINB Power supply for internal circuitry — must be connected to PVINB using an R-C filter of 1Ω and 10nF. 14 PGOODB Power Good indicator for channel B. When the output voltage reaches the PGOODB threshold, this pin will be open drain (after the PGOOD delay), otherwise it is pulled low internally. 15 CTL0B Channel B — Control bit 0, see Table 1 for decoding. This pin has a 1 MΩ internal pulld-own resistor. This resistor is switched in circuit whenever the pin voltage is below the input high threshold, or when the part is in under-voltage lockout. 16 CTL1B Channel B — Control bit 1 - see Table 1 for decoding. This pin has a 1 MΩ internal pull-down resistor. This resistor is switched in circuit whenever the pin voltage is below the input high threshold, or when the part is in under-voltage lockout. 17 CTL2B Channel B — Control bit 2, see Table 1 for decoding. This pin has a 1 MΩ internal pull-down resistor. This resistor is switched in circuit whenever the pin voltage is below the input high threshold, or when the part is in under-voltage lockout. 18 VOUTA Output voltage sense pin of Channel A 19 PGNDA Channel A — Ground connection for converter power stage and internal circuitry. 20 LXA Switching node of Channel A — connect an inductor between this pin and the output capacitor. PAD Thermal pad for heatsinking purposes. Switching node of Channel B — connect an inductor between this pin and the output capacitor. 12 SC284P Block Diagram Current Amp AVINA 1 PVINA 20 LXA 19 PGNDA 11 PVINB 10 LXB 9 PGNDB 3 Plimit Amp Oscillator and Slope Generator Control Logic VOUTA 18 CTL0A 5 CTL1A 6 CTL2A 7 AGNDA 2 PGOODA 500mV Ref Voltage Select PWM Comp Error Amp PSAVE Comp PGOOD Detector Delay 4 Current Amp AVINB 13 Plimit Amp Oscillator and Slope Generator VOUTB CTL0B 8 15 CTL1B 16 CTL2B 17 AGNDB 12 PGOODB Control Logic 14 Voltage Select 500mV Ref Error Amp PWM Comp PSAVE Comp PGOOD Detector Delay 13 SC284P Applications Information Detailed Description enough in value for the current through the resistor chain The SC284P is a two channel synchronous step-down converter. Both channels of this device are designed to operate at a fixed-frequency of 2.5MHz in CCM and provide the same current capacity of up to 2A. The switching frequency is chosen to minimize the size of the external inductor and capacitors while maintaining high efficiency. Both channels of SC284P are independent. to be at least 20µA in order to ignore the VOUT pin current. Operation CFF is needed to maintain good transient response performance. The correct value of CFF can be found using the following equation. During normal operation, the PMOS FET is activated on each rising edge of the internal oscillator. The voltage feedback loop uses an internal feedback resistor divider. The period is set by the internal oscillator. The device has an internal synchronous NMOS rectifier and does not where VOSTD is the pre-determined output voltage via the CTL pins. require a Schottky diode on the LX pin. Programmable Output Voltage Both channels on SC284P have seven pre-determined output voltage values which can be individually selected by programming the CTL input pins (see Table 1 — Output Voltage Settings). Each CTL pin has an active 1 MΩ internal pull-down resistor. The 1MΩ resistor is switched in circuit whenever the CTL input voltage is below the input threshold, or when the part is in under-voltage lockout. It is recommended to tie all high CTL pins together and use an external pull-up resistor to VIN if there is no enable signal, or if the enable input is an open drain/collector signal. The CTL pins may be driven by a microprocessor to allow dynamic voltage adjustment for systems that reduce the supply voltage when entering sleep states. Avoid all zeros being present on the CTL pins when changing programmable output voltages as this would momentarily disable the device. SC284P is also capable of regulating a different (higher) output voltage, which is not shown in the Table 1, via an external resistor divider. There will be a typical 2µA current flowing into the VOUT pin. The typical schematic for an adjustable output voltage option from the standard 1.0V with CTLX=[001], is shown in Figure 1. RFB1A/B and RFB2A/B are used to adjust the desired output voltage. If the RFB2A/B current To simplify the design, it is recommended to program the desired output voltage from a standard 1.0V as shown in Figure 1 with the correct CFF calculated from Equation 2. For programming the output voltage from other standard voltages, RFB1, RFB2 and CFF need to be adjusted to meet Equations 1 and 2. VINA RAVINA 1Ω CINA 10µF CAVINA 0.1µF SC284P AGNDA CINB 10µF CAVINB 0.1µF PGOODA Enable A RFB1A VOUTA PVINB Enable B CFFA COUTA RFB1A = (VOUTA-1) x RFB2A for CTLAX = 0010 (1.0V) L VOUTB LXB RFB1B PGOODA CFFB COUTB CTL3A CTL2A VOUTB CTL1A PGOODB RFB2A 10kΩ AVINB AGNDB VOUTA LXA AVINA VINB RAVINB 1Ω L PVINA PGOODB PGNDA RFB2B 10kΩ RFB1B = (VOUTB-1) x RFB2B for CTLBX = 0010 (1.0V) CTL3B CTL2B CTL1B PGNDB Figure 1 — Output Voltage Programming is such that the 2µA VOUT pin current can be ignored, then RFB1A/B can be found by the next equation. RFB2A/B need to be low 14 SC284P Power Save Mode Operation When the load current decreases below the PSAVE threshold, PWM switching stops and the device automatically enters PSAVE mode. This threshold varies depending upon the input voltage and the output voltage setting, optimizing efficiency for all possible load currents in PWM or PSAVE mode. While in PSAVE mode, output voltage regulation is controlled by a series of switching bursts. During a burst, the inductor current is limited to a peak value which controls the on-time of the PMOS switch. After reaching this peak, the PMOS switch is disabled and the inductor current decreases to near 0mA. Switching bursts continue until the output voltage climbs to VOUT +2.5% or until the PSAVE current limit is reached. Switching is then stopped to eliminate switching losses, enhancing overall efficiency. Switching resumes when the output voltage reaches the lower threshold of VOUT and continues until the upper threshold again is reached. Note that the output voltage is regulated hysteretically while in PSAVE mode between VOUT and VOUT + 2.5%. The period and duty cycle while in PSAVE mode are solely determined by VIN and VOUT until PWM mode resumes. This can result in the switching frequency being much lower than the PWM mode frequency. If the output load current increases enough to cause VOUT to decrease below the PSAVE exit threshold (VOUT-4%), the device automatically exits PSAVE and operates in continuous PWM mode. Note that the PSAVE high and low threshold levels are both set at or above VOUT to minimize undershoot when the SC284P exits PSAVE mode and returns to PWM mode. Load (IOUT) V O U T + 2 .5 % Maximum Power Dissipation Each channel of SC284P has its own ΘJA of 40°C/W when only one channel is in operation. Since both channels are within the same package, please make sure to use both channels for power calculations. To guarantee an operating junction temperature of less than 125°C, Figure 3 shows the maximum allowable power loss for each channel. The curve is based upon the junction temperature of either channel reaching a maximum of 125°C. Each channel of SC284P can support up to 2A load current. 2.8 2.6 2.4 2.2 2 T A = 25 °C 1.8 1.6 1.4 1.2 1 0.8 0.6 T A = 85 °C T A = 55 °C 0.4 0.2 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 Loss of Channel A (W) 2.2 2.4 2.6 2.8 Figure 3 — Maximum allowable loss for each channel for a maximum junction temperature of 125°C BURST VLX PW M M ode at M e d iu m /H ig h Load PGOOD is an open-drain output. When the output voltage drops below nominal voltage, the PGOOD pin is pulled low after a 20μs delay. During start-up, PGOOD will be asserted 1.7ms (typ.) after the output voltage reaches 90% of the final regulation voltage.Over voltage, fold-back current limit and thermal shutdown will force PGOOD low after a 20μs delay. When recovering from a fault, PGOOD will be asserted 1.7ms (typ.) after Vout reaches 90% of the final regulation voltage. OFF VOUT V OUT - 4% Power Good Loss of Channel B (W) Applications Information (continued) PSAVE E X IT PSAVE M ode at L ig h t L o a d T im e PW M M ode at M e d iu m /H ig h Load Figure 2 - Transitions Between PWM and PSAVE Modes 15 SC284P Applications Information (continued) Protection Features Soft-Start The SC284P provides the following protection features: Current Limit Over-Voltage Protection Soft-Start Thermal Shutdown Soft-start is activated once VIN reaches the UVLO and one or more CTL pins are set high to enable the part. A thermal shutdown event will also activate the soft-start sequence. Soft-start controls the maximum current during startup thus limiting inrush current. The PMOS current limit is stepped through four soft-start levels of approximately 20%, 25%, 40%, & 100%. Each step is maintained for 400μs following an internal reference start up duration of 100μs giving a total nominal startup period of 1700μs. During startup, the chip operates by controlling the inductor current swings between 0A and current limit. If at any time VOUT reaches 86% of the target or at the end of the softstart period, the SC284P will switch to PWM mode operation. • • • • Current Limit The internal PMOS power device in the switching stage is protected by a current limit feature. If the inductor current is above the PMOS current limit for 16 consecutive cycles, the part enters foldback current limit mode and the output current is limited to the current limit holding current (ICL_HOLD) of a few hundred milliampere. Under this condition, the output voltage will be the product of ICL_HOLD and the load resistance. The current limit holding current will decrease when the output voltage increases. The load presented must fall below the current limit holding current for the part to exit foldback current limit mode. Figure 4 shows how the typical current limit holding current varies with output voltage. The SC284P is capable of sustaining an indefinite short circuit without damage and will resume normal operation when the fault is removed. The foldback current limit mode is disabled during soft-start. When all CTL pins of a channel are low, the corresponding channel will be disabled, drawing less than 1μA from that input power supply. The internal switches and bandgap voltage will be immediately turned off. The device has a thermal shutdown feature to protect the SC284P if the junction temperature exceeds 160°C. During thermal shutdown, the on-chip power devices are disabled, tri-stating the LX output. When the temperature drops by 10°C, it will initiate a soft-start cycle to resume normal operation. 300 TA= 25°C Current Limit Holding Current (mA) Shut Down Thermal Shutdown Current Limit Holding Current over Vout 250 The SC284P is capable of starting up into a pre-biased output. VIN= 3.6V VIN= 5.0V 200 150 Inductor Selection 100 VIN= 3.3V 50 0 1.0 1.5 2.0 2.5 3.0 3.5 Output Voltage (V) Figure 4— Typical Current Limit Holding Current vs. Output Voltage Over-Voltage Protection In the event of a 15% over-voltage on the output, the PWM drive is disabled leaving the LX pin floating. The SC284P converter has internal loop compensation. The compensation is designed to work with an output filter corner frequency of less than 40kHz for a VIN of 5V and 50KHz for a VIN of 3.3V over any operating condition. The corner frequency of the output filter is shown in the following equation. 1 fC 2S L u C OUT Values outside this range may lead to instability, malfunction, or out-of-specification performance. 16 SC284P Applications Information (continued) In general, the inductance is chosen by making the inductor ripple current to be less than 30% of maximum load current. When choosing an inductor, it is important to consider the change in inductance with DC bias current. The inductor saturation current is specified as the current at which the inductance drops a specific percentage from the nominal value. This is approximately 30%. Except for short-circuit or other fault conditions, the peak current must always be less than the saturation current specified by the manufacturer. The peak current is the maximum load current plus one half of the inductor ripple current at the maximum input voltage. Load and/or line transients can cause the peak current to exceed this level for short durations. Maintaining the peak current below the inductor saturation specification keeps the inductor ripple current and the output voltage ripple at acceptable levels. Manufacturers often provide graphs of actual inductance and saturation characteristics versus applied inductor current. The saturation characteristics of the inductor can vary significantly with core temperature. Core and ambient temperatures should be considered when examining the core saturation characteristics. When the inductance has been determined, the DC resistance (DCR) must be examined. The efficiency that can be achieved is dependent upon the DCR of the inductor. Lower values give higher efficiency. The RMS DC current rating of the inductor is associated with losses in the copper windings and the resulting temperature rise of the inductor. This is usually specified as the current which produces a 40˚C temperature rise. Most copper windings are rated to accommodate this temperature rise above maximum ambient. Magnetic fields associated with the output inductor can interfere with nearby circuitry. This can be minimized by the use of low noise shielded inductors which use the minimum gap possible to limit the distance that magnetic fields can radiate from the inductor. However shielded inductors typically have a higher DCR and are thus less efficient than a similarly sized non-shielded inductor. Final inductor selection depends upon various design considerations such as efficiency, EMI, size, and cost. Table 2 lists the manufacturers of recommended inductor options. The saturation characteristics and DC current ratings are also shown. Manufacturer Part Number L (μH) DCR Max (Ω) Rated Current (A) L at Rated Current (μH) Dimensions LxWxH (mm) TOKO 1071AS-1R0N 1.00±30% 0.040 2.70 0.70 2.8x3.0x1.5 TOKO 1127AS-2R2M 2.20±20% 0.048 2.50 1.54 3.5x3.7x1.8 Panasonic ELLVGG1R0N 1.00±23% 0.062 2.20 0.70 3.2x3.2x1.5 Table 2 – Recommended Inductors COUT Selection The internal voltage loop compensation in the SC284P limits the minimum output capacitor value to 22µF if using a 2.2µH inductor or 44µF if using a 1µH inductor. This is due to its influence on the the loop crossover frequency, phase margin, and gain margin. The total output capacitance should not exceed 50µF to avoid any start-up problems. For most typical applications it is recommended to use an output capacitance of 22µF to 44µF. When choosing the output capacitor’s capacitance, verify the voltage derating effect from the capacitor vendor’s data sheet. Capacitors with X7R or X5R ceramic dielectric are recommended for their low ESR and superior temperature and voltage characteristics. Y5V capacitors should not be used as their temperature coefficients make them unsuitable for this application. The output voltage droop due to a load transient is determined by the capacitance of the ceramic output capacitor. The ceramic capacitor supplies the load current initially until the loop responds. Within a few switching cycles the loop will respond and the inductor current will increase to match the required load. The output voltage droop during the period prior to the loop responding can be related to the choice of output capacitor by the relationship from the following equation. & 287 u ',/2$' 9'5223 u I26& The output capacitor RMS ripple current may be calculated 17 SC284P Applications Information (continued) from the following equation. ,&287 506 § 9287 u 9,10$; 9287 · ¸¸ ¨¨ / u I26& u 9,1 ¹ © Table 3 lists the manufac turers of recommended capacitor options. Type Rated Voltage (VDC) Value at 3.3V (μF) Dimensions LxWxH (mm) 10±10% X5R 6.3 4.74 2.0x1.25x1.25 (EIA:0805) Murata GRM219R60J106K 10±10% X5R 6.3 4.05 2.0x1.25x0.85 (EIA:0805) Murata GRM21BR60J226M 22±20% X5R 6.3 6.57 2.0x1.25x1.25 (EIA:0805) Murata GRM31CR60J476M 47±20% X5R 6.3 20.3 3.2x1.6x1.6 (EIA:1206) Manufacturer Part Nunber Value (μF) Murata GRM21BR60J106K ,&,1506 9287 9,1 § 9 ¨¨ 287 9,1 © · ¸¸ ¹ The input voltage ripple and RMS current ripple are at a maximum when the input voltage is twice the output voltage or 50% duty cycle. The input capacitor provides a low impedance loop for the edges of pulsed current drawn by the PMOS switch. Low ESR/ESL X5R ceramic capacitors are recommended for this function. To minimize stray inductance, the capacitor should be placed as close as possible to the VIN and GND pins of the SC284P. Table 3 – Recommended Capacitors CIN Selection The SC284P source input current is a DC supply current with a triangular ripple imposed on it. To prevent large input voltage ripple, a low ESR ceramic capacitor is required. A minimum value of 10μF should be used. It is important to consider the DC voltage coefficient characteristics when determining the actual required value. It should be noted a 10µF, 6.3V, X5R ceramic capacitor with 5V DC applied may exhibit a capacitance as low as 4.05µF. To estimate the required input capacitor, determine the acceptable input ripple voltage and calculate the minimum value required for CIN as shown by the following equation. &,1 § · 9 ¨¨ 287 ¸¸ 9 ,1 ¹ © § '9 · ¨¨ (65 ¸¸ u I26& ¹ © ,287 9287 9,1 The input capacitor RMS ripple current varies with the input and output voltage. The maximum input capacitor RMS current is found from the next equation . 18 SC284P Applications Information (continued) J 6WDJH 6WDJH Stages K 6 6WDJH 7 M 8 Conditions J K L M L Operation description Normal PWM operation Overload protection is enabled and peak current limit at 100% level Cycle by cycle peak current limit OCP protection is activated. Foldback peak current limit. PWM "ON" when inductor current of 0A PWM "OFF" when inductor current hits peak current limit of foldback mode. Operation description Inductor current hits peak current limit Peak current limit for 16 consecutive cycles Vout ≥ 100% target Inductor current doesn't hit peak current limit Figure 5 — Current Limit Protection Stages 0 1 2 % 6WDJH $ 6WDJH 6WDJH 3 & * ) 4 + 6WDJH 5 ' 6WDJH , 6WDJH ( 6WDJH 6 Conditions A B C D E F G H I Operation description Chip is OFF. Peak current limit at 20% level PW M "ON" when inductor current of 0A PW M "OFF" when inductor current hits peak current limit Stage duration of 400µs Peak current limit at 25% level PW M "ON" when inductor current of 0A PW M "OFF" when inductor current hits peak current limit Stage duration of 400µs Peak current limit at 40% level PW M "ON" when inductor current of 500mA PW M "OFF" when inductor current hits peak current limit Stage duration of 400µs Peak current limit at 100% level PW M "ON" when inductor current of 500mA PW M "OFF" when inductor current hits peak current limit Stage duration of 400µs Peak current limit at 100% level Switch to closed-loop PW M operation. Soft Start ends. Normal PW M operation Overload protection is enabled Operation description VIN > UVLO Threshold AND One or more CTL pin is high. AND Internal reference is ready. End of stage 1 AND Vout<86% of target End of stage 2 AND Vout<86% of target End of stage 3 AND Vout<86% of target End of stage 4 AND Vout<86% of target Vout>86% of target Vout>86% of target Vout>86% of target End of soft start time of 1700µs Figure 6 — Soft Start Operation 19 SC284P Applications Information (continued) PCB Layout Considerations The layout diagram in Figure 7 shows a recommended PCB top layer for the SC284P and supporting components. Figure 8 shows the bottom layer for this PCB. Fundamental layout rules must be followed since the layout is critical for achieving the performance specified in the Electrical Characteristics table. Poor layout can degrade the performance of the DC-DC converter and can contribute to EMI problems, ground bounce, and resistive voltage losses. Poor regulation and instability can result. The following guidelines are recommended when developing a PCB layout: . The input capacitor, CIN, should be placed as close to the VIN and PGND pins as possible. This capacitor provides a low impedance loop for the pulsed currents present at the buck converter’s input. Use short wide traces to connect as closely to the IC as possible. This will minimize EMI and input voltage ripple by localizing the high frequency current pulses. 2. Keep the LX pin traces as short as possible to minimize pickup of high frequency switching edges to other parts of the circuit. COUT and L should be connected as close as possible between the LX and PGND pins, with a direct return to the PGND pin from COUT. 3. Route the output voltage feedback/sense path away from the inductor and LX node to minimize noise and magnetic interference. 4. Use a ground plane referenced to the SC284P PGND pin. Use several vias to connect to the component side ground to further reduce noise and interference on sensitive circuit nodes. 5. If possible, minimize the resistance from the output and PGND pin to the load. This will reduce the voltage drop on the ground plane and improve the load regulation. It will also improve the overall efficiency by reducing the copper losses on the output and ground planes. 6. Connect the AGND pins to the thermal pad. Figure 7 — Recommended PCB Layout (Top Layer) Figure 8 — PCB Bottom Layer C5 U1 L2 U1 R1 C1 C3 U1 U1 U1 U1 C4 C2 R2 U1 U1 U1 C6 U1 L1 U1 Figure 9 — Recommended PCB Layout (Top Layer Details) 20 SC284P Outline Drawing – 3x3 MLPQ-UT20 Land Pattern – 3x3 MLPQ-UT20 21 SC284P © Semtech 2014 All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. Semtech assumes no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified range. SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTEDTO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF SEMTECH PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER’S OWN RISK. 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