Ultrafast 3.3 V/5 V Single-Supply SiGe Comparators ADCMP572/ADCMP573 3.3 V/5.2 V single-supply operation 150 ps propagation delay 15 ps overdrive and slew rate dispersion 8 GHz equivalent input rise time bandwidth 80 ps minimum pulse width 35 ps typical output rise/fall 10 ps deterministic jitter (DJ) 200 fs random jitter (RJ) On-chip terminations at both input pins Robust inputs with no output phase reversal Resistor-programmable hysteresis Differential latch control Extended industrial −40°C to +125°C temperature range FUNCTIONAL BLOCK DIAGRAM VCCI VCCO VTP TERMINATION VP NONINVERTING INPUT VN INVERTING INPUT Q OUTPUT ADCMP572 ADCMP573 CML/ RSPECL Q OUTPUT VTN TERMINATION LE INPUT HYS LE INPUT 04409-025 FEATURES Figure 1. APPLICATIONS Clock and data signal restoration and level shifting Automatic test equipment (ATE) High speed instrumentation Pulse spectroscopy Medical imaging and diagnostics High speed line receivers Threshold detection Peak and zero-crossing detectors High speed trigger circuitry GENERAL DESCRIPTION The ADCMP572 and ADCMP573 are ultrafast comparators fabricated on Analog Devices’ proprietary XFCB3 Silicon Germanium (SiGe) bipolar process. The ADCMP572 features CML output drivers and latch inputs, and the ADCMP573 features reduced swing PECL (RSPECL) output drivers and latch inputs. Both devices offer 150 ps propagation delay and 80 ps minimum pulse width for 10 Gbps operation with 200 fs rms random jitter (RJ). Overdrive and slew rate dispersion are typically less than 15 ps. A flexible power supply scheme allows both devices to operate with a single 3.3 V positive supply and a −0.2 V to +1.2 V input signal range or with split input/output supplies to support a wider −0.2 V to +3.2 V input signal range and an independent range of output levels. 50 Ω on-chip termination resistors are provided at both inputs with the optional capability to be left open (on an individual pin basis) for applications requiring high impedance inputs. The CML output stage is designed to directly drive 400 mV into 50 Ω transmission lines terminated to between 3.3 V to 5.2 V. The RSPECL output stage is designed to drive 400 mV into 50 Ω terminated to VCCO − 2 V and is compatible with several commonly used PECL logic families. The comparator input stage offers robust protection against large input overdrive, and the outputs do not phase reverse when the valid input signal range is exceeded. High speed latch and programmable hysteresis features are also provided. The ADCMP572 and ADCMP573 are available in a 16-lead LFCSP package and have been characterized over an extended industrial temperature range of −40°C to +125°C. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. ADCMP572/ADCMP573 TABLE OF CONTENTS Electrical Characteristics ................................................................. 3 Using/Disabling the Latch Feature..............................................9 Absolute Maximum Ratings............................................................ 5 Optimizing High Speed Performance ..................................... 10 Thermal Considerations.............................................................. 5 Comparator Propagation Delay Dispersion ........................... 10 ESD Caution.................................................................................. 5 Comparator Hysteresis .............................................................. 11 Pin Configuration and Function Descriptions............................. 6 Minimum Input Slew Rate Requirements .............................. 11 Typical Performance Characteristics ............................................. 7 Typical Application Circuits.......................................................... 12 Application Information.................................................................. 9 Timing Information ....................................................................... 13 Power/Ground Layout and Bypassing ....................................... 9 Outline Dimensions ....................................................................... 14 CML/RSPECL Output Stage ....................................................... 9 Ordering Guide .......................................................................... 14 REVISION HISTORY 4/05—Revision 0: Initial Version Rev. 0 | Page 2 of 16 ADCMP572/ADCMP573 ELECTRICAL CHARACTERISTICS VCCI = VCCO = 3.3 V, TA = −40°C to +125°C, typical at TA = +25°C, unless otherwise noted. Table 1. Parameter DC INPUT CHARACTERISTICS Input Voltage Range Input Differential Voltage Input Offset Voltage Offset Voltage Tempco Input Bias Current Input Bias Current Tempco Input Offset Current Input Impedance Input Resistance, Differential Input Resistance, Common-Mode Active Gain Common-Mode Rejection Power Supply Rejection—VCCI Hysteresis LATCH ENABLE CHARACTERISTICS ADCMP572 Latch Enable Input Range Latch Enable Input Differential Latch Setup Time Latch Hold Time ADCMP573 Latch Enable Input Range Latch Enable Input Differential Latch Setup Time Latch Hold Time Latch Enable Input Impedance Latch to Output Delay Latch Minimum Pulse Width DC OUTPUT CHARACTERISTICS ADCMP572 (CML) Output Impedance Output Voltage High Level Output Voltage Low Level Output Voltage Differential ADCMP573 (RSPECL) Output Voltage High −40°C Output Voltage High +25°C Output Voltage High +125°C Output Voltage Low −40°C Output Voltage Low +25°C Output Voltage Low +125°C Output Voltage Differential Symbol Conditions Min VP, VN VCCI = 3.3 V, VCCO = 3.3 V VCCI = 5.2 V, VCCO = 3.3 V −0.2 −0.2 −1.2 −5.0 VOS ∆VOS/dT IP, IN Open termination −50.0 Open termination Open termination AV CMRR PSRVCCI VCCI = 3.3 V, VCCO = 3.3 V, VCM = 0.0 V to 1.0 V VCCI = 5.2 V, VCCO = 3.3 V, VCM = 0.0 V to 3.0 V VCCI = 3.3 V ± 5%, VCCO = 3.3 V RHYS = ∞ 2.8 0.2 tS tH VOD = 100 mV VOD = 100 mV 1.8 0.2 Typ ±2.0 10.0 −25.0 50.0 ±2.0 50 50 500 54 65 Max Unit +1.2 +3.1 +1.2 +5.0 V V V mV µV/°C µA nA/°C µA Ω kΩ kΩ dB dB 0.0 65 dB 74 ±1 dB mV 0.4 15 5 0.4 90 100 50.0 150 100 VCCO + 0.2 0.5 V V ps ps VCCO − 0.6 0.5 V V ps ps Ω ps ps tS tH VOD = 100 mV VOD = 100 mV tPLOH, tPLOL tPL VOD = 100 mV VOD = 100 mV ZOUT VOH VOL −8 mA < IOUT < 8 mA 50 Ω terminate to VCCO 50 Ω terminate to VCCO 50 Ω terminate to VCCO VCCO − 0.10 VCCO − 0.60 300 50.0 VCCO − 0.05 VCCO − 0.45 375 VCCO VCCO − 0.30 450 Ω V V mV VOH VOH VOH VOL VOL VOL 50 Ω terminate to VCCO − 2.0 50 Ω terminate to VCCO − 2.0 50 Ω terminate to VCCO − 2.0 50 Ω terminate to VCCO − 2.0 50 Ω terminate to VCCO − 2.0 50 Ω terminate to VCCO − 2.0 50 Ω terminate to VCCO − 2.0 VCCO − 1.14 VCCO − 1.10 VCCO − 1.04 VCCO − 1.54 VCCO − 1.50 VCCO − 1.44 300 VCCO − 1.02 VCCO − 0.98 VCCO − 0.92 VCCO − 1.39 VCCO − 1.35 VCCO − 1.29 375 VCCO − 0.90 VCCO − 0.86 VCCO − 0.80 VCCO − 1.24 VCCO − 1.20 VCCO − 1.14 450 V V V V V V mV Rev. 0 | Page 3 of 16 ADCMP572/ADCMP573 Parameter AC PERFORMANCE Propagation Delay Propagation Delay Tempco Prop Delay Skew—Rising Transition to Falling Transition Overdrive Dispersion Symbol Conditions tPD VCCI = 3.3 V, VOD = 200 mV VCCI = 3.3 V, VOD = 20 mV VCCI = 5.2 V, VOD = 200 mV ∆tPD/dT VOD = 200 mV, 5 V/ns Slew Rate Dispersion Pulse Width Dispersion 10% – 90% Duty Cycle Dispersion Common-Mode Dispersion Equivalent Input Bandwidth1 Toggle Rate Deterministic Jitter RMS Random Jitter Minimum Pulse Width Rise Time Fall Time POWER SUPPLY Input Supply Voltage Range Output Supply Voltage Range Positive Supply Differential ADCMP572 (CML) Positive Supply Current Device Power Dissipation ADCMP573 (RSPECL) Positive Supply Current Device Power Dissipation 1 Min BWEQ DJ RJ PWMIN PWMIN tR tF 50 mV < VOD < 0.2 V, 5 V/ns 10 mV < VOD < 0.2 V, 5 V/ns 2 V/ns to 10 V/ns, 250 mV OD 100 ps to 5 ns, 250 mV OD VCCI = 3.3 V, 1 V/ns, 250 mV OD VCCI = 5.2 V, 1 V/ns, 250 mV OD VOD = 0.2V, 0.0 V < VCM < 2.9 V 0.0 V to 250 mV input tR = tF = 17 ps, 20/80 >50% Output Swing VOD = 200 mV, 5 V/ns, PRBS31 − 1 NRZ, 4 Gbps VOD = 200 mV, 5 V/ns, PRBS31 − 1 NRZ, 10 Gbps VOD = 200 mV, 5 V/ns, 1.25 GHz ∆tPD/∆PW < 5 ps, 200 mV OD ∆tPD/∆PW < 10 ps, 200 mV OD 20/80 20/80 VCCI VCCO VCCI −VCCO IVCCI + IVCCO PD IVCCI + IVCCO PD Typ Max Unit 150 165 145 0.5 10 ps ps ps ps/°C ps 15 15 15 5 5 10 5 8.0 ps ps ps ps ps ps/V GHz 12.5 10 Gbps ps 20 ps 0.2 100 80 35 35 ps ps ps ps ps 3.1 3.1 −0.2 5.4 5.4 +2.3 V V V mA VCCI = 3.3 V, VCCO = 3.3 V, terminate 50 Ω to VCCO VCCI = 5.2 V, VCCO = 5.2 V, terminate 50 Ω to VCCO VCCI = 3.3 V, VCCO = 3.3 V, terminate 50 Ω to VCCO VCCI = 5.2 V, VCCO = 5.2 V, terminate 50 Ω to VCCO 44 52 44 52 140 165 230 265 VCCI = 3.3 V, VCCO = 3.3 V, 50 Ω to VCCO − 2 V VCCI = 5.2 V, VCCO = 5.2 V, 50 Ω to VCCO − 2V VCCI = 3.3 V, VCCO = 3.3 V, 50 Ω to VCCO − 2 V VCCI = 5.2 V, VCCO = 5.2 V, 50 Ω to VCCO − 2 V 62 80 64 80 110 160 146 230 mW mA mW Equivalent input bandwidth assumes a simple first-order response and is calculated with the following formula: BWEQ = 0.22/√(trCOMP2−trIN2), where trIN is the 20/80 transition time of a quasi-Gaussian signal applied to the comparator input, and trCOMP is the effective transition time digitized by the comparator. Rev. 0 | Page 4 of 16 ADCMP572/ADCMP573 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter SUPPLY VOLTAGE Input Supply Voltage (VCCI to GND) Output Supply Voltage (VCCO to GND) Positive Supply Differential (VCCI − VCCO) INPUT VOLTAGE Input Voltage Differential Input Voltage Input Voltage, Latch Enable HYSTERESIS CONTROL PIN Applied Voltage (HYS to GND) Maximum Input/Output Current OUTPUT CURRENT ADCMP572 (CML) ADCMP573 (RSPECL) TEMPERATURE Operating Temperature, Ambient Operating Temperature, Junction Storage Temperature Range Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rating −0.5 V to +6.0 V −0.5 V to +6.0 V −0.5 V to +3.5 V −0.5 V to VCCI + 0.5 V ±(VCCI + 0.5 V) −0.5 V to VCCO + 0.5 V THERMAL CONSIDERATIONS The ADCMP572/ADCMP573 LFCSP 16-lead package has a θJA (junction-to-ambient thermal resistance) of 70°C/W in still air. −0.5 V to +1.5 V ±1 mA ±20 mA −35 mA −40°C to +125°C +150°C −65°C to +150°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 5 of 16 ADCMP572/ADCMP573 GND GND 16 HYS VCCI PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 15 14 13 PIN1 VTP 1 12 VCCO ADCMP572 ADCMP573 VP 2 VN 3 11 Q 10 Q TOP VIEW (Not to Scale) VTN 4 8 VCCO/VTT 04409-026 7 LE VCCI 6 LE 9 VCCO 5 Figure 2. ADCMP572/ADCMP573 Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 2 3 4 5, 16 6 Mnemonic VTP VP VN VTN VCCI LE 7 LE 8 VCCO/VTT 9, 12 13, 15 10 VCCO GND Q 11 Q 14 HYS Isolated Heat sink N/C Description Termination Resistor Return Pin for VP Input. Noninverting Analog Input. Inverting Analog Input. Termination Resistor Return Pin for VN Input. Positive Supply Voltage for Input Stage. Latch Enable Input Pin, Inverting Side. In compare mode (LE = low), the output tracks changes at the input of the comparator. In latch mode (LE = high), the output reflects the input state just prior to the comparator’s being placed into latch mode. LE must be driven in complement with LE. Latch Enable Input Pin, Noninverting Side. In compare mode (LE = high), the output tracks changes at the input of the comparator. In latch mode (LE = low), the output reflects the input state just prior to the comparator’s being placed into latch mode. LE must be driven in compliment with LE. Termination Return Pin for the LE/LE Input Pins. For the ADCMP572 (CML output stage), this pin is internally connected to and also should be externally connected to the positive VCCO supply. For the ADCMP573 (RSPECL output stage), this pin should normally be connected to the VCCO – 2 V termination potential. Positive Supply Voltage for the CML/RSPECL Output Stage. Ground. Inverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN, provided the comparator is in compare mode. See the LE/LE descriptions (Pins 6 and 7) for more information. Noninverting Output. Q is at logic high if the analog voltage at the noninverting input VP is greater than the analog voltage at the inverting input, VN, provided the comparator is in compare mode. See the LE/LE descriptions (Pins 6 and 7) for more information. Hysteresis Control Pin. Leave this pin disconnected for zero hysteresis. Connect to GND with a suitably sized resistor to add the desired amount of hysteresis. Refer to Figure 7 for proper sizing of RHYS hysteresis control resistor. The metallic back surface of the package is not electrically connected to any part of the circuit, and it can be left floating for best electrical isolation between the package handle and the substrate of the die. However, it can be soldered to the application board if improved thermal and/or mechanical stability is desired. Rev. 0 | Page 6 of 16 ADCMP572/ADCMP573 TYPICAL PERFORMANCE CHARACTERISTICS VCCI = VCCO = 3.3 V, TA = 25°C, unless otherwise noted. 39.0 38.5 RISE/FALL TIME (ps) 15 10 38.0 37.5 37.0 5 0 0 50 100 150 200 250 INPUT OVERDRIVE VOLTAGE (mV) 36.0 –60 0 20 40 60 80 100 Figure 6. Rise/Fall Time vs. Temperature 158.5 60 158.0 50 157.5 HYSTERESIS (mV) 157.0 156.5 40 30 20 156.0 10 0.2 0.4 0.6 0.8 1.0 1.2 INPUT COMMON-MODE VOLTAGE (V) 0 0 1 2 3 4 5 04409-043 0 04409-040 155.5 6 RHYS (kΩ) Figure 4. Propagation Delay vs. Input Common-Mode Figure 7. Hysteresis vs. RHYS Control Resistor 160 80 70 156 60 HYSTERESIS (mV) 158 154 152 150 50 40 30 20 148 –40 –20 0 20 40 60 80 TEMPERATURE (°C) 100 04409-041 10 146 –60 Figure 5. Propagation Delay vs. Temperature 0 –600 04409-047 PROPAGATION DELAY (ps) –20 TEMPERATURE (°C) Figure 3. Propagation Delay vs. Input Overdrive PROPAGATION DELAY (ps) –40 04409-042 36.5 04409-039 PROPAGATION DELAY ERROR (ps) 20 –500 –400 –300 –200 RHYS SINK CURRENT (µA) Figure 8. Hysteresis vs. RHYS Sink Current Rev. 0 | Page 7 of 16 –100 0 –15.0 380 –15.5 379 –16.0 378 OUTPUT LEVELS (mV) –16.5 –17.0 –17.5 377 376 375 374 –18.5 –0.5 –0.3 –0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 04409-044 –18.0 1.5 VP INPUT VOLTAGE (VN = –0.2V) 373 –60 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 12. Output Levels vs. Temperature Figure 9. Input Bias Current vs. Input Differential –16.2 496.0mV –16.4 –16.5 –16.6 –16.7 –16.8 –20 0 20 40 60 80 100 TEMPERATURE (°C) 504.0mV 60.00ps/DIV 04409-049 –40 04409-045 M1 –16.9 –60 Figure 13. ADCMP572 Eye Diagram at 2.5 Gbps Figure 10. Input Bias Current vs. Temperature 0.5 500.0mV 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.4 –0.5 –50 –25 0 25 50 TEMPERATURE (°C) 75 100 500.0mV 125 25.00ps/DIV Figure 14. ADCMP572 Eye Diagram at 6.5 Gbps Figure 11. Input Offset Voltage vs. Temperature Rev. 0 | Page 8 of 16 04409-050 –0.3 04409-024 OFFSET (mV) INPUT BIAS CURRENT (µA) –16.3 04409-046 INPUT BIAS CURRENT (µA) ADCMP572/ADCMP573 ADCMP572/ADCMP573 APPLICATION INFORMATION POWER/GROUND LAYOUT AND BYPASSING The ADCMP572/ADCMP573 comparators are very high speed SiGe devices. Consequently, it is essential to use proper high speed design techniques to achieve the specified performance. Of critical importance is the use of low impedance supply planes, particularly the output supply plane (VCCO) and the ground plane (GND). Individual supply planes are recommended as part of a multilayer board. Providing the lowest inductance return path for switching currents ensures the best possible performance in the target application. strip line techniques are essential to ensure proper transition times and to prevent output ringing and pulse width dependent propagation delay dispersion. For the most timing critical applications where transmission line reflections pose the greatest risk to performance, the ADCMP572 provides the best match to 50 Ω output transmission paths. VCCO 50Ω Q It is important to adequately bypass the input and output supplies. A 1 µF electrolytic bypass capacitor should be placed within several inches of each power supply pin to ground. In addition, multiple high quality 0.01 µF bypass capacitors should be placed as close as possible to each of the VCCI and VCCO supply pins and should be connected to the GND plane with redundant vias. High frequency bypass capacitors should be carefully selected for minimum inductance and ESR. Parasitic layout inductance should be avoided to maximize the effectiveness of the bypass at high frequencies. Q GND 04409-037 16mA Figure 15. Simplified Schematic Diagram of the ADCMP572 CML Output Stage If the input and output supplies are connected separately such that VCCI ≠ VCCO, care should be taken to bypass each of these supplies separately to the GND plane. A bypass capacitor should not be connected between them. It is recommended that the GND plane separate the VCCI and VCCO planes when the circuit board layout is designed to minimize coupling between the two supplies and to take advantage of the additional bypass capacitance from each respective supply to the ground plane. This enhances the performance when split input/output supplies are used. If the input and output supplies are connected together for single-supply operation such that VCCI = VCCO, coupling between the two supplies is unavoidable; however, every effort should be made to keep the supply plane adjacent to the GND plane to maximize the additional bypass capacitance this arrangement provides. VCCO Q GND 04409-038 Q Figure 16. Simplified Schematic Diagram of the ADCMP573 RSPECL Output Stage CML/RSPECL OUTPUT STAGE USING/DISABLING THE LATCH FEATURE Specified propagation delay dispersion performance can be achieved only by using proper transmission line terminations. The outputs of the ADCMP572 are designed to directly drive 400 mV into 50 Ω cable, microstrip, or strip line transmission lines properly terminated to the VCCO supply plane. The CML output stage is shown in the simplified schematic diagram of Figure 15. The outputs are each back terminated with 50 Ω for best transmission line matching. The RSPECL outputs of the ADCMP573 are illustrated in Figure 16 and should be terminated to VCCO − 2 V. As an alternative, Thevenin equivalent termination networks can be used in either case if the direct termination voltage is not readily available. If high speed output signals must be routed more than a centimeter, microstrip or The latch inputs (LE/LE) are active low for latch mode and are internally terminated with 50 Ω resistors to Pin 8. This pin corresponds to and is internally connected to the VCCO supply for the CML-compatible ADCMP572. With the aid of these resistors the ADCMP572 latch function can be disabled by connecting the LE pin to GND with an external pull-down resistor and leaving the LE pin unconnected. To avoid excessive power dissipation, the resistor should be 750 Ω when VCCO = 3.3 V, and 1.2 kΩ when VCCO = 5.2 V. In the PECL-compatible ADCMP573, the VTT pin should be connected externally to the PECL termination supply at VCCO – 2 V. The latch can then be disabled by connecting the LE pin to VCCO with an external Rev. 0 | Page 9 of 16 ADCMP572/ADCMP573 500 Ω resistor and leaving the LE pin disconnected. In this case, the resistor value does not depend on the VCCO supply voltage. COMPARATOR PROPAGATION DELAY DISPERSION VCCO is the signal return for the output stage and VCCO pins should of course be connected to a supply plane for maximum performance. The ADCMP572/ADCMP573 comparators are designed to reduce propagation delay dispersion over a wide input overdrive range of 5 mV to 500 mV. Propagation delay dispersion is variation in the propagation delay that results from a change in the degree of overdrive or slew rate (how far or how fast the input signal exceeds the switching threshold). For applications working in a 50 Ω environment, input and output matching has a significant impact on data dependent (or deterministic) jitter (DJ) and on pulse width dispersion performance. The ADCMP572/ADCMP573 comparators provide internal 50 Ω termination resistors for both the VP and VN inputs, and the ADCMP572 provides 50 Ω back terminated outputs. The return side for each input termination is pinned out separately with the VTP and VTN pins, respectively. If a 50 Ω termination is desired at one or both of the VP/VN inputs, then the VTP and VTN pins can be connected (or disconnected) to (from) the desired termination potential as required. The termination potential should be carefully bypassed using high quality bypass capacitors as discussed earlier to prevent undesired aberrations on the input signal due to parasitic inductance in the circuit board layout. If a 50 Ω input termination is not desired, either one or both of the VTP/VTN termination pins can be left disconnected. In this case, the pins should be left floating with no external pull-downs or bypassing capacitors. Propagation delay dispersion is a specification that becomes important in high speed, time-critical applications such as data communication, automatic test and measurement, instrumentation, and event driven applications such as pulse spectroscopy, nuclear instrumentation, and medical imaging. Dispersion is defined as the variation in propagation delay as the input overdrive conditions vary (Figure 17 and Figure 18). For the ADCMP572/ADCMP573, dispersion is typically <15 ps because the overdrive varies from 10 mV to 500 mV, and the input slew rate varies from 2 V/ns to 10 V/ns. This specification applies for both positive and negative signals since the ADCMP572/ ADCMP573 has substantially equal delays for either positive going or negative going inputs. When leaving an input termination disconnected, the internal resistor acts as a small stub on the input transmission path and can cause problems for very high speed inputs. Reflections should then be expected from the comparator inputs because they no longer provide matched impedance to the input path leading to the device. In this case, it is important to back match the drive source impedance to the input transmission path to minimize multiple reflections. For applications in which the comparator is very close to the driving signal source, the source impedance should be minimized. High source impedance in combination with parasitic input capacitance of the comparator might cause an undesirable degradation in bandwidth at the input, therefore degrading the overall response. Although the ADCMP572/ ADCMP573 comparators have been designed to minimize input capacitance, some parasitic capacitance is inevitable. It is therefore recommended that the drive source impedance be no more than 50 Ω for best high speed performance. Rev. 0 | Page 10 of 16 500mV OVERDRIVE INPUT VOLTAGE 10mV OVERDRIVE VN ± VOS DISPERSION Q/Q OUTPUT 04409-0-027 As with any high speed comparator, proper design and layout techniques are essential to obtaining the specified performance. Stray capacitance, inductance, inductive power and ground impedances, or other layout issues can severely limit performance and often cause oscillation. Discontinuities along input and output transmission lines can severely limit the specified pulse width dispersion performance. Figure 17. Propagation Delay—Overdrive Dispersion INPUT VOLTAGE 1V/ns VN ± VOS 10V/ns DISPERSION Q/Q OUTPUT 04409-0-028 OPTIMIZING HIGH SPEED PERFORMANCE Figure 18. Propagation Delay—Slew Rate Dispersion ADCMP572/ADCMP573 The addition of hysteresis to a comparator is often desirable in a noisy environment or when the differential input amplitudes are relatively small or slow moving, but excessive hysteresis has a cost in degraded accuracy and slew-induced timing shifts. The transfer function for a comparator with hysteresis is shown in Figure 19. If the input voltage approaches the threshold (0.0 V in this example) from the negative direction, the comparator switches from low to high when the input crosses +VH/2. The new switching threshold becomes −VH/2. The comparator remains in the high state until the threshold −VH/2 is crossed from the positive direction. In this manner, noise centered on 0.0 V input does not cause the comparator to switch states unless it exceeds the region bounded by ±VH/2. OUTPUT applied as a function of external resistor value. The advantages of applying hysteresis in this manner are improved accuracy, stability, and reduced component count. An external bypass capacitor is not recommended on the HYS pin because it would likely degrade the jitter performance of the device. The hysteresis pin could also be driven by a CMOS DAC. It is biased to approximately 250 mV and has an internal series resistance of 600 Ω. 60 50 HYSTERESIS (mV) COMPARATOR HYSTERESIS VOH 40 30 20 0 0 1 2 3 4 5 6 RHYS (kΩ) VOL 04409-043 10 Figure 20. Hysteresis vs. RHYS Control Resistor 0 +VH 2 INPUT MINIMUM INPUT SLEW RATE REQUIREMENTS 04409-005 –VH 2 Figure 19. Comparator Hysteresis Transfer Function The customary technique for introducing hysteresis into a comparator uses positive feedback from the output back to the input. A limitation of this approach is that the amount of hysteresis varies with the output logic levels, resulting in hysteresis that can be load dependent and is not symmetrical about the threshold. The external feedback network can also introduce significant parasitics, which reduce high speed performance and can even induce oscillation in some cases. The ADCMP572/ADCMP573 comparators offer a programmable hysteresis feature that can significantly improve the accuracy and stability of the desired hysteresis. By connecting an external pull-down resistor from the HYS pin to GND, a variable amount of hysteresis can be applied. Leaving the HYS pin disconnected disables the feature, and hysteresis is then less than 1 mV as specified. The maximum hysteresis that can be applied using this method is approximately ±25 mV with the pin grounded. Figure 20 illustrates the amount of hysteresis As with all high speed comparators, a minimum slew rate requirement must be met to ensure that the device does not oscillate as the input signal crosses the threshold. This oscillation is due in part to the high input bandwidth of the comparator and the feedback parasitics inherent in the package. A minimum slew rate of 50 V/µs should ensure clean output transitions from the ADCMP572/ ADCMP573 comparators. The slew rate may be too slow for other reasons. The extremely high bandwidth of these devices means that broadband noise can be a significant factor when input slew rates are low. There will be at least 120 µv of thermal noise generated over the full comparator bandwidth by two 50 Ω terminations at room temperature. With a slew rate of only 50 V/µs the input will be inside this noise band for over 2 ps, rendering the comparator’s jitter performance of 200 fs moot. Raising the slew rate of the input signal and/or reducing the bandwidth over which this resistance is seen at the input can greatly reduce jitter. Rev. 0 | Page 11 of 16 ADCMP572/ADCMP573 TYPICAL APPLICATION CIRCUITS 3.3V VCCI VCCO VCCI 50Ω VTP VCCO = 3.3V 50Ω 5V 75Ω VP VIN VN Q ADCMP572 100Ω ADCMP572 Q VTN 100Ω 50Ω Figure 25. Interfacing 3.3 V CML to a 50 Ω Ground Terminated Instrument Figure 21. Zero-Crossing Detector with 3.3 V CML Outputs VCCI = 5.2V VCCI VCCO = 3.3V VCCO VTP 50Ω VN VN 50Ω Q VP ADCMP572 VN Q VCCO 750Ω 04409-035 04409-030 LATCH INPUTS Figure 26. Disabling the ADCMP572 Latch Feature Figure 22. LVDS to 50 Ω Back Terminated RSPECL Receiver VCCI = 3.3V VCCO = 2.5V/3.3V VCCI = 5.2V = VCCO 2.5V/3.3V 50Ω VIN VTH – 50Ω Q VP ADCMP572 VN Q ADCMP573 VTT = 3.2V VCCO Figure 27. Disabling the ADCMP573 Latch Feature Figure 23. Comparator with ±1 V Input Range and 2.5 V or 3.3 V CML Outputs VCCI = 5.2V VCCO = 3.3V/5.2V VCCI 3.3V/5.2V 50Ω VCCO VCCO 50Ω 50Ω 50Ω Q ADCMP572 ADCMP572 Q 0Ω TO 5kΩ 04409-036 LATCH INPUTS HYS 04409-032 VTH 50Ω 04409-048 GND = –1V 50Ω 500Ω 04409-031 LATCH INPUTS VIN 50Ω ADCMP572 VTN + VCCO 50Ω VP VP 04409-034 04409-029 LATCH INPUTS 50Ω LATCH INPUTS Figure 28. Adding Hysteresis Using the HYS Control Pin Figure 24. Comparator with 0 V to 3 V Input Range and 3.3 V or 5.2 V Positive CML Outputs Rev. 0 | Page 12 of 16 ADCMP572/ADCMP573 TIMING INFORMATION Figure 29 illustrates the ADCMP572/ADCMP573 compare and latch timing relationships. Table 4 provides definitions of the terms shown in the figure. LATCH ENABLE 50% LATCH ENABLE tS tPL tH DIFFERENTIAL INPUT VOLTAGE VIN VN ± VOS VOD tPDL tPLOH Q OUTPUT 50% tF tPDH tPLOL tR 04409-003 50% Q OUTPUT Figure 29. System Timing Diagram Table 4. Timing Descriptions Symbol tPDH Timing Input to output high delay tPDL Input to output low delay tPLOH Latch enable to output high delay tPLOL Latch enable to output low delay tH Minimum hold time tPL Minimum latch enable pulse width tS Minimum setup time tR Output rise time tF Output fall time VOD Voltage overdrive Description Propagation delay measured from the time the input signal crosses the reference (± the input offset voltage) to the 50% point of an output low-to-high transition. Propagation delay measured from the time the input signal crosses the reference (± the input offset voltage) to the 50% point of an output high-to-low transition. Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output low-to-high transition. Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output high-to-low transition. Minimum time after the negative transition of the latch enable signal that the input signal must remain unchanged to be acquired and held at the outputs. Minimum time that the latch enable signal must be high to acquire an input signal change. Minimum time before the negative transition of the latch enable signal that an input signal change must be present to be acquired and held at the outputs. Amount of time required to transition from a low to a high output as measured at the 20% and 80% points. Amount of time required to transition from a high to a low output as measured at the 20% and 80% points. Difference between the input voltages VA and VB. Rev. 0 | Page 13 of 16 ADCMP572/ADCMP573 OUTLINE DIMENSIONS 3.00 BSC SQ 0.60 MAX 13 12 0.45 PIN 1 INDICATOR TOP VIEW 2.75 BSC SQ 0.80 MAX 0.65 TYP 1.00 0.85 0.80 SEATING PLANE PIN 1 INDICATOR 16 1 1.65 1.50 SQ* 1.35 EXPOSED PAD 0.50 BSC 12° MAX 0.50 0.40 0.30 9 (BOTTOM VIEW) 4 8 5 0.25 MIN 1.50 REF 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF *COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2 EXCEPT FOR EXPOSED PAD DIMENSION Figure 30. 16-Lead Lead Frame Chip Scale Package [LFCSP] 3 x 3 mm Body (CP-16-3) Dimensions shown in millimeters ORDERING GUIDE Model ADCMP572BCP-WP ADCMP572BCP-R2 ADCMP572BCP-RL7 EVAL-ADCMP572BCP ADCMP573BCP-WP ADCMP573BCP-R2 ADCMP573BCP-RL7 EVAL-ADCMP573BCP Temperature Range −40°C to 85°C −40°C to 85°C −40°C to 85°C −40°C to 85°C −40°C to 85°C −40°C to 85°C Package Description LFCSP-16 LFCSP-16 LFCSP-16 Evaluation Board LFCSP-16 LFCSP-16 LFCSP-16 Evaluation Board Rev. 0 | Page 14 of 16 Package Option CP-16-3 CP-16-3 CP-16-3 CP-16-3 CP-16-3 CP-16-3 ADCMP572/ADCMP573 NOTES Rev. 0 | Page 15 of 16 ADCMP572/ADCMP573 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04409–0–4/05(0) Rev. 0 | Page 16 of 16