Ultrafast SiGe Voltage Comparators ADCMP580/ADCMP581/ADCMP582 180 ps propagation delay 25 ps overdrive and slew rate dispersion 8 GHz equivalent input rise time bandwidth 100 ps minimum pulse width 37 ps typical output rise/fall 10 ps deterministic jitter (DJ) 200 fs random jitter (RJ) −2 V to +3 V input range with +5 V/−5 V supplies On-chip terminations at both input pins Resistor-programmable hysteresis Differential latch control Power supply rejection > 70 dB FUNCTIONAL BLOCK DIAGRAM VTP TERMINATION VP NONINVERTING INPUT VN INVERTING INPUT ADCMP580/ ADCMP581/ ADCMP582 Q OUTPUT CML/ECL/ PECL Q OUTPUT VTN TERMINATION LE INPUT HYS LE INPUT 04672-001 FEATURES Figure 1. APPLICATIONS Automatic test equipment (ATE) High speed instrumentation Pulse spectroscopy Medical imaging and diagnostics High speed line receivers Threshold detection Peak and zero-crossing detectors High speed trigger circuitry Clock and data signal restoration GENERAL DESCRIPTION The ADCMP580/ADCMP581/ADCMP582 are ultrafast voltage comparators fabricated on Analog Devices’ proprietary XFCB3 Silicon Germanium (SiGe) bipolar process. The ADCMP580 features CML output drivers; the ADCMP581 features reduced swing ECL (negative ECL) output drivers; and the ADCMP582 features reduced swing PECL (positive ECL) output drivers. All three comparators offer 180 ps propagation delay and 100 ps minimum pulse width for 10 Gbps operation with 200 fs random jitter (RJ). Overdrive and slew rate dispersion are typically less than 15 ps. The ±5 V power supplies enable a wide −2 V to +3 V input range with logic levels referenced to the CML/NECL/PECL outputs. The inputs have 50 Ω on-chip termination resistors with the optional capability to be left open (on an individual pin basis) for applications requiring high impedance input. The CML output stage is designed to directly drive 400 mV into 50 Ω transmission lines terminated to ground. The NECL output stages are designed to directly drive 400 mV into 50 Ω terminated to −2 V. The PECL output stages are designed to directly drive 400 mV into 50 Ω terminated to VCCO − 2 V. High speed latch and programmable hysteresis are also provided. The differential latch input controls are also 50 Ω terminated to an independent VTT pin to interface to either CML or ECL or to PECL logic. The ADCMP580/ADCMP581/ADCMP582 are available in a 16-lead LFCSP package. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. ADCMP580/ADCMP581/ADCMP582 TABLE OF CONTENTS Specifications..................................................................................... 3 Power/Ground Layout and Bypassing..................................... 11 Timing Information ......................................................................... 5 ADCMP58x Family of Output Stages ..................................... 11 Absolute Maximum Ratings............................................................ 6 Using/Disabling the Latch Feature........................................... 11 Thermal Considerations.............................................................. 6 Optimizing High Speed Performance ..................................... 12 ESD Caution.................................................................................. 6 Comparator Propagation Delay Dispersion ........................... 12 Pin Configurations and Function Descriptions ........................... 7 Comparator Hysteresis .............................................................. 13 Typical Performance Characteristics ............................................. 8 Minimum Input Slew Rate Requirement ................................ 13 Typical Application Circuits.......................................................... 10 Outline Dimensions ....................................................................... 14 Application Information................................................................ 11 Ordering Guide .......................................................................... 14 REVISION HISTORY 7/05—Revision 0: Initial Version Rev. 0 | Page 2 of 16 ADCMP580/ADCMP581/ADCMP582 SPECIFICATIONS VCCI = +5.0 V; VEE = −5.0 V; VCCO = +3.3 V; TA = 25°C, unless otherwise noted. Table 1. Parameter DC INPUT CHARACTERISTICS Input Voltage Range Input Differential Range Input Offset Voltage Offset Voltage Tempco Input Bias Current Input Bias Current Tempco Input Offset Current Input Resistance Input Resistance, Differential Mode Input Resistance, Common Mode Active Gain Common-Mode Rejection Hysteresis LATCH ENABLE CHARACTERISTICS Latch Enable Input Impedance Latch to Output Delay Latch Minimum Pulse Width ADCMP580 (CML) Latch Enable Input Range Latch Enable Input Differential Latch Setup Time Latch Hold Time ADCMP581 (NECL) Latch Enable Input Range Latch Enable Input Differential Latch Setup Time Latch Hold Time ADCMP582 (PECL) Latch Enable Input Range Latch Enable Input Differential Latch Setup Time Latch Hold Time DC OUTPUT CHARACTERISTICS ADCMP580 (CML) Output Impedance Output Voltage High Level Output Voltage Low Level Output Voltage Differential ADCMP581 (NECL) Output Voltage High Level Output Voltage High Level Output Voltage High Level Output Voltage Low Level Output Voltage Low Level Output Voltage Low Level Output Voltage Differential Symbol Condition VP, VN VOS ΔVOS/dT IP, IN ΔIB/dT Min −2.0 −2.0 −10.0 Typ CMRR VCM = −2.0 V to +3.0 V RHYS = ∞ ±4 10 15 50 2 47 to 53 50 500 48 60 1 ZIN tPLOH, tPLOL tPL Each pin, VTT at ac ground VOD = 200 mV VOD = 200 mV 47 to 53 175 100 Open termination Open termination Open termination AV −0.8 0.2 tS tH VOD = 200 mV VOD = 200 mV −1.8 0.2 tS tH VOD = 200 mV VOD = 200 mV VCCO − 1.8 0.2 tS tH VOD = 200 mV VOD = 200 mV ZOUT VOH VOL VOH VOH VOH VOL VOL VOL 0.4 95 −90 0.4 70 −65 0.4 30 −25 Max Unit +3.0 +2.0 +10.0 V V mV μV/°C μA nA/°C μA Ω kΩ kΩ dB dB mV 30.0 ±5.0 Ω ps ps 0 0.5 V V ps ps +0.8 0.5 V V ps ps VCCO − 0.8 0.5 V V ps ps 50 Ω to GND 50 Ω to GND 50 Ω to GND −0.10 −0.50 340 50 0 −0.40 395 0.03 −0.35 450 Ω V V mV 50 Ω to −2 V, TA = 125°C 50 Ω to −2 V, TA = 25°C 50 Ω to −2 V, TA = −55°C 50 Ω to −2 V, TA = 125°C 50 Ω to −2 V, TA = 25°C 50 Ω to −2 V, TA = −55°C 50 Ω to −2.0 V −0.99 −1.06 −1.11 −1.43 −1.50 −1.55 340 −0.87 −0.94 −0.99 −1.26 −1.33 −1.38 395 −0.75 −0.82 −0.87 −1.13 −1.20 −1.25 450 V V V V V V mV Rev. 0 | Page 3 of 16 ADCMP580/ADCMP581/ADCMP582 Parameter ADCMP582 (PECL) Output Voltage High Level Output Voltage High Level Output Voltage High Level Output Voltage Low Level Output Voltage Low Level Output Voltage Low Level Output Voltage Differential AC PERFORMANCE Propagation Delay Propagation Delay Tempco Prop Delay Skew—Rising Transition to Falling Transition Overdrive Dispersion VOH VOH VOH VOL VOL VOL tPD ΔtPD/dT Condition Vcco = 3.3 V 50 Ω to VCCO − 2 V, TA = 125°C 50 Ω to VCCO − 2 V, TA = 25°C 50 Ω to VCCO − 2 V, TA = −55°C 50 Ω to VCCO − 2 V, TA = 125°C 50 Ω to VCCO − 2 V, TA = 25°C 50 Ω to VCCO − 2 V, TA = −55°C 50 Ω to VCCO − 2.0 V Min Typ Max Unit VCCO − 0.99 VCCO − 1.06 VCCO − 1.11 VCCO − 1.43 VCCO − 1.50 VCCO − 1.55 340 VCCO − 0.87 VCCO − 0.94 VCCO − 0.99 VCCO − 1.26 VCCO − 1.33 VCCO − 1.35 395 VCCO − 0.75 VCCO − 0.82 VCCO − 0.87 VCCO − 1.13 VCCO − 1.20 VCCO − 1.25 450 V V V V V V mV VOD = 500 mV VOD = 500 mV, 5 V/ns Slew Rate Dispersion Pulse Width Dispersion Duty Cycle Dispersion 5% to 95% Common-Mode Dispersion Equivalent Input Bandwidth 1 BWEQ Toggle Rate Deterministic Jitter DJ Deterministic Jitter DJ RMS Random Jitter Minimum Pulse Width Minimum Pulse Width Rise/Fall Time POWER SUPPLY Positive Supply Voltage Negative Supply Voltage ADCMP580 (CML) Positive Supply Current Negative Supply Current Power Dissipation ADCMP581 (NECL) Positive Supply Current Negative Supply Current Power Dissipation ADCMP582 (PECL) Logic Supply Voltage Input Supply Current Output Supply Current Negative Supply Current Power Dissipation Power Supply Rejection (VCCI) Power Supply Rejection (VEE) Power Supply Rejection (VCCO) 1 Symbol RJ PWMIN PWMIN tR, tF 50 mV < VOD < 1.0 V 10 mV < VOD < 200m V 2 V/ns to 10 V/ns 100 ps to 5 ns 1.0 V/ns, 15 MHz, VCM = 0.0 V VOD = 0.2 V, −2 V < VCM < 3 V 0.0 V to 400 mV input tR = tF = 25 ps, 20/80 >50% output swing VOD = 500 mV, 5 V/ns PRBS31 − 1 NRZ, 5 Gbps VOD = 200 mV, 5 V/ns PRBS31 − 1 NRZ, 10 Gbps VOD = 200 mV, 5 V/ns, 1.25 GHz ΔtPD < 5 ps ΔtPD < 10 ps 20/80 VCCI VEE +4.5 −5.5 180 0.25 10 ps ps/°C ps 10 15 15 15 10 5 8 ps ps ps ps ps ps/V GHz 12.5 15 Gbps ps 25 ps 0.2 100 80 37 ps ps ps ps −5.0 +5.0 +5.5 −4.5 V V IVCCI IVEE PD VCCI = +5.0 V, 50 Ω to GND VEE = −5.0 V, 50 Ω to GND 50 Ω to GND −50 6 −40 230 8 −34 260 mA mA mW IVCCI IVEE PD VCCI = +5.0 V, 50 Ω to −2 V VEE = −5.0 V, 50 Ω to −2 V 50 Ω to −2 V −35 6 −25 155 8 −19 200 mA mA mW VCCO IVCCI IVCCO IVEE PD PSRVCCI PSRVEE PSRVCCO VCCI = +5.0 V, 50 Ω to VCCO − 2 V VCCO = +5.0 V, 50 Ω to VCCO − 2 V VEE = −5.0 V, 50 Ω to VCCO − 2 V 50 Ω to VCCO − 2 V VCCI = 5.0 V + 5% VEE = −5.0 V + 5% VCCO = 3.3 V + 5% (ADCMP582) +3.3 6 44 −25 310 −75 −60 −75 +5.0 8 55 −19 350 V mA mA mA mW dB dB dB +2.5 −35 Equivalent input bandwidth assumes a simple first-order input response and is calculated with the following formula: BWEQ = 0.22/(trCOMP2 – trIN2), where trIN is the 20/80 transition time of a quasi-Gaussian input edge applied to the comparator input and trCOMP is the effective transition time digitized by the comparator. Rev. 0 | Page 4 of 16 ADCMP580/ADCMP581/ADCMP582 TIMING INFORMATION Figure 2 shows the ADCMP580/ADCMP581/ADCMP582 compare and latch timing relationships. Table 2 provides the definitions of the terms shown in the figure. LATCH ENABLE 50% LATCH ENABLE tS tPL tH DIFFERENTIAL INPUT VOLTAGE VN VN ± VOS VOD tPDL tPLOH Q OUTPUT 50% tF tPDH tPLOL tR 04672-028 50% Q OUTPUT Figure 2. Comparator Timing Diagram Table 2. Timing Descriptions Symbol tPDH Timing Input to Output High Delay tPDL Input to Output Low Delay tPLOH Latch Enable to Output High Delay tPLOL Latch Enable to Output Low Delay tH Minimum Hold Time tPL Minimum Latch Enable Pulse Width tS Minimum Setup Time tR Output Rise Time tF Output Fall Time VN VOD Normal Input Voltage Voltage Overdrive Description Propagation delay measured from the time the input signal crosses the reference (± the input offset voltage) to the 50% point of an output low-to-high transition. Propagation delay measured from the time the input signal crosses the reference (± the input offset voltage) to the 50% point of an output high-to-low transition. Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output low-to-high transition. Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output high-to-low transition. Minimum time after the negative transition of the latch enable signal that the input signal must remain unchanged to be acquired and held at the outputs. Minimum time that the latch enable signal must be high to acquire an input signal change. Minimum time before the negative transition of the latch enable signal that an input signal change must be present to be acquired and held at the outputs. Amount of time required to transition from a low to a high output as measured at the 20% and 80% points. Amount of time required to transition from a high to a low output as measured at the 20% and 80% points. Difference between the input voltages VP and VN for output true. Difference between the input voltages VP and VN for output false. Rev. 0 | Page 5 of 16 ADCMP580/ADCMP581/ADCMP582 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter SUPPLY VOLTAGES Positive Supply Voltage (VCCI to GND) Negative Supply Voltage (VEE to GND) Logic Supply Voltage (VCCO to GND) INPUT VOLTAGES Input Voltage Differential Input Voltage Input Voltage, Latch Enable HYSTERESIS CONTROL PIN Applied Voltage (HYS to VEE) Maximum Input/Output Current OUTPUT CURRENT ADCMP580 (CML) ADCMP581 (NECL) ADCMP582 (PECL) TEMPERATURE Operating Temperature, Ambient Operating Temperature, Junction Storage Temperature Range Rating −0.5 V to +6.0 V –6.0 V to +0.5 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. −0.5 V to +6.0 V THERMAL CONSIDERATIONS −3.0 V to +4.0 V −2 V to +2 V −2.5 V to +5.5 V The ADCMP580/ADCMP581/ADCMP582 LFCSP 16-lead package option has a θJA (junction-to-ambient thermal resistance) of 70°C/W in still air. −5.5 V to +0.5 V 1 mA −25 mA −40 mA −40 mA −40°C to +125°C 125°C −65°C to +150°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 6 of 16 ADCMP580/ADCMP581/ADCMP582 Figure 3. ADCMP580 Pin Configuration Figure 4. ADCMP581 Pin Configuration 12 VCCO 11 Q 10 Q 9 VCCO 04672-004 VTN 4 9 GND 14 HYS TOP VIEW (Not to Scale) LE 7 VN 3 ADCMP582 VTT 8 10 Q 13 VEE 16 VCCI 15 GND VP 2 LE 6 14 HYS 13 VEE 11 Q PIN 1 INDICATOR VCCI 5 VTN 4 9 GND TOP VIEW (Not to Scale) VTP 1 04672-003 VN 3 12 GND VTT 8 10 Q ADCMP581 LE 7 VP 2 15 GND 16 VCCI 11 Q PIN 1 INDICATOR LE 6 VTP 1 VCCI 5 VTT 8 VCCI 5 VTN 4 LE 7 TOP VIEW (Not to Scale) 12 GND 04672-002 14 HYS ADCMP580 LE 6 VN 3 13 VEE PIN 1 INDICATOR VTP 1 VP 2 15 GND 16 VCCI PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 5. ADCMP582 Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 4 5, 16 6 Mnemonic VTP VP VN VTN VCCI LE 7 LE 8 VTT 9, 12 GND/VCCO 10 Q 11 Q 13 14 VEE HYS 15 Heat Sink Paddle GND N/C Description Termination Resistor Return Pin for VP Input. Noninverting Analog Input. Inverting Analog Input. Termination Resistor Return Pin for VN Input. Positive Supply Voltage. Latch Enable Input Pin, Inverting Side. In compare mode (LE = low), the output tracks changes at the input of the comparator. In latch mode (LE = high), the output reflects the input state just prior to the comparator being placed into latch mode. LE must be driven in complement with LE. Latch Enable Input Pin, Noninverting Side. In compare mode (LE = high), the output tracks changes at the input of the comparator. In latch mode (LE = low), the output reflects the input state just prior to the comparator being placed into latch mode. LE must be driven in complement with LE. Termination Return Pin for the LE/LE Input Pins. For the ADCMP580 (CML output stage), this pin should be connected to the GND ground. For the ADCMP581 (ECL output stage), this pin should be connected to the –2 V termination potential. For the ADCMP582 (PECL output stage), this pin should be connected to the VCCO – 2 V termination potential. Digital Ground Pin/Positive Logic Power Supply Terminal. For the ADCMP580/ADCMP581, this pin should be connected to the GND pin. For the ADCMP582, this pin should be connected to the positive logic power VCCO supply. Inverting Output. Q is logic low if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN, provided that the comparator is in compare mode. See the LE/LE descriptions (Pin 6 to Pin 7) for more information. Noninverting Output. Q is logic high if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN, provided that the comparator is in compare mode. See the LE/LE descriptions (Pin 6 to Pin 7) for more information. Negative Power Supply. Hysteresis Control. Leave this pin disconnected for zero hysteresis. Connect this pin to the VEE supply with a suitably sized resistor to add the desired amount of hysteresis. Refer to Figure 9 for proper sizing of the HYS hysteresis control resistor. Analog Ground. The metallic back surface of the package is not electrically connected to any part of the circuit. It can be left floating for optimal electrical isolation between the package handle and the substrate of the die. It can also be soldered to the application board if improved thermal and/or mechanical stability is desired. Rev. 0 | Page 7 of 16 ADCMP580/ADCMP581/ADCMP582 TYPICAL PERFORMANCE CHARACTERISTICS VCCI = +5.0 V, VEE = −5.0 V, VCCO = +3.3 V, TA = 25°C, unless otherwise noted. 80 12 70 10 60 HYSTERESIS (mV) BIAS CURRENT (μA) VIN COMMON-MODE BIAS SWEEP 8 6 4 50 40 30 20 2 0 –4 –2 0 2 04672-009 04672-005 10 0 0 4 10 100 1k 10k RESISTOR (Ω) COMMON MODE (V) Figure 6. Bias Current vs. Common-Mode Voltage Figure 9. Hysteresis vs. RHYS Control Resistor 2.5 –0.8 VOH VS TEMP OUTPUT (NECL) –0.9 2.4 VOH VS TEMP OUTPUT (PECL) –1.0 OUTPUT (V) OUTPUT (V) 2.3 –1.1 –1.2 2.2 2.1 VOL VS TEMP OUTPUT (NECL) –1.3 04672-007 –1.5 –55 –5 45 VOL VS TEMP OUTPUT (PECL) 1.9 –55 145 95 04672-010 2.0 –1.4 –5 45 95 145 TEMP (°C) TEMP (°C) Figure 10. ADCMP582 Output Voltage vs. Temperature Figure 7. ADCMP581 Output Voltage vs. Temperature 80 8 70 7 60 6 50 5 OFFSET (mV) 40 30 4 3 25°C COMMON-MODE OFFSET SWEEP 20 2 10 1 0 0 100 200 300 400 500 0 –2 600 –IHYST (μA) 04672-011 –55°C COMMON-MODE OFFSET SWEEP 04672-008 HYSTERESIS (mV) 125°C COMMON-MODE OFFSET SWEEP 0 2 COMMON-MODE (V) Figure 11. A Typical VOS vs. Common- Mode Voltage Figure 8. Hysteresis vs. −IHYST Rev. 0 | Page 8 of 16 4 5 45 4 43 3 41 2 39 1 37 TR/TF (ps) 0 –1 35 33 31 –2 LOT2 CHAR1 RISE LOT2 CHAR1 FALL LOT3 CHAR1 RISE LOT3 CHAR1 FALL –4 –5 –2 –1 QBARRISE QRISE QBARFALL QFALL 29 04672-031 –3 0 1 2 27 25 –55 3 –35 –15 5 25 45 65 85 105 04672-033 TPD ERROR (ps) ADCMP580/ADCMP581/ADCMP582 125 TEMPERATURE (°C) VCM (V) Figure 15. ADCMP581 TR/TF vs. Temperature Figure 12. ADCMP580 Prop Delay vs. Common-Mode Voltage 500mV M1 M1 M1 500mV Figure 13. ADCMP580 Eye Diagram at 7.5 Gbps Figure 16. ADCMP582 Eye Diagram at 2.5 Gbps 18 16 12 10 8 6 OD DISPERSION FALL 04672-032 DISPERSION (PS) 14 4 2 OD DISPERSION RISE 0 0 50 100 150 200 20ps/DIV 250 OVERDRIVE (mV) Figure 14. Dispersion vs. Overdrive Rev. 0 | Page 9 of 16 04672-030 04672-029 M1 ADCMP580/ADCMP581/ADCMP582 TYPICAL APPLICATION CIRCUITS GND VTP VIN 50Ω 50Ω VP VP VN VN Q ADCMP580 CML ADCMP580 Q 1.5kΩ 50Ω VEE 04672-020 LATCH INPUTS 50Ω 04672-025 VTN Figure 17. Zero-Crossing Detector with CML Outputs Figure 21. Disabling the Latch Feature on the ADCMP580 VTP VP VP VN VN Q VP ADCMP581 VN Q ADCMP581 RSECL VTN 50Ω 50Ω 50Ω 50Ω 450Ω VEE Figure 18. LVDS to a 50 Ω Back-Terminated (RS) ECL Receiver Figure 22. Disabling the Latch Feature on the ADCMP581 VN HYS 50Ω 1kΩ 04672-026 50Ω VEE VIN VTH – 50Ω Q ADCMP580 04672-022 Q LATCH INPUTS 50Ω 50Ω Figure 23. Disabling the Latch Feature on the ADCMP582 GND 50Ω RSPECL VTT Figure 19. Adding Hysteresis Using the HYS Control + ADCMP582 04672-027 VP ADCMP580 0Ω TO 5kΩ 04672-023 VTT 04672-021 VTT LATCH INPUTS Figure 20. Comparator with −2 to +3 V Input Range Rev. 0 | Page 10 of 16 ADCMP580/ADCMP581/ADCMP582 APPLICATION INFORMATION GND POWER/GROUND LAYOUT AND BYPASSING The ADCMP58x family of comparators is designed for very high speed applications. Consequently, high speed design techniques must be used to achieve the specified performance. It is critically important to use low impedance supply planes, particularly for the negative supply (VEE), the output supply plane (VCCO), and the ground plane (GND). Individual supply planes are recommended as part of a multilayer board. Providing the lowest inductance return path for the switching currents ensures the best possible performance in the target application. 50Ω 50Ω Q Q It is also important to adequately bypass the input and output supplies. A 1 μF electrolytic bypass capacitor should be placed within several inches of each power supply pin to ground. In addition, multiple high quality 0.1 μF bypass capacitors should be placed as close as possible to each of the VEE, VCCI, and VCCO supply pins and should be connected to the GND plane with redundant vias. High frequency bypass capacitors should be carefully selected for minimum inductance and ESR. Parasitic layout inductance should be strictly avoided to maximize the effectiveness of the bypass at high frequencies. VEE 04672-014 16mA Figure 24. Simplified Schematic Diagram of the ADCMP580 CML Output Stage GND / Vcco ADCMP58x FAMILY OF OUTPUT STAGES Q Q VEE 04672-015 Specified propagation delay dispersion performance is achieved by using proper transmission line terminations. The outputs of the ADCMP580 family comparators are designed to directly drive 400 mV into 50 Ω cable or microstrip/stripline transmission lines terminated with 50 Ω referenced to the proper return. The CML output stage is shown in the simplified schematic diagram in Figure 24. Each output is back-terminated with 50 Ω for best transmission line matching. The outputs of the ADCMP581/ADCMP582 are illustrated in Figure 25; they should be terminated to −2 V for ECL outputs of ADCMP581 and VCCO − 2 V for PECL outputs of ADCMP582. As an alternative, Thevenin equivalent termination networks may also be used. If these high speed signals must be routed more than a centimeter, then either microstrip or stripline techniques are required to ensure proper transition times and to prevent excessive output ringing and pulse width-dependent propagation delay dispersion. Figure 25. Simplified Schematic Diagram of the ADCMP581/ADCMP582 ECL/PECL Output Stage USING/DISABLING THE LATCH FEATURE The latch inputs (LE/LE) are active low for latch mode and are internally terminated with 50 Ω resistors to the VTT pin. When using the ADCMP580, VTT should be connected to ground. When using the ADCMP581, VTT should be connected to −2 V. When using the ADCMP582, VTT should be connected externally to VCCO − 2 V, preferably with its own low inductance plane. When using the ADCMP580/ADCMP582, the latch function can be disabled by connecting the LE pin to VEE with an external pull-down resistor and leaving the LE pin disconnected. To prevent excessive power dissipation, the resistor should be 1.5 kΩ for the ADCMP580 and 1 kΩ for the ADCMP582. When using the ADCMP581 comparators, the latch can be disabled by connecting the LE pin to GND with an external 450 Ω resistor and leaving the LE pin disconnected. The idea is to create an approximate 0.5 V offset using the internal resistor as half of the voltage divider. The VTT pin should be connected as recommended. Rev. 0 | Page 11 of 16 ADCMP580/ADCMP581/ADCMP582 OPTIMIZING HIGH SPEED PERFORMANCE As with any high speed comparator, proper design and layout techniques are essential to obtaining the specified performance. Stray capacitance, inductance, inductive power, and ground impedances or other layout issues can severely limit performance and can cause oscillation. Discontinuities along input and output transmission lines can also severely limit the specified pulse width dispersion performance. For applications in a 50 Ω environment, input and output matching have a significant impact on data-dependent (or deterministic) jitter (DJ) and pulse width dispersion performance. The ADCMP58x family of comparators provides internal 50 Ω termination resistors for both VP and VN inputs. The return side for each termination is pinned out separately with the VTP and VTN pins, respectively. If a 50 Ω termination is desired at one or both of the VP/VN inputs, the VTP and VTN pins can be connected (or disconnected) to (from) the desired termination potential as appropriate. The termination potential should be carefully bypassed using ceramic capacitors as discussed previously to prevent undesired aberrations on the input signal due to parasitic inductance in the termination return path. If a 50 Ω termination is not desired, either one or both of the VTP/VTN termination pins can be left disconnected. In this case, the open pins should be left floating with no external pull downs or bypassing capacitors. COMPARATOR PROPAGATION DELAY DISPERSION The ADCMP58x family of comparators has been specifically designed to reduce propagation delay dispersion over a wide input overdrive range of 5 mV to 500 mV. Propagation delay dispersion is a change in propagation delays, which results from a change in the degree of overdrive or slew rate (how far or fast the input signal exceeds the switching threshold). The overall result is a higher degree of timing accuracy. Propagation delay dispersion is a specification that becomes important in critical timing applications, such as data communication, automatic test and measurement, instrumentation, and event-driven applications, such as pulse spectroscopy, nuclear instrumentation, and medical imaging. Dispersion is defined as the variation in the overall propagation delay as the input overdrive conditions are changed (see Figure 26 and Figure 27). For the ADCMP58x family of comparators, dispersion is typically <25 ps, as the overdrive varies from 5 mV to 500 mV, and the input slew rate varies from 1 V/ns to 10 V/ns. This specification applies for both positive and negative signals, because the ADCMP58x family of comparators has almost equal delays for positive- and negative-going inputs. 500mV OVERDRIVE INPUT VOLTAGE 5mV OVERDRIVE VN ± VOS DISPERSION Q/Q OUTPUT 04672-016 For applications that require high speed operation but do not have on-chip 50 Ω termination resistors, some reflections should be expected, because the comparator inputs can no longer provide matched impedance to the input trace leading up to the device. It then becomes important to back-match the drive source impedance to the input transmission path leading to the input to minimize multiple reflections. For applications in which the comparator is less than 1 cm from the driving signal source, the source impedance should be minimized. High source impedance in combination with parasitic input capacitance of the comparator could cause undesirable degradation in bandwidth at the input, thus degrading the overall response. It is therefore recommended that the drive source impedance should be no more than 50 Ω for best high speed performance. Figure 26. Propagation Delay—Overdrive Dispersion INPUT VOLTAGE 1V/ns VN ± VOS DISPERSION Q/Q OUTPUT 04672-017 10V/ns Figure 27. Propagation Delay—Slew Rate Dispersion Rev. 0 | Page 12 of 16 ADCMP580/ADCMP581/ADCMP582 Adding hysteresis to a comparator is often desirable in a noisy environment or when the differential inputs are very small or slow moving. The transfer function for a comparator with hysteresis is shown in Figure 28. If the input voltage approaches the threshold from the negative direction, the comparator switches from a low to a high when the input crosses +VH/2. The new switching threshold becomes −VH/2. The comparator remains in the high state until the threshold −VH/2 is crossed from the positive direction. In this manner, noise centered on 0 V input does not cause the comparator to switch states unless it exceeds the region bounded by ±VH/2. The hysteresis pin may also be driven by a current source. It is biased approximately 400 mV above VEE and has an internal series resistance of approximately 600 Ω. 80 70 60 HYSTERESIS (mV) COMPARATOR HYSTERESIS 50 40 30 20 The customary technique for introducing hysteresis into a comparator uses positive feedback from the output back to the input. A limitation of this approach is that the amount of hysteresis varies with the output logic levels, resulting in hysteresis that is not symmetric about the threshold. The external feedback network can also introduce significant parasitics that reduce high speed performance and can even reduce overall stability in some cases. –VH 2 0 0 100 1k 10k Figure 29. Comparator Hysteresis vs. RHYS Control Resistor MINIMUM INPUT SLEW RATE REQUIREMENT As with many high speed comparators, a minimum slew rate requirement must be met to ensure that the device does not oscillate as the input signal crosses the threshold. This oscillation is due in part to the high input bandwidth of the comparator and the feedback parasitics inherent in the package. A minimum slew rate of 50 V/μs should ensure clean output transitions from the ADCMP58x family of comparators. INPUT 1 04672-018 0 OUTPUT 10 RESISTOR (Ω) +VH 2 0V 04672-034 10 Figure 28. Comparator Hysteresis Transfer Function The ADCMP58x family of comparators offers a programmable hysteresis feature that can significantly improve the accuracy and stability of the desired hysteresis. By connecting an external pull-down resistor from the HYS pin to VEE, a variable amount of hysteresis can be applied. Leaving the HYS pin disconnected disables the feature, and hysteresis is then less than 1 mV, as specified. The maximum range of hysteresis that can be applied by using this method is approximately ±25 mV. The slew rate may be too slow for other reasons. The extremely high bandwidth of these devices means that broadband noise can be a significant factor when input slew rates are low. There is 120 μV of thermal noise generated over the comparator’s bandwidth by the two 50 Ω terminations at room temperature. With a slew rate of only 50 V/μs, the inputs will be inside this noise band for over 2 ps, rendering the comparator’s jitter performance of 200 fs irrelevant. Raising the slew rate of the input signal and/or reducing the bandwidth over which that resistance is seen at the input can greatly reduce jitter. We do not characterize the devices this way, but simply bypassing a reference input close to the package can reduce jitter 30% in low slew rate applications. Figure 29 illustrates the amount of applied hysteresis as a function of external resistor value. The advantage of applying hysteresis in this manner is improved accuracy, stability, and reduced component count. An external bypass capacitor is not required on the HYS pin and it would likely degrade the jitter performance of the device. Rev. 0 | Page 13 of 16 ADCMP580/ADCMP581/ADCMP582 OUTLINE DIMENSIONS 3.00 BSC SQ 0.60 MAX 13 12 0.45 PIN 1 INDICATOR TOP VIEW 2.75 BSC SQ 0.80 MAX 0.65 TYP 12° MAX SEATING PLANE 16 1 PIN 1 INDICATOR *1.65 1.50 SQ 1.35 EXPOSED PAD 0.50 BSC 0.90 0.85 0.80 0.50 0.40 0.30 9 (BOTTOM VIEW) 4 8 5 0.25 MIN 1.50 REF 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF *COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2 EXCEPT FOR EXPOSED PAD DIMENSION. Figure 30. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] (CP-16-3) Dimensions shown in millimeters ORDERING GUIDE Model ADCMP580BCP-WP ADCMP580BCP–R2 ADCMP580BCP–RL7 ADCMP581BCP-WP ADCMP581BCP–R2 ADCMP581BCP–RL7 ADCMP582BCP-WP ADCMP582BCP-R2 ADCMP582BCP-RL7 EVAL-ADCMP580BCP EVAL-ADCMP581BCP EVAL-ADCMP582BCP Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 16-LEAD LFCSP-VQ 16-LEAD LFCSP-VQ 16-LEAD LFCSP-VQ 16-LEAD LFCSP-VQ 16-LEAD LFCSP-VQ 16-LEAD LFCSP-VQ 16-LEAD LFCSP-VQ 16-LEAD LFCSP-VQ 16-LEAD LFCSP-VQ Evaluation Board Evaluation Board Evaluation Board Rev. 0 | Page 14 of 16 Package Option CP-16-3 CP-16-3 CP-16-3 CP-16-3 CP-16-3 CP-16-3 CP-16-3 CP-16-3 CP-16-3 Branding GO7 GO7 GO7 GO9 GO9 GO9 GOB GOB GOB ADCMP580/ADCMP581/ADCMP582 NOTES Rev. 0 | Page 15 of 16 ADCMP580/ADCMP581/ADCMP582 Preliminary Technical Data NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04672-0-7/05(0) Rev. 0 | Page 16 of 16