EM78P372K 8-BIT Microcontroller Product Specification DOC. VERSION 1.1 ELAN MICROELECTRONICS CORP. February 2015 Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation. ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation. Copyright © 2015 by ELAN Microelectronics Corporation All Rights Reserved Printed in Taiwan The contents of in this specification are subject to change without notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. Such information and material may change to conform to each confirmed order. In no event shall ELAN Microelectronics be made responsible to any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising out of the use of such information or material. The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement. ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics product in such applications is not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESS WRITTEN PERMISSION OF ELAN MICROELECTRONICS. ELAN MICROELECTRONICS CORPORATION Headquarters: Hong Kong: st No. 12, Innovation 1 Road Hsinchu Science Park Hsinchu, TAIWAN 30076 Tel: +886 3 563-9977 Fax: +886 3 563-9966 [email protected] http://www.emc.com.tw USA: Elan (HK) Microelectronics Elan Information Corporation, Ltd. Technology Group Flat A, 19F., World Tech Centre (U.S.A.) 95 How Ming Street, Kwun Tong PO Box 601 Kowloon, HONG KONG Cupertino, CA 95015 Tel: +852 2723-3376 U.S.A. Fax: +852 2723-7780 Tel: +1 408 366-8225 Fax: +1 408 366-8225 Shenzhen: Shanghai: Elan Microelectronics Shenzhen, Ltd. Elan Microelectronics Shanghai, Ltd. 8A Floor, Microprofit Building 6F, Ke Yuan Building Gaoxin South Road 6 No. 5 Bibo Road Shenzhen Hi-Tech Industrial Park Zhangjiang Hi-Tech Park South Area, Shenzhen Shanghai, CHINA 201203 CHINA 518057 Tel: +86 21 5080-3866 Tel: +86 755 2601-0565 Fax: +86 21 5080-0273 Fax: +86 755 2601-0500 [email protected] [email protected] Contents Contents 1 General Description ................................................................................................ 1 2 Features ................................................................................................................... 1 3 Applications ............................................................................................................. 2 4 Pin Assignment (Package) ...................................................................................... 2 5 Block Diagram ......................................................................................................... 4 6 Pin Description ........................................................................................................ 5 7 Functional Description ............................................................................................ 7 7.1 Operational Registers ....................................................................................... 7 7.1.1 R0 (Indirect Addressing Register) ....................................................................... 7 7.1.2 R1 (Timer Clock Counter) ................................................................................... 7 7.1.3 R2 (Program Counter) and Stack........................................................................ 7 7.1.4 R3 (Status Register) .......................................................................................... 10 7.1.5 R4 (RAM Select Register) ................................................................................. 10 7.1.6 Bank 0 R5~R7 (Ports 5~7 I/O Data Register) ................................................... 11 7.1.7 Bank 0 R8 (ADC Input Select Register) ............................................................ 11 7.1.8 Bank 0 R9 (ADC Control Register) ................................................................... 13 7.1.9 Bank 0 RA (ADC Offset Calibration Register) ................................................... 14 7.1.10 Bank 0 RB (Converted value AD11~AD4 of ADC) ............................................ 15 7.1.11 Bank 0 RC (Converted value AD11~AD8 of ADC) ............................................ 15 7.1.12 Bank 0 RD (Converted value AD7~AD0 of ADC) ............................................. 16 7.1.13 Bank 0 RE (Interrupt Status 2 and Wake-up Control Register 1) ..................... 16 7.1.14 Bank 0 RF (Interrupt Status Register 1) ............................................................ 18 7.1.15 Bank 1 R5 (TBHP: Table Point Register) .......................................................... 18 7.1.16 Bank 1 R6 (TBLP: Table Point Register)........................................................... 19 7.1.17 Bank 1 R7 (PWMCON: PWM Control Register) ............................................... 19 7.1.18 Bank 1 R8 (TMRCON: Timer Control Register) ................................................ 20 7.1.19 Bank 1 R9 (PRD1: PWM1 Time Period) ........................................................... 21 7.1.20 Bank 1 RA (PRD2: PWM2 Time Period) ........................................................... 21 7.1.21 Bank 1 RB (DT1: PWM1 Duty Cycle) ............................................................... 21 7.1.22 Bank 1 RC (DT2: PWM2 Duty Cycle) ............................................................... 21 7.1.23 Bank 1 RE (LVD Control and Wake-up Control Register 2) ............................... 21 7.1.24 Bank 1 RF (Mode Select and IRC Switch Register) ......................................... 22 7.1.25 R10~R1F ........................................................................................................... 24 7.2 Special Purpose Registers.............................................................................. 25 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 A (Accumulator)................................................................................................. 25 CONT (Control Register)................................................................................... 25 IOC50 ~ IOC70 (I/O Port Control Register) ...................................................... 26 IOC80 (Comparator Control Register) .............................................................. 26 IOC90 (TMR1: PWM1 Timer)............................................................................ 26 Product Specification (V1.1) 02.09.2015 iii Contents 7.2.6 7.2.7 7.2.8 7.2.9 7.2.10 7.2.11 7.2.12 7.2.13 7.2.14 7.2.15 7.2.16 7.2.17 7.2.18 7.3 TCC/WDT and Prescaler ............................................................................... 35 7.4 I/O Ports ......................................................................................................... 37 7.4.1 7.5 Usage of Ports 5, 7 Input Change Wake-up/Interrupt Function ........................ 39 Reset and Wake-up....................................................................................... 39 7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 Reset and Wake-up Operation.......................................................................... 39 Wake-up and Interrupt Modes Operation Summary ......................................... 42 Register Initial Values after Reset ..................................................................... 44 Controller Reset Block Diagram........................................................................ 50 The T and P Status under Status Register ........................................................ 50 7.6 Interrupt .......................................................................................................... 51 7.7 Analog-to-Digital Converter (ADC) .................................................................. 53 7.7.1 7.7.2 7.7.3 7.7.4 7.7.5 7.7.6 7.8 7.9 ADC Control Register (AISR/R8, ADCON/R9, ADOC/RA) ............................... 54 ADC Data Register (ADDATA/RB, ADDATA1H/RC, ADDATA1L/RD) ............... 57 ADC Sampling Time .......................................................................................... 57 AD Conversion Time ......................................................................................... 58 ADC Operation during Sleep Mode .................................................................. 58 Programming Process/Considerations ............................................................. 59 Dual Sets of PWM (Pulse Width Modulation) .................................................. 62 7.8.1 7.8.2 7.8.3 7.8.4 7.8.5 7.8.6 Overview ........................................................................................................... 62 Increment Timer Counter (TMRX: TMR1 or TMR2) .......................................... 67 PWM Time Period (TMRX: TMR1 or TMR2)..................................................... 67 PWM Duty Cycle (DTX: DT1 or DT2; DLX: DL1 or DL2) .................................. 68 Comparator X .................................................................................................... 68 PWM Programming Process/Steps................................................................... 68 Timer .............................................................................................................. 69 7.9.1 7.9.2 7.9.3 7.9.4 7.9.5 iv IOCA0 (TMR2: PWM2 Timer) ........................................................................... 26 IOCB0 (Pull-down Control Register) ................................................................. 27 IOCC0 (Open-drain Control Register)............................................................... 27 IOCD0 (Pull-high Control Register)................................................................... 28 IOCE0 (WDT Control Register and Interrupt Mask Register 2) ........................ 29 IOCF0 (Interrupt Mask Register 1).................................................................... 30 IOC51 (HSCR1: High Sink Control Register 1) ................................................ 31 IOC61 (HSCR2: High Sink Control Register 2) ................................................ 31 IOC71 (HDCR1: High Driver Control Register 1).............................................. 32 IOC81 (HDCR2: High Driver Control Register 2).............................................. 32 IOC91 (DeadTCR: Dead Time Control Register) .............................................. 33 IOCA1 (DeadTR: Dead Time Register) ............................................................ 34 IOCF1 (Pull-high Control Register) ................................................................... 34 Overview ........................................................................................................... 69 Function Description ......................................................................................... 69 Programming the Related Registers ................................................................. 70 Timer Programming Process/Steps .................................................................. 70 PWM Cascade Mode ........................................................................................ 70 Product Specification (V1.1) 02.09.2015 Contents 7.10 Comparator .................................................................................................... 71 7.11 Oscillator ........................................................................................................ 74 7.11.3 External RC Oscillator Mode............................................................................. 78 7.11.4 Internal RC Oscillator Mode .............................................................................. 79 7.12 Power-on Considerations ............................................................................... 79 7.12.1 Programmable WDT Time-out Period ............................................................... 79 7.12.2 External Power-on Reset Circuit ....................................................................... 80 7.12.3 Residual Voltage Protection .............................................................................. 80 7.13 Code Option ................................................................................................... 81 7.13.1 7.13.2 7.13.3 7.13.4 7.13.5 7.13.6 Code Option Register (Word 0) ....................................................................... 81 Code Option Register (Word 1) ....................................................................... 83 Code Option Register (Word 2) ....................................................................... 84 Code Option Register (Word 3) ....................................................................... 85 Customer ID Register (Word 0x10) ................................................................... 85 Customer ID Register (Word 0x11) ................................................................... 85 7.14 Low Voltage Detector/Low Voltage Reset ....................................................... 86 7.14.1 Low Voltage Reset ............................................................................................ 86 7.14.2 Low Voltage Detector ........................................................................................ 86 7.14.3 Programming Process ...................................................................................... 88 7.15 Instruction Set ................................................................................................ 89 8 Absolute Maximum Ratings .................................................................................. 91 9 DC Electrical Characteristics ................................................................................ 91 9.1 9.2 AD Converter Characteristics ......................................................................... 93 Comparator Characteristics ............................................................................ 94 9.3 OP Characteristics .......................................................................................... 94 9.4 Vref 2V/2.5V/3V/4V Characteristics ................................................................ 95 10 AC Electrical Characteristics ................................................................................ 96 11 Timing Diagrams ................................................................................................... 97 Product Specification (V1.1) 02.09.2015 v Contents APPENDIX A Package Type ......................................................................................................... 98 B Packaging Configuration ...................................................................................... 99 B.1 EM78P372KD14 ............................................................................................. 99 B.2 EM78P372KSO14 ........................................................................................ 100 B.3 EM78P372KSO16A ...................................................................................... 101 B.4 EM78P372KD18 ........................................................................................... 102 B.5 EM78P372KSO18 ........................................................................................ 103 B.6 EM78P372KD20 ........................................................................................... 104 B.7 EM78P372KSO20 ........................................................................................ 105 B.8 EM78P372KSS20......................................................................................... 106 B.9 EM78P372KMS10 ........................................................................................ 107 B.10 EM78P372KQN16 ........................................................................................ 108 Specification Revision History Version Revision Description Date 0.1 Preliminary version 2014/06/11 1.0 Initial release version 2014/09/30 1. Modified the Pin Description 2. Modified the Program Counter Organization and the description in 1.1 Section 7.1.3. 2015/02/09 3. Deleted the Block Diagram of ADC in Section 7.1.9. 4. Modified the description about Bank 1 R6 Control Register. vi Product Specification (V1.1) 02.09.2015 EM78P372K 8-bit Microcontroller 1 General Description The EM78P372K is an 8-bit microprocessor designed and developed with low-power and high-speed CMOS technology. The device has an on-chip 2K13-bit Electrical One Time Programmable Read Only Memory (OTP-ROM). It provides a protection bit to prevent intrusion of user’s OTP memory code. Three Code option bits are also available to meet user’s requirements. With enhanced OTP-ROM features, the EM78P372K provides a convenient way of developing and verifying user’s programs. Moreover, this OTP device offers the advantages of easy and effective program updates, using development and programming tools. User can avail of the ELAN Writer to easily program his development code. 2 Features CPU configuration 2K13 bits on-chip ROM 808 bits on-chip registers (SRAM) 8-level stacks for subroutine nesting 4 programmable Level Voltage Detector (LVD) : 4.5V, 4.0V, 3.3V, 2.2V Three programmable Level Voltage Reset (LVR) : 4.0V, 3.5V, 2.7V Less than 1.5 mA at 5V/4 MHz Typically 15 A, at 3V/32kHz Typically 2 A, during sleep mode I/O port configuration Three bidirectional I/O ports: P5, P6, P7 18 I/O pins Wake-up ports : P5, P70, P71 8 programmable pull-down I/O pins 16 programmable pull-high I/O pins 8 programmable open-drain I/O pins 14 high driver I/O pins 14 high sink I/O pins External interrupt : P60 Operating voltage range: 2.1V~5.5V at 0C~70C (commercial) 2.3V~5.5V at -40C~85C (industrial) 8-bit real time clock/counter (TCC) with selective signal sources, trigger edges, and overflow interrupt 8-bit multi-channel Analog-to-Digital Converter with 12-bit resolution in Vref mode Two Pulse Width Modulation (PWM) with 8-bit resolution. One pair of comparator or OP (offset voltage: smaller than 10mV) Ten available interrupts TCC overflow interrupt Input-port status changed interrupt (wake up from sleep mode) External interrupt ADC completion interrupt Comparator status change interrupt Low voltage detect (LVD) interrupt PWM period match interrupt PWM duty match interrupt Special Features: Programmable free running Watchdog Timer (4.5ms, 18ms) Power saving Sleep mode Selectable Oscillation mode Power-on voltage detector available (1.9V 0.2V) High EFT immunity (better performance at 4 MHz or below) Operating frequency range (based on 2 clocks): Crystal mode: DC ~ 16 MHz, 3.0V; DC ~ 8 MHz, 2.5V; DC ~ 4 MHz, 2.1V ERC mode: DC ~ 2 MHz, 2.1V; IRC mode Oscillation mode: 4 MHz, 16 MHz, 8 MHz, 1 MHz Drift Rate Internal RC Frequency Peripheral configuration Package Type: 10-pin MSOP 118mil : EM78P372KMS10J/S 14-pin DIP 300mil : EM78P372KD14J/S 14-pin SOP 150mil : EM78P372KSO14J/S 16-pin SOP 150mil : EM78P372KSO16AJ/S Temperature (-40°C~85°C) Voltage (2.1V~5.5V) Process 4 MHz ±2% ±1% ±1% ±4% 18-pin DIP 300mil : EM78P372KD18J/S 16 MHz ±2% ±1% ±1% ±4% 18-pin SOP 300mil : EM78P372KSO18J/S 8 MHz ±2% ±1% ±1% ±4% 20-pin DIP 300mil : EM78P372KD20J/S 1 MHz ±2% ±1% ±1% ±4% 20 pin SOP 300mil : EM78P372KSO20J/S 20 pin SSOP 209mil : EM78P372KSS20J/S 16-pin QFN 3×3×0.8mm : EM78P372KQN16S Total Fast set-up time requires only 0.8ms (VDD: 5V Crystal: 4 MHz, C1/C2: 30pF) in HXT2 mode and 10s in IRC mode (VDD: 5V, IRC: 4 MHz) Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) Note: These are Green products which do not contain hazardous substances. 1 EM78P372K 8-bit Microcontroller 3 4 2 Applications Charger Washing machine Control board of an air conditioner Toaster Electromagnetic-stove Coffee pot Pin Assignment (Package) Figure 4-1 EM78P372KD14/SO14 Figure 4-2 EM78P372KSO16A Figure 4-3 EM78P372KD18/SO18 Figure 4-4 EM78P372KD20/SO20/SS20 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller P55/ADC6/OSCO/ERCin P65/CIN+ P50/ADC0 P64/CO P51/ADC1/PWM2 P61 P60//INT P52/ADC2/PWM2A Figure 4-5 EM78P372KMS10 Figure 4-6 EM78P372KQN16S Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 3 EM78P372K 8-bit Microcontroller 5 Block Diagram Figure 5-1 Functional Block Diagram 4 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller 6 Pin Description Name Input Type Output Type P50 ST CMOS ADC0 AN P51 ST CMOS ADC1 AN PWM2 CMOS PWM2 output P52 ST CMOS Bidirectional I/O pin with programmable pull-down, pull-high, high-driver, high-sink and pin change wake-up. ADC2 AN CMOS Inverse PWM2 output P53 ST CMOS Bidirectional I/O pin with programmable pull-down, pull-high, high-driver, high-sink and pin change wake-up. ADC3 AN CMOS Inverse PWM1 output P54 ST CMOS Bidirectional I/O pin with programmable pull-down, pull-high, high-driver, high-sink and pin change wake-up. TCC ST Real Time Clock/Counter clock input VREF AN ADC external voltage reference P55 ST CMOS ADC6 AN OSCO ERCin AN P56 ST CMOS Bidirectional I/O pin with programmable pull-down, pull-high, high-driver, high-sink and pin change wake-up. P57 ST CMOS Bidirectional I/O pin with programmable pull-down, pull-high, high-driver, high-sink and pin change wake-up. ADC7 ST Function P50 P51 P52 PWM2A P53 PWM1A P54 P55 P56 XTAL P57 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) Description Bidirectional I/O pin with programmable pull-down, pull-high and pin change wake-up. ADC Input 0 Bidirectional I/O pin with programmable pull-down, pull-high, high-driver, high-sink and pin change wake-up. ADC Input 1 ADC Input 2 ADC Input 3 Bidirectional I/O pin with programmable pull-down, pull-high and pin change wake-up. ADC Input 6 Clock output of crystal/ resonator oscillator External RC input pin ADC Input 7 5 EM78P372K 8-bit Microcontroller Name Input Type Output Type P60 ST CMOS /INT ST P61~P63 ST CMOS P64 CMOS CO ST P65 ST CMOS CIN+ ST P66 ST CMOS CIN- ST P67 ST CMOS ADC4 AN PWM1 CMOS P70 P70 Bidirectional I/O pin ADC5 AN ADC Input 5 OSCI XTAL Clock input of crystal/ resonator oscillator CMOS Clock output of internal RC oscillator Clock output of external RC oscillator (open-drain) P71 ST CMOS Bidirectional I/O pin (open-drain) /RESET ST System reset pin (should be external pull-high) Function P60//INT P61~P63 P64/CO P65/CIN+ P66/CIN- P67/ADC4/PWM1 P70/ADC5/OSCI/ RCOUT ROCUT P71//RESET Bidirectional I/O pin with programmable open-drain, pull-high, high-driver and high sink. External interrupt pin Bidirectional I/O pins with programmable open-drain, pull-high, high-driver and high sink. Bidirectional I/O pins with programmable open-drain, pull-high, high-driver and high sink. Comparator output Bidirectional I/O pins with programmable open-drain, pull-high, high-driver and high sink. Non-inverting end of comparator Bidirectional I/O pins with programmable open-drain, pull-high, high-driver and high sink. Inverting end of comparator Bidirectional I/O pins with programmable open-drain, pull-high, high-driver and high sink. ADC Input 4 PWM1 output VDD VDD Power Power VSS VSS Power Ground Legend: ST: Schmitt Trigger input AN: analog pin XTAL: oscillation pin for crystal/resonator 6 Description CMOS: CMOS output Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller 7 Functional Description 7.1 Operational Registers 7.1.1 R0 (Indirect Addressing Register) R0 is not a physically implemented register. Its major function is to perform as an indirect address pointer. Any instruction using R0 as a pointer, actually accesses the data pointed by the RAM Select Register (R4). 7.1.2 R1 (Timer Clock Counter) R1 is incremented by an external signal edge, which is defined by the TE bit (CONT-4) through the TCC pin, or by the internal clock (Fm/Fs). It is writable and readable as any other registers. It is defined by resetting PSTE (CONT-3). The prescaler is assigned to TCC, if the PSTE bit (CONT-3) is reset. The content of the prescaler counter is cleared only when the TCC register is written with a value. 7.1.3 R2 (Program Counter) and Stack Fig. 7-1 Program Counter Organization Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 7 EM78P372K 8-bit Microcontroller R2 and hardware stacks are 11-bit wide. The structure is depicted in the Data Memory Configuration (next page). Generates 2K13 bits on-chip ROM addresses to the relative programming instruction codes. One program page is 1024 words long. The contents of R2 are all set to "0"s when a RESET condition occurs. "JMP" instruction allows direct loading of the lower 10 program counter bits. Thus, "JMP" allows PC to jump to any location within a page. "CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the stack. Thus, the subroutine entry address can be located anywhere within a page. "LJMP" instruction allows direct loading of the program counter bits (A0 ~ A10). 11 Therefore, "LJMP" allows PC to jump to any location within 2K (2 ) "LCALL" instruction loads the program counter bits (A0 ~ A10), and then PC+1 is pushed into the stack. Thus, the subroutine entry address can be located anywhere 11 within 2K (2 ) "RET" ("RETL k", "RETI") instruction loads the program counter with the contents of the top of stack. "ADD R2, A" allows a relative address to be added to the current PC, and the ninth and above bits of the PC will increase progressively. "MOV R2, A" allows loading of an address from the "A" register to the lower 8 bits of the PC, and the ninth and above bits of the PC will remain unchanged. Any instruction (except “ADD R2, A”) that is written to R2 (e.g., "MOV R2, A", "BC R2, 6",) will cause the ninth bit and the above bits (A8 ~ A10) of the PC to remain unchanged. All instructions are single instruction cycle (fclk/2 or fclk/4) except for the instructions that are written to R2. 8 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller Register Register IOC IOC Bank 0 Bank 1 Page 0 Page1 Address 00 R0 (Indirect Addressing Register) 01 R1 (Timer Clock Counter) 02 R2 (Program Counter) 03 R3 (Status Register) 04 R4 (RSR,bank select) 05 R5 (Port 5 I/O data) R5 (TBHP: Table Point Register) IOC50 (Port 5 I/O control) IOC51 (HSCR1: High Sink Control Register 1) 06 R6 (Port 6 I/O data) R6 (TBLP: Table Point Register) IOC60 (Port 6 I/O control) IOC61 (HSCR2: High Sink Control Register 2) 07 R7 (Port 7 I/O data) R7 (PWMCON: PWM Control Register) IOC70 (Port 7 I/O control) IOC71 (HDCR1: High Driver Control Register 1) 08 R8 (ADC Input Select Register) R8 (TMRCON: Timer Control Register) IOC80 (Comparator Control Register) IOC81 (HDCR2: High Driver Control Register 2) 09 R9 (ADC Control Register) R9 (PRD1: PWM1 Time Period) IOC90 (TMR1: PWM1 Timer) IOC91 (DeadTCR:Dead Time Control Register) 0A RA (ADC Offset Calibration Register) RA (PRD2: PWM2 Time Period) IOCA1 (DeadTR:Dead Time IOCA0 (TMR2: PWM2 Timer) Register) 0B RB (Converted value AD11~AD4 of ADC) RB (DT1: PWM1 Duty Cycle) IOCB0 (Pull-down Control Register) IOCB1 (Reserved) 0C RC (Converted value AD11~AD8 of ADC) RC (DT2: PWM2 Duty Cycle) IOCC0 (Open-drain Control Register) IOCC1 (Reserved) 0D RD (Converted value AD7~AD0 of ADC) RD ( Reserved ) IOCD0 (Pull-high Control Register) IOCD1 (Reserved) 0E RE (Interrupt Status 2 and Wake-up Control Register1) RE (LVD Control and Wake-up Control Register2) 0F RF (Interrupt Status Register 1) RF (Mode Select and IRC Switch Register) IOCE0 (WDT Control Register and Interrupt Mask Register 2) IOCF0 (Interrupt Mask Register 1) IOCE1 (Reserved) IOCF1 (Pull-high Control Register) 10 : 16 - Byte Commo n R egister 1F 20 : 3F Bank 0 32 x 8 Bank 1 32 x 8 Fig. 7-2 Data Memory Configuration Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 9 EM78P372K 8-bit Microcontroller 7.1.4 R3 (Status Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RST IOCS - T P Z DC C Bit 7 (RST): Bit of reset type Set to “1” if wake-up from sleep on pin change, comparator status change, External interrupt, Low Voltage Detector interrupt, or AD conversion completed. Set to “0” if wake-up from other reset types. Bit 6 (IOCS): Select the Segment of I/O control register 0 : Segment 0 (IOC50 ~ IOCF0) selected 1 : Segment 1 (IOC51 ~ IOCF1) selected Bit 5: Not used, set “0” at all the time. Bit 4 (T): Time-out bit. Set to “1” by the "SLEP" and "WDTC" commands or during power on, and reset to “0” by WDT time-out (for more details see Section 6.5.2, The T and P Status under Status Register). Bit 3 (P): Power-down bit. Set to “1” during power-on or by a "WDTC" command and reset to “0” by a "SLEP" command (see Section 6.5.2, The T and P Status under Status Register for more details). Bit 2 (Z): Zero flag. Set to "1" if the result of an arithmetic or logic operation is zero. Bit 1 (DC): Auxiliary carry flag Bit 0 (C): Carry flag 7.1.5 R4 (RAM Select Register) Bit 7 (SBANK):Special Register 0X05~0X0F Bank Selection Bit. 0 : SBANK 0 1 : SBANK 1 Bit 6: Used to select Bank 0 ~ Bank 1 of the register. Bits 5~0: Used to select a register (Address: 00~0F, 10~3F) in indirect addressing mode. 10 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller 7.1.6 Bank 0 R5~R7 (Ports 5~7 I/O Data Register) R5~R6 and P70, P71 are I/O registers. 7.1.7 Bank 0 R8 (ADC Input Select Register) The AISR register individually defines the I/O Port as analog input or as digital I/O. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 Bit 7 (ADE7): AD converter enable bit of P57 pin 0 = Disable ADC7, P57 functions as I/O pin 1 = Enable ADC7 to function as analog input pin Bit 6 (ADE6): AD converter enable bit of P55 pin 0 = Disable ADC6, P55 functions as I/O pin 1 = Enable ADC6 to function as analog input pin Bit 5 (ADE5): AD converter enable bit of P70 pin 0 = Disable ADC5, P70 functions as I/O pin 1 = Enable ADC5 to function as analog input pin Bit 4 (ADE4): AD converter enable bit of P67 pin 0 = Disable ADC4, P67 functions as I/O pin 1 = Enable ADC4 to function as analog input pin Bit 3 (ADE3): AD converter enable bit of P53 pin 0 = Disable ADC3, P53 functions as I/O pin 1 = Enable ADC3 to function as analog input pin Bit 2 (ADE2): AD converter enable bit of P52 pin 0 = Disable ADC2, P52 functions as I/O pin 1 = Enable ADC2 to function as analog input pin Bit 1 (ADE1): AD converter enable bit of P51 pin 0 = Disable ADC1, P51 functions as I/O pin 1 = Enable ADC1 to function as analog input pin Bit 0 (ADE0): AD converter enable bit of P50 pin 0 = Disable ADC0, P50 functions as I/O pin 1 = Enable ADC0 to function as analog input pin Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 11 EM78P372K 8-bit Microcontroller NOTE The P55/ADC6/OSCO/ERCin pin cannot be applied to OSCO and ADC6 at the same time. If P55/ADC6/OSCO/ERCin functions as OSCO oscillator input pin, then ADE6 bit for R8 must be “0” and ADIS2~0 do not select “110”. The P55/ADC6/OSCO/ERCin pin priority is as follows: P55/ADC6/OSCO/ERCin Pin Priority High Medium Low OSCO/ERCin ADC6 P55 The P70/ADC5/OSCI/RCOUT pin cannot be applied to OSCI and ADC5 at the same time. If P70/ADC5/OSCI/RCOUT acts as OSCI oscillator input pin, then ADE5 bit for R8 must be “0” and ADIS2~0 do not select “101”. The P70/ADC5/OSCI/RCOUT pin priority is as follows: P70/ADC5/OSCI/RCOUT Pin Priority High Medium Low OSCI/RCOUT ADC5 P70 The P67/ADC4/PWM1 pin cannot be applied to PWM1 and ADC4 at the same time. If P67/ADC4/PWM1 functions as ADC4 analog input pin, The P67/ADC4/PWM1 pin priority is as follows: P67/ADC4/PWM1 Pin Priority High Medium Low ADC4 PWM1 P67 The P51/ADC1/PWM2 pin cannot be applied to PWM2 and ADC1 at the same time. If P51/ADC1/PWM2 functions as ADC1 analog input pin, The P51/ADC1/PWM2 pin priority is as follows: P51/ADC1/PWM2 Pin Priority High Medium ADC1 Low PWM2 P51 The P50/ADC0 pin cannot be applied to and ADC0 at the same time. If P50/ADC0 functions as ADC0 analog input pin, The P50/ADC0 pin priority is as follows: P50/ADC0 Pin Priority High Low ADC0 12 P50 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller 7.1.8 Bank 0 R9 (ADC Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 VREFS CKR1 CKR0 ADRUN ADPD ADIS2 ADIS1 ADIS0 Bit 7 (VREFS): The input source of Vref of the ADC 0: The Vref of the ADC is connected to internal reference voltage (default value), and the P54/TCC/VREF pin carries out the function of P54. 1: The Vref of the ADC is connected to P54/TCC/VREF NOTE The P54/TCC/VREF pin cannot be applied to TCC and VREF at the same time. If P54/TCC/VREF functions as VREF analog input pin, then CONT Bit 5 “TS” must be “0”. The VREF/TCC/P54 Pin Priority is as follows: P54/TCC/VREF Pin Priority High Medium Low VREF TCC P54 Bit 6 and Bit 5 (CKR1 and CKR0): The prescaler of ADC oscillator clock rate CPUS CKR1 : CKR0 Operation Mode Max. Operation Frequency ( if TAD=4µs, match 372N ) Max. Operation Frequency ( if TAD=1µs, match 372N ) 1 1 1 1 0 00 (default) 01 10 11 FOSC/16 FOSC/4 FOSC/64 FOSC/1 - 4 MHz 1 MHz 16 MHz 16K/128kHz 16 MHz 4 MHz 1 MHz 16K/128kHz Bit 4 (ADRUN): ADC starts to RUN 0: Reset upon completion of the conversion. This bit cannot be reset through software 1: AD conversion is started. This bit can be set by software Bit 3 (ADPD): ADC Power-down mode 0: Switch off the resistor reference to save power even while the CPU is operating. 1: ADC is operating Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 13 EM78P372K 8-bit Microcontroller Bits 2 ~ 0 (ADIS2 ~ ADIS0): Analog Input Select 7.1.9 ADICS ADIS2 ADIS1 ADIS0 Analog Input Select 0 0 0 0 ADC0 / P50 0 0 0 1 ADC1 / P51 0 0 1 0 ADC2 / P52 0 0 1 1 ADC3 / P53 0 1 0 0 ADC4 / P67 0 1 0 1 ADC5 / P70 0 1 1 0 ADC6 / P55 0 1 1 1 ADC7 / P57 1 0 x x Internal ADC Channel Select: OPOUT 1 1 0 0 Internal ADC Channel Select: 1/4 VDD 1 1 0 1 Internal ADC Channel Select: 1/2 VDD 1 1 1 0 Reserved 1 1 1 1 Reserved Bank 0 RA (ADC Offset Calibration Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CALI SIGN VOF[2] VOF[1] VOF[0] VREF1 VREF0 ADICS Bit 7 (CALI): Calibration enable bit for ADC offset 0: Disable the Calibration 1: Enable the Calibration Bit 6 (SIGN): Polarity bit of offset voltage 0: Negative voltage 1: Positive voltage Bit 5 ~ Bit 3 (VOF[2] ~ VOF[0]): Offset voltage bits 14 VOF[2] VOF[1] VOF[0] EM78P372K 0 0 0 0 LSB 0 0 1 2 LSB 0 1 0 4 LSB 0 1 1 6 LSB 1 0 0 8 LSB 1 0 1 10 LSB 1 1 0 12 LSB 1 1 1 14 LSB Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller Bits 2 ~ 1 (VREF1 ~ VREF0): ADC internal reference voltage source. VREFSEL in Option Word 3 Bit 11 VREF[1] VREF[0] ADC Int. Ref. Volt 0 0 0 VDD 0 0 1 4.0V ± 1% 0 1 0 3.0V ± 1% 0 1 1 2.5V ± 1% 1 0 0 VDD 1 0 1 4.0V ± 1% 1 1 0 3.0V ± 1% 1 1 1 2.0V ± 1% If VREF[1:0]＝00, internal reference does not turn on. If VREF[1:0]≠00, internal reference will turn on automatically. Moreover, the power of internal reference is irrelevant to power of ADC. That means one of VREF[1:0] is set, the internal reference turns on. If VREF[1:0]＝11, internal reference will turn on by code option selected with VREF 2.0V or VREF 2.5V. Bit 0 (ADICS): ADC internal channel select. (Select ADC internal 1/4 VDD or OP output pin connects to ADC input) 0 = Disable 1 = Enable 7.1.10 Bank 0 RB (Converted value AD11~AD4 of ADC) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 When AD conversion is completed, the result is loaded into the ADDATA. The ADRUN bit is cleared and the ADIF is set. RB is read only. 7.1.11 Bank 0 RC (Converted value AD11~AD8 of ADC) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - - - AD11 AD10 AD9 AD8 When AD conversion is completed, the result is loaded into the ADDATA1H. The ADRUN bit is cleared and the ADIF is set. RC is read only. Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 15 EM78P372K 8-bit Microcontroller 7.1.12 Bank 0 RD (Converted value AD7~AD0 of ADC) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 When AD conversion is completed, the result is loaded into the ADDATA1L. The ADRUN bit is cleared and the ADIF is set. RD is read only 7.1.13 Bank 0 RE (Interrupt Status 2 and Wake-up Control Register 1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 /LVD LVDIF ADIF CMP1IF ADWE CMPWE ICWE LVDWE Note: 1. RE <5, 4> can be cleared by instruction but cannot be set. 2. IOCE0 is the interrupt mask register. 3. Reading RE will result to “Logic AND” of the RE and IOCE0. Bit 7 (/LVD): Low voltage Detector state. This is a read only bit. When the VDD pin voltage is lower than LVD voltage interrupt level (selected by LVD1 and LVD0), this bit will be cleared. 0 : Low voltage is detected 1 : Low voltage is not detected or LVD function is disabled Bit 6 (LVDIF): Low Voltage Detector Interrupt flag LVDIF is reset to “0” by software. Bit 5 (ADIF): Interrupt flag for Analog to Digital conversion. Set when AD conversion is completed. Reset by software. 0 : no interrupt occurs 1 : with interrupt request Bit 4 (CMP1IF): Comparator 1 Interrupt flag. Set when a change occurs in the Comparator 1 output. Reset by software. 0 : no interrupt occurs 1 : with interrupt request Bit 3 (ADWE): ADC wake-up enable bit 0 : Disable ADC wake-up 1 : Enable ADC wake-up When AD Conversion enters sleep/idle mode, this bit must be set to “Enable”. 16 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller Bit 2 (CMPWE): Comparator wake-up enable bit 0 : Disable Comparator wake-up 1: Enable Comparator wake-up When Comparator 1 enters sleep/idle mode, this bit must be set to “Enable”. Bit 1 (ICWE): Port 5, P70, and P71 input change to wake-up status enable bit 0 : Disable Port 5, P70, P71 input change to wake-up status 1 : Enable Port 5, P70, P71 input change to wake-up status When Port 5, P70, P71 change enters sleep/idle mode, this bit must be set to “Enable”. Bit 0 (LVDWE): Low Voltage Detect wake-up enable bit 0 : Disable Low Voltage Detect wake-up 1 : Enable Low Voltage Detect wake-up When the Low Voltage Detect is used to enter an interrupt vector or to wake-up the IC from sleep/idle with Low Voltage Detect running, the LVDWE bit must be set to “Enable”. Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 17 EM78P372K 8-bit Microcontroller 7.1.14 Bank 0 RF (Interrupt Status Register 1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P7ICIF DT2IF DT1IF PWM2IF PWM1IF EXIF ICIF TCIF Note: 1. “1” means there is an interrupt request, “0” means no interrupt occurs. 2. RF can be cleared by instruction but cannot be set. 3. IOCF0 is the interrupt mask register. 4. Reading RF will result to “Logic AND” of the RF and IOCF0. Bit 7 (P7ICIF): Port 7 input status change interrupt flag. Set when Port 7 input changes. Reset by software. Bit 6 (DT2IF): PWM2 duty match interrupt flag. Reset by software. Bit 5 (DT1IF): PWM1 duty match interrupt flag. Reset by software. Bit 4 (PWM2IF): PWM2 period match interrupt flag. Reset by software. Bit 3 (PWM1IF): PWM1 period match interrupt flag. Reset by software. Bit 2 (EXIF): External interrupt flag. Set by falling edge on /INT pin. Reset by software. Bit 1 (ICIF): Port 5 input status change interrupt flag. Set when Port 5 input changes. Reset by software. Bit 0 (TCIF): TCC overflow interrupt flag. Set when TCC overflows. Reset by software. 7.1.15 Bank 1 R5 (TBHP: Table Point Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MLB TRS - - - RBit10 RBit9 RBit8 Bit 7 (MLB): Choosing MSB or LSB machine code to be moved to the register. The machine code is pointed by TBLP and TBHP register. Bit 6 (TRS): Table Read Select 0: read ROM 1: read Customer ID Register NOTE When TRS = 1 (read Customer ID Register) ■ Can read Customer ID Register II, III (Word 0x10 or Word 0x11) ■ Cannot read Customer ID Register I (Word 2) ■ Don’t care RBit10 ~ RBit3 Bits 5~3: Not used, set to “0” at all time. Bits 2 ~ 0: These are the most 3 significant bits of address for program code. 18 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller 7.1.16 Bank 1 R6 (TBLP: Table Point Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RBit7 RBit6 RBit5 RBit4 RBit3 RBit2 RBit1 RBit0 Bits 7 ~ 0 (RBit7~RBit0): Table point low byte bits. When TRS = 0 (Read ROM): RBit7~RBit6 are the least 8 significant bits of address for program code. When TRS = 1 (Read Customer ID Register): RBit7 RBit6 RBit5 RBit4 RBit3 RBit2 RBit1 RBit0 Customer ID x x x x x 0 0 0 Word 0x10 x x x x x 0 0 1 Word 0x11 x x x x x 0 1 x Reserved x x x x x 1 x x Reserved NOTE ■ Bank 1 R6 overflow will carry to Bank 1 R5. ■ Bank 1 R6 underflow will borrow from Bank 1 R5. 7.1.17 Bank 1 R7 (PWMCON: PWM Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IPWM2E IPWM1E - - - PWMCAS PWM2E PWM1E Bit 7 (IPWM2E): Inverse PWM2 Enable bit 0: Inverse PWM2 is off (default value), and its related pin carries out the P52 function. 1: Inverse PWM2 is on, and its related pin is automatically set to output. Bit 6 (IPWM1E): Inverse PWM1 Enable bit 0: Inverse PWM1 is off (default value), and its related pin carries out the P53 function. 1: Inverse PWM1 is on, and its related pin is automatically set to output. Bits 5 ~ 3: Not used Bit 2 (PWMCAS): PWM Cascade Mode 0: Two Independent 8-bit PWM function (default value) 1: 16-bit PWM Mode (Cascaded from two 8-bit PWM function) Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 19 EM78P372K 8-bit Microcontroller Bit 1 (PWM2E): PWM2 Enable bit 0: PWM2 is off (default value), and its related pin carries out the P67 function. 1: PWM2 is on, and its related pin is automatically set to output. Bit 0 (PWM1E): PWM1 Enable bit 0: PWM1 is off (default value), and its related pin carries out the P51 function. 1: PWM1 is on, and its related pin is automatically set to output. 7.1.18 Bank 1 R8 (TMRCON: Timer Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 T2EN T1EN T2P2 T2P1 T2P0 T1P2 T1P1 T1P0 Bit 7 (T2EN): TMR2 Enable bit 0: TMR2 is off (default value) 1: TMR2 is on Bit 6 (T1EN): TMR1 Enable bit 0: TMR1 is off (default value) 1: TMR1 is on Bit 5 ~ Bit 3 (T2P2 ~ T2P0): TMR2 clock prescaler option bits 20 T2P2 T2P1 T2P0 Prescaler 0 0 0 1:1 (default) 0 0 1 1:2 0 1 0 1:4 0 1 1 1:8 1 0 0 1:16 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller Bit 2 ~ Bit 0 (T1P2 ~ T1P0): TMR1 clock prescaler option bits T1P2 T1P1 T1P0 Prescaler 0 0 0 1:1 (default) 0 0 1 1:2 0 1 0 1:4 0 1 1 1:8 1 0 0 1:16 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 7.1.19 Bank 1 R9 (PRD1: PWM1 Time Period) The content of Bank 1-R9 is the time period (time base) of PWM1. The frequency of PWM1 is the reverse of the period. 7.1.20 Bank 1 RA (PRD2: PWM2 Time Period) The content of Bank 1-RA is the time period (time base) of PWM2. The frequency of PWM2 is the reverse of the period. 7.1.21 Bank 1 RB (DT1: PWM1 Duty Cycle) A specified value keeps the output of PWM1 to remain high until the value matches with TMR1. 7.1.22 Bank 1 RC (DT2: PWM2 Duty Cycle) A specified value keeps the output of PWM2 to remain high until the value matches with TMR2. 7.1.23 Bank 1 RE (LVD Control and Wake-up Control Register 2) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LVDIE LVDEN LVD1 LVD0 - - - EXWE Bit 7 (LVDIE): Low voltage Detector interrupt enable bit 0 : Disable Low voltage Detector interrupt 1 : Enable Low voltage Detector interrupt When detect low level voltage is used to enter an interrupt vector or enter the next instruction, the LVDIE bit must be set to “Enable”. Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 21 EM78P372K 8-bit Microcontroller Bit 6 (LVDEN): Low Voltage Detector enable bit 0 : Low voltage detector disable 1 : Low voltage detector enable Bits 5~4 (LVD1:0): Low Voltage Detector level bits. LVDEN LVD1, LVD0 1 11 1 10 1 LVD Voltage Interrupt Level /LVD Vdd 2.2V 0 Vdd 2.2V Vdd 3.3V 1 0 Vdd 3.3V 1 Vdd 4.0V 0 Vdd 4.0V 1 Vdd 4.5V 0 Vdd 4.5V 1 NA 1 01 1 00 0 XX Bits 3~1: Not used, set to “0” at all time. Bit 0 (EXWE): External /INT wake-up enable bit 0: Disable External /INT pin wake-up 1: Enable External /INT pin wake-up 7.1.24 Bank 1 RF (Mode Select and IRC Switch Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - TIMERSC CPUS IDLE SHS1 SHS0 RCM1 RCM0 Bit 7: Not used. Set “0” all the time. Bit 6 (TIMERSC): TCC, PWM1, PWM2 clock sources select 0/1 Fs/Fm* 0 : Fs: Sub-oscillator clock from WDT 16kHz ± 30% or System hold RC 128kHz ± 30% (determined by Word 2 SFS bit) 1 : Fm: main-oscillator clock Bit 5 (CPUS): CPU Oscillator Source Select 0 : Sub-oscillator (Fs) 1 : Main-oscillator (Fm) When CPUS=0, the CPU oscillator selects the sub-oscillator and the main oscillator is stopped. Bit 4 (IDLE): Idle Mode Enable Bit. From SLEP instruction, this bit will determine as to which mode to go. 0 : Idle= “0”+SLEP instruction sleep mode 1 : Idle= “1”+SLEP instruction idle mode 22 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller Bits 3 ~ 2 (SHS1~0): Select AD sample and hold period. SHS1 SHS0 AD Sample and Hold Period (TAD) 0 0 2 0 1 4 1 0 8 1 1 12 (default) CPU Operation Mode Figure 7-5 CPU Operation Mode ( *) If the Watchdog function is enabled before going into sleep mode, some circuits like the Timer (its clock source is Fs) must stop counting. If the Watchdog function is enabled before going into sleep mode, some circuits like the Timer (its clock source is an external pin) can still count and its Interrupt flag can be active at matching conditions, as corresponding interrupt is enabled. But CPU cannot be awakened by this event. (**) Switching Operation Mode from Sleep Normal, Green Normal If the clock source of the Timer is Fm, the Timer/Counter must stop counting at Sleep or Green mode. Then the Timer can continue to count until the clock source is stable at Normal mode. That the clock source is stable means that the CPU starts to work at Normal mode. Switching Operation Mode from Sleep Green If the clock source of the Timer is Fs, the Timer must stop counting at Sleep mode. Then the Timer can continue to count until the clock source is stable at Green mode. That the clock source is stable means that the CPU starts to work at Green mode. Switching Operation Mode from Sleep Normal If the clock source of the Timer is Fs, the Timer must stop counting at Sleep mode. Then the Timer can continue to count until the clock source is stable at Normal mode. That the clock source is stable means that the CPU starts to work at Normal mode. Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 23 EM78P372K 8-bit Microcontroller NOTE ■ Crystal MOD1 for LXT1, XT, HXT2, HXT1: Sleep Normal = Oscillator Stable Time + 510 clock (main frequency). Sleep Green = Oscillator Stable Time + 8 clock (sub frequency). Green Normal = Oscillator Stable Time + 510 clock (main frequency) NOTE ■ Crystal MOD2 for LXT2 : Sleep Normal = Oscillator Stable Time + 254 clock (main frequency). Sleep Green = Oscillator Stable Time + 8 clock (sub frequency). Green Normal = Oscillator Stable Time + 254 clock (main frequency) ■ IRC MOD : Sleep Normal = Oscillator Stable Time + 8 or 32 clock (main frequency). Sleep Green = Oscillator Stable Time + 8 clock (sub frequency). Green Normal = Oscillator Stable Time + 8 clock (main frequency) Bits 3~2: Not used, set to “0” at all time. Bits 1~0 (RCM1: 0): IRC mode selection bits RCM 1 RCM 0 *Frequency(MHz) 1 1 4 1 0 16 0 1 8 0 0 1 NOTE ■ Word 2<11> COBS0=0 : Bank1 RF<1~0> of the initialized values will be kept the same as Word 1<6~5>. Bank1 RF<1~0> cannot change ■ Word 2<11> COBS0=1 : Bank1 RF<1~0> of the initialized values will be kept the same as Word 1<6~5>. Bank1 RF<1~0> can change, When user wants to work on other IRC frequency. Stable time is 8 clocks 7.1.25 R10~R1F All of these are 8-bit general-purpose registers. 24 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller 7.2 Special Purpose Registers 7.2.1 A (Accumulator) Internal data transfer operation, or instruction operand holding usually involves the temporary storage function of the Accumulator, which is not an addressable register. 7.2.2 CONT (Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTE INT TS TE PSTE PST2 PST1 PST0 Note: The CONT register is both readable and writable. Bit 6 is read only. Bit 7 (INTE): INT signal edge 0 : Interrupt occurs at a rising edge of the INT pin 1 : Interrupt occurs at a falling edge of the INT pin Bit 6 (INT): Interrupt Enable flag 0 : Masked by DISI or hardware interrupt 1 : Enabled by the ENI/RETI instructions This bit is readable only. Bit 5 (TS): TCC signal source 0 : Internal instruction cycle clock. If P54 is used as I/O pin 1 : Transition on the TCC pin Bit 4 (TE): TCC signal edge 0 : Increment if the transition from low to high takes place on the TCC pin 1 : Increment if the transition from high to low takes place on the TCC pin. Bit 3 (PSTE): Prescaler enable bit for TCC 0 = prescaler disable bit. TCC rate is 1:1. 1 = prescaler enable bit. TCC rate is set at Bit 2 ~ Bit 0. Bit 2 ~ Bit 0 (PST2 ~ PST0): TCC prescaler bits PST2 PST1 PST0 TCC Rate 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1 1 1 1:256 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 25 EM78P372K 8-bit Microcontroller Note: 1 FT TCC Timeout period 256 TCC cnt 1 , where FT Fm or Fs , decide by BANK1 RF TIMERSC bit. 7.2.3 IOC50 ~ IOC70 (I/O Port Control Register) "0" defines the relative I/O pin as output "1" sets the relative I/O pin into high impedance 7.2.4 IOC80 (Comparator Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 – – CMPOUT COS1 COS0 – – – Note: Bits 4~0 of the IOC80 register are both readable and writable. Bit 5 of the IOC80 register is read only. Bit 7 and Bit 6: Not used Bit 5 (CMPOUT): Result of the comparator output. This bit is readable only. Bit 4 and Bit 3 (COS1 and COS0): Comparator/OP Select bits COS1 COS0 Function Description 0 0 Comparator and OP are not used. P64, P65, and P66 are normal I/O pins 0 1 P65 and P66 are Comparator input pins and P64 is a normal I/O pin 1 0 1 1 P65 and P66 are Comparator input pins and P64 is a Comparator output pin (CO) Used as OP and P64 is OP output pin (CO) Bits 2~0: Not used. 26 7.2.5 IOC90 (TMR1: PWM1 Timer) 7.2.6 IOCA0 (TMR2: PWM2 Timer) Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller 7.2.7 IOCB0 (Pull-down Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 /PD57 /PD56 /PD55 /PD54 /PD53 /PD52 /PD51 /PD50 The IOCB0 register is both readable and writable. Bit 7 (/PD57): Control bit used to enable internal pull-down of the P57 pin. 0 : Enable internal pull-down 1 : Disable internal pull-down Bit 6 (/PD56): Control bit used to enable internal pull-down of the P56 pin. Bit 5 (/PD55): Control bit used to enable internal pull-down of the P55 pin. Bit 4 (/PD54): Control bit used to enable internal pull-down of the P54 pin. Bit 3 (/PD53): Control bit used to enable internal pull-down of the P53 pin. Bit 2 (/PD52): Control bit used to enable internal pull-down of the P52 pin. Bit 1 (/PD51): Control bit used to enable internal pull-down of the P51 pin. Bit 0 (/PD50): Control bit used to enable internal pull-down of the P50 pin. 7.2.8 IOCC0 (Open-drain Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OD67 OD66 OD65 OD64 OD63 OD62 OD61 OD60 The IOCC0 register is both readable and writable. Bit 7 (OD67): Control bit used to enable open-drain output of the P67 pin. 0 : Disable open-drain output 1 : Enable open-drain output Bit 6 (OD66): Control bit used to enable open-drain output of the P66 pin. Bit 5 (OD65): Control bit used to enable open-drain output of the P65 pin. Bit 4 (OD64): Control bit used to enable open-drain output of the P64 pin. Bit 3 (OD63): Control bit used to enable open-drain output of the P63 pin. Bit 2 (OD62): Control bit used to enable open-drain output of the P62 pin. Bit 1 (OD61): Control bit used to enable open-drain output of the P61 pin. Bit 0 (OD60): Control bit used to enable open-drain output of the P60 pin. Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 27 EM78P372K 8-bit Microcontroller 7.2.9 IOCD0 (Pull-high Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 /PH57 /PH56 /PH55 /PH54 /PH53 /PH52 /PH51 /PH50 The IOCD0 register is both readable and writable. Bit 7 (/PH57): Control bit used to enable internal pull-high of the P57 pin. 0 = Enable internal pull-high 1 = Disable internal pull-high Bit 6 (/PH56): Control bit used to enable internal pull-high of the P56 pin. Bit 5 (/PH55): Control bit used to enable internal pull-high of the P55 pin. Bit 4 (/PH54): Control bit used to enable internal pull-high of the P54 pin. Bit 3 (/PH53): Control bit used to enable internal pull-high of the P53 pin. Bit 2 (/PH52): Control bit used to enable internal pull-high of the P52 pin. Bit 1 (/PH51): Control bit used to enable internal pull-high of the P51 pin. Bit 0 (/PH50): Control bit used to enable internal pull-high of the P50 pin. 28 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller 7.2.10 IOCE0 (WDT Control Register and Interrupt Mask Register 2) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WDTE EIS ADIE CMPIE PSWE PSW2 PSW1 PSW0 Bit 7 (WDTE): Control bit used to enable Watchdog Timer 0 : Disable WDT 1 : Enable WDT WDTE is both readable and writable. Bit 6 (EIS): Control bit used to define the function of the P60 (/INT) pin 0 : P60, bidirectional I/O pin 1 : /INT, external interrupt pin. In this case, the I/O control bit of P60 (Bit 0 of IOC60) must be set to "1". NOTE ■ When EIS is "0", the path of /INT is masked. When EIS is "1", the status of the /INT pin can also be read by way of reading Port 6 (R6). ■ EIS is both readable and writable. Bit 5 (ADIE): ADIF interrupt enable bit 0 : disable ADIF interrupt 1 : enable ADIF interrupt Bit 4 (CMPIE): CMPIF interrupt enable bit. 0 : disable CMPIF interrupt 1 : enable CMPIF interrupt Bit 3 (PSWE): Prescaler enable bit for WDT 0 : prescaler disable bit, WDT rate is 1:1 1 : prescaler enable bit, WDT rate is set as Bit 2 ~ Bit 0 Bit 2 ~ Bit 0 (PSW2 ~ PSW0): WDT prescaler bits PSW2 PSW1 PSW0 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) WDT Rate 29 EM78P372K 8-bit Microcontroller 7.2.11 IOCF0 (Interrupt Mask Register 1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P7ICIE DT2IE DT1IE PWM2IE PWM1IE EXIE ICIE TCIE Note: The IOCF0 register is both readable and writable. Individual interrupt is enabled by setting to “1” its associated control bit in the IOCF0 and in IOCEO Bits 4 and 5. Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. Bit 7 (P7ICIE): P7ICIF interrupt enable bit 0 : Disable ICIF interrupt 1 : Enable ICIF interrupt Bit 6 (DT2IE): DT2IE interrupt enable bit 0 : Disable DT2IF interrupt 1 : Enable DT2IF interrupt Bit 5 (DT1IE): DT1IE interrupt enable bit 0 : Disable DT1IF interrupt 1 : Enable DT1IF interrupt Bit 4 (PWM2IE): PWM2IE interrupt enable bit 0 : Disable PWM2IF interrupt 1 : Enable PWM2IF interrupt Bit 3 (PWM1IE): PWM1IE interrupt enable bit 0 : Disable PWM1IF interrupt 1 : Enable PWM1IF interrupt Bit 2 (EXIE): EXIF interrupt enable bit 0 : Disable EXIF interrupt 1 : Enable EXIF interrupt Bit 1 (ICIE): ICIF interrupt enable bit 0 : Disable ICIF interrupt 1 : Enable ICIF interrupt Bit 0 (TCIE): TCIF interrupt enable bit. 0 : Disable TCIF interrupt 1 : Enable TCIF interrupt 30 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller 7.2.12 IOC51 (HSCR1: High Sink Control Register 1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HS57 HS56 - HS54 HS53 HS52 HS51 - Bit 7 (HS57): Output High Sink Current Select for P57 Bit 6 (HS56): Output High Sink Current Select for P56 Bit 5: Not used Bit 4 (HS54): Output High Sink Current Select for P54 Bit 3 (HS53): Output High Sink Current Select for P53 Bit 2 (HS52): Output High Sink Current Select for P52 Bit 1 (HS51): Output High Sink Current Select for P51 Bit 0: Not used HDxx VDD = 5V, Sink Current 0 10 mA (in 0.1VDD) 1 25 mA (in 0.1VDD) 7.2.13 IOC61 (HSCR2: High Sink Control Register 2) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HS67 HS66 HS65 HS64 HS63 HS62 HS61 HS60 Bit 7 (HS67): Output High Sink Current Select for P67 Bit 6 (HS66): Output High Sink Current Select for P66 Bit 5 (HS65): Output High Sink Current Select for P65. Bit 4 (HS64): Output High Sink Current Select for P64 Bit 3 (HS63): Output High Sink Current Select for P63 Bit 2 (HS62): Output High Sink Current Select for P62 Bit 1 (HS61): Output High Sink Current Select for P61 Bit 0 (HS60): Output High Sink Current Select for P60 HDxx VDD = 5V, Sink Current 0 10 mA (in 0.1VDD) 1 25 mA (in 0.1VDD) Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 31 EM78P372K 8-bit Microcontroller 7.2.14 IOC71 (HDCR1: High Driver Control Register 1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HD57 HD56 - HD54 HD53 HD52 HD51 - Bit 7 (HD57): Output High Driver Current Select for P57 Bit 6 (HD56): Output High Driver Current Select for P56 Bit 5: Not used Bit 4 (HD54): Output High Driver Current Select for P54 Bit 3 (HD53): Output High Driver Current Select for P53 Bit 2 (HD52): Output High Driver Current Select for P52 Bit 1 (HD51): Output High Driver Current Select for P51 Bit 0: Not used HDxx VDD = 5V, Drive Current 0 3.7 mA (in 0.9VDD) 1 10 mA (in 0.9VDD) 7.2.15 IOC81 (HDCR2: High Driver Control Register 2) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HD67 HD66 HD65 HD64 HD63 HD62 HD61 HD60 Bit 7 (HD67): Output High Driver Current Select for P67 Bit 6 (HD66): Output High Driver Current Select for P66 Bit 5 (HD65): Output High Driver Current Select for P65 Bit 4 (HD64): Output High Driver Current Select for P64 Bit 3 (HD63): Output High Driver Current Select for P63 Bit 2 (HD62): Output High Driver Current Select for P62 Bit 1 (HD61): Output High Driver Current Select for P61 Bit 0 (HD60): Output High Driver Current Select for P60 32 HDxx VDD = 5V, Driver Current 0 3.7 mA (in 0.9VDD) 1 10 mA (in 0.9VDD) Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller 7.2.16 IOC91 (DeadTCR: Dead Time Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IPWM2A IPWM1A PWM2A PWM1A DEADT2E DEADT1E DEADTP1 DEADTP0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 7 (IPWM2A): Active level of inverse PWM2 0: period-duty-dead time is Logic 1 (default) 1: period-duty-dead time is Logic 0 Bit 6 (IPWM1A): Active level of inverse PWM1 0: period-duty-dead time is Logic 1 (default) 1: period-duty-dead time is Logic 0 Bit 5 (PWM2A): Active level of PWM2 0: duty-dead time is Logic 1 (default) 1: duty-dead time is Logic 0 Bit 4 (PWM1A): Active level of PWM1 0: duty-dead time is Logic 1 (default) 1: duty-dead time is Logic 0 Bit 3 (DEADT2E): Enable dead-time function for PWM2 and /PWM2 (for dual PWM) 0: Disable (default) 1: Enable Bit 2 (DEADT1E): Enable dead-time function for PWM1 and /PWM1 (for dual PWM) 0: Disable (default) 1: Enable Bits 1~0 (DEADTP1~DEADTP0): Dead-time prescaler DEADTP1 DEADTP0 Prescale 0 0 1:1 (default) 0 1 1:2 1 0 1:4 1 1 1:8 NOTE The dead time function is only for dual PWM. If used in single PWM function (not dual PWM), the dead time function is always disabled. Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 33 EM78P372K 8-bit Microcontroller 7.2.17 IOCA1 (DeadTR: Dead Time Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DEADTR7 DEADTR6 DEADTR5 DEADTR4 DEADTR3 DEADTR2 DEADTR1 DEADTR0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bits 7~0 (DEADTR7~0): The content of the register is dead-time. 7.2.18 IOCF1 (Pull-high Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 /PH67 /PH66 /PH65 /PH64 /PH63 /PH62 /PH61 /PH60 Note: The IOCD0 register is both readable and writable. Bit 7 (/PH67): Control bit used to enable pull-high of the P67 pin. 0 = Enable internal pull-high 1 = Disable internal pull-high Bit 6 (/PH66): Control bit used to enable internal pull-high of the P66 pin. Bit 5 (/PH65): Control bit used to enable internal pull-high of the P65 pin. Bit 4 (/PH64): Control bit used to enable internal pull-high of the P64 pin. Bit 3 (/PH63): Control bit used to enable internal pull-high of the P63 pin. Bit 2 (/PH62): Control bit used to enable internal pull-high of the P62 pin. Bit 1 (/PH61): Control bit used to enable internal pull-high of the P61 pin. Bit 0 (/PH60): Control bit used to enable internal pull-high of the P60 pin. 34 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller 7.3 TCC/WDT and Prescaler There are two 8-bit counters available as prescalers for the TCC and WDT respectively. The PST2 ~ PST0 bits of the CONT register are used to determine the ratio of the TCC prescaler, and the PSW2 ~ PSW0 bits of the IOCE0 register are used to determine the prescaler of WDT. The prescaler counter is cleared by the instructions each time such instructions are written into TCC. The WDT and prescaler will be cleared by the “WDTC” and “SLEP” instructions. Figure 7-3 depicts the block diagram of TCC/WDT. TCC (R1) is an 8-bit timer/counter. The TCC clock source can be an internal clock (Fm/Fs) or external signal input (edge selectable from the TCC pin). If TCC signal source is from the internal clock (Fm/Fs), TCC will increase by 1 at every Fm clock or Fs clock (without prescaler), decide by BANK1 RF TIMERSC bit. If TCC signal source is from an external clock input, TCC will increase by 1 at every falling edge or rising edge of the TCC pin. The TCC pin input time length (kept in High or Low level) must be greater than Fm clock or Fs clock, determined by Bank 1 RF CPUS bit. NOTE The internal TCC will stop running when in sleep mode. However, during AD conversion, when TCC is set to “SLEP” instruction, if the ADWE bit of the RE register is enabled, the TCC will keep on running. The watchdog timer is a free running on-chip RC oscillator. The WDT will keep on running even when the oscillator driver has been turned off (i.e., in sleep mode). During normal operation or in sleep mode, a WDT time-out (if enabled) will cause the device to reset. The WDT can be enabled or disabled any time during normal mode through software programming. With no prescaler, the WDT time-out period is approximately 1 2 18ms or 4.5ms . 1 2 VDD=5V, WDT time-out period = 16.5ms ± 30% VDD=3V, WDT time-out period = 18ms ± 30% VDD=5V, WDT time-out period = 4.2ms ± 30% VDD=3V, WDT time-out period = 4.5ms ± 30% Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 35 EM78P372K 8-bit Microcontroller Figure 7-6 TCC and WDT Block Diagram 36 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller 7.4 I/O Ports The I/O registers (Port 5, Port 6, and Port 7) are bidirectional tri-state I/O ports. Port 5 is pulled-high and pulled-down internally by software. Likewise, P6 has its open-drain output set through software. Port 5 features an input status changed interrupt (or wake-up) function. Each I/O pin can be defined as "input" or "output" pin by the I/O control register (IOC5 ~ IOC7). The I/O registers and I/O control registers are both readable and writable. The I/O interface circuits for Port 5, Port 6, and Port 7 are illustrated in Figures 7-7, 7-8, 7-9, and 7-10. PCRD Q PO R T P R D _ C LK Q C L Q P R PC W R IO D D _ C LK Q C L PDW R PD R D 0 1 M U X Note: Pull-high and Open-drain are not shown in the figure. Figure 7-7 I/O Port and I/O Control Register Circuit for Port 6 and Port 7 PCRD P Q R D _ CLK Q C L Q P R D _ CLK Q C L PORT Bit 6 of IOCE0 P R Q CLK _ C Q L D PCWR IOD PDWR 0 1 M U X PDRD INT Note: Pull-high and Open-drain are not shown in the figure. Figure 7-8 I/O Port and I/O Control Register Circuit for P60 (/INT) Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 37 EM78P372K 8-bit Microcontroller PCRD Q P R D _ CLK Q C L PCWR P50 ~ P57 Q PORT 0 P R D _ CLK Q C L IOD PDWR M U X 1 PDRD TI n D P R CLK C L Q _ Q Note: Pull-high (down) and Open-drain are not shown in the figure. Figure 7-9 I/O Port and I/O Control Register Circuit for Ports 50~57 I O C F.1 R F.1 TI 0 TI 1 …. TI 8 Figure 7-10 Port 5 Input Change Interrupt / Wake-up Block Diagram 38 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller 7.4.1 Usage of Ports 5, 7 Input Change Wake-up/Interrupt Function (1) Wake-up (2) Wake-up and Interrupt (a) Before Sleep (a) Before Sleep 1. Disable WDT 1. Disable WDT 2-1. Read I/O Port 5 (MOV R5,R5) 2-1. Read I/O Port 5 (MOV R5,R5) 2-2. Read I/O Port 7 (MOV R7,R7) 2-2. Read I/O Port 7 (MOV R7,R7) 3. Execute "ENI" or "DISI" 3. Execute "ENI" or "DISI" 4. Enable wake-up bit (Set RE ICWE =1) 4. Enable wake-up bit (Set RE ICWE =1) 5. Execute "SLEP" instruction 5. Enable interrupt (Set IOCF ICIE =1) (b) After wake-up 6. Execute "SLEP" instruction Next instruction (b) After wake-up 1. IF "ENI" Interrupt vector (008H) 2. IF "DISI" Next instruction (3) Interrupt (a) Before Port 5,7 pin change 1-1. Read I/O Port 5 (MOV R5,R5) 1-2. Read I/O Port 7 (MOV R7,R7) 2. Execute "ENI" or "DISI" 3. Enable interrupt (Set IOCF ICIE =1) (b) After Port 5,7 pin changed (interrupt) 1. IF "ENI" Interrupt vector (006H) 2. IF "DISI" Next instruction 7.5 Reset and Wake-up 7.5.1 Reset and Wake-up Operation A reset is initiated by one of the following events: 1. Power-on reset 2. /RESET pin input "low" 3. WDT time-out (if enabled) 3 The device is kept in reset condition for a period of approximately 18ms (except in LXT mode) after the reset is detected. When in LXT2 mode, the reset time is 500ms. Two 3 4 choices (18ms or 4.5ms ) are available for WDT-time out period. Once a reset occurs, the following functions are performed (the initial Address is 000h): 3 4 The oscillator continues running, or will be started (if in sleep mode). The Program Counter (R2) is set to all "0". VDD=5V, Setup time period = 16.5ms ± 30% VDD=3V, Setup time period = 18ms ± 30% VDD=5V, Setup time period = 4.2ms ± 30% VDD=3V, Setup time period = 4.5ms ± 30% Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 39 EM78P372K 8-bit Microcontroller All I/O port pins are configured as input mode (high-impedance state) The Watchdog Timer and prescaler are cleared When power is switched on, the upper three bits of R3 is cleared The IOCB0 register bits are set to all "1" The IOCC0 register bits are set to all "0" The IOCD0 register bits are set to all "1" Bits 7, 5, and 4 of the IOCE0 register are cleared Bits 5 and 4 of the RE register are cleared RF and IOCF0 registers are cleared Executing the “SLEP” instruction will assert the sleep (power down) mode (When IDLE=“0”.). While entering into sleep mode, the Oscillator, TCC, TMR1 and TMR2 are stopped. The WDT (if enabled) is cleared but keeps on running. During AD conversion, when “SLEP” instruction is set; the Oscillator, TMR1 and TMR2 keep on running. The WDT (if enabled) is cleared but keeps on running. The controller can be awakened by: Case 1 External reset input on /RESET pin Case 2 WDT time-out (if enabled) Case 3 Port 5, P70, P71 input status changes (if ICWE is enabled) Case 4 Comparator output status changes (if CMPWE is enabled) Case 5 AD conversion completed (if ADWE is enabled) Case 6 Low Voltage Detector (if LVDWE is enabled) The first two cases (1 and 2) will cause the EM78P372K to reset. The T and P flags of R3 can be used to determine the source of the reset (wake-up). Cases 3, 4, 5 and 6 are considered the continuation of program execution and the global interrupt ("ENI" or "DISI" being executed) determines whether or not the controller branches to the interrupt vector following wake-up. If ENI is executed before SLEP, the instruction will begin to execute from Address 0x06 (Case 3), 00F (Case 4), 0x0C (Case 5) and 021 (Case 6) after wake-up. If DISI is executed before SLEP, the execution will restart from the instruction next to SLEP after wake-up. Only one of Cases 2 to 6 can be enabled before entering into sleep mode. That is: Case [a] If WDT is enabled before SLEP, all of the RE bit is disabled. Hence, the EM78P372K can be awakened only with Case 1 or Case 2. Refer to the section on Interrupt (Section 6.6) for further details. Case [b] If Port 5, P70, P71 Input Status Change is used to wake up the EM78P372K and the ICWE bit of the RE register is enabled before SLEP, and WDT must be disabled. Hence, the EM78P372K can be awakened only with Case 3. Wake-up time is dependent on the oscillator mode. In RC mode, Wake-up time is 10s (for stable oscillators). In HXT2 (4MHz) mode, Wake-up time is 800s (for stable oscillators), and in LXT2 mode, Wake-up time is 2 ~ 3s. 40 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller Case [c] If the Comparator output status change is used to wake-up the EM78P372K and the CMPWE bit of the RE register is enabled before SLEP, WDT must be disabled by software. Hence, the EM78P372K can be awakened only with Case 4. Wake-up time is dependent on the oscillator mode. In RC mode, Wake-up time is 10s (for stable oscillators). In HXT2 (4MHz) mode, Wake-up time is 800s (for stable oscillators), and in LXT2 mode, Wake-up time is 2s ~ 3s. Case [d] If completed AD conversion is used to wake-up the EM78P372K and ADWE bit of RE register is enabled before SLEP, WDT must be disabled by software. Hence, the EM78P372K can be awakened only with Case 5. The wake-up time is 15 TAD (ADC clock period). Case[e] If Low voltage detector is used to wake-up the EM78P372K and the LVDWE bit of Bank 0-RE register is enabled before SLEP, WDT must be disabled by software. Hence, the EM78P372K can be awakened only with Case 6. Wake-up time is dependent on oscillator mode. If Port 5, P70, P71 Input Status Change Interrupt is used to wake up the EM78P372K (as in Case [b] above), the following instructions must be executed before SLEP: BC MOV IOW WDTC MOV MOV ENI (or DISI) MOV MOV MOV IOW SLEP R3, 6 A, @00xx1110b IOCE0 R5, R5 R7, R7 A, @xxxxxx1xb RE A, @1xxxxx1xb IOCF0 ; Select Segment 0 ; Select WDT prescaler and Disable WDT ; ; ; ; ; Clear WDT and prescaler Read Port 5 Read Port 7 Enable (or disable) global interrupt Enable Port 5,7 input change wake-up bit ; Enable Port 5,7 input change interrupt ; Sleep Similarly, if the Comparator Interrupt is used to wake up the EM78P372K (as in Case [c] above), the following instructions must be executed before SLEP: BC MOV R3, 6 A, @xxx10XXXb IOW MOV IOC80 A, @00x11110b IOW WDTC ENI (or DISI) MOV IOCE0 MOV SLEP RE A, @xxx0x1xxb Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) ; Select Segment 0 ; Select a comparator and P64 functions as ; CO pin ; Select WDT prescaler and Disable WDT, ; and enable comparator output status ; change interrupt ; ; ; ; Clear WDT and prescaler Enable (or disable) global interrupt Enable comparator output status change wake-up bit ; Sleep 41 EM78P372K 8-bit Microcontroller 7.5.2 Wake-up and Interrupt Modes Operation Summary The controller can be awakened from sleep mode and idle mode. The wake-up signals are listed as follows. Wake-up Signal Condition Signal Sleep Mode DISI ENI Idle Mode DISI ENI Green Mode DISI ENI Normal Mode DISI ENI EXWE = 0, EXIE = 0 Wake-up is invalid Wake-up is invalid Interrupt is invalid Interrupt is invalid EXWE = 0, EXIE = 1 External INT EXWE = 1, EXIE = 0 EXWE = 1, EXIE = 1 ICWE = 0, ICIE = 0, P7ICIE = 0 Port 5, P70, P71 pin change ICWE = 0, ICIE = 1, P7ICIE = 1 ICWE = 1, ICIE = 0, P7ICIE = 0 ICWE = 1, ICIE = 1, P7ICIE = 1 Wake-up is invalid Wake-up is invalid Wake up + Next Instruction Wake up Wake up + + Next Interrupt Instruction Vector Wake up + Next Instruction Wake up Wake up + + Next Interrupt Instruction Vector Wake-up is invalid Wake-up is invalid. Wake up + Next Instruction Wake up Wake up + + Next Interrupt Instruction Vector Wake up + Next Instruction Wake up Wake up + + Next Interrupt Instruction Vector wake-up is invalid. TCIE = 1 ADWE = 0, ADIE = 0 ADWE = 0, ADIE = 1 AD Conversion complete ADWE = 1, ADIE = 0 ADWE = 1, ADIE = 1 42 Wake-up is invalid Wake up + Next Instruction Interrupt is invalid Next Instruction Next Instruction Wake-up is invalid Wake-up is invalid Interrupt + Interrupt Vector Interrupt + Interrupt Vector Interrupt is invalid Wake-up is invalid TCIE = 0 TCC Overflow Next Instruction Interrupt + Interrupt Vector Interrupt is invalid Next Instruction Interrupt + Interrupt Vector Interrupt is invalid. Wake up + Interrupt Vector Wake-up is invalid Next Instruction Interrupt + Interrupt Vector Interrupt is invalid. Next Instruction Wake-up is invalid Wake-up is invalid Wake up + Next Instruction Wake up Wake up + + Next Interrupt Instruction Vector Wake up + Next Instruction Wake up Wake up + + Next Interrupt Instruction Vector Interrupt + Interrupt Vector Interrupt is invalid Next Instruction Interrupt + Interrupt Vector Interrupt Next + Instruction Interrupt Vector Interrupt is invalid Interrupt Next + Instruction Interrupt Vector Interrupt is invalid Interrupt Next + Instruction Interrupt Vector Interrupt is invalid Interrupt Next + Instruction Interrupt Vector Interrupt is invalid. Interrupt Next + Instruction Interrupt Vector Interrupt is invalid. Interrupt Next + Instruction Interrupt Vector Interrupt is invalid Interrupt Next + Instruction Interrupt Vector Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller Wake-up Signal Condition Signal Sleep Mode DISI ENI Idle Mode DISI ENI Green Mode DISI ENI Normal Mode DISI ENI CMPWE = 0, CMPIE = 0 Wake-up is invalid Wake-up is invalid Interrupt is invalid Interrupt is invalid CMPWE = 0, CMPIE = 1 Comparator Interrupt Wake-up is invalid Wake up + Next Instruction Wake up Wake up CMPWE = 1, + + Next Interrupt CMPIE = 1 Instruction Vector CMPWE = 1, CMPIE = 0 Wake-up is invalid PWM1IE = 1 PWM2IE = 0 PWM2 period match interrupt Wake-up is invalid PWM2IE = 1 Wake-up is invalid DT1IE = 1 DT2IE = 1 LVDWE = 0, LVDIE = 1 Low Voltage Detector LVWE = 1, LVDIE = 0 LVDWE = 1, LVDIE = 1 WDT Timeout Low voltage reset WDTE = 1 Wake up + Next Instruction Wake up + Interrupt Vector Wake up + Next Instruction Wake up + Interrupt Vector wake-up is invalid Wake-up is invalid LVDWE = 0, LVDIE = 0 Wake up + Interrupt Vector Wake-up is invalid DT2IE = 0 PWM2 duty match interrupt Wake up + Next Instruction Wake-up is invalid DT1IE = 0 PWM1 duty match interrupt Wake up + Next Instruction Wake up Wake up + + Next Interrupt Instruction Vector wake-up is invalid PWM1IE = 0 PWM1 period match interrupt Wake-up is invalid Wake-up is invalid Wake up + Next Instruction Wake up + Interrupt Vector Wake-up is invalid Next Instruction Interrupt + Interrupt Vector Interrupt is invalid Next Instruction Interrupt + Interrupt Vector Interrupt is invalid Next Instruction Interrupt + Interrupt Vector Interrupt is invalid Next Instruction Interrupt + Interrupt Vector Interrupt is invalid Next Instruction Interrupt + Interrupt Vector Interrupt is invalid Next Instruction Interrupt + Interrupt Vector Interrupt is invalid Next Instruction Interrupt + Interrupt Vector Interrupt Next + Instruction Interrupt Vector Interrupt is invalid Interrupt Next + Instruction Interrupt Vector Interrupt is invalid Interrupt Next + Instruction Interrupt Vector Interrupt is invalid Interrupt Next + Instruction Interrupt Vector Interrupt is invalid Interrupt Next + Instruction Interrupt Vector Interrupt is invalid Interrupt Next + Instruction Interrupt Vector Interrupt is invalid Interrupt Next + Instruction Interrupt Vector Wake-up is invalid Wake-up is invalid Wake up + Next Instruction Wake up Wake up + + Next Interrupt Instruction Vector Wake up + Next Instruction Wake up Wake up + + Next Interrupt Instruction Vector Wake up + Reset Wake up + Reset Reset Reset Wake up + Reset Wake up + Reset Reset Reset Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) Interrupt is invalid Next Instruction Interrupt + Interrupt Vector Interrupt is invalid Interrupt Next + Instruction Interrupt Vector 43 EM78P372K 8-bit Microcontroller 7.5.3 Register Initial Values after Reset The following summarizes the initialized values for registers. Address N/A N/A N/A N/A Name IOC50 IOC60 IOC70 IOC80 Reset Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit Name C57 C56 C55 C54 C53 C52 C51 C50 Power-on 1 1 1 1 1 1 1 1 /RESET and WDT 1 1 1 1 1 1 1 1 Wake-up from Pin Change P P P P P P P P Bit Name C67 C66 C65 C64 C63 C62 C61 C60 Power-on 1 1 1 1 1 1 1 1 /RESET and WDT 1 1 1 1 1 1 1 1 Wake-up from Pin Change P P P P P P P P Bit Name C71 C70 Power-on 0 0 0 0 0 0 1 1 /RESET and WDT 0 0 0 0 0 0 1 1 Wake-up from Pin Change P P P P P P P P Bit Name CMPOUT COS1 COS0 Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Bit Name N/A IOC90 (TMR1) 0 0 0 0 0 0 0 1 /RESET and WDT 0 0 0 0 0 0 0 1 Wake-up from Pin Change P P P P P P P P Bit Name N/A N/A 44 IOCA0 (TMR2) IOCB0 (PDCR) TMR1[7] TMR1[6] TMR1[5] TMR1[4] TMR1[3] TMR1[2] TMR1[1] TMR1[0] Power-on TMR2[7] TMR2[6] TMR2[5] TMR2[4] TMR2[3] TMR2[2] TMR2[1] TMR2[0] Power-on 0 0 0 0 0 0 0 1 /RESET and WDT 0 0 0 0 0 0 0 1 Wake-up from Pin Change P P P P P P P P Bit Name /PD57 /PD56 /PD55 /PD54 /PD53 /PD52 /PD51 /PD50 Power-on 1 1 1 1 1 1 1 1 /RESET and WDT 1 1 1 1 1 1 1 1 Wake-up from Pin Change P P P P P P P P Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller Address N/A N/A N/A N/A N/A N/A N/A N/A Name IOCC0 (ODCR) IOCD0 (PHCR1) IOCE0 IOCF0 IOC51 (HSCR1) IOC61 (HSCR2) IOC71 (HDCR1) IOC81 (HDCR2) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit Name Reset Type OD67 OD66 OD65 OD64 OD63 OD62 OD61 OD60 Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Bit Name /PH57 /PH56 /PH55 /PH54 /PH53 /PH52 /PH51 /PH50 Power-on 1 1 1 1 1 1 1 1 /RESET and WDT 1 1 1 1 1 1 1 1 Wake-up from Pin Change P P P P P P P P Bit Name WDTE EIS ADIE CMPIE PSWE PSW2 PSW1 PSW0 Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Bit Name P7ICIE DT2IE DT1IE EXIE ICIE TCIE Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Bit Name HS57 HS56 HS54 HS53 HS52 HS51 Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Bit Name HS67 HS66 HS65 HS64 HS63 HS62 HS61 HS60 Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Bit Name HD57 HD56 HD54 HD53 HD52 HD51 Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Bit Name HD67 HD66 HD65 HD64 HD63 HD62 HD61 HD60 Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Bit Name IPWM2A IPWM1A PWM2A PWM1A DEADT2E DEADT1E DEADTP1 DEADTP0 Power-on N/A PWM2IE PWM1IE IOC91 (DeadTCR) /RESET and WDT Wake-up from Pin Change 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P P P P P P P P Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 45 EM78P372K 8-bit Microcontroller Address Name Reset Type Bit Name N/A N/A N/A 000 001 46 IOCA1 (DeadTR) IOCF1 (PHCR2) CONT R0 (IAR) R1 (TCC) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DEADTR7 DEADTR6 DEADTR5 DEADTR4 DEADTR3 DEADTR2 DEADTR1 DEADTR0 Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Bit Name /PH67 /PH66 /PH65 /PH64 /PH63 /PH62 /PH61 /PH60 Power-on 1 1 1 1 1 1 1 1 /RESET and WDT 1 1 1 1 1 1 1 1 Wake-up from Pin Change P P P P P P P P Bit Name INTE INT TS TE PSTE PST2 PST1 PST0 Power-on 1 0 1 1 0 0 0 0 /RESET and WDT 1 0 1 1 0 0 0 0 Wake-up from Pin Change P P P P P P P P Bit Name – – – – – – – – Power-on U U U U U U U U /RESET and WDT P P P P P P P P Wake-up from Pin Change P P P P P P P P Bit Name – – – – – – – – Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller Address 002 Name R2 (PC) Reset Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit Name – – – – – – – – Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change 003 004 005 006 07 08 09 0A R3 (SR) R4 (RSR) R5 R6 R7 R8 (AISR) R9 (ADCON) RA (ADOC) Jump to Address 0x06 or continue to execute next instruction Bit Name RST IOCS – T P Z DC C Power-on 0 0 0 1 1 U U U /RESET and WDT 0 0 0 T t P P P Wake-up from Pin Change 1 P P T t P P P Bit Name SBANK BS0 – – – – – – Power-on 0 0 U U U U U U /RESET and WDT 0 0 P P P P P P Wake-up from Pin Change P P P P P P P P Bit Name P57 P56 P55 P54 P53 P52 P51 P50 Power-on 1 1 1 1 1 1 1 1 /RESET and WDT 1 1 1 1 1 1 1 1 Wake-up from Pin Change P P P P P P P P Bit Name P67 P66 P65 P64 P63 P62 P61 P60 Power-on 1 1 1 1 1 1 1 1 /RESET and WDT 1 1 1 1 1 1 1 1 Wake-up from Pin Change P P P P P P P P Bit Name P71 P70 Power-on 0 0 0 0 0 0 1 1 /RESET and WDT 0 0 0 0 0 0 1 1 Wake-up from Pin Change P P P P P P P P Bit Name ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Bit Name VREFS CKR1 CKR0 ADRUN ADPD ADIS2 ADIS1 ADIS0 Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Bit Name CALI SIGN VOF[2] VOF[1] VOF[0] VREF1 VREF0 ADICS Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 47 EM78P372K 8-bit Microcontroller Address 0B 0C 0D 0E 0F 005 006 Name RB (ADDATA) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit Name Reset Type AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 Power-on U U U U U U U U /RESET and WDT U U U U U U U U Wake-up from Pin Change P P P P P P P P Bit Name AD11 AD10 AD9 AD8 Power-on 0 0 0 0 U U U U 0 0 0 0 U U U U P P P P P P P P Bit Name AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Power-on U U U U U U U U U U U U U U U U P P P P P P P P Bit Name /LVD LVDIF ADIF CMPIF ADWE CMPWE ICWE LVDWE Power-on 1 0 0 0 0 0 0 0 /RESET and WDT 1 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Bit Name P7ICIF DT2IF DT1IF EXIF ICIF TCIF Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Bit Name MLB TRS RBit11 RBit10 RBit9 RBit8 Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Bit Name RBit7 RBit6 RBit5 RBit4 RBit3 RBit2 RBit1 RBit0 Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P RC /RESET and WDT (ADDATA1H) Wake-up from Pin Change RD /RESET and WDT (ADDATA1L) Wake-up from Pin Change RE (ISR2) RF (ISR1) BANK1 R5 BANK1 R6 Bit Name 007 48 BANK1 R7 (PWMCON) IPWM2E IPWM1E PWM2IF PWM1IF PWMCAS PWM2E PWM1E Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller Address 008 Name Reset Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit Name T2EN T1EN T2P2 T2P1 T2P0 T1P2 T1P1 T1P0 Power-on 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P P P P P P P P BANK1 R8 (TMRCON) /RESET and WDT Wake-up from Pin Change Bit Name 009 Power-on BANK1 R9 /RESET and WDT (PRD1) Wake-up from Pin Change Bit Name 00A 00B 00C 00E 0F PWM1[7] PWM1[6] PWM1[5] PWM1[4] PWM1[3] PWM1[2] PWM1[1] PWM1[0] BANK 1 RA (PRD2) BANK 1 RB (DT1) BANK 1 RC (DT2) BANK 1 RE BANK 1 RF 0x10~0x3F R10~R3F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P P P P P P P P PWM2[7] PWM2[6] PWM2[5] PWM2[4] PWM2[3] PWM2[2] PWM2[1] PWM2[0] Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Bit Name DT1[7] DT1[6] DT1[5] DT1[4] DT1[3] DT1[2] DT1[1] DT1[0] Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Bit Name DT2[7] DT2[6] DT2[5] DT2[4] DT2[3] DT2[2] DT2[1] DT2[0] Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Bit Name LVDIE LVDEN LVD1 LVD0 EXWE Power-on 0 0 1 1 0 0 0 0 /RESET and WDT 0 0 1 1 0 0 0 0 Wake-up from Pin Change P P P P P P P P Bit Name - TIMERSC CPUS IDLE SHS1 SHS0 RCM1 RCM0 Power-on 0 1 1 0 1 1 WORD1 <6~5> /RESET and WDT 0 1 1 0 1 1 WORD1 <6~5> Wake-up from Pin Change P P P P P P P P Bit Name – – – – – – – – Power-on U U U U U U U U /RESET and WDT P P P P P P P P Wake-up from Pin Change P P P P P P P P Legend: “” = not used “u” = unknown or don’t care “P” = previous value before reset “t” = check “Reset Type” Table in Section 6.5.2 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 49 EM78P372K 8-bit Microcontroller 7.5.4 Controller Reset Block Diagram VDD D Oscillator Q CLK CLK CLR Power-on Reset Voltage Detector ENWDTB WDT Timeout Reset Setup time WDT /RESET Figure 7-11 Controller Reset Block Diagram 7.5.5 The T and P Status under Status Register A reset condition is initiated by one of the following events: 1. Power-on reset 2. /RESET pin input "low" 3. WDT time-out (if enabled) The values of T and P as listed in the table below, are used to check how the processor wakes up. Reset Type RST T P Power-on /RESET during Operating mode 0 0 1 *P 1 *P /RESET wake-up during Sleep mode 0 1 0 LVR during Operating mode 0 *P *P LVR wake-up during Sleep mode 0 1 0 WDT during Operating mode 0 0 1 WDT wake-up during Sleep mode 0 0 0 Wake-up on pin change during Sleep mode 1 1 0 *P: Previous status before reset The following shows the events that may affect the status of T and P. Event RST T P 0 *P 1 1 1 1 WDT time-out 0 0 *P SLEP instruction *P 1 0 Wake-up on pin changed during Sleep mode 1 1 0 Power-on WDTC instruction *P: Previous value before reset 50 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller 7.6 Interrupt The EM78P372K has seven interrupts enumerated below: 1. PWM1~2 period match and duty cycle match interrupt 2. Port 5, P70, P71 Input Status Change Interrupt 3. External interrupt [(P60, /INT) pin] 4. Analog to Digital conversion completed 5. PWM1, 2 underflow interrupt 6. When the comparators status changes 7. Low voltage detector interrupt Before the Port 5, P70, P71 Input Status Change Interrupt is enabled, reading Port 5, P70, P71 (e.g. "MOV R5, R5" and "MOV R7, R7") is necessary. Each Port 5, P70, P71 pin will have this feature if its status changes. The Port 5, P70, P71 Input Status Change Interrupt will wake up the EM78P372K from sleep mode if it is enabled prior to going into sleep mode by executing SLEP instruction. When wake up occurs, the controller will continue to execute program in-line if the global interrupt is disabled. If enabled, the global interrupt will branch out to the Interrupt Vector 006H. External interrupt equipped with digital noise rejection circuit (input pulse less than system clock time) is eliminated as noise. However, under Low Crystal oscillator (LXT) mode the noise rejection circuit will be disabled. Edge selection is possible with INTE of CONT. When an interrupt is generated by the External interrupt (when enabled), the next instruction will be fetched from Address 003H. Refer to Word 1 Bits 9 and 8, Section 6.14.2, Code Option Register (Word 1) for digital noise rejection definition. RF and RE are the interrupt status register that records the interrupt requests in the relative flags/bits. IOCF0 and IOCE0 are Interrupt mask registers. The global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. Once in the interrupt service routine, the source of an interrupt can be determined by polling the flag bits in RF. The interrupt flag bit must be cleared by instructions before leaving the interrupt service routine to avoid recursive interrupts. When interrupt mask bits is “Enable”, the flag in the Interrupt Status Register (RF) is set regardless of the ENI execution. Note that the result of RF will be the Logic AND of RF and IOCF0 (refer to the figure below). The RETI instruction ends the interrupt routine and enables the global interrupt (the ENI execution). When an interrupt is generated by the Timer clock/counter (when enabled), the next instruction will be fetched from Address 009, 012, 015, 018 and 01BH (PWM1~2 period match and duty match respectively). When an interrupt generated by AD conversion is completed (when enabled), the next instruction will be fetched from Address 00CH. When an interrupt is generated by the Comparators (when enabled), the next instruction will be fetched from Address 00FH (Comparator interrupt). Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 51 EM78P372K 8-bit Microcontroller When an interrupt is generated by the Low Voltage Detect (when enabled), the next instruction will be fetched from Address 021H (Low Voltage Detector interrupt). Before an interrupt subroutine is executed, the contents of ACC and the R3 and R4 registers are saved first by the hardware. If another interrupt occurs, the ACC, R3, and R4 will be replaced by the new interrupt. After an interrupt service routine is completed, the ACC, R3, and R4 registers are restored. VCC D /IRQn P R CLK C L Q IRQn INT _ Q IRQm RFRD RF ENI/DISI Q IOCF _ Q P R C L IOD D CLK IOCFWR /RESET IOCFRD RFWR Interrupt sources ACC Interrupt occurs Stack ACC ENI/DISI R3 (7~5, 2~0) RETI R4 (6~0) Stack R3 Stack R4 Figure 7-12 Interrupt Back-up Diagram 52 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller In EM78P372K, each individual interrupt source has its own interrupt vector as depicted in the table below. Interrupt Vector Priority * Interrupt Status 003H External interrupt 2 006H Port 5, P70, P71 pin change 3 009H TCC overflow interrupt 4 00CH AD conversion complete interrupt 5 00FH Comparator interrupt 6 012H PWM1 period match interrupt 7 015H PWM2 period match interrupt 8 018H PWM1 duty match interrupt 9 01BH PWM2 duty match interrupt 10 021H Low Voltage Detector interrupt 1 Note: *Priority: 1 = highest ; 11 = lowest priority 7.7 Analog-to-Digital Converter (ADC) The analog-to-digital circuitry consists of an 8-bit analog multiplexer; three control registers (AISR/R8, ADCON/R9, and ADOC/RA), three data registers (ADDATA1/RB, ADDATA1H/RC, and ADDATA1L/RD) and an ADC with 12-bit resolution as shown in the functional block diagram below. The analog reference voltage (Vref) and the analog ground are connected via separate input pins. Connecting to an external VREF is more accurate than connecting to an internal VDD. The ADC module utilizes successive approximation to convert the unknown analog signal into a digital value. The result is fed to the ADDATA, ADDATA1H, and ADDATA1L. Input channels are selected by the analog input multiplexer via the ADCON register Bits ADIS1 and ADIS0. ADC7 Vref 8-1 Analog Switch ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 Power-Down ADC ( successive approximation ) Start to Convert Fsco 4-1 MUX Internal RC 7 ~ 0 AISR 2 1 0 ADCON 6 3 5 ADCON RF 11 10 9 8 ADDATA1H 7 6 5 4 3 2 ADDATA1L 1 4 0 3 ADCON DATA BUS Figure 7-13 Analog-to-Digital Conversion Functional Block Diagram Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 53 EM78P372K 8-bit Microcontroller 7.7.1 ADC Control Register (AISR/R8, ADCON/R9, ADOC/RA) 7.7.1.1 R8 (AISR: ADC Input Select Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 The AISR register individually defines the P5, P6 and P7 pins as analog inputs or as digital I/O. Bit 7 (ADE7): AD converter enable bit of P57 pin 0 : Disable ADC7, P57 functions as I/O pin 1 : Enable ADC7 to function as analog input pin Bit 6 (ADE6): AD converter enable bit of P55 pin 0 : Disable ADC6, P55 functions as I/O pin 1 : Enable ADC6 to function as analog input pin Bit 5 (ADE5): AD converter enable bit of P70 pin 0 : Disable ADC5, P70 functions as I/O pin 1 : Enable ADC5 to function as analog input pin Bit 4 (ADE4): AD converter enable bit of P67 pin 0 : Disable ADC4, P67 functions as I/O pin 1 : Enable ADC4 to function as analog input pin Bit 3 (ADE3): AD converter enable bit of P53 pin 0 : Disable ADC3, P53 functions as I/O pin 1 : Enable ADC3 to function as analog input pin Bit 2 (ADE2): AD converter enable bit of P52 pin 0 : Disable ADC2, P52 functions as I/O pin 1 : Enable ADC2 to function as analog input pin Bit 1 (ADE1): AD converter enable bit of P51 pin 0 : Disable ADC1, P51 acts as I/O pin 1 : Enable ADC1 acts as analog input pin Bit 0 (ADE0): AD converter enable bit of P50 pin 0 : Disable ADC0, P50 functions as I/O pin 1 : Enable ADC0 to function as analog input pin 54 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller 7.7.1.2 R9 (ADCON: ADC Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 VREFS CKR1 CKR0 ADRUN ADPD ADIS2 ADIS1 ADIS0 The ADCON register controls the operation of the AD conversion and determines which pin should be currently active. Bit 7 (VREFS): The input source of the ADC Vref 0 : The Vref of the ADC is connected to internal reference voltage (default value), and the P54/TCC/VREF pin carries out the function of P54. 1 : The Vref of the ADC is connected to P54/TCC/VREF NOTE The P54/TCC/VREF pin cannot be applied to TCC and VREF at the same time. If P54/TCC/VREF functions as VREF analog input pin, then CONT Bit 5 (TS) must be “0”. The P54/TCC/VREF pin priority is as follows: P54/TCC/VREF Pin Priority High Medium Low VREF TCC P54 Bit 6 ~ Bit 5 (CKR1 ~ CKR0): The prescaler of ADC oscillator clock rate CPUS CKR1 : CKR0 Operation Mode Max. Operation Freq. ( if TAD=4us, match 372N ) Max. Operation Freq. ( if TAD=1us, match 372N ) 1 1 1 1 0 00 (default) 01 10 11 FOSC/16 FOSC/4 FOSC/64 FOSC/1 – 4 MHz 1 MHz 16 MHz – 16K/128kHz 16 MHz 4 MHz – 1 MHz 16K/128kHz Bit 4 (ADRUN): ADC starts to RUN 0: Reset upon completion of the conversion. This bit cannot be reset though software. 1: AD conversion is started. This bit can be set by software. Bit 3 (ADPD): ADC Power-down mode 0: Switch off the resistor reference to conserve power even while the CPU is operating 1: ADC is operating Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 55 EM78P372K 8-bit Microcontroller Bits 2 ~ 0 (ADIS2 ~ ADIS0): Analog Input Select ADICS ADIS2 ADIS1 ADIS0 Analog Input Select 0 0 0 0 ADIN0/P50 0 0 0 1 ADIN1/P51 0 0 1 0 ADIN2/P52 0 0 1 1 ADIN3/P53 0 1 0 0 ADIN4/P67 0 1 0 1 ADIN5/P70 0 1 1 0 ADIN6/P55 0 1 1 1 ADIN7/P57 1 0 X X OPOUT 1 1 0 0 Internal ADC Channel Select: 1/4 VDD 1 1 0 1 Internal ADC Channel Select: 1/2 VDD 1 1 1 0 Reserved 1 1 1 1 Reserved 7.7.1.3 RA (ADOC: AD Offset Calibration Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CALI SIGN VOF[2] VOF[1] VOF[0] VREF1 VREF0 ADICS Bit 7 (CALI): Calibration enable bit for ADC offset 0 = Disable the Calibration 1 = Enable the Calibration Bit 6 (SIGN): Polarity bit of offset voltage 0 = Negative voltage 1 = Positive voltage Bit 5 ~ Bit 3 (VOF[2] ~ VOF[0]): Offset voltage bits 56 VOF[2] VOF[1] VOF[0] EM78P372K 0 0 0 0 LSB 0 0 1 2 LSB 0 1 0 4 LSB 0 1 1 6 LSB 1 0 0 8 LSB 1 1 0 1 1 0 10 LSB 12 LSB 1 1 1 14 LSB Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller Bits 2 ~ 1 (VREF1~0): ADC internal reference voltage source. VREFSEL in Option Word 3 bit 11 VREF1 VREF0 ADC Int. Ref. Volt. 0 0 0 VDD 0 0 1 4.0V ± 1% 0 1 0 3.0V ± 1% 0 1 1 2.5V ± 1% 1 0 0 VDD 1 0 1 4.0V ± 1% 1 1 0 3.0V ± 1% 1 1 1 2.0V ± 1% 1 = Positive voltage Bit 0 (ADICS): ADC internal channel select. (Select ADC internal 1/4 VDD or OP output pin connects to ADC input) 0 = disable 1 = enable 7.7.1.4 Bank 1 RF (IRC switch Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - TIMERSC CPUS IDLE SHS1 SHS0 RCM1 RCM0 Bits 3 ~ 2 (SHS1~0): Select AD sample and Hold period SHS1 SHS0 AD sample and Hold period (TAD) 0 0 2 0 1 4 1 0 8 1 1 12 (default) 7.7.2 ADC Data Register (ADDATA/RB, ADDATA1H/RC, ADDATA1L/RD) When the AD conversion is completed, the result is loaded to the ADDATA, ADDATA1H and ADDATA1L registers. The ADRUN bit is cleared, and the ADIF is set. 7.7.3 ADC Sampling Time The accuracy, linearity, and speed of the successive approximation of the AD converter are dependent on the properties of the ADC and the comparator. The source impedance and the internal sampling impedance directly affect the time required to charge the sample holding capacitor. The application program controls the length of the sample time to meet the specified accuracy. Generally speaking, the program should wait for 2s for each K of the analog source impedance and at least 2s for the Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 57 EM78P372K 8-bit Microcontroller low-impedance source. The maximum recommended impedance for analog source is 10K at Vdd=5V. After the analog input channel is selected, this acquisition time must be done before the conversion is started. 7.7.4 AD Conversion Time CKR1 and CKR0 select the conversion time (Tct), in terms of instruction cycles. This allows the MCU to run at the maximum frequency without sacrificing the AD conversion accuracy. For the EM78P372K, the conversion time per bit is about 1s. The table below shows the relationship between Tct and the maximum operating frequencies. TAD = 1µs CPUS CKR1 : CKR0 1 1 1 1 0 00 (default) 01 10 11 Operation Max. Operation Max. Conversion Mode Frequency Rate/Bit FOSC/16 FOSC/4 FOSC/64 FOSC/1 16 MHz 4 MHz 1 MHz 16K/128kHz 1 MHz (1µs) 1 MHz (1µs) 1 MHz (1µs) Max. Conversion Rate 16*1µs=16µs (62.5kHz) 16*1µs=16µs (62.5kHz) 16*1µs=16µs (62.5kHz) TAD = 4µs CPUS Max. Conversion CKR1 : CKR0 Operation Max. Operation Mode Frequency Rate/Bit 00 (default) 01 10 11 1 1 1 1 0 FOSC/16 FOSC/4 FOSC/64 FOSC/1 4 MHz 1 MHz 16 MHz 16K/128kHz 250kHz (4µs) 250kHz (4µs) 250kHz (4µs) - Max. Conversion Rate 16*4µs=64µs (15.625kHz) 16*4µs=64µs (15.625kHz) 16*4µs=64µs (15.625kHz) - NOTE ■ Pin not used as an analog input pin can be used as regular input or output pin. ■ During conversion, do not perform output instruction to maintain precision for all of the pins. 7.7.5 ADC Operation during Sleep Mode In order to obtain a more accurate ADC value and reduce power consumption, the AD conversion remains operational during sleep mode. As the SLEP instruction is executed, all the MCU operations will stop except for the Oscillator, TCC, and AD conversion. The AD Conversion is considered completed as determined by: 1. The ADRUN bit of the R9 register is cleared to “0”. 2. The ADIF bit of the RE register is set to “1”. 3. The ADWE bit of the RE register is set to “1”. Wakes up from ADC conversion (where it remains in operation during sleep mode). 58 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller 4. Wake up and execution of the next instruction if the ADIE bit of the IOCE0 is enabled and the “DISI” instruction is executed. 5. Wake up and enters into Interrupt vector (Address 0x00C) if the ADIE bit of the IOCE0 is enabled and the “ENI” instruction is executed. 6. Enters into an Interrupt vector (Address 0x00C) if the ADIE bit of the IOCE0 is enabled and the “ENI” instruction is executed. The results are fed into the ADDATA, ADDATA1H, and ADDATA1L registers when the conversion is completed. If the ADIE is enabled, the device will wake up. Otherwise, the AD conversion will be shut off, no matter what the status of the ADPD bit is. 7.7.6 Programming Process/Considerations 7.7.6.1 Programming Process Follow these steps to obtain data from the ADC: 1. Write to the eight bits (ADE7: ADE0) on the R8 (AISR) register to define the characteristics of R5 (digital I/O, analog channels, or voltage reference pin) 2. Write to the R9/ADCON register to configure the AD module: a) Select the ADC input channel ( ADIS2 : ADIS0 ) b) Define the AD conversion clock rate ( CKR1 : CKR0 ) c) Select the VREFS input source of the ADC d) Set the ADPD bit to 1 to begin sampling 3. Set the ADWE bit, if the wake-up function is employed 4. Set the ADIE bit, if the interrupt function is employed 5. Write “ENI” instruction, if the interrupt function is employed 6. Set the ADRUN bit to “1” 7. Write “SLEP” instruction or Polling. 8. Wait for wake-up or for the ADRUN bit to be cleared to “0” , interrupt flag (ADIF) is set “1” or ADC interrupt occurs. 9. Read the ADDATA or ADDATA1H and ADDATA1L conversion data registers. If the ADC input channel changes at this time, the ADDATA, ADDATA1H, and ADDATA1L values can be cleared to ‘0’. 10. Clear the interrupt flag bit (ADIF). 11. For next conversion, go to Step 1 or Step 2 as required. At least two Tct is required before the next acquisition starts. NOTE In order to obtain accurate values, it is necessary to avoid any data transition on I/O pins during AD conversion Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 59 EM78P372K 8-bit Microcontroller 7.7.6.2 Sample Demo Programs R_0 == 0 PSW == 3 PORT5 == 5 PORT6 == 6 RE== 0XE ; Indirect addressing register ; Status register ; Interrupt status register B. Define a Control Register IOC50 == 0X5 IOC60 == 0X6 IOCE0== 0XE C_INT== 0XF ; ; ; ; Control Register of Port 5 Control Register of Port 6 Interrupt Mask Register 2 Interrupt Mask Register C. ADC Control Register ADDATA == 0xB AISR == 0x08 ADCON == 0x9 ; The contents are the results of ADC ; ADC input select register ; 7 6 5 4 3 2 1 0 ; VREFS CKR1 CKR0 ADRUN ADPD ADIS2 ADIS1 ADIS0 D. Define Bits in ADCON ADRUN == 0x4 ADPD == 0x3 ; ADC is executed as the bit is set ; Power Mode of ADC E. Program Starts ORG 0 JMP INITIAL ; Initial address ; ORG 0x0C ; Interrupt vector JMP CLRRE ; ;(User program section) ; CLRRE: MOV A,RE AND A, @0BXX0XXXXX ; To clear the ADIF bit, “X” by application MOV RE,A BS ADCON, ADRUN ; To start to execute the next AD conversion ; if necessary RETI INITIAL: MOV A,@0B00000001 ; To define P50 as an analog input MOV AISR,A MOV A,@0B00001000 ; To select P50 as an analog input channel, and AD power on MOV ADCON,A ; To define P50 as an input pin and set clock rate at fosc/16 En_ADC: MOV A, @0BXXXXXXX1 ; To define P50 as an input pin, and the others ; are dependent on applications IOW PORT5 60 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller MOV A, @0BXXXX1XXX ; ; MOV RE,A MOV A, @0BXX1XXXXX ; ; IOW IOCE0 ENI ; BS ADCON, ADRUN Enable the ADWE wake-up function of ADC, “X” by application Enable the ADIE interrupt function of ADC, “X” by application Enable the interrupt function ; Start to run the ADC ; If the interrupt function is employed, the following three lines may be ignored ; If Sleep: SLEP ; ; (User program section) ; or ; If Polling: POLLING: JBC ADCON, ADRUN ; To check the ADRUN bit continuously; JMP POLLING ; ADRUN bit will be reset as the AD conversion ; is completed ; ; (User program section) Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 61 EM78P372K 8-bit Microcontroller 7.8 7.8.1 Dual Sets of PWM (Pulse Width Modulation) Overview In PWM mode, PWM1 and PWM2 pins produce to 8-bit resolution PWM output (see. the functional block diagram below). A PWM output consists of a time period and a duty cycle, and it keeps the output high. The baud rate of PWM is the inverse of the time period. Fig 6-13 ~ Fig 6-16 (PWM Output Timing) depicts the relationships between a time period and a duty cycle. Figure 7-14 PWM System Block Diagram 62 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller PWM and /PWM (inverted PWM) can be used individually or used as dual PWM. When used individually, the definitions of active level between PWM and /PWM are somewhat different. For example, set period and duty cycle (period > duty), PWMXE=1/0 and IPWMXE=0/1, PWMXA = 1/0, /PWMXA=1/0, and finally set TXEN = 1. The following figures show PWM output timing according to different PWMXA and /PWMXA settings. PWMX PWMXE=1 & IPWMXE=0 /PWMX PWMXE=0 & IPWMXE=1 Duty Period-duty Period Figure 7-15 PWM Output Timing (PWMXA=0 and /PWMXA=0) PWMX PWMXE=1 & IPWMXE=0 /PWMX PWMXE=0 & IPWMXE=1 Duty Period-duty Period Figure 7-16 PWM Output Timing (PWMXA=0 and /PWMXA=1) PWMX PWMXE=1 & IPWMXE=0 /PWMX PWMXE=0 & IPWMXE=1 Duty Period-duty Period Figure 7-17 PWM Output Timing (PWMXA=1 and /PWMXA=0) Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 63 EM78P372K 8-bit Microcontroller PWMX PWMXE=1 & IPWMXE=0 /PWMX PWMXE=0 & IPWMXE=1 Duty Period-duty Period Figure 7-18 PWM Output Timing (PWMXA=1 and /PWMXA=1) 7.8.1.1 Dual PWM function It is consists of a complementary PWM (i.e. PWMX and /PWMX), one outputs PWM signal and the other outputs inverted PWM signal, It can output any pulse width signal you want by programming relative control registers. The dead time mode is supported. It means that the complementary PWM signals can be controlled to get a time interval that the complementary PWM signals won’t be intersected. The following Figures 6-17 ~ 6-18 show the dual PWM output waveform. Disable dead time control (DEADTXE = 0). Set period and duty cycle (period > duty). Set PWMXE & IPWMXE =1, PWMXA = 0/1, IPWMXA = 0/1, and finally set TXEN = 1. Figure 7-19 Dual PWMX Output Waveform (DEADTXE = 0) Set dead time > 0 (set dead time prescaler if required). Enable dead time control ( DEADTXE = 1). Set period and duty cycle (period > duty). Set PWMXE and IPWMXE =1, PWMXA = 0, IPWMXA = 0, and finally set TXEN = 1. For loading new duty, period, and dead time value at run time, follow the subsection “PWM Programming Process/Steps” to see the descriptions. 64 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller Figure 7-20 Dual PWMX output waveform (DEADTXE = 1, Dead Time > 0) The following figures show PWM output timing according to different PWMXA and /PWMXA settings. Figure 7-21 Dual PWMX output waveform (PWMXA = 0, IPWMXA=0, Dead Time = 0) Figure 7-22 Dual PWMX output waveform (PWMXA = 0, IPWMXA=0, Dead Time > 0) Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 65 EM78P372K 8-bit Microcontroller Figure 7-23 Dual PWMX output waveform (PWMXA = 1, IPWMXA=0, Dead Time > 0) PWMX duty Period-duty Dead time /PWMX Dead time Figure 7-24 Dual PWMX output waveform (PWMXA = 0, IPWMXA=1, Dead Time > 0) Figure 7-25 Dual PWMX output waveform (PWMXA = 1, IPWMXA=1, Dead Time > 0) 66 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller 7.8.2 Increment Timer Counter (TMRX: TMR1 or TMR2) TMRX are 8-bit clock counters with programmable prescalers. They are designed for the PWM module as baud rate clock generators. If employed, they can be turned off for power saving purposes by setting the T1EN bit [BANK1-R8<6>] or T2EN bit [BANK1-R8<7>] to “0”. TMR1 and TMR2 are internal designs and cannot be read 7.8.3 PWM Time Period (TMRX: TMR1 or TMR2) PPWM Time Period (PRDX: PRD1 or PRD2) The PWM time period is defined by writing to the PRDX register. When TMRX is equal to PRDX, the following events occur on the next increment cycle: 1) TMR is cleared 2) The PWMX pin is set to “1” 3) The PWM duty cycle is latched from DT1/DT2 to DL1/DL2 NOTE The PWM output will not be set, if the duty cycle is “0”. 4) The PWMXIF pin is set to “1” The following formula describes how to calculate the PWM time period: 1 Period PRDX 1 TMRX prescale value FOSC Example: PRDX=49; Fosc=4 MHz; TMRX (0, 0, 0) = 1:1, then 1 Period 49 1 1 12.5 µS 4M Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 67 EM78P372K 8-bit Microcontroller 7.8.4 PWM Duty Cycle (DTX: DT1 or DT2; DLX: DL1 or DL2) The PWM duty cycle is defined by writing to the DTX register, and is latched from DTX to DLX while TMRX is cleared. When DLX is equal to TMRX, the PWMX pin is cleared. DTX can be loaded anytime. However, it cannot be latched into DLX until the current value of DLX is equal to TMRX. The following formula describes how to calculate the PWM duty cycle: 1 Duty Cycle DTX FOSC TMRX prescale value Example: DTX=10; Fosc=4 MHz; TMRX (0, 0, 0) = 1:1, then 7.8.5 1 Duty Cycle 10 1 2.5 µS 4M Comparator X Changing the output status while a match occurs will simultaneously set the PWMXIF (TMRXIF) flag. 7.8.6 PWM Programming Process/Steps Load PRDX with the PWM time period. 1. Load DTX with the PWM Duty Cycle. 2. Enable interrupt function by writing IOCF0, if required. 3. Set PWMX pin to be output by writing a desired value to Bank 1-R7. 4. Load a desired value to BANK1-R8 with TMRX prescaler value and enable both PWMx and TMRX 68 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller 7.9 Timer 7.9.1 Overview Timer 1 (TMR1) and Timer 2 (TMR2) (TMRX) are 8-bit clock counters with programmable prescalers. They are designed for the PWM module as baud rate clock generators. TMRX can be read only. The Timer 1 and Timer 2 will stop running when sleep mode occurs with AD conversion not running. However, if AD conversion is running when sleep mode occurs, Timer 1 and Timer 2 will keep on running. 7.9.2 Function Description Fosc 1:1 1:2 1:4 1:8 1:16 1:64 1:128 1:256 To TMR1IF(PWM1IF) MUX TMR1 reset Period Match Comparator T1P2 T1P1 T1P0 T1EN PRD1 Data Bus Data Bus PRD2 T2P2 T2P1 T2P0 T2EN Comparator TMR2 Fosc 1:1 1:2 1:4 1:8 1:16 1:64 1:128 1:256 reset Period Match MUX To TMR2IF(PWM2IF) Figure 7-26 Timer Block Diagram Where: Fosc: Input clock. Prescaler (T1P2, T1P1 and T1P0 / T2P2, T2P1 and T2P0): The options 1:1, 1:2, 1:4, 1:8, 1:16, 1:64, 1:128, and 1:256 are defined by TMRX. It is cleared when any type of reset occurs. TMR1 and TMR2: Timer X register. TMRX is increased until it matches with PRDX, and then is reset to “0” (default value). DT1 and DT2: Timer X register. TMRX is increased until it matches with DTX, and then is reset to “0” (default value). PRDX (PRD1, PRD2): PWM time period register Comparator X (Comparator 1 and Comparator 2): Reset TMRX while a match occurs. The TMRXIF (PWMXIF) flag is set at the same time. Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 69 EM78P372K 8-bit Microcontroller 7.9.3 Programming the Related Registers When defining TMRX, refer to the operation of its related registers as shown in the following table. It must be noted that the PWMX bits must be disabled if their related TMRXs are utilized. That is, Bit 7 ~ Bit 3 of the PWMCON register must be set to “0”. Related Control Registers of TMR1 and TMR2 Addr. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 0x07 PWMCON/R7 IPWM2 IPWM1 E E “0” “0” “0” 0x08 TMRCON/R8 T2EN T1EN T2P2 T2P1 T2P0 7.9.4 Timer Programming Process/Steps Bit 2 Bit 1 Bit 0 PWMCAS PWM2E PWM1E T1P2 T1P1 T1P0 1. Load PRDX with the Timer duration 2. Enable interrupt function by writing IOCF0, if required 3. Load a desired value for the TMRX prescaler, enable TMRX and disable PWMX 7.9.5 PWM Cascade Mode The PWM Cascade Mode merges two 8-bit PWM function into one 16-bit. In this mode, the necessary parameters are redefined as shown on the table below: Parameter DT (Duty) PRD (Period) TMR (Timer) MSB (15~8) DT2 PRD2 TMR2 LSB (7~0) DT1 PRD1 TMR1 16-bit PWM The prescaler of this 16-bit PWM uses the prescaler of the TMR1. The MSB of TMR is counted when LSB carry and the PWM1IF bit/PWM1 pins are redefined as the PWMIF bit/PWM pin (or PWM1 pin). To PWMIF (PWM1IF) latch DL Fosc DT 1:1 1:2 1:4 1:8 1:16 1:64 1:128 1:256 Duty Cycle MUX 16-bit Comparator Match PWM (PWM1) R TMR reset Q S IOC51,2 16-bit Comparator T1P2 T1P1T1P0 T1EN Period Match PRD Data Bus Data Bus Figure 7-27 16-Bit PWM Functional Block Diagram (Merged from Two 8 Bits) 70 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller 7.10 Comparator The EM78P372K has one Cin - comparator which has two Cin+ CMP CO + analog inputs and one output. The comparator can be employed to wake up the system Cin Cin+ from sleep/idle mode. The Figure at right shows the comparator circuit. Output 10mV Figure 7-28 Comparator Operating Mode 7.10.1 External Reference Signal The analog signal that is presented at Cin– compares to the signal at Cin+, and the digital output (CO) of the comparator is adjusted accordingly by taking the following notes into considerations: NOTE ■ The reference signal must be between Vss and Vdd. ■ The reference voltage can be applied to either pin of the comparator. ■ Threshold detector applications may be of the same reference. ■ The comparator can operate from the same or different reference sources. 7.10.2 Comparator Output The compared result is stored in the CMPOUT of IOC80. The comparator outputs are sent to CO (P64) by programming Bit 4 and Bit 3 <COS1, COS0> of the IOC80 register to <1,0>. See table under Section 6.2.4, IOC80 (Comparator and TCCA Control Registers) for Comparator/OP select bits function description. Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 71 EM78P372K 8-bit Microcontroller The following figure shows the Comparator Output block diagram. To C0 F ro m O P I/O CMRD EN EN Q Q D D To CMPO UT RESET T o C P IF CMRD F r o m o th e r c o m p a r a to r Figure 7-29 Comparator Output Configuration 7.10.3 Using Comparator as an Operation Amplifier The comparator can be used as an operation amplifier if a feedback resistor is externally connected from the input to the output. In this case, the Schmitt trigger function can be disabled for power saving purposes, by setting Bit 4, Bit 3 <COS1, COS0> of the IOC80 register to <1,1>. See table under Section 6.2.4, IOC80 (Comparator and TCCA Control Registers) for Comparator/OP select bits function description. NOTE Under Operation Amplifier: ■ The CMPIE (IOCE0.4), CMPWE (RE.2), and CMPIF (RE.4) bits are invalid. ■ The comparator interrupt is invalid. ■ The comparator wake-up is invalid. 7.10.4 Comparator Interrupt CMPIE (IOCE0.4) must be enabled for the “ENI” instruction to take effect Interrupt is triggered whenever a change occurs on the comparator output pin The actual change on the pin can be determined by reading the Bit CMPOUT, IOC80<5>. 72 CMPIF (RE.4), the comparator interrupt flag, can only be cleared by software Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller 7.10.5 Wake-up from Sleep Mode If the CMPWE bit of the RE register is set to “1,” the comparator remains active and the interrupt remains functional, even under Sleep mode. If a mismatch occurs, the change will wake up the device from Sleep mode. The power consumption should be taken into consideration for the benefit of energy conservation. If the function is unemployed during Sleep mode, turn off the comparator before entering into sleep mode. The Comparator is considered completed as determined by: 1. COS1 and COS0 bits of IOC80 register setting selects Comparator. 2. CMPIF bit of RE register is set to “1”. 3. CMPWE bit of RE register is set to “1”. Wakes up from Comparator (where it remains in operation during sleep/idle mode). 4. Wakes-up and executes the next instruction, if CMPIE bit of IOCE0 is enabled and the “DISI” instruction is executed. 5. Wake-up and enters into Interrupt vector (Address 0x00F), if CMPIE bit of IOCE0 is enabled and the “ENI” instruction is executed. 6. Enters into Interrupt vector (Address 0x00F), if CMPIE bit of IOCE0 is enabled and the “ENI” instruction is executed. Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 73 EM78P372K 8-bit Microcontroller 7.11 7.11.1 Oscillator Oscillator Modes The EM78P372K can be operated in seven different oscillator modes, such as Crystal Oscillator Mode (XT), High Crystal Oscillator Mode 1 (HXT1), High Crystal Oscillator Mode 2 (HXT2), Low Crystal Oscillator Mode 1 (LXT1), Low Crystal Oscillator Mode 2 (LXT2), External RC Oscillator Mode (ERC), and RC Oscillator Mode with Internal RC Oscillator Mode (IRC). You can select one of them by programming the OSC3 ~ OSC0 in the Code Option register. The Oscillator modes defined by OSC3 ~ OSC0 are described below. Oscillator Modes OSC3 OSC2 OSC1 OSC0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 3 0 1 0 0 3 0 1 0 1 3 0 1 1 0 3 0 1 1 1 1 1 1 1 1 ERC (External RC oscillator mode); P55/ADC6/OSCO/ERCin acts as ERCin P70/ADC5/OSCI/RCOUT acts as P70 1 ERC (External RC oscillator mode); P55/ADC6/OSCO/ERCin acts as ERCin P70/ADC5/OSCI/RCOUT acts as RCOUT 2 IRC (Internal RC oscillator mode); P55/ADC6/OSCO/ERCin acts as P55 P70/ADC5/OSCI/RCOUT acts as P70 (default) 2 IRC (Internal RC oscillator mode); P55/ADC6/OSCO/ERCin acts as P55 P70/ADC5/OSCI/RCOUT acts as RCOUT LXT1 (Frequency range of XT, mode is 100kHz ~ 1MHz) HXT1 (Frequency range of XT mode is 12MHz ~ 20MHz) LXT2 (Frequency range of XT mode is 32.768kHz) HXT2 (Frequency range of XT mode is 6MHz ~ 12MHz) 3 XT (Frequency range of XT mode is 1MHz ~ 6MHz) The maximum operating frequency limit of crystal/resonator at different VDDs, are as follows: Conditions Two clocks 74 VDD Max. Freq. (MHz) 2.1V 4 3.0V 8 4.5V 16 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller 7.11.2 Crystal Oscillator/Ceramic Resonators (Crystal) The EM78P372K can be driven by an external clock signal through the OSCI pin as illustrated below. OSCI OSCO Figure 7-30 External Clock Input Circuit In most applications, Pin OSCI and Pin OSCO can be connected with a crystal or ceramic resonator to generate oscillation. Figure 6-18 below depicts such a circuit. The same applies to the XT mode, HXT1 mode, HTX2 mode, LXT1 mode and LXT2 mode. C1 OSCI Crystal OSCO RS C2 Figure 7-31 Crystal/Resonator Circuit The following table provides the recommended values for C1 and C2. Since each resonator has its own attribute, user should refer to the resonator specifications for the appropriate values of C1 and C2. RS, a serial resistor, maybe required for AT strip cut crystal or low frequency mode. Figure 6-21 is PCB layout suggestion. When the system works in Crystal mode (16 MHz), a 10 K is connected between OSCI and OSCO. Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 75 EM78P372K 8-bit Microcontroller Capacitor selection guide for crystal oscillator or ceramic resonators: Oscillator Type Frequency Mode Frequency LXT1 (100 K ~ 1 MHz) Ceramic Resonators XT (1 M ~ 6 MHz) LXT2 (32.768kHz) LXT1 (100 K ~ 1 MHz) Crystal Oscillator XT (1~6 MHz) HXT2 (6~12 MHz) HXT1 (12~20 MHz) C1 (pF) C2 (pF) 100kHz 60 pF 60 pF 200kHz 60 pF 60 pF 455kHz 40 pF 40 pF 1 MHz 30 pF 30 pF 1.0 MHz 30 pF 30 pF 2.0 MHz 30 pF 30 pF 4.0 MHz 20 pF 20 pF 32.768kHz 40 pF 40 pF 100kHz 60 pF 60 pF 200kHz 60 pF 60 pF 455kHz 40 pF 40 pF 1 MHz 30 pF 30 pF 1.0 MHz 30 pF 30 pF 2.0 MHz 30 pF 30 pF 4.0 MHz 20 pF 20 pF 6.0 MHz 30 pF 30 pF 6.0 MHz 30 pF 30 pF 8.0 MHz 20 pF 20 pF 12.0 MHz 30 pF 30 pF 12.0 MHz 30 pF 30 pF 16.0 MHz 20 pF 20 pF Circuit diagrams for serial and parallel modes Crystal/Resonator: 330 330 C OSCI 7404 7404 7404 Crysta l Figure 7-32 Serial Mode Crystal/Resonator Circuit Diagram 76 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller 7404 4.7K 10K Vdd O S CI 10K 7404 C rystal C1 10K C2 Figure 7-33 Parallel Mode Crystal/Resonator Circuit Diagram Figure 7-34 Parallel Mode Crystal/Resonator Circuit Diagram Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 77 EM78P372K 8-bit Microcontroller 7.11.3 External RC Oscillator Mode For some applications that do not require Vcc precise timing calculation, the RC oscillator (Figure 7-35) could offer an Rext effective cost savings. Nevertheless, it should be noted that the frequency of the ERCin RC oscillator is influenced by the supply Cext voltage, the values of the resistor (Rext), the capacitor (Cext), and even by the operation temperature. Moreover, the frequency also changes slightly from one chip to another due to the manufacturing Figure 7-35 External RC Oscillator Mode Circuit process variation. In order to maintain a stable system frequency, the values of the Cext should be no less than 20 pF, and the value of Rext should not be greater than 1 M. If the frequency cannot be kept within this range, the frequency can be affected easily by noise, humidity, and leakage. The smaller the Rext in the RC oscillator is, the faster its frequency will be. On the contrary, for very low Rext values, for instance, 1 K, the oscillator will become unstable because the NMOS cannot correctly discharge the capacitance current. Based on the above reasons, it must be kept in mind that all supply voltage, the operation temperature, the components of the RC oscillator, the package types, and the PCB layout have certain effects on the system frequency. The RC Oscillator frequencies: Cext 20 pF 100 pF 300 pF Rext Average Fosc 5V, 25C Average Fosc 3V, 25C 3.3k 2.064 MHz 1.901 MHz 5.1k 1.403 MHz 1.316 MHz 10k 750.0 kHz 719.0 kHz 100k 81.45 kHz 81.33 kHz 3.3k 647.0 kHz 615.0 kHz 5.1k 430.8 kHz 414.3 kHz 10k 225.8 kHz 219.8 kHz 100k 23.88 kHz 23.96 kHz 3.3k 256.6 kHz 245.3 kHz 5.1k 169.5 kHz 163.0 kHz 10k 88.53 kHz 86.14 kHz 100k 9.283 kHz 9.255 kHz 1 Note: : Measured based on DIP packages. 2 : The values are for design reference only. : The frequency drift is 30% 3 78 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller 7.11.4 Internal RC Oscillator Mode The EM78P372K offers a versatile internal RC mode with default frequency value of 4MHz. The Internal RC oscillator mode has other frequencies (16 MHz, 8 MHz, and 1 MHz) that can be set by Code Option (Word 1), RCM1, and RCM0. The Table below describes the EM78P372K internal RC drift with voltage, temperature, and process variations. Internal RC Drift Rate (Ta=25°C, VDD=5V±5%, VSS=0V) Drift Rate Internal Temperature Voltage (-40°C ~+85°C) (2.1V~5.5V) 4 MHz ±2% 16 MHz RC Frequency Process Total ±1% ±1% ±4% ±2% ±1% ±1% ±4% 8 MHz ±2% ±1% ±1% ±4% 1 MHz ±2% ±1% ±1% ±4% Note: Theoretical values are for reference only. Actual values may vary depending on the actual process. 7.12 Power-on Considerations Any microcontroller is not warranted to start operating properly before the power supply stabilizes in steady state. The EM78P372K POR voltage range is 1.9V 0.2V. Under customer application, when power is switched OFF, Vdd must drop below 1.6V and remains at OFF state for 10s before power can be switched ON again. Subsequently, the EM78P372K will reset and work normally. The extra external reset circuit will work well if Vdd rises fast enough (50ms or less). However, under critical applications, extra devices are still required to assist in solving power-on problems. 7.12.1 Programmable WDT Time-out Period 5 The Option word (WDTPS) is used to define the WDT time-out period (18ms or 6 4.5ms ). Theoretically, the range is from 4.5ms or 18ms. For most crystal or ceramic resonators, the lower the operation frequency is, the longer is the required set-up time. 5 6 VDD=5V, WDT time-out period = 16.5ms ± 30%. VDD=3V, WDT time-out period = 18ms ± 30%. VDD=5V, WDT time-out period = 4.2ms ± 30%. VDD=3V, WDT time-out period = 4.5ms ± 30%. Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 79 EM78P372K 8-bit Microcontroller 7.12.2 External Power-on Reset Circuit The circuits shown in the VDD following figure implements an external RC to produce a /RESET R D reset pulse. The pulse width (time constant) should be Rin kept long enough to allow C the Vdd to reach the minimum operating voltage. This circuit is used when the Figure 7-36 External Power-on Reset Circuit power supply has a slow power rise time. Because the current leakage from the /RESET pin is about 5A, it is recommended that R should not be greater than 40KΩ. This way, the voltage at Pin /RESET is held below 0.2V. The diode (D) functions as a short circuit at power-down. The “C” capacitor is discharged rapidly and fully. Rin, the current-limited resistor, prevents high current discharge or ESD (electrostatic discharge) from flowing into Pin /RESET. 7.12.3 Residual Voltage Protection When the battery is replaced, device power (Vdd) is removed but residual voltage remains. The residual voltage may trip below Vdd minimum, but not to zero. This condition may cause a poor power-on reset. Figure 7-37 and Figure 7-38 show how to create a protection circuit against residual voltage. VDD VDD 33K Q1 10K /RESET 100K 1N4684 Figure 7-37 Residual Voltage Protection Circuit 1 80 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller VDD VDD R1 Q1 /RESET R2 R3 Figure 7-38 Residual Voltage Protection Circuit 2 7.13 Code Option EM78P372K has six Code Option Words and three Customer ID words that are not part of the normal program memory. Word 0 Word1 Word 2 Word 3 Word 0x10 Word 0x11 Bit 12~Bit 0 Bit 12~Bit 0 Bit12~Bit 0 Bit12~Bit 0 Bit12~Bit 0 Bit12~Bit 0 7.13.1 Code Option Register (Word 0) Word 0 Bit Bit 12 Mne TYPE1 monic Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bits 2~0 TYPE0 WK_CLK CLKS LVR1 LVR0 RESETEN ENWDT NRHL NRE Protect 1 High High 8 clock High High High Disable Disable 32/fc Enable Disable 0 Low Low 32 clock Low Low Low Enable Enable 8/fc Enable Disable Bits 12~11 (TYPE1 ~ TYPE0): Type selection for EM78P372K TYPE 1, TYPE 0 MCU Type PIN Not Used 00 EM78P372K-10Pin Ports 60 ~ 66 / 54 / 56 / 57 are output low. 01 EM78P372K-14Pin Ports 62 / 63 / 64 / 65 / 56 / 57 are output low. 10 EM78P372K-18Pin Ports 56 / 57 are output low. 11 EM78P372K-20Pin (Default) X Bit 10 (WK_CLK): Selecting 8 or 32 clocks wake up from sleep and idle mode (only IRC mode) 0 : 32 clocks 1 : 8 clocks (default) Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 81 EM78P372K 8-bit Microcontroller Bit 9 (CLKS): Instruction period option bit 0 = two oscillator periods 1 = four oscillator periods (default) Bits 8~7 (LVR1 ~ LVR0): Low Voltage Reset Enable bits LVR1, LVR0 VDD Reset Level 11 VDD Release Level NA (Power-on Reset) (Default) 10 2.7V 2.9V 01 3.5V 3.7V 00 4.0V 4.2V Bit 6 (RESETEN): RESET/P71 Pin Select Bit 0 : P71 set to /RESET pin 1 : P71 is general purpose input pin or open-drain for output Port (default) Bit 5 (ENWDT): Watchdog timer enable bit 0 = Enable 1 = Disable (default) Bit 4 (NRHL): Noise rejection high/low pulses define bit. INT pin is falling or rising edge trigger 0 : Pulses equal to 8/fc is regarded as signal 1 : Pulses equal to 32/fc is regarded as signal (default) NOTE The noise rejection function is turned off in the LXT2 and sleep mode. Bit 3 (NRE): Noise Rejection Enable 0 : Disable noise rejection 1 : Enable noise rejection (default), but in Low Crystal oscillator (LXT) mode, the noise rejection circuit is always disabled. Bits 2 ~ 0 (Protect): Protect Bit 82 Protect Bits Protect 0 Enable 1 Disable (default) Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller 7.13.2 Code Option Register (Word 1) Word 1 Bit Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnem onic C5 C4 C3 C2 C1 C0 1 High High High High High High High High High High High High Syste m_clk 0 Low Low Low Low Low Low Low Low Low Low Low Low Open_ drain RCM1 RCM0 OSC3 OSC2 OSC1 OSC0 RCOU T Bits 12~7 (C5~C0): Calibrator of internal RC mode C5~C0 must be set to “1” only (auto-calibration). Bit 6~5 (RCM1, RCM0): RC mode selection bits RCM 1 RCM 0 Frequency (MHz) 1 1 4 (Default) 1 0 16 0 1 8 0 0 1 Bits 4 ~ 1 (OSC3 ~ OSC0): Oscillator Modes Selection bits Oscillator Modes OSC3 OSC2 OSC1 OSC0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 3 0 1 0 0 3 0 1 0 1 3 0 1 1 0 3 0 1 1 1 1 1 1 1 1 ERC (External RC oscillator mode); P55/ADC6/OSCO/ERCin acts as ERCin P70/ADC5/OSCI/RCOUT acts as P70 1 ERC (External RC oscillator mode); P55/ADC6/OSCO/ERCin acts as ERCin P70/ADC5/OSCI/RCOUT acts as RCOUT 2 IRC (Internal RC oscillator mode); P55/ADC6/OSCO/ERCin acts as P55 P70/ADC5/OSCI/RCOUT acts as P70 (default) 2 IRC (Internal RC oscillator mode); P55/ADC6/OSCO/ERCin acts as P55 P70/ADC5/OSCI/RCOUT acts as RCOUT LXT1 (Frequency range of XT, mode is 100kHz~1 MHz) HXT1 (Frequency range of XT mode is 12MHz~20 MHz) LXT2 (Frequency range of XT mode is 32.768kHz) HXT2 (Frequency range of XT mode is 6 MHz~12 MHz) 3 XT (Frequency range of XT mode is 1 MHz~6 MHz) Bit 0 (RCOUT): Instruction clock output enable bit in IRC or ERC mode. 0 : RCOUT pin output instruction clock with open drain. 1 : RCOUT pin output instruction clock(default) Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 83 EM78P372K 8-bit Microcontroller 7.13.3 Code Option Register (Word 2) Word 2 Bit Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 – Mne monic – – – SFS 1 – – – 16kHz – 0 – – – 128kHz – Bit 7 Bit 6 Bit 5 Bit 4 – Bit 3 Bit 2 Bit 1 Bit 0 WDTPS ID2 ID1 ID0 IRCPSS IRCIRS HLP Internal Regulator High – 18ms High High High Low – 4.5ms Low Low Low VDD Bandgap Bit 12: Not used, (reserved). This bit is set to “1” all the time. Bit 11: Not used, (reserved). This bit is set to “0” all the time. Bit 10: Not used, (reserved). This bit is set to “1” all the time. Bit 9 (SFS): Sub-oscillator select for Green mode and TCC, PWM1, PWM2 clock source. (Not include WDT time-out and free run setup-up time) 0 : 128kHz 1 : 16kHz (default) Bit 8: Not used, (reserved). This bit is set to “0” all the time. Bit 7 (IRCPSS): IRC Power Source Select 0 = VDD 1 = Internal reference (default) Bit 6 (IRCIRS): IRC Internal reference Select. 0 = IRC Bandgap Mode (Vref is used from Bandgap). 1 = IRC Regulator Mode (default) Bit 5 (HLP): Power consumption selection 0: Low power consumption mode, applies to operating frequency at 400 kHz or below 400kHz 1: High power consumption mode, applies to operating frequency above 400 kHz (Default) (User selects LXT1 or LXT2 in crystal mode, HLP function automatically selects low) Bit 4 (LPS): Not used, (reserved). This bit is set to “1” all the time. Bit 3 (WDTPS): WDT Time-out Period WDT Time Watchdog Timer* 1 18 ms (Default) 0 4.5 ms *Theoretical values, for reference only. Bits 2 ~ 0: 84 Customer’s ID Ⅰcode (Can’t be read from Table Point Register) Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller 7.13.4 Code Option Register (Word 3) Word 3 Bit Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic – VREFSEL – – – – – – – – – – – 1 – High – – – – – – – – – – – 0 – Low – – – – – – – – – – – Bit 12: Not used, (reserved). This bit is set to “1” all the time. Bit 11 (VREFSEL): ADC internal reference voltage select. [Depend on VREF[1:0] (Bank 0-RA[2:1]) = 11] 0: ADC Internal reference voltage 2.5V. 1: ADC Internal reference voltage 2.0V (Default) Bits 10 ~ 0: 7.13.5 Not used (Reserved). This bit is set to “1” all the time. Customer ID Register (Word 0x10) Word 0x10 Bit Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 1 High High High High High High High High High High High High High 0 Low Low Low Low Low Low Low Low Low Low Low Low Low Bits 12 ~ 0: Customer’s ID Ⅱ code (Can be read from Table Point Register) 7.13.6 Customer ID Register (Word 0x11) Word 0x11 Bit Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID19 ID18 ID17 ID16 1 High High High High High High High High High High High High High 0 Low Low Low Low Low Low Low Low Low Low Low Low Low Bits 12 ~ 0: Customer’s ID Ⅲ code (Can be read from Table Point Register) Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 85 EM78P372K 8-bit Microcontroller 7.14 Low Voltage Detector/Low Voltage Reset The Low Voltage Reset (LVR) and the Low Voltage Detector (LVD) are designed for unstable power situation, such as external power noise interference or in EMS test condition. When LVR is enabled, the system supply voltage (Vdd) drops below Vdd reset level (VRESET) and remains at 10s, a system reset will occur and the system will remain in reset status. The system will remain at reset status until Vdd voltage rises above Vdd release level. If Vdd drops below the low voltage detector level, /LVD (Bit 7 of RE) is cleared to “0’ to show a low voltage signal when LVD is enabled. This signal can be used for low voltage detection. 7.14.1 Low Voltage Reset LVR property is set at Bits 12 and 11 of Code Option Word 0. Detailed operation mode is as follows: Word 0 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 TYPE1 TYPE0 WK_CLK CLKS LVR1 LVR0 Bit 6 Bit 5 RESETEN ENWDT Bit 4 Bit 3 Bits 2~0 NRHL NRE Protect Bits 8~7 (LVR1 ~ LVR0): Low Voltage Reset Enable bits. LVR1, LVR0 7.14.2 VDD Reset Level VDD Release Level 11 10 01 NA (Power-on Reset) 2.7V 3.5V 2.9V 3.7V 00 4.0V 4.2V Low Voltage Detector LVD property is set and Register detailed operation mode is as follows: 7.14.2.1 Bank 1 RE (LVD Control and Wake-up Control Register 2) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LVDIE LVDEN LVD1 LVD0 - - - EXWE NOTE ■ Bank 1 RE<6> register is both readable and writable ■ Individual interrupt is enabled by setting its associated control bit in the Bank 1 RE<7> to "1". ■ Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. 86 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller Bit 7 (LVDIE): Low voltage Detector interrupt enable bit. 0 : Disable Low voltage Detector interrupt 1 : Enable Low voltage Detector interrupt When detect low level voltage state is used to enter an interrupt vector or enter next instruction, the LVDIE bit must be set to “Enable”. Bit 6 (LVDEN): Low Voltage Detector Enable bit 0 : Low voltage detector disable 1 : Low voltage detector enable Bits 5~4 (LVD1:0): Low Voltage Detector level bits. LVDEN 7.14.2.2 LVD1, LVD0 1 11 1 10 1 01 1 00 0 ×× LVD voltage Interrupt Level /LVD Vdd ≤ 2.2V Vdd > 2.2V Vdd ≤ 3.3V Vdd > 3.3V Vdd ≤ 4.0V Vdd > 4.0V Vdd ≤ 4.5V Vdd > 4.5V NA 0 1 0 1 0 1 0 1 1 Bank 0 RE (Interrupt Status 2 and Wake-up Control Register 1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 /LVD LVDIF ADIF CMPIF ADWE CMPWE ICWE LVDWE NOTE ■ RE < 6, 5, 4 > can be cleared by instruction but cannot be set. ■ IOCE0 is the interrupt mask register. ■ Reading RE will result to "Logic AND" of RE and IOCE0. Bit 7 (/LVD): Low voltage Detector state. This is a read only bit. When the VDD pin voltage is lower than LVD voltage interrupt level (selected by LVD1 and LVD0), this bit will be cleared. 0 : Low voltage is detected. 1 : Low voltage is not detected or LVD function is disabled. Bit 6 (LVDIF): Low Voltage Detector Interrupt flag LVDIF reset to “0” by software or hardware. Bit 0 (LVDWE): Low Voltage Detect wake-up enable bit. 0 : Disable Low Voltage Detect wake-up. 1 : Enable Low Voltage Detect wake-up. Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 87 EM78P372K 8-bit Microcontroller When the Low Voltage Detect is used to enter an interrupt vector or to wake up the IC from sleep/idle with Low Voltage Detect running, the LVDWE bit must be set to “Enable“. 7.14.3 Programming Process Follow these steps to obtain data from the LVD: 1. Write to the two bits (LVD1: LVD0) on the LVDCR register to define the LVD level. 2. Set the LVDWE bit, if the wake-up function is employed. 3. Set the LVDIE bit, if the interrupt function is employed. 4. Write “ENI” instruction, if the interrupt function is employed. 5. Set LVDEN bit to 1 6. Write “SLEP” instruction or Polling /LVD bit. 7. Clear the low voltage detector interrupt flag bit (LVDIF) when Low Voltage Detector interrupt occurred. The LVD module uses the internal circuit. When LVDEN (Bit 6 of Bank 1 RE) is set to “1”, the LVD module is enabled. When LVDWE (Bit 0 of RE) is set to “1”, the LVD module will continue to operate during sleep/idle mode. If Vdd drops slowly and crosses the detect point (VLVD), the LVDIF (Bit 6 of RE) will be set to “1”, the /LVD (Bit 7 of RE) will be cleared to “0”, and the system will wake up from Sleep/Idle mode. When a system reset occurs, the LVDIF will be cleared. When Vdd remains above VLVD, LVDIF is kept at “0” and /LVD is kept at “1”. When Vdd drops below VLVD, LVDIF is set to “1” and /LVD is kept at “0”. If ENI instruction is executed, LVDIF will be set to “1”, and the next instruction will branch to interrupt Vector 021H. The LVDIF is cleared to “0” by software. Refer Figure 6-26 below. LVDIF is cleared by software Vdd VLVD VRESET LVDIF Internal Reset 18ms <LVR Voltage drop >LVR Voltage drop Vdd < Vreset not longer than 10us, the system still keeps on operating System occur reset Figure 7-34 LVD/LVR Waveform Situation 88 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller 7.15 Instruction Set Each instruction in the instruction set is a 13-bit word divided into an OP code and one or more operands. Normally, all instructions are executed within one single instruction cycle (one instruction consists of two oscillator time periods), unless the program counter is changed by instructions "MOV R2,A," "ADD R2,A," or by instructions of arithmetic or logic operation on R2 (e.g., "SUB R2,A," "BS(C) R2,6," "CLR R2," etc.). In addition, the instruction set has the following features: 1. Every bit of any register can be set, cleared, or tested directly. 2. The I/O registers can be regarded as general registers. That is, the same instruction can operate on I/O registers. The following symbols are used in the Instruction Set table: Convention: R = Register designator that specifies which one of the registers (including operation and general purpose registers) is to be utilized by the instruction. Bits 6 and 7 in R4 determine the selected register bank. b = Bit field designator that selects the value for the bit located in the register R and which affects the operation. k = 8 or 10-bit constant or literal value Mnemonic NOP DAA CONTW SLEP WDTC IOW R ENI DISI RET RETI CONTR IOR R MOV R,A CLRA CLR R SUB A,R SUB R,A DECA R DEC R OR A,R OR R,A AND A,R AND R,A XOR A,R XOR R,A Operation No Operation Decimal Adjust A A CONT 0 WDT, Stop oscillator 0 WDT A IOCR Enable Interrupt Disable Interrupt [Top of Stack] PC [Top of Stack] PC, Enable Interrupt CONT A IOCR A AR 0A 0R R-A A R-A R R-1 A R-1 R A VR A A VR R A&RA A&RR ARA ARR Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) Status Affected None C None T, P T, P 1 None None None None None None 1 None None Z Z Z, C, DC Z, C, DC Z Z Z Z Z Z Z Z 89 EM78P372K 8-bit Microcontroller Mnemonic ADD A,R ADD R,A MOV A,R MOV R,R COMA R COM R INCA R INC R DJZA R DJZ R RRCA R Operation Status Affected SWAP R JZA R JZ R BC R,b BS R,b JBC R,b JBS R,b CALL k JMP k MOV A,k OR A,k AND A,k XOR A,k RETL k SUB A,k Add A,K PAGE k BANK k A+RA A+RR RA RR /R A /R R R+1 A R+1 R R-1 A, skip if zero R-1 R, skip if zero R(n) A(n-1), R(0) C, C A(7) R(n) R(n-1), R(0) C, C R(7) R(n) A(n+1), R(7) C, C A(0) R(n) R(n+1), R(7) C, C R(0) R(0-3) A(4-7), R(4-7) A(0-3) R(0-3) R(4-7) R+1 A, skip if zero R+1 R, skip if zero 0 R(b) 1 R(b) if R(b)=0, skip if R(b)=1, skip PC+1 [SP], (Page, k) PC (Page, k) PC kA AkA A&kA AkA k A, [Top of Stack] PC k-A A k+A A k R3(5) k R4(6) LCALL k PC+1[SP], kPC None LJMP k kPC None RRC R RLCA R RLC R SWAPA R Z, C, DC Z, C, DC Z Z Z Z Z Z None None C C C C None None None None 2 None 3 None None None None None None Z Z Z None Z, C, DC Z, C, DC None None If Bank 1 R5.7=0, machine code(7~0) R TBRD R Else Bank1 R5.7=1, machine code(12~8) R(4~0), None R(7~5)=(0,0,0) Note: 1 This instruction is applicable to IOC50~IOCF0, IOC51 ~ IOCF1 only. 2 This instruction is not recommended for RF operation. 3 This instruction cannot operate under RF. 90 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller 8 Absolute Maximum Ratings Items 9 Rating Temperature under bias -40C to 85C Storage temperature -65C to 150C Input voltage Vss-0.3V to Vdd+0.5V Output voltage Vss-0.3V to Vdd+0.5V Working Voltage 2.1V to 5.5V Working Frequency DC to 16 MHz DC Electrical Characteristics Ta= 25C, VDD= 5.0V, VSS= 0V Symbol Parameter Condition Min. Typ. Max. Unit 32.768k 4 16 MHz 760 950 1140 kHz Ports 5, 6, 7 0.7VDD VDD+0.3 V Ports 5, 6, 7 -0.3V 0.3VDD V /RESET 1.8 V /RESET 1.1 V TCC, INT 0.7VDD VDD+0.3 V TCC, INT -0.3V 0.3VDD V -3.7 FXT Crystal: VDD to 5V Two cycle with two clocks ERC ERC: VDD to 5V R: 5.1K, C: 100 pF VIH1 VIL1 VIHT1 VILT1 VIHT2 VILT2 IOH1 Input High Voltage (Schmitt Trigger) Input Low Voltage (Schmitt Trigger ) Input High Threshold Voltage (Schmitt Trigger) Input Low Threshold Voltage (Schmitt trigger) Input High Threshold Voltage (Schmitt Trigger) Input Low Threshold Voltage (Schmitt Trigger) Output High Voltage (Ports 5, 6, 7) Output High Voltage IOH2 VOH = 0.9VDD (Ports 51~54, mA -10 10 56~57,60~67) IOL1 Output Low Voltage (Ports 5, 6, 7) Output Low Voltage IOL2 VOL = 0.1VDD (Ports 51~54, 56~57, mA 25 60~67) Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 91 EM78P372K 8-bit Microcontroller Symbol LVR1 LVR2 LVR3 Parameter Condition Min. Typ. Max. Unit Ta=25°C 2.41 2.7 2.99 V Ta=-40~85°C 2.14 2.7 3.25 V Ta=25°C 3.1 3.5 3.92 V Ta=-40~85°C 2.73 3.5 4.25 V Ta=25°C 3.56 4.0 4.43 V Ta=-40~85°C 3.16 4.0 4.81 V Low voltage reset level Low voltage reset level Low voltage reset level IPH Pull-high current Pull-high active, input pin at VSS 70 A IPL Pull-low current Pull-low active, input pin at Vdd 40 A ISB1 Power down current 1.0 2.0 A ISB2 Power down current 10 A 15 20 A 15 25 A 1.5 1.7 mA 2.8 3.0 mA Operating supply current ICC1 ICC2 at two clocks Operating supply current at two clocks Operating supply current ICC3 at two clocks Operating supply current ICC4 at two clocks All input and I/O pins at VDD, Output pin floating, WDT disabled All input and I/O pins at VDD, Output pin floating, WDT enabled /RESET= 'High', Fosc=32kHz (Crystal type, CLKS="0"), Output pin floating, WDT disabled /RESET= 'High', Fosc=32kHz (Crystal type,CLKS="0"), Output pin floating, WDT enabled /RESET= 'High', Fosc=4 MHz (Crystal type, CLKS="0"), Output pin floating, WDT enabled /RESET= 'High', Fosc=10 MHz (Crystal type, CLKS="0"), Output pin floating, WDT enabled Note: 1. These parameters are hypothetical (not tested) and are provided for design reference use only. 2. Data under Minimum, Typical, and Maximum (Min., Typ., and Max.) columns are based on hypothetical results at 25C. These data are for design reference only. 92 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller 9.1 AD Converter Characteristics Vdd=2.5V to 5.5V, Vss=0V, Ta=-40 to 85°C Symbol VAREF Parameter VASS Analog reference voltage VAI Analog input voltage Ivdd IAI1 Ivref Condition VAREF - VASS 2.5V VDD=VAREF=5.0V, Analog supply current VASS = 0.0V (V reference from Vdd) Ivdd IAI2 VDD=VAREF=5.0V, Analog supply current VASS = 0.0V (V reference IVref from VREF) ADREF=0, Internal VDD Min. Typ. Max. Unit 2.5 Vdd V Vss Vss V VASS VAREF V 1400 µA 10 µA 900 µA 500 µA 9 10 Bits RN1 Resolution RN2 Resolution VDD=VREF=5.0V, VSS = 0.0V 11 12 Bits LN1 Linearity error VDD = 2.5 to 5.5V Ta=25°C ±4 LSB DNL Differential nonlinear error VDD = 2.5 to 5.5V Ta=25°C ±1 LSB FSE1 Full scale error VDD=VAREF=5.0V, VASS = 0.0V ±8 LSB OE Offset error VDD=VAREF=5.0V, VASS = 0.0V ±4 LSB ZAI Recommended impedance of analog voltage source 10 KΩ TAD ADC clock duration VDD=VAREF=5.0V, VASS = 0.0V 1 µs TCN AD conversion time VDD=VAREF=5.0V, VASS = 0.0V 16 TAD PSR Power Supply Rejection VDD=5.0V±0.5V 2 LSB VDD=5.0V, VSS = 0.0V ADREF=1, External VREF V1/4VDD Accuracy for 1/4 VDD ±3 % V1/2VDD Accuracy for 1/2 VDD ±3 % Note: 1. These parameters are hypothetical (not tested) and provided for design reference use only. 2. When ADC is off, there is no current consumption other than minor leakage current. 3. AD conversion result will not decrease when an increase of input voltage and no missing code will result. 4. These parameters are subject to change without further notice. Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 93 EM78P372K 8-bit Microcontroller 9.2 Comparator Characteristics Vdd = 5.0V, Vss=0V, Ta=-40 to 85°C Symbol Parameter Condition Min. Typ. Max. Unit VOS Input offset voltage 10 mV Vcm Input common-mode voltage range GND VDD V ICO Supply current of comparator Co=0V, Ta= -40~85℃ 70 µA TRS Response time VREF=1.0V, VRL=5V, 1 RL=5.1k, CL=15p (Note ) 1 µs TLRS Large signal response VREF=2.5V, VRL = 5V, 2 time RL = 5.1k (Note ) 250 ns 12 mA 0.2 0.4 V 2.5 - 5.5 V IOL Output sink current VSAT Saturation voltage VS Operating voltage Vi(-) = 1V, Vi(+) = 0V, 3 Vo = GND+0.5V (Note ) Vi(-)=1V, Vi(+)=0V, 3 IOL <= 4mA (Note ) Note: 1. The response time specified is a 100mV input step with 5mV overdrive. 2. The response time specified is a 0V~VDD input step with 1/2*VDD overdrive. 3. The driving ability is decided by digital output block. 9.3 OP Characteristics Vdd = 5.0V, Vss=0V, Ta=-40 to 85°C Symbol Parameter Condition Min. Typ. Max. Unit VOS Input offset voltage , Vin+=0V 10 mV SR Slew rate Ta= -40~85℃ 1.5 V/µs IVR Input voltage range 0 5 V 123 mV 4.68 V Vip=0V,IL=1.0mA OVS Output voltage swing Ta= -40~85℃ Vip=5V, IL=1.0mA Ta= -40~85℃ IOP Supply current of OP Ta= -40~85℃ 255 µA PSRR Power supply rejection ratio Ta= -40~85℃ 75 dB CMRR Common mode reject ratio 0V≦VCM≦VDD 90 dB GBP Gain bandwidth product RL=1Meg, CL=100p 2.6 MHz VS Operating Range 2.5 5.5 V Note: 1. These parameters are hypothetical (not tested) and provided for design reference use only. 2. These parameters are subject to change without further notice. 94 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller 9.4 Vref 2V/2.5V/3V/4V Characteristics Vdd = 5.0V, Vss=0V, Ta=-40 to 85°C Symbol Parameter Condition Min. Typ. Max. Unit 2.1 5.5 V VDD Power Supply IVDD DC Supply Current VDD = 5.5V, No load 200 µA Vref Voltage reference output 2V 3V 4V ±1 % VrefRT Switch Vref response time VDD = 2.1 - 5.5V, Cload = 19.2pf, Rload = 15.36KΩ 5 µs VrefWT Enable Vref warm up time VDD = VDDmin 5.5V, Cload = 19.2pf, Rload = 15.36KΩ 8 µs VDDmin Minimum Power Supply Vref + 0.2* V *VDDmin : can work at (Vref+0.1V), but has a poor PSRR. Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 95 EM78P372K 8-bit Microcontroller 10 AC Electrical Characteristics Ta=-40 to 85C, VDD=5V 5%, VSS=0V Symbol Parameter Conditions Min. Typ. Max. Unit – 45 50 55 % 125 – DC ns RC type – 16 30% – ns – – WSTO + 510/Fm – ns Dclk Input CLK duty cycle Tins Instruction cycle time (CLKS="0") Ttcc TCC input time period Tdrh Device reset hold time Ta = 25C – WSTO + 8/Fs – ms Trst /RESET pulse width Ta = 25C – WSTO + 8/Fm – ns Twdt Watchdog timer duration Ta = 25C – WSTO + 8/Fs – ms Tset Input pin setup time – – 1 s – ns Thold Input pin hold time – – 1 s – ns Tdelay Output pin delay time Cload=20pF – 16 30% – ns Tdrc ERC delay time Ta = 25C – 20 – ns Crystal type Note: 1. WSTO: The waiting time of Start-to-Oscillation 2. These parameters are hypothetical (not tested) and are provided for design reference only. 3. Data under Minimum, Typical, and Maximum (Min., Typ. and Max.) columns are based on hypothetical results at 25C. These data are for design reference use only. *. Tpor and Twdt are 16 30% ms at FSS0=1(16kHz), Ta=-40~85C, and VDD=2.1~5.5V 96 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller 11 Timing Diagrams AC Test Input / Output Waveform Note: AC Testing: Input are driven at VDD-0.5V for Logic “1” and GND+0.5V for Logic “0” Timing measurements are made at 0.75V VDD for Logic “1” and 0.25V VDD for Logic “0” Figure 11-1a AC Test Input / Output Waveform Timing Diagram Reset Timing (CLK=“0”) Figure 11-1b Reset Timing Diagram TCC Input Timing (CLKS=“0”) Figure 11-1c TCC Input Timing Diagram Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 97 EM78P372K 8-bit Microcontroller APPENDIX A Package Type OTP MCU Package Type Pin Count Package Size MSOP 10 118 mil EM78P372KD14J/S DIP 14 300 mil EM78P372KSO14J/S SOP 14 150 mil EM78P372KSO16AJ/S SOP 16 150 mil EM78P372KD18J/S DIP 18 300 mil EM78P372KSO18J/S SOP 18 300 mil EM78P372KD20J/S DIP 20 300 mil EM78P372KSO20J/S SOP 20 300 mil EM78P372KSS20J/S SSOP 20 209 mil QFN 16 3×3×0.8mm EM78P372KMS10J/S EM78P372KQN16S These are Green products which do not contain hazardous substances and comply with the third edition of Sony SS-00259 standard. Pb content is less than 100ppm and complies with Sony specifications. Part No. Electroplate type Pure Tin Ingredient (%) Sn: 100% Melting point (°C) 98 EM78P372KxJ/xS 232°C Electrical resistivity (µ-cm) 11.4 Hardness (hv) 8~10 Elongation (%) >50% Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller B Packaging Configuration B.1 EM78P372KD14 Figure B-1 EM78P372K 14-pin PDIP Package Type Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 99 EM78P372K 8-bit Microcontroller B.2 EM78P372KSO14 Figure B-2 EM78P372K 14-pin SOP Package Type 100 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller B.3 EM78P372KSO16A Min. 1.350 0.100 1.300 0.330 0.190 3.800 5.800 9.800 0.600 Normal 1.400 Max. 1.750 0.250 1.500 0.510 0.250 4.000 6.200 10.000 1.270 1.27 (TYP) 0 8 A2 Symbol A A1 A2 b c E H D L e θ Figure B-3 EM78P372K 16-pin SOP Package Type Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 101 EM78P372K 8-bit Microcontroller B.4 EM78P372KD18 Figure B-4 EM78P372K 18-pin PDIP Package Type 102 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller B.5 EM78P372KSO18 Figure B-5 EM78P372K 18-pin SOP Package Type Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 103 EM78P372K 8-bit Microcontroller EM78P372KD20 A1 A2 B.6 Figure B-6 EM78P372K 20-pin PDIP Package Type 104 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller B.7 EM78P372KSO20 Figure B-7 EM78P372K 20-pin SOP Package Type Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 105 EM78P372K 8-bit Microcontroller A2 E EM78P372KSS20 E1 B.8 Figure B-8 EM78P372K 20-pin SSOP Package Type 106 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) EM78P372K 8-bit Microcontroller B.9 EM78P372KMS10 Figure B-9 EM78P372K 10-pin MSOP Package Type Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice) 107 EM78P372K 8-bit Microcontroller B.10 EM78P372KQN16 Figure B-10 EM78P372K 16-pin QFN Package Type 108 Product Specification (V1.1) 02.09.2015 (This specification is subject to change without prior notice)