AT8PE53 EPROM/ROM-Based 8-Bit Microcontroller Series Devices Included in this Data Sheet: ‧ AT8PE53E : EPROM device ‧ AT8PE53 : Mask ROM device FEATURES ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ Only 42 single word instructions All instructions are single cycle except for program branches which are two-cycle 13-bit wide instructions All ROM/EPROM area GOTO instruction All ROM/EPROM area subroutine CALL instruction 8-bit wide data path 5-level deep hardware stack Operating speed: DC-20 MHz clock input DC-100 ns instruction cycle Device Pins # I/O # EPROM/ROM (Byte) RAM (Byte) AT8PE53/E53E 14 12 1K 49 Direct, indirect addressing modes for data accessing 8-bit real time clock/counter (Timer0) with 8-bit programmable prescaler Internal Power-on Reset (POR) Built-in Low Voltage Detector (LVD) for Brown-out Reset (BOR) Power-up Reset Timer (PWRT) and Oscillator Start-up Timer(OST) On chip Watchdog Timer (WDT) with internal oscillator for reliable operation and soft-ware watch-dog enable/disable control Two I/O ports IOA and IOB with independent direction control Soft-ware I/O pull-high/pull-down or open-drain control One internal interrupt source: Timer0 overflow; Two external interrupt source: INT pin, Port B input change Wake-up from SLEEP by INT pin or Port B input change Power saving SLEEP mode Built-in 8MHz, 4MHz, 1MHz, and 455KHz internal RC oscillator Programmable Code Protection Built-in internal RC oscillator Selectable oscillator options: - ERC: External Resistor/Capacitor Oscillator - HF: High Frequency Crystal/Resonator Oscillator - XT: Crystal/Resonator Oscillator - LF: Low Frequency Crystal Oscillator - IRC: Internal Resistor/Capacitor Oscillator - ERIC: External Resistor/Internal Capacitor Oscillator Wide-operating voltage range: - EPROM : 2.3V to 5.5V - ROM : 2.3V to 5.5V This datasheet contains new product information. ATWin Technology reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product. Rev1.2 Mar 27, 2010 P.1/AT8PE53 AT8PE53 GENERAL DESCRIPTION The AT8PE53 series is a family of low-cost, high speed, high noise immunity, EPROM/ROM-based 8-bit CMOS microcontrollers. It employs a RISC architecture with only 42 instructions. All instructions are single cycle except for program branches which take two cycles. The easy to use and easy to remember instruction set reduces development time significantly. The AT8PE53 series consists of Power-on Reset (POR), Brown-out Reset (BOR), Power-up Reset Timer (PWRT), Oscillator Start-up Timer(OST), Watchdog Timer, EPROM/ROM, SRAM, tri-state I/O port, I/O pull-high/open-drain/pull-down control, Power saving SLEEP mode, real time programmable clock/counter, Interrupt, Wake-up from SLEEP mode, and Code Protection for EPROM products. There are three oscillator configurations to choose from, including the power-saving LP (Low Power) oscillator and cost saving RC oscillator. The AT8PE53 address 1K×13 of program memory. The AT8PE53 can directly or indirectly address its register files and data memory. All special function registers including the program counter are mapped in the data memory. BLOCK DIAGRAM Oscillator Circuit 5-level STACK Watchdog Timer Program Counter FSR SRAM ALU EPROM / ROM Instruction Decoder PORTA PORTB Interrupt Control Timer0 Accumulator Rev1.2 Mar 27, 2010 P.2/AT8PE53 AT8PE53 PIN CONNECTION PDIP, SOP IOA0 1 14 IOA1 IOB7 2 13 IOA2 IOB6 3 12 IOA3 11 Vss 10 IOB0/INT AT8PE53 AT8PE53E Vdd 4 IOB5/OSCI 5 IOB4/OSCO 6 9 IOB1 IOB3/RSTB 7 8 IOB2/T0CKI PIN DESCRIPTIONS Name I/O IOA0 ~ IOA3 I/O IOB0/INT I/O IOB1 I/O IOB2/T0CKI I/O IOB3/RSTB I IOB4/OSCO I/O IOB5/OSCI I/O IOB6 ~ IOB7 I/O Vdd Vss - Description IOA0 ~ IOA3 as bi-direction I/O pin Software controlled pull-down Bi-direction I/O pin with system wake-up function Software controlled pull-high/open-drain/pull-down / External interrupt input Bi-direction I/O pin with system wake-up function Software controlled pull-high/open-drain/pull-down Bi-direction I/O pin with system wake-up function Software controlled pull-high/open-drain/pull-down / External clock input to Timer0 IOB3 is input pin only with system wake-up function / System clear (RESET) input. Active low RESET to the device. Weak pull-high always on if configured as RSTB. Bi-direction I/O pin with system wake-up function (RCOUT optional in IRC/ERIC, ERC mode) Software controlled pull-high/open-drain / Oscillator crystal output (XT, LP mode) Outputs with the instruction cycle rate (RCOUT optional in IRC/ERIC, ERC mode) Bi-direction I/O pin with system wake-up function (IRC mode) Software controlled pull-high/open-drain / Oscillator crystal input (XT, LP mode) External clock source input (ERIC, ERC mode) Bi-direction I/O pin with system wake-up function Software controlled pull-high/open-drain Positive supply Ground Legend: I=input, O=output, I/O=input/output Rev1.2 Mar 27, 2010 P.3/AT8PE53 AT8PE53 1.0 MEMORY ORGANIZATION AT8PE53 memory is organized into program memory and data memory. 1.1 Program Memory Organization The AT8PE53 have a 10-bit Program Counter capable of addressing a 1K×13 program memory space. The RESET vector for the AT8PE53 is at 3FFh. The H/W interrupt vector is at 008h. And the S/W interrupt vector is at 002h. AT8PE53 supports all ROM/EPROM area CALL/GOTO instructions without page. FIGURE 1.1: Program Memory Map and STACK PC<9:0> Stack 1 Stack 2 Stack 3 Stack 4 Stack 5 3FFh Reset Vector : : 008h H/W Interrupt Vector 002h S/W Interrupt Vector 000h AT8PE53/53E Rev1.2 Mar 27, 2010 P.4/AT8PE53 AT8PE53 1.2 Data Memory Organization Data memory is composed of Special Function Registers and General Purpose Registers. The General Purpose Registers are accessed either directly or indirectly through the FSR register. The Special Function Registers are registers used by the CPU and peripheral functions to control the operation of the device. TABLE 1.1: Registers File Map for AT8PE53 Series Address Description 00h INDF 01h TMR0 02h PCL 03h STATUS 04h FSR 05h PORTA 06h PORTB 07h General Purpose Register 08h PCON 09h WUCON 0Ah PCHBUF 0Bh PDCON 0Ch ODCON 0Dh PHCON 0Eh INTEN 0Fh INTFLAG 10h ~ 3Fh General Purpose Registers N/A OPTION 05h 06h IOSTA IOSTB TABLE 1.2: The Registers Controlled by OPTION or IOST Instructions Address Name B7 B6 B5 B4 B3 N/A (w) 05h (w) 06h (w) OPTION IOSTA IOSTB * INTEDG TABLE 1.3: Operational Registers Map Address Name B7 B6 00h (r/w) 01h (r/w) 02h (r/w) 03h (r/w) 04h (r/w) 05h (r/w) 06h (r/w) 07h (r/w) 08h (r/w) 09h (r/w) 0Ah (r/w) 0Bh (r/w) 0Ch (r/w) 0Dh (r/w) 0Eh (r/w) 0Fh (r/w) INDF TMR0 PCL STATUS FSR PORTA PORTB SRAM PCON WUCON PCHBUF PDCON ODCON PHCON INTEN INTFLAG B2 T0CS T0SE PSA PS2 Port A I/O Control Register Port B I/O Control Register B5 B4 B3 B2 B1 B0 PS1 PS0 B1 B0 Uses contents of FSR to address data memory (not a physical register) 8-bit real-time clock/counter Low order 8 bits of PC RST GP1 GP0 TO PD Z DC C * * Indirect data memory address pointer IOA3 IOA2 IOA1 IOA0 IOB7 IOB6 IOB5 IOB4 IOB3 IOB2 IOB1 IOB0 General Purpose Register WDTE EIS LVDTE * * * * * WUB7 WUB6 WUB5 WUB4 WUB3 WUB2 WUB1 WUB0 2 MSBs Buffer of PC /PDB2 /PDB1 /PDB0 /PDA3 /PDA2 /PDA1 /PDA0 ODB7 ODB6 ODB5 ODB4 ODB2 ODB1 ODB0 /PHB7 /PHB6 /PHB5 /PHB4 /PHB2 /PHB1 /PHB0 GIE * * * * INTIE PBIE T0IE INTIF PBIF T0IF Legend: - = unimplemented, read as ‘0’, * = unimplemented, read as ‘1’, Rev1.2 Mar 27, 2010 P.5/AT8PE53 AT8PE53 2.0 FUNCTIONAL DESCRIPTIONS 2.1 Operational Registers 2.1.1 INDF (Indirect Addressing Register) Address Name 00h (r/w) INDF B7 B6 B5 B4 B3 B2 B1 B0 Uses contents of FSR to address data memory (not a physical register) The INDF Register is not a physical register. Any instruction accessing the INDF register can actually access the register pointed by FSR Register. Reading the INDF register itself indirectly (FSR=”0”) will read 00h. Writing to the INDF register indirectly results in a no-operation (although status bits may be affected). The bits 5-0 of FSR register are used to select up to 64 registers (address: 00h ~ 3Fh). EXAMPLE 2.1: INDIRECT ADDRESSING ‧ Register file 38 contains the value 10h ‧ Register file 39 contains the value 0Ah ‧ Load the value 38 into the FSR Register ‧ A read of the INDF Register will return the value of 10h ‧ Increment the value of the FSR Register by one (@FSR=39h) ‧ A read of the INDR register now will return the value of 0Ah. FIGURE 2.1: Direct/Indirect Addressing Direct Addressing 5 from opcode location select Indirect Addressing 0 5 from FSR register 0 00h location select addressing INDF register 3Fh Rev1.2 Mar 27, 2010 P.6/AT8PE53 AT8PE53 2.1.2 TMR0 (Time Clock/Counter register) Address Name 01h (r/w) TMR0 B7 B6 B5 B4 B3 B2 B1 B0 8-bit real-time clock/counter The Timer0 is a 8-bit timer/counter. The clock source of Timer0 can come from the instruction cycle clock or by an external clock source (T0CKI pin) defined by T0CS bit (OPTION<5>). If T0CKI pin is selected, the Timer0 is increased by T0CKI signal rising/falling edge (selected by T0SE bit (OPTION<4>)). The prescaler is assigned to Timer0 by clearing the PSA bit (OPTION<3>). In this case, the prescaler will be cleared when TMR0 register is written with a value. 2.1.3 PCL (Low Bytes of Program Counter) & Stack Address 02h (r/w) Name PCL B7 B6 B5 B4 B3 Low order 8 bits of PC B2 B1 B0 AT8PE53 devices have a 10-bit wide Program Counter (PC) and five-level deep 10-bit hardware push/pop stack. The low byte of PC is called the PCL register. This register is readable and writable. The high byte of PC is called the PCH register. This register contains the PC<9:8> bits and is not directly readable or writable. All updates to the PCH register go through the PCHBUF register. As a program instruction is executed, the Program Counter will contain the address of the next program instruction to be executed. The PC value is increased by one, every instruction cycle, unless an instruction changes the PC. For a GOTO instruction, the PC<9:0> is provided by the GOTO instruction word. The PCL register is mapped to PC<7:0>, and the PCHBUF register is not updated. For a CALL instruction, the PC<9:0> is provided by the CALL instruction word. The next PC will be loaded (PUSHed) onto the top of STACK. The PCL register is mapped to PC<7:0>, and the PCHBUF register is not updated. For a RETIA, RETFIE, or RETURN instruction, the PC are updated (POPed) from the top of STACK. The PCL register is mapped to PC<7:0>, and the PCHBUF register is not updated. For any instruction where the PCL is the destination, the PC<7:0> is provided by the instruction word or ALU result. However, the PC<9:8> will come from the PCHBUF<1:0> bits (PCHBUF Æ PCH). PCHBUF register is never updated with the contents of PCH. Rev1.2 Mar 27, 2010 P.7/AT8PE53 AT8PE53 FIGURE 2.2: Loading of PC in Different Situations Situation 1: GOTO Instruction PCH 9 8 PCL 7 0 PC Opcode<9:0> - - - - - PCHBUF Situation 2: CALL Instruction PCH 9 8 STACK<9:0> PCL 7 0 PC Opcode<9:0> - - - - - PCHBUF Situation 3: RETIA, RETFIE, or RETURN Instruction STACK<9:0> PCH 9 8 7 PCL - - 0 PC - - - PCHBUF Situation 4: Instruction with PCL as destination PCH 9 8 PCL 7 0 PC PCHBUF<1:0> - - - - - ALU result<7:0> or Opcode<7:0> PCHBUF Note: 1. PCHBUF is used only for instruction with PCL as destination for AT8PE53. Rev1.2 Mar 27, 2010 P.8/AT8PE53 AT8PE53 2.1.4 STATUS (Status Register) Address Name B7 B6 B5 B4 B3 B2 B1 B0 03h (r/w) STATUS RST GP1 GP0 TO PD Z DC C This register contains the arithmetic status of the ALU, the RESET status. If the STATUS Register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS Register as destination may be different than intended. For example, CLRR STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS Register as 000u u1uu (where u = unchanged). C : Carry/borrow bit. ADDAR, ADDIA = 1, a carry occurred. = 0, a carry did not occur. SUBAR, SUBIA = 1, a borrow did not occur. = 0, a borrow occurred. Note : A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRR, RLR) instructions, this bit is loaded with either the high or low order bit of the source register. DC : Half carry/half borrow bit. ADDAR, ADDIA = 1, a carry from the 4th low order bit of the result occurred. = 0, a carry from the 4th low order bit of the result did not occur. SUBAR, SUBIA = 1, a borrow from the 4th low order bit of the result did not occur. = 0, a borrow from the 4th low order bit of the result occurred. Z : Zero bit. = 1, the result of a logic operation is zero. = 0, the result of a logic operation is not zero. PD : Power down flag bit. = 1, after power-up or by the CLRWDT instruction. = 0, by the SLEEP instruction. TO : Time overflow flag bit. = 1, after power-up or by the CLRWDT or SLEEP instruction. = 0, a watch-dog time overflow occurred. GP1:GP0 : General purpose read/write bits. RST : Bit for wake-up type. = 1, Wake-up from SLEEP on Port B input change. = 0, Wake-up from other reset types. Rev1.2 Mar 27, 2010 P.9/AT8PE53 AT8PE53 2.1.5 FSR (Indirect Data Memory Address Pointer) Address Name B7 B6 04h (r/w) FSR * * B5 B4 B3 B2 B1 B0 Indirect data memory address pointer Bit5:Bit0 : Select registers address in the indirect addressing mode. See 2.1.1 for detail description. Bit7:Bit6 : Not used. Read as “1”s. 2.1.6 PORTA, PORTB (Port Data Registers) Address Name 05h (r/w) 06h (r/w) PORTA PORTB B7 IOB7 B6 IOB6 B5 IOB5 B4 B3 B2 B1 B0 IOB4 IOA3 IOB3 IOA2 IOB2 IOA1 IOB1 IOA0 IOB0 Reading the port (PORTA, PORTB register) reads the status of the pins independent of the pin’s input/output modes. Writing to these ports will write to the port data latch. PORTA is a 4-bit port data Register. Only the low order 4 bits are used (PORTA<3:0>). Bits 7-4 are general purpose read/write bits. PORTB is a 8-bit port data register. And IOB3 is input only. 2.1.7 PCON (Power Control Register) Address Name B7 B6 B5 B4 B3 B2 B1 B0 08h (r/w) PCON WDTE EIS LVDTE * * * * * Bit4:Bit0 : Not used. Read as “1”s. LVDTE : LVDT (low voltage detector) enable bit. = 0, Disable LVDT. = 1, Enable LVDT. EIS : Define the function of IOB0/INT pin. = 0, IOB0 (bi-directional I/O pin) is selected. The path of INT is masked. = 1, INT (external interrupt pin) is selected. In this case, the I/O control bit of IOB0 must be set to “1”. The path of Port B input change of IOB0 pin is masked by hardware, the status of INT pin can also be read by way of reading PORTB. WDTE : WDT (watch-dog timer) enable bit. = 0, Disable WDT. = 1, Enable WDT. 2.1.8 WUCON (Port B Input Change Interrupt/Wake-up Control Register) Address Name B7 B6 B5 B4 B3 B2 B1 B0 09h (r/w) WUCON WUB7 WUB6 WUB5 WUB4 WUB3 WUB2 WUB1 WUB0 WUB0 : = 0, Disable the input change interrupt/wake-up function of IOB0 pin. = 1, Enable the input change interrupt/wake-up function of IOB0 pin. WUB1 : = 0, Disable the input change interrupt/wake-up function of IOB1 pin. = 1, Enable the input change interrupt/wake-up function of IOB1 pin. Rev1.2 Mar 27, 2010 P.10/AT8PE53 AT8PE53 WUB2 : = 0, Disable the input change interrupt/wake-up function of IOB2 pin. = 1, Enable the input change interrupt/wake-up function of IOB2 pin. WUB3 : = 0, Disable the input change interrupt/wake-up function of IOB3 pin. = 1, Enable the input change interrupt/wake-up function of IOB3 pin. WUB4 : = 0, Disable the input change interrupt/wake-up function of IOB4 pin. = 1, Enable the input change interrupt/wake-up function of IOB4 pin. WUB5 : = 0, Disable the input change interrupt/wake-up function of IOB5 pin. = 1, Enable the input change interrupt/wake-up function of IOB5 pin. WUB6 : = 0, Disable the input change interrupt/wake-up function of IOB6 pin. = 1, Enable the input change interrupt/wake-up function of IOB6 pin. WUB7 : = 0, Disable Enable the input change interrupt/wake-up function of IOB7 pin. = 1, Enable the input change interrupt/wake-up function of IOB7 pin. 2.1.9 PCHBUF (High Byte Buffer of Program Counter) Address Name B7 B6 B5 B4 B3 B2 0Ah (r/w) PCHBUF - - - - - - B1 B0 2 MSBs Buffer of PC Bit1:Bit0 : See 2.1.3 for detail description. Bit7:Bit2 : Not used. Read as “0”s. 2.1.10 PDCON (Pull-down Control Register) Address Name 0Bh (r/w) PDCON B7 B6 B5 B4 B3 B2 B1 B0 /PDB2 /PDB1 /PDB0 /PDA3 /PDA2 /PDA1 /PDA0 /PDA0 : = 0, Enable the internal pull-down of IOA0 pin. = 1, Disable the internal pull-down of IOA0 pin. /PDA1 : = 0, Enable the internal pull-down of IOA1 pin. = 1, Disable the internal pull-down of IOA1 pin. /PDA2 : = 0, Enable the internal pull-down of IOA2 pin. = 1, Disable the internal pull-down of IOA2 pin. /PDA3 : = 0, Enable the internal pull-down of IOA3 pin. = 1, Disable the internal pull-down of IOA3 pin. /PDB0 : = 0, Enable the internal pull-down of IOB0 pin. = 1, Disable the internal pull-down of IOB0 pin. /PDB1 : = 0, Enable the internal pull-down of IOB1 pin. = 1, Disable the internal pull-down of IOB1 pin. /PDB2 : = 0, Enable the internal pull-down of IOB2 pin. = 1, Disable the internal pull-down of IOB2 pin. Bit7 : General purpose read/write bit. Rev1.2 Mar 27, 2010 P.11/AT8PE53 AT8PE53 2.1.11 ODCON (Open-drain Control Register) Address Name B7 B6 B5 B4 0Ch (r/w) ODCON ODB7 ODB6 ODB5 ODB4 B3 B2 B1 B0 ODB2 ODB1 ODB0 ODB0 : = 0, Disable the internal open-drain of IOB0 pin. = 1, Enable the internal open-drain of IOB0 pin. ODB1 : = 0, Disable the internal open-drain of IOB1 pin. = 1, Enable the internal open-drain of IOB1 pin. ODB2 : = 0, Disable the internal open-drain of IOB2 pin. = 1, Enable the internal open-drain of IOB2 pin. Bit3 : General purpose read/write bit. ODB4 : = 0, Disable the internal open-drain of IOB4 pin. = 1, Enable the internal open-drain of IOB4 pin. ODB5 : = 0, Disable the internal open-drain of IOB5 pin. = 1, Enable the internal open-drain of IOB5 pin. ODB6 : = 0, Disable the internal open-drain of IOB6 pin. = 1, Enable the internal open-drain of IOB6 pin. ODB7 : = 0, Disable the internal open-drain of IOB7 pin. = 1, Enable the internal open-drain of IOB7 pin. 2.1.12 PHCON (Pull-high Control Register) Address Name B7 B6 B5 B4 0Dh (r/w) PHCON /PHB7 /PHB6 /PHB5 /PHB4 B3 B2 B1 B0 /PHB2 /PHB1 /PHB0 /PHB0 : = 0, Enable the internal pull-high of IOB0 pin. = 1, Disable the internal pull-high of IOB0 pin. /PHB1 : = 0, Enable the internal pull-high of IOB1 pin. = 1, Disable the internal pull-high of IOB1 pin. /PHB2 : = 0, Enable the internal pull-high of IOB2 pin. = 1, Disable the internal pull-high of IOB2 pin. Bit3 : General purpose read/write bit. /PHB4 : = 0, Enable the internal pull-high of IOB4 pin. = 1, Disable the internal pull-high of IOB4 pin. /PHB5 : = 0, Enable the internal pull-high of IOB5 pin. = 1, Disable the internal pull-high of IOB5 pin. /PHB6 : = 0, Enable the internal pull-high of IOB6 pin. = 1, Disable the internal pull-high of IOB6 pin. Rev1.2 Mar 27, 2010 P.12/AT8PE53 AT8PE53 /PHB7 : = 0, Enable the internal pull-high of IOB7 pin. = 1, Disable the internal pull-high of IOB7 pin. 2.1.13 INTEN (Interrupt Mask Register) Address Name B7 B6 B5 B4 B3 B2 B1 B0 0Eh (r/w) INTEN GIE * * * * INTIE PBIE T0IE T0IE : Timer0 overflow interrupt enable bit. = 0, Disable the Timer0 overflow interrupt. = 1, Enable the Timer0 overflow interrupt. PBIE : Port B input change interrupt enable bit. = 0, Disable the Port B input change interrupt. = 1, Enable the Port B input change interrupt . INTIE : External INT pin interrupt enable bit. = 0, Disable the External INT pin interrupt. = 1, Enable the External INT pin interrupt. Bit6:BIT3 : Not used. Read as “1”s. GIE : Global interrupt enable bit. = 0, Disable all interrupts. For wake-up from SLEEP mode through an interrupt event, the device will continue execution at the instruction after the SLEEP instruction. = 1, Enable all un-masked interrupts. For wake-up from SLEEP mode through an interrupt event, the device will branch to the interrupt address (008h). Note : When an interrupt event occur with the GIE bit and its corresponding interrupt enable bit are all set, the GIE bit will be cleared by hardware to disable any further interrupts. The RETFIE instruction will exit the interrupt routine and set the GIE bit to re-enable interrupt. 2.1.14 INTFLAG (Interrupt Status Register) Address Name B7 B6 B5 B4 B3 B2 B1 B0 0Fh (r/w) INTFLAG - - - - - INTIF PBIF T0IF T0IF : Timer0 overflow interrupt flag. Set when Timer0 overflows, reset by software. PBIF : Port B input change interrupt flag. Set when Port B input changes, reset by software. INTIF : External INT pin interrupt flag. Set by rising/falling (selected by INTEDG bit (OPTION<6>)) edge on INT pin, reset by software. Bit7:BIT3 : Not used. Read as “0”s. 2.1.15 ACC (Accumulator) Address Name N/A (r/w) ACC B7 B6 B5 B4 B3 B2 B1 B0 Accumulator Accumulator is an internal data transfer, or instruction operand holding. It can not be addressed. Rev1.2 Mar 27, 2010 P.13/AT8PE53 AT8PE53 2.1.16 OPTION Register Address Name B7 N/A (w) OPTION * Accessed by OPTION instruction. B6 B5 B4 B3 B2 B1 B0 INTEDG T0CS T0SE PSA PS2 PS1 PS0 By executing the OPTION instruction, the contents of the ACC Register will be transferred to the OPTION Register. The OPTION Register is a 7-bit wide, write-only register which contains various control bits to configure the Timer0/WDT prescaler, Timer0, and the external INT interrupt. The OPTION Register are “write-only” and are set all “1”s except INTEDG bit. PS2:PS0 : Prescaler rate select bits. PS2:PS0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 Timer0 Rate WDT Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 0 1 0 1 0 1 0 1 PSA : Prescaler assign bit. = 1, WDT (watch-dog timer). = 0, TMR0 (Timer0). T0SE : TMR0 source edge select bit. = 1, Falling edge on T0CKI pin. = 0, Rising edge on T0CKI pin. T0CS : TMR0 clock source select bit. = 1, External T0CKI pin. Pin IOB2/T0CKI is forced to be an input even if IOST IOB2 = “0”. = 0, internal instruction clock cycle. INTEDG : Interrupt edge select bit. = 1, interrupt on rising edge of INT pin. = 0, interrupt on falling edge of INT pin. Bit7 : Not used. 2.1.17 IOSTA & IOSTB (Port I/O Control Registers) Address Name 05h (w) 06h (w) IOSTA IOSTB B7 B6 B5 B4 B3 B2 B1 B0 Port A I/O Control Register Port B I/O Control Register Accessed by IOST instruction. The Port I/O Control Registers are loaded with the contents of the ACC Register by executing the IOST R (05h~06h) instruction. A ‘1’ from a IOST Register bit puts the corresponding output driver in hi-impedance state (input mode). A ‘0’ enables the output buffer and puts the contents of the output data latch on the selected pins (output mode). The IOST Registers are “write-only” and are set (output drivers disabled) upon RESET. Rev1.2 Mar 27, 2010 P.14/AT8PE53 AT8PE53 2.2 I/O Ports Port A and port B are bi-directional tri-state I/O ports. Port A is a 4-pin I/O port. Port B is a 8-pin I/O port. Please note that IOB3 is an input only pin. All I/O pins have data direction control registers (IOSTA, IOSTB) which can configure these pins as output or input. The exceptions are IOB3 which is input only and IOB2 which may be controlled by the T0CS bit (OPTION<5>). IOB<7:4> and IOB<2:0> have its corresponding pull-high control bits (PHCON register) to enable the weak internal pull-high. The weak pull-high is automatically turned off when the pin is configured as an output pin. IOA<3:0> and IOB<2:0> have its corresponding pull-down control bits (PDCON register) to enable the weak internal pull-down. The weak pull-down is automatically turned off when the pin is configured as an output pin. IOB<7:4> and IOB<2:0> have its corresponding open-drain control bits (ODCON register) to enable the open-drain output when these pins are configured to be an output pin. IOB<7:0> also provides the input change interrupt/wake-up function. Each pin has its corresponding input change interrupt/wake-up enable bits (WUCON) to select the input change interrupt/wake-up source. The IOB0 is also an external interrupt input signal by setting the EIS bit (PCON<6>). In this case, IOB0 input change interrupt/wake-up function will be disabled by hardware even if it is enabled by software. The CONFIGURATION words can set several I/Os to alternate functions. When acting as alternate functions the pins will read as “0” during port read. FIGURE 2.3: Block Diagram of I/O PINs IOA3 ~ IOA0 : Data bus D Q IOST Latch Q > EN IOST R I/O PIN D Q DATA Latch Q > EN WR PORT RD PORT Pull-down is not shown in the figure IOB3 : Data bus I/O PIN RD PORT Q Set PBIF WUBn D Latch Q EN< Rev1.2 Mar 27, 2010 P.15/AT8PE53 AT8PE53 IOB0/INT : Data bus D Q IOST Latch Q > EN IOST R I/O PIN D Q DATA Latch Q > EN WR PORT RD PORT Q Set PBIF D Latch Q WUBn EN< EIS INTEDG INT EIS Pull-high/pull-down and open-drain are not shown in the figure IOB7 ~ IOB1 : Data bus D Q IOST Latch IOST R Q > EN I/O PIN D Q DATA Latch WR PORT Q > EN RD PORT Set PBIF WUBn Q D Latch Q EN< Pull-high/pull-down and open-drain are not shown in the figure Rev1.2 Mar 27, 2010 P.16/AT8PE53 AT8PE53 2.3 Timer0/WDT & Prescler 2.3.1 Timer0 The Timer0 is a 8-bit timer/counter. The clock source of Timer0 can come from the internal clock or by an external clock source (T0CKI pin). 2.3.1.1 Using Timer0 with an Internal Clock : Timer mode Timer mode is selected by clearing the T0CS bit (OPTION<5>). In timer mode, the timer0 register (TMR0) will increment every instruction cycle (without prescaler). If TMR0 register is written, the increment is inhibited for the following two cycles. 2.3.1.2 Using Timer0 with an External Clock : Counter mode Counter mode is selected by setting the T0CS bit (OPTON<5>). In this mode, Timer0 will increment either on every rising or falling edge of pin T0CKl. The incrementing edge is determined by the source edge select bit T0SE (OPTION<4>). The external clock requirement is due to internal phase clock (Tosc) synchronization. Also, there is a delay in the actual incrementing of Timer0 after synchronization. When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the T2 and T4 cycles of the internal phase clocks. Therefore, it is necessary for T0CKI to be high for at least 2 TOSC and low for at least 2 Tosc. When a prescaler is used, the external clock input is divided by the asynchronous prescaler. For the external clock to meet the sampling requirement, the ripple counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4Tosc divided by the prescaler value. 2.3.2 Watchdog Timer (WDT) The Watchdog Timer (WDT) is a free running on-chip RC oscillator which does not require any external components. So the WDT will still run even if the clock on the OSCI and OSCO pins is turned off, such as in SLEEP mode. During normal operation or in SLEEP mode, a WDT time-out will cause the device reset and the TO bit (STATUS<4>) will be cleared. The WDT can be disabled by clearing the control bit WDTE (PCON<7>) to “0”. The WDT has a nominal time-out period of 18 ms, 4.5ms, 288ms or 72ms selected by SUT<1:0> bits of configuration word (without prescaler). If a longer time-out period is desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT controlled by the OPTION register. Thus, the longest time-out period is approxmately 36.8 seconds. The CLRWDT instruction clears the WDT and the prescaler, if assigned to the WDT, and prevents it from timing out and generating a device reset. The SLEEP instruction resets the WDT and the prescaler, if assigned to the WDT. This gives the maximum SLEEP time before a WDT Wake-up Reset. 2.3.3 Prescaler An 8-bit counter (down counter) is available as a prescaler for the Timer0, or as a postscaler for the Watchdog Timer (WDT). Note that the prescaler may be used by either the Timer0 module or the WDT, but not both. Thus, a prescaler assignment for the Timer0 means that there is no prescaler for the WDT, and vice-versa. The PSA bit (OPTION<3>) determines prescaler assignment. The PS<2:0> bits (OPTION<2:0>) determine prescaler ratio. When the prescaler is assigned to the Timer0 module, all instructions writing to the TMR0 register will clear the prescaler. When it is assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT. The prescaler is neither readable nor writable. On a RESET, the prescaler contains all ‘1’s. To avoid an unintended device reset, CLRWDT or CLRR TMR0 instructions must be executed when changing the Rev1.2 Mar 27, 2010 P.17/AT8PE53 AT8PE53 prescaler assignment from Timer0 to the WDT, and vice-versa. FIGURE 2.4: Block Diagram of The Timer0/WDT Prescaler Instruction Cycle (Fosc/4 or Fosc/2 or Fosc/8) 0 T0CKI 1 1 MUX 0 T0SE MUX Sync 2 Cycles T0CS TMR0 Register 8 Data Bus Set T0IF flag on overflow PSA 0 Watchdog Timer 1 MUX 8-Bit Prescaler 1 0 PSA MUX WDT Time-out PS2:PS0 PSA 2.4 Interrupts The AT8PE53 series has up to three sources of interrupt: 1. External interrupt INT pin. 2. TMR0 overflow interrupt. 3. Port B input change interrupt (pins IOB7:IOB0). INTFLAG is the interrupt flag register that recodes the interrupt requests in the relative flags. A global interrupt enable bit, GIE (INTEN<7>), enables (if set) all un-masked interrupts or disables (if cleared) all interrupts. Individual interrupts can be enabled/disabled through their corresponding enable bits in INTEN register regardless of the status of the GIE bit. When an interrupt event occur with the GIE bit and its corresponding interrupt enable bit are all set, the GIE bit will be cleared by hardware to disable any further interrupts, and the next instruction will be fetched from address 008h. The interrupt flag bits must be cleared by software before re-enabling GIE bit to avoid recursive interrupts. The RETFIE instruction exits the interrupt routine and set the GIE bit to re-enable interrupt. The flag bit (except PBIF bit) in INTFLAG register is set by interrupt event regardless of the status of its mask bit. Reading the INTFLAG register will be the logic AND of INTFLAG and INTEN. When an interrupt is generated by the INT instruction, the next instruction will be fetched from address 002h. 2.4.1 External INT Interrupt External interrupt on INT pin is rising or falling edge triggered selected by INTEDG (OPTION<6>). When a valid edge appears on the INT pin the flag bit INTIF (INTFLAG<2>) is set. This interrupt can be disabled by clearing INTIE bit (INTEN<2>). The INT pin interrupt can wake-up the system from SLEEP condition, if bit INTIE was set before going to SLEEP. If GIE bit was set, the program will execute interrupt service routine after wake-up; or if GIE bit was cleared, the program will execute next PC after wake-up. 2.4.2 Timer0 Interrupt An overflow (FFh Æ 00h) in the TMR0 register will set the flag bit T0IF (INTFLAG<0>). This interrupt can be disabled by clearing T0IE bit (INTEN<0>). Rev1.2 Mar 27, 2010 P.18/AT8PE53 AT8PE53 2.4.3 Port B Input Change Interrupt An input change on IOB<7:0> set flag bit PBIF (INTFLAG<1>). This interrupt can be disabled by clearing PBIE bit (INTEN<1>). Before the port B input change interrupt is enabled, reading PORTB (any instruction accessed to PORTB, including read/write instructions) is necessary. Any pin which corresponding WUBn bit (WUCON<7:0>) is cleared to “0” or configured as output or IOB0 pin configured as INT pin will be excluded from this function. The port B input change interrupt also can wake-up the system from SLEEP condition, if bit PBIE was set before going to SLEEP. And GIE bit also decides whether or not the processor branches to the interrupt vector following wake-up. If GIE bit was set, the program will execute interrupt service routine after wake-up; or if GIE bit was cleared, the program will execute next PC after wake-up. 2.5 Power-down Mode (SLEEP) Power-down mode is entered by executing a SLEEP instruction. When SLEEP instruction is executed, the PD bit (STATUS<3>) is cleared, the TO bit is set, the watchdog timer will be cleared and keeps running, and the oscillator driver is turned off. All I/O pins maintain the status they had before the SLEEP instruction was executed. 2.5.1 Wake-up from SLEEP Mode The device can wake-up from SLEEP mode through one of the following events: 1. RSTB reset. 2. WDT time-out reset (if enabled). 3. Interrupt from RB0/INT pin, or PORTB change interrupt. External RSTB reset and WDT time-out reset will cause a device reset. The PD and TO bits can be used to determine the cause of device reset. The PD bit is set on power-up and is cleared when SLEEP instruction is executed. The TO bit is cleared if a WDT time-out occurred. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set. Wake-up is regardless of the GIE bit. If GIE bit is cleared, the device will continue execution at the instruction after the SLEEP instruction. If the GIE bit is set, the device will branch to the interrupt address (008h). In HF or LF oscillation mode, the system wake-up delay time is 18/4.5/288/72ms (selected by SUT<1:0> bits of configuration word) plus 16 oscillator cycles time. And in IRC/ERIC or ERC oscillation mode, the system wake-up delay time is 140us. 2.6 Reset AT8PE53 devices may be RESET in one of the following ways: 1. Power-on Reset (POR) 2. Brown-out Reset (BOR) 3. RSTB Pin Reset 4. WDT time-out Reset Some registers are not affected in any RESET condition. Their status is unknown on Power-on Reset and unchanged in any other RESET. Most other registers are reset to a “reset state” on Power-on Reset, RSTB or WDT Reset. A Power-on RESET pulse is generated on-chip when Vdd rise is detected. To use this feature, the user merely ties the RSTB pin to Vdd. On-chip Low Voltage Detector (LVD) places the device into reset when Vdd is below a fixed voltage. This ensures that the device does not continue program execution outside the valid operation Vdd range. Brown-out RESET is typically used in AC line or heavy loads switched applications. A RSTB or WDT Wake-up from SLEEP also results in a device RESET, and not a continuation of operation before SLEEP. Rev1.2 Mar 27, 2010 P.19/AT8PE53 AT8PE53 The TO and PD bits (STATUS<4:3>) are set or cleared depending on the different reset conditions. 2.6.1 Power-up Reset Timer(PWRT) The Power-up Reset Timer provides a nominal 18/4.5/288/72ms (selected by SUT<1:0> bits of configuration word) (or 140us, varies based on oscillator selection and reset condition) delay after Power-on Reset (POR), Brown-out Reset (BOR), RSTB Reset or WDT time-out Reset. The device is kept in reset state as long as the PWRT is active. The PWDT delay will vary from device to device due to Vdd, temperature, and process variation. TABLE 2.1: PWRT Period Power-on Reset Oscillator Mode Brown-out Reset RSTB Reset WDT time-out Reset ERC & IRC/ERIC 18/4.5/288/72 ms 140 us HF & LF 18/4.5/288/72 ms 18/4.5/288/72ms 2.6.2 Oscillator Start-up Timer(OST) The OST timer provides a 16 oscillator cycle delay (from OSCI input) after the PWRT delay (18/4.5/288/72ms) is over in HF or LF oscillation mode. This delay ensures that the X’tal oscillator or resonator has started and stabilized. The device is kept in reset state as long as the OST is active. This counter only starts incrementing after the amplitude of the OSCI signal reaches the oscillator input thresholds. 2.6.3 Reset Sequence When Power-on Reset (POR), Brown-out Reset (BOR), RSTB Reset or WDT time-out Reset is detected, the reset sequence is as follows: 1. The reset latch is set and the PWRT & OST are cleared. 2. When the internal POR, BOR, RSTB Reset or WDT time-out Reset pulse is finished, then the PWRT begins counting. 3. After the PWRT time-out, the OST is activated. 4. And after the OST delay is over, the reset latch will be cleared and thus end the on-chip reset signal. In HF or LF oscillation mode, the totally system reset delay time is 18/4.5/288/72ms plus 16 oscillator cycle time. And in IRC/ERIC or ERC oscillation mode, the totally system reset delay time is 18/4.5/288/72ms after Power-on Reset (POR), Brown-out Reset (BOR), or 140us after RSTB Reset or WDT time-out Reset. FIGURE 2.5: Simplified Block Diagram of on-chip Reset Circuit WDT Module WDT Time-out S RSTB Vdd Low Voltage BOR Detector (LVD) Power-on Reset (POR) R Q CHIP RESET POR On-Chip RC OSC OSCI Q Reset Latch RESET RESET Power-up Reset Timer (PWRT) Oscillator Start-up Timer (OST) Rev1.2 Mar 27, 2010 P.20/AT8PE53 AT8PE53 TABLE 2.2: Reset Conditions for All Registers Register Address Power-on Reset Brown-out Reset RSTB Reset WDT Reset ACC N/A xxxx xxxx uuuu uuuu OPTION N/A -011 1111 -011 1111 IOSTA N/A ---- 1111 ---- 1111 IOSTB N/A 1111 1111 1111 1111 INDF 00h xxxx xxxx uuuu uuuu TMR0 01h xxxx xxxx uuuu uuuu PCL 02h 1111 1111 1111 1111 STATUS 03h 0001 1xxx 000# #uuu FSR 04h 11xx xxxx 11uu uuuu PORTA 05h xxxx xxxx uuuu uuuu PORTB 06h xxxx xxxx uuuu uuuu General Purpose Register 07h xxxx xxxx uuuu uuuu PCON 08h 101- ---- 101- ---- WUCON 09h 0000 0000 0000 0000 PCHBUF 0Ah ---- --00 ---- --00 PDCON 0Bh 1111 1111 1111 1111 ODCON 0Ch 0000 0000 0000 0000 PHCON 0Dh 1111 1111 1111 1111 INTEN 0Eh 0--- -000 0--- -000 INTFLAG 0Fh ---- -000 ---- -000 General Purpose Registers 10 ~ 3Fh xxxx xxxx uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented, # = refer to the following table for possible values. TABLE 2.3: RST/ TO / PD Status after Reset or Wake-up RST TO PD 0 1 1 Power-on Reset 0 1 1 Brown-out reset 0 u u RSTB Reset during normal operation 0 1 0 RSTB Reset during SLEEP 0 0 1 WDT Reset during normal operation 0 0 0 WDT Wake-up during SLEEP 1 1 0 Wake-up on pin change during SLEEP RESET was caused by Legend: u = unchanged TABLE 2.4: Events Affecting TO / PD Status Bits Event TO PD Power-on 1 1 WDT Time-Out 0 u SLEEP instruction 1 0 CLRWDT instruction 1 1 Legend: u = unchanged Rev1.2 Mar 27, 2010 P.21/AT8PE53 AT8PE53 2.7 Hexadecimal Convert to Decimal (HCD) Decimal format is another number format for AT8PE53. When the content of the data memory has been assigned as decimal format, it is necessary to convert the results to decimal format after the execution of ALU instructions. When the decimal converting operation is processing, all of the operand data (including the contents of the data memory (RAM), accumulator (ACC), immediate data, and look-up table) should be in the decimal format, or the results of conversion will be incorrect. Instruction DAA can convert the ACC data from hexadecimal to decimal format after any addition operation and restored to ACC. The conversion operation is illustrated in example 2.2. EXAMPLE 2.2: DAA CONVERSION MOVIA 90h ;Set immediate data = decimal format number “90” (ACC Å 90h) MOVAR 30h ;Load immediate data “90” to data memory address 30H MOVIA 10h ;Set immediate data = decimal format number “10” (ACC Å 10h) ADDAR 30h, 0 ;Contents of the data memory address 30H and ACC are binary-added ;the result loads to the ACC (ACC Å A0h, C Å 0) DAA ;Convert the content of ACC to decimal format, and restored to ACC ;The result in the ACC is “00” and the carry bit C is “1”. This represents the ;decimal number “100” Instruction DAS can convert the ACC data from hexadecimal to decimal format after any subtraction operation and restored to ACC. The conversion operation is illustrated in example 2.3. EXAMPLE 2.3: DAS CONVERSION MOVIA 10h ;Set immediate data = decimal format number “10” (ACC Å 10h) MOVAR 30h ;Load immediate data “10” to data memory address 30H MOVIA 20h ;Set immediate data = decimal format number “20” (ACC Å 20h) SUBAR 30h, 0 ;Contents of the data memory address 30H and ACC are binary-subtracted ;the result loads to the ACC (ACC Å F0h, C Å 0) DAS ;Convert the content of ACC to decimal format, and restored to ACC ;The result in the ACC is “90” and the carry bit C is “0”. This represents the ;decimal number “ -10” Rev1.2 Mar 27, 2010 P.22/AT8PE53 AT8PE53 2.8 Oscillator Configurations AT8PE53 can be operated in six different oscillator modes. Users can program three configuration bits (Fosc<2:0>) to select the appropriate modes: ‧ ERC: External Resistor/Capacitor Oscillator ‧ HF: High Frequency Crystal/Resonator Oscillator ‧ XT: Crystal/Resonator Oscillator ‧ LF: Low Frequency Crystal Oscillator ‧ IRC: Internal Resistor/Capacitor Oscillator ‧ ERIC: External Resistor/Internal Capacitor Oscillator In LF, XT, or HF modes, a crystal or ceramic resonator in connected to the OSCI and OSCO pins to establish oscillation. When in LF, XT, or HF modes, the devices can have an external clock source drive the OSCI pin. The ERC device option offers additional cost savings for timing insensitive applications. The RC oscillator frequency is a function of the resistor (Rext) and capacitor (Cext), the operating temperature, and the process parameter. The IRC/ERIC device option offers largest cost savings for timing insensitive applications. These devices offer 4 different internal RC oscillator frequency, 8MHz, 4MHz, 1MHz, and 455KHz, which is selected by two configuration bits (RCM<1:0>). Or user can change the oscillator frequency with external resistor. The ERIC oscillator frequency is a function of the resistor (Rext), the operating temperature, and the process parameter. FIGURE 2.6: HF, or LF Oscillator Modes (Crystal Operation or Ceramic Resonator) FM8PE53 OSCI C1 X’TAL C2 RS RF SLEEP OSCO Internal Circuit FIGURE 2.7: HF, or LF Oscillator Modes (External Clock Input Operation) OSCI Clock from External System Open FM8PE53 OSCO Rev1.2 Mar 27, 2010 P.23/AT8PE53 AT8PE53 FIGURE 2.8: ERC Oscillator Mode (External RC Oscillator) Rext FM8PE53 OSCI Internal Circuit Cext OSCO /2,/4,/8 FIGURE 2.9: ERIC Oscillator Mode (External R, Internal C Oscillator) Rext FM8PE53 OSCI Internal Circuit C OSCO /2,/4,/8 FIGURE 2.10: IRC Oscillator Mode (Internal R, Internal C Oscillator) FM8PE53 OSCI Internal Circuit C OSCO /2,/4,/8 Rev1.2 Mar 27, 2010 P.24/AT8PE53 AT8PE53 2.9 Configurations Word TABLE 2.4: Configurations Word Name Fosc<2:0> LVDT<2:0> RCM<1:0> SUT<2:0> OSCOUT RSTBIN WDTEN PROTECT Description Oscillator Selection Bits = 1, 1, 1 Æ ERC mode (external R & C) (default) OSCI pin is selected for IOB5/OSCI pin IOB4/OSCO pin is controlled by OSCOUT configuration bit = 1, 1, 0 Æ HF mode = 1, 0, 1 Æ XT mode = 1, 0, 0 Æ LF mode = 0, 1, 1 Æ IRC mode (internal R & C) IOB5 pin is selected for IOB5/OSCI pin IOB4/OSCO pin controlled by OSCOUT configuration bit = 0, 1, 0 Æ ERIC mode (external R & internal C) OSCI pin is selected for IOB5/OSCI pin IOB4/OSCO pin controlled by OSCOUT configuration bit Low Voltage Detector Selection Bit = 1, 1, 1 Æ disable (default) = 1, 1, 0 Æ enable, LVDT voltage = 2.0V, controlled by SLEEP = 1, 0, 1 Æ enable, LVDT voltage = 2.0V = 1, 0, 0 Æ enable, LVDT voltage = 3.6V = 0, 1, 1 Æ enable, LVDT voltage = 1.8V = 0, 1, 0 Æ enable, LVDT voltage = 2.2V = 0, 0, 1 Æ enable, LVDT voltage = 2.4V = 0, 0, 0 Æ enable, LVDT voltage = 2.6V IRC Mode Selection Bits = 1, 1 Æ 4MHz (default) = 1, 0 Æ 8MHz = 0, 1 Æ 1MHz = 0, 0 Æ 455KHz PWRT & WDT Time Period Selection Bits (The value must be a multiple of prescaler rate) = 1, 1, 1 Æ PWRT = WDT prescaler rate = 18ms (default) = 1, 1, 0 Æ PWRT = WDT prescaler rate = 4.5ms = 1, 0, 1 Æ PWRT = WDT prescaler rate = 288ms = 1, 0, 0 Æ PWRT = WDT prescaler rate = 72ms = 0, 1, 1 Æ PWRT = 140us, WDT prescaler rate = 18ms = 0, 1, 0 Æ PWRT = 140us, WDT prescaler rate = 4.5ms = 0, 0, 1 Æ PWRT = 140us, WDT prescaler rate = 288ms = 0, 0, 0 Æ PWRT = 140us, WDT prescaler rate = 72ms IOB4/OSCO Pin Selection Bit for IRC/ERIC/ERC Mode = 1, OSCO pin is selected (default) = 0, IOB4 pin is selected IOB3/RSTB Pin Selection Bit = 1, IOB3 pin is selected (default) = 0, RSTB pin is selected Watchdog Timer Enable Bit = 1, WDT enabled (default) = 0, WDT disabled Code Protection Bit = 1 Æ EPROM code protection off (default) = 0 Æ EPROM code protection on Rev1.2 Mar 27, 2010 P.25/AT8PE53 AT8PE53 Name OSCD<1:0> PMOD RDPORT SCHMITT CAL<6:0> Description Instruction Period Selection Bits = 1, 1 Æ four oscillator periods (default) = 1, 0 Æ two oscillator periods = 0, 0 Æ eight oscillator periods Power Mode Selection Bit = 1, Non-power saving (default) = 0, Power saving Read Port Control Bit for Output Pins = 1, From registers (default) = 0, From pins I/O Pin Input Buffer Control Bit = 1, With Schmitt-trigger (default) = 0, Without Schmitt-trigger Calibration Selection Bits for IRC Mode TABLE 2.5: Selection of IOB5/OSCI and IOB4/OSCO Pins Mode of oscillation IOB5/OSCI IOB4/OSCO IRC ERC, ERIC HF, XT, LF IOB5 OSCI OSCI IOB4/OSCO selected by OSCOUT bit IOB4/OSCO selected by OSCOUT bit OSCO Rev1.2 Mar 27, 2010 P.26/AT8PE53 AT8PE53 3.0 INSTRUCTION SET Mnemonic, Operands Description Operation Cycles Status Affected - BCR R, bit Clear bit in R 0 Æ R<b> 1 BSR R, bit Set bit in R 1 Æ R<b> 1 (1) - BTRSC R, bit Test bit in R, Skip if Clear Skip if R<b> = 0 1/2 BTRSS R, bit Test bit in R, Skip if Set Skip if R<b> = 1 1/2 (1) - NOP No Operation No operation 1 - CLRWDT Clear Watchdog Timer 00h Æ WDT, 00h Æ WDT prescaler 1 TO , PD OPTION Load OPTION register ACC Æ OPTION 1 - Go into power-down mode 00h Æ WDT, 00h Æ WDT prescaler 1 TO , PD 1 C 1 - 2 - SLEEP Adjust ACC’s data format from HEX to DEC after any addition ACC(hex) Æ ACC(dec) operation Adjust ACC’s data format from HEX to DEC after any subtraction ACC(hex) Æ ACC(dec) operation PC + 1 Æ Top of Stack, S/W interrupt 002h Æ PC DAA DAS INT RETURN Return from subroutine Top of Stack Æ PC 2 - RETFIE Return from interrupt, set GIE bit Top of Stack Æ PC, 1 Æ GIE 2 - CLRA Clear ACC 00h Æ ACC 1 Z IOST R Load IOST register ACC Æ IOST register 1 - CLRR R Clear R 00h Æ R 1 Z MOVAR R Move ACC to R ACC Æ R 1 - MOVR R, d Move R R Æ dest 1 Z DECR R, d Decrement R R - 1 Æ dest 1 Z DECRSZ R, d Decrement R, Skip if 0 R - 1 Æ dest, Skip if result = 0 1/2 (1) - INCR Increment R R + 1 Æ dest 1 Z 1/2 (1) - R, d INCRSZ R, d Increment R, Skip if 0 R + 1 Æ dest, Skip if result = 0 ADDAR R, d Add ACC and R R + ACC Æ dest 1 C, DC, Z SUBAR R, d Subtract ACC from R R - ACC Æ dest 1 C, DC, Z ADCAR R, d Add ACC and R with Carry R + ACC + C Æ dest 1 C, DC, Z SBCAR R, d Subtract ACC from R with Carry R + ACC + C Æ dest 1 C, DC, Z ANDAR R, d AND ACC with R ACC and R Æ dest 1 Z IORAR R, d Inclusive OR ACC with R ACC or R Æ dest 1 Z XORAR R, d Exclusive OR ACC with R R xor ACC Æ dest 1 Z COMR R, d Complement R R Æ dest 1 Z Rotate left R through Carry R<7> Æ C, R<6:0> Æ dest<7:1>, C Æ dest<0> 1 C RLR R, d Rev1.2 Mar 27, 2010 P.27/AT8PE53 AT8PE53 Mnemonic, Operands Description Operation C Æ dest<7>, R<7:1> Æ dest<6:0>, R<0> Æ C R<3:0> Æ dest<7:4>, R<7:4> Æ dest<3:0> Cycles Status Affected 1 C 1 - RRR R, d Rotate right R through Carry SWAPR R, d Swap R MOVIA I Move Immediate to ACC I Æ ACC 1 - ADDIA I Add ACC and Immediate I + ACC Æ ACC 1 C, DC, Z SUBIA I Subtract ACC from Immediate I - ACC Æ ACC 1 C, DC, Z ANDIA I AND Immediate with ACC ACC and I Æ ACC 1 Z IORIA I OR Immediate with ACC ACC or I Æ ACC 1 Z XORIA I Exclusive OR Immediate to ACC ACC xor I Æ ACC 1 Z 2 - 2 - 2 - RETIA I Return, place Immediate in ACC CALL I Call subroutine GOTO I Unconditional branch I Æ ACC, Top of Stack Æ PC PC + 1 Æ Top of Stack, I Æ PC I Æ PC Note: 1. 2 cycles for skip, else 1 cycle 2. bit : Bit address within an 8-bit register R R : Register address (00h to 3Fh) I : Immediate data ACC : Accumulator d : Destination select; =0 (store result in ACC) =1 (store result in file register R) dest : Destination PC : Program Counter PCHBUF : High Byte Buffer of Program Counter WDT : Watchdog Timer Counter GIE : Global interrupt enable bit TO : Time-out bit PD : Power-down bit C : Carry bit DC : Digital carry bit Z : Zero bit Rev1.2 Mar 27, 2010 P.28/AT8PE53 AT8PE53 ADCAR Syntax: Operands: Operation: Status Affected: Description: Cycles: ADDAR Syntax: Operands: Operation: Status Affected: Description: Cycles: ADDIA Syntax: Operands: Operation: Status Affected: Description: Cycles: ANDAR Syntax: Operands: Operation: Status Affected: Description: Cycles: ANDIA Syntax: Operands: Operation: Status Affected: Description: Cycles: Add ACC and R with Carry ADCAR R, d 0 ≤ R ≤ 63 d ∈ [0,1] R + ACC + C Æ dest C, DC, Z Add the contents of the ACC register and register ‘R’ with Carry. If ‘d’ is 0 the result is stored in the ACC register. If ‘d’ is ‘1’ the result is stored back in register ‘R’. 1 Add ACC and R ADDAR R, d 0 ≤ R ≤ 63 d ∈ [0,1] ACC + R Æ dest C, DC, Z Add the contents of the ACC register and register ‘R’. If ‘d’ is 0 the result is stored in the ACC register. If ‘d’ is ‘1’ the result is stored back in register ‘R’. 1 Add ACC and Immediate ADDIA I 0 ≤ I ≤ 255 ACC + I Æ ACC C, DC, Z Add the contents of the ACC register with the 8-bit immediate ‘I’. The result is placed in the ACC register. 1 AND ACC and R ANDAR R, d 0 ≤ R ≤ 63 d ∈ [0,1] ACC and R Æ dest Z The contents of the ACC register are AND’ed with register ‘R’. If ‘d’ is 0 the result is stored in the ACC register. If ‘d’ is ‘1’ the result is stored back in register ‘R’. 1 AND Immediate with ACC ANDIA I 0 ≤ I ≤ 255 ACC AND I Æ ACC Z The contents of the ACC register are AND’ed with the 8-bit immediate ‘I’. The result is placed in the ACC register. 1 Rev1.2 Mar 27, 2010 P.29/AT8PE53 AT8PE53 BCR Syntax: Operands: Operation: Status Affected: Description: Cycles: BSR Syntax: Operands: Operation: Status Affected: Description: Cycles: BTRSC Syntax: Operands: Operation: Status Affected: Description: Cycles: BTRSS Syntax: Operands: Operation: Status Affected: Description: Cycles: CALL Syntax: Operands: Operation: Status Affected: Description: Cycles: Clear Bit in R BCF R, b 0 ≤ R ≤ 63 0≤b≤7 0 Æ R<b> None Clear bit ‘b’ in register ‘R’. 1 Set Bit in R BSR R, b 0 ≤ R ≤ 63 0≤b≤7 1 Æ R<b> None Set bit ‘b’ in register ‘R’. 1 Test Bit in R, Skip if Clear BTRSC R, b 0 ≤ R ≤ 63 0≤b≤7 Skip if R<b> = 0 None If bit ‘b’ in register ‘R’ is 0 then the next instruction is skipped. If bit ‘b’ is 0 then next instruction fetched during the current instruction execution is discarded, and a NOP is executed instead making this a 2-cycle instruction.. 1(2) Test Bit in R, Skip if Set BTRSS R, b 0 ≤ R ≤ 63 0≤b≤7 Skip if R<b> = 1 None If bit ‘b’ in register ‘R’ is ‘1’ then the next instruction is skipped. If bit ‘b’ is ‘1’, then the next instruction fetched during the current instruction execution, is discarded and a NOP is executed instead, making this a 2-cycle instruction. 1(2) Subroutine Call CALL I 0 ≤ I ≤ 1023 PC +1 Æ Top of Stack; I Æ PC None Subroutine call. First, return address (PC+1) is pushed onto the stack. The 10-bit immediate address is loaded into PC bits <9:0>. CALL is a two-cycle instruction. 2 Rev1.2 Mar 27, 2010 P.30/AT8PE53 AT8PE53 CLRA Syntax: Operands: Operation: Status Affected: Description: Cycles: CLRR Syntax: Operands: Operation: Status Affected: Description: Cycles: CLRWDT Syntax: Operands: Operation: Status Affected: Description: Cycles: COMR Syntax: Operands: Operation: Status Affected: Description: Cycles: Clear ACC CLRA None 00h Æ ACC; 1ÆZ Z The ACC register is cleared. Zero bit (Z) is set. 1 Clear R CLRR R 0 ≤ R ≤ 63 00h Æ R; 1ÆZ Z The contents of register ‘R’ are cleared and the Z bit is set. 1 Clear Watchdog Timer CLRWDT None 00h Æ WDT; 00h Æ WDT prescaler (if assigned); 1 Æ TO ; 1 Æ PD TO , PD The CLRWDT instruction resets the WDT. It also resets the prescaler, if the prescaler is assigned to the WDT and not Timer0. Status bits TO and PD are set. 1 Complement R COMR R, d 0 ≤ R ≤ 63 d ∈ [0,1] R Æ dest Z The contents of register ‘R’ are complemented. If ‘d’ is 0 the result is stored in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’. 1 Adjust ACC’s data format from HEX to DEC DAA Syntax: Operands: Operation: Status Affected: Description: DAA None ACC(hex) Æ ACC(dec) C Cycles: 1 Convert the ACC data from hexadecimal to decimal format after any addition operation and restored to ACC. Rev1.2 Mar 27, 2010 P.31/AT8PE53 AT8PE53 DAS Syntax: Operands: Operation: Status Affected: Description: Cycles: DECR Syntax: Operands: Operation: Status Affected: Description: Cycles: DECRSZ Syntax: Operands: Operation: Status Affected: Description: Cycles: GOTO Syntax: Operands: Operation: Status Affected: Description: Cycles: INCR Syntax: Operands: Operation: Status Affected: Description: Cycles: Adjust ACC’s data format from HEX to DEC DAS None ACC(hex) Æ ACC(dec) None Convert the ACC data from hexadecimal to decimal format after any subtraction operation and restored to ACC. 1 Decrement R DECR R, d 0 ≤ R ≤ 63 d ∈ [0,1] R - 1 Æ dest Z Decrement register ‘R’. If ‘d’ is 0 the result is stored in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’. 1 Decrement R, Skip if 0 DECRSZ R, d 0 ≤ R ≤ 63 d ∈ [0,1] R - 1 Æ dest; skip if result =0 None The contents of register ‘R’ are decremented. If ‘d’ is 0 the result is placed in the ACC register. If ‘d’ is 1 the result is placed back in register ’R’. If the result is 0, the next instruction, which is already fetched, is discarded and a NOP is executed instead making it a two-cycle instruction. 1(2) Unconditional Branch GOTO I 0 ≤ I ≤ 1023 I Æ PC None GOTO is an unconditional branch. The 10-bit immediate value is loaded into PC bits <9:0>. GOTO is a two-cycle instruction. 2 Increment R INCR R, d 0 ≤ R ≤ 63 d ∈ [0,1] R + 1 Æ dest Z The contents of register ‘R’ are incremented. If ‘d’ is 0 the result is placed in the ACC register. If ‘d’ is 1 the result is placed back in register ‘R’. 1 Rev1.2 Mar 27, 2010 P.32/AT8PE53 AT8PE53 INCRSZ Syntax: Operands: Operation: Status Affected: Description: Cycles: INT Syntax: Operands: Operation: Status Affected: Description: Cycles: IORAR Syntax: Operands: Operation: Status Affected: Description: Cycles: IORIA Syntax: Operands: Operation: Status Affected: Description: Increment R, Skip if 0 INCRSZ R, d 0 ≤ R ≤ 63 d ∈ [0,1] R + 1 Æ dest, skip if result = 0 None The contents of register ‘R’ are incremented. If ‘d’ is 0 the result is placed in the ACC register. If ‘d’ is the result is placed back in register ‘R’. If the result is 0, then the next instruction, which is already fetched, is discarded and a NOP is executed instead making it a two-cycle instruction. 1(2) S/W Interrupt INT None PC + 1 Æ Top of Stack, 002h Æ PC None Interrupt subroutine call. First, return address (PC+1) is pushed onto the stack. The address 002h is loaded into PC bits <10:0>. 2 OR ACC with R IORAR R, d 0 ≤ R ≤ 63 d ∈ [0,1] ACC or R Æ dest Z Inclusive OR the ACC register with register ‘R’. If ‘d’ is 0 the result is placed in the ACC register. If ‘d’ is 1 the result is placed back in register ‘R’. 1 Cycles: OR Immediate with ACC IORIA I 0 ≤ I ≤ 255 ACC or I Æ ACC Z The contents of the ACC register are OR’ed with the 8-bit immediate ‘I’. The result is placed in the ACC register. 1 IOST Syntax: Operands: Operation: Status Affected: Description: Cycles: Load IOST Register IOST R R = 5 or 6 ACC Æ IOST register R None IOST register ‘R’ (R = 5 or 6) is loaded with the contents of the ACC register. 1 Rev1.2 Mar 27, 2010 P.33/AT8PE53 AT8PE53 MOVAR Syntax: Operands: Operation: Status Affected: Description: Cycles: Move ACC to R MOVAR R 0 ≤ R ≤ 63 ACC Æ R None Move data from the ACC register to register ‘R’. 1 MOVIA Syntax: Operands: Operation: Status Affected: Description: Cycles: Move Immediate to ACC MOVIA I 0 ≤ I ≤ 255 I Æ ACC None The 8-bit immediate ‘I’ is loaded into the ACC register. The don’t cares will assemble as 0s. 1 MOVR Syntax: Operands: Cycles: Move R MOVR R, d 0 ≤ R ≤ 63 d ∈ [0,1] R Æ dest Z The contents of register ‘R’ is moved to destination ‘d’. If ‘d’ is 0, destination is the ACC register. If ‘d’ is 1, the destination is file register ‘R’. ‘d’ is 1 is useful to test a file register since status flag Z is affected. 1 NOP Syntax: Operands: Operation: Status Affected: Description: Cycles: No Operation NOP None No operation None No operation. 1 OPTION Syntax: Operands: Operation: Status Affected: Description: Cycles: Load OPTION Register OPTION None ACC Æ OPTION None The content of the ACC register is loaded into the OPTION register. 1 RETFIE Syntax: Operands: Operation: Status Affected: Description: Return from Interrupt, Set ‘GIE’ Bit RETFIE None Top of Stack Æ PC None The program counter is loaded from the top of the stack (the return address). The ‘GIE’ bit is set to 1. This is a two-cycle instruction. 2 Operation: Status Affected: Description: Cycles: Rev1.2 Mar 27, 2010 P.34/AT8PE53 AT8PE53 RETIA Syntax: Operands: Operation: Status Affected: Description: Cycles: RETURN Syntax: Operands: Operation: Status Affected: Description: Cycles: RLR Syntax: Operands: Operation: Status Affected: Description: Cycles: RRR Syntax: Operands: Operation: Status Affected: Description: Cycles: Return with Immediate in ACC RETIA I 0 ≤ I ≤ 255 I Æ ACC; Top of Stack Æ PC None The ACC register is loaded with the 8-bit immediate ‘I’. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. 2 Return from Subroutine RETURN None Top of Stack Æ PC None The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. 2 Rotate Left R through Carry RLR R, d 0 ≤ R ≤ 63 d ∈ [0,1] R<7> Æ C; R<6:0> Æ dest<7:1>; C Æ dest<0> C The contents of register ‘R’ are rotated one bit to the left through the Carry Flag. If ‘d’ is 0 the result is placed in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’. 1 Rotate Right R through Carry RRR R, d 0 ≤ R ≤ 63 d ∈ [0,1] C Æ dest<7>; R<7:1> Æ dest<6:0>; R<0> Æ C C The contents of register ‘R’ are rotated one bit to the right through the Carry Flag. If ‘d’ is 0 the result is placed in the ACC register. If ‘d’ is 1 the result is placed back in register ‘R’. 1 Rev1.2 Mar 27, 2010 P.35/AT8PE53 AT8PE53 SLEEP Syntax: Operands: Operation: Status Affected: Description: Cycles: SBCAR Syntax: Operands: Operation: Status Affected: Description: Cycles: SUBAR Syntax: Operands: Operation: Status Affected: Description: Cycles: SUBIA Syntax: Operands: Operation: Status Affected: Description: Cycles: SWAPR Syntax: Operands: Operation: Status Affected: Description: Cycles: Enter SLEEP Mode SLEEP None 00h Æ WDT; 00h Æ WDT prescaler; 1 Æ TO ; 0 Æ PD TO , PD Time-out status bit ( TO ) is set. The power-down status bit ( PD ) is cleared. The WDT and its prescaler are cleared. The processor is put into SLEEP mode. 1 Subtract ACC from R with Carry SBCAR R, d 0 ≤ R ≤ 63 d ∈ [0,1] R + ACC + C Æ dest C, DC, Z Add the 2’s complement data of the ACC register from register ‘R’ with Carry. If ‘d’ is 0 the result is stored in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’. 1 Subtract ACC from R SUBAR R, d 0 ≤ R ≤ 63 d ∈ [0,1] R - ACC Æ dest C, DC, Z Subtract (2’s complement method) the ACC register from register ‘R’. If ‘d’ is 0 the result is stored in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’. 1 Subtract ACC from Immediate SUBIA I 0 ≤ I ≤ 255 I - ACC Æ ACC C, DC, Z Subtract (2’s complement method) the ACC register from the 8-bit immediate ‘I’. The result is placed in the ACC register. 1 Swap nibbles in R SWAPR R, d 0 ≤ R ≤ 63 d ∈ [0,1] R<3:0> Æ dest<7:4>; R<7:4> Æ dest<3:0> None The upper and lower nibbles of register ‘R’ are exchanged. If ‘d’ is 0 the result is placed in ACC register. If ‘d’ is 1 the result in placed in register ‘R’. 1 Rev1.2 Mar 27, 2010 P.36/AT8PE53 AT8PE53 XORAR Syntax: Operands: Operation: Status Affected: Description: Cycles: XORIA Syntax: Operands: Operation: Status Affected: Description: Cycles: Exclusive OR ACC with R XORAR R, d 0 ≤ R ≤ 63 d ∈ [0,1] ACC xor R Æ dest Z Exclusive OR the contents of the ACC register with register ’R’. If ‘d’ is 0 the result is stored in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’. 1 Exclusive OR Immediate with ACC XORIA I 0 ≤ I ≤ 255 ACC xor I Æ ACC Z The contents of the ACC register are XOR’ed with the 8-bit immediate ‘I’. The result is placed in the ACC register. 1 Rev1.2 Mar 27, 2010 P.37/AT8PE53 AT8PE53 4.0 ABSOLUTE MAXIMUM RATINGS Ambient Operating Temperature Store Temperature DC Supply Voltage (Vdd) Input Voltage with respect to Ground (Vss) 0℃ to +70℃ -65℃ to +150℃ 0V to +6.0V -0.3V to (Vdd + 0.3)V 5.0 OPERATING CONDITIONS DC Supply Voltage Operating Temperature +2.3V to +5.5V 0℃ to +70℃ Rev1.2 Mar 27, 2010 P.38/AT8PE53 AT8PE53 6.0 ELECTRICAL CHARACTERISTICS 6.1 ELECTRICAL CHARACTERISTICS of AT8PE53E Under Operating Conditions, at four clock instruction cycles and WDT & LVDT are disabled Sym Description FHF X’tal oscillation range FLF X’tal oscillation range FERC RC oscillation range FIRC/ERIC RC oscillation range Conditions Input high voltage Typ. Max. HF mode, Vdd=5V 1 20 HF mode, Vdd=3V 1 15 LF mode, Vdd=5V 32 4000 LF mode, Vdd=3V 32 1000 ERC mode, Vdd=5V DC 15 ERC mode, Vdd=3V DC 7 ERIC mode, external R, Vdd=5V DC 15 ERIC mode, external R, Vdd=3V DC 7 IRC mode, internal R, Vdd=5V 0.455 8 IRC mode, internal R, Vdd=3V 0.455 8 I/O ports, Vdd=5V VIH Min. Unit MHz KHZ MHz MHz 2.0 RSTB, T0CKI pins, Vdd=5V 2.0 I/O ports, Vdd=3V 1.5 RSTB, T0CKI pins, Vdd=3V 1.5 V I/O ports, Vdd=5V 1.0 RSTB, T0CKI pins, Vdd=5V 1.0 I/O ports, Vdd=3V 0.6 VIL Input low voltage VOH Output high voltage IOH=-5.4mA, Vdd=5V VOL Output low voltage IOL=8.7mA, Vdd=5V IPH Pull-high current Input pin at Vss, Vdd=5V -65 uA IPD Pull-down current Input pin at Vdd, Vdd=5V 45 uA Vdd=5V 9 12 Vdd=3V 2 4 RSTB, T0CKI pins, Vdd=3V IWDT WDT current TWDT WDT period ILVDT ISB LVDT current Power down current V 0.6 3.6 V 0.6 Vdd=3V Vdd=4V Vdd=5V Vdd=5V LVDT = 3.6V Vdd=5V LVDT = 2V 20.4 17.9 16.2 30 23 40 30 Vdd=3V LVDT = 2V 6.8 8.0 Sleep mode, Vdd=5V, WDT enable 20 Sleep mode, Vdd=5V, WDT disable 3 Sleep mode, Vdd=3V, WDT enable 2.5 Sleep mode, Vdd=3V, WDT disable 1.1 V uA mS uA uA 6.2 ELECTRICAL CHARACTERISTICS of AT8PE53 To be defined Rev1.2 Mar 27, 2010 P.39/AT8PE53 AT8PE53 7.0 PACKAGE DIMENSION 7.1 14-PIN PDIP 300mil 1 7 L E eB E1 8 £o D 14 0.100typ. 0.018typ. 0.060typ. Symbols Dimension In Inches Min Nom Max A - - 0.210 A1 0.015 - - A2 0.125 0.130 0.135 D 0.735 0.750 0.775 E 0.300 BSC. E1 0.245 0.250 0.255 L 0.115 0.130 0.150 eB 0.335 0.355 0.375 o θ o 0 o 7 15o Rev1.2 Mar 27, 2010 P.40/AT8PE53 AT8PE53 8 1 7 H E 14 0.015x45o 7.2 14-PIN SOP 150mil ¨ A C A1 A D e B GAUGE PLANE SEATING PLANE £o 0.010 0.004max L DETAIL : A Symbols Dimension In Inches Min Nom Max A 0.058 0.064 0.068 A1 0.004 - 0.010 B 0.013 0.016 0.020 C 0.0075 0.008 0.0098 D 0.336 0.341 0.344 E 0.150 0.154 0.157 e - 0.050 - H 0.228 0.236 0.244 L 0.015 0.025 0.050 θo 0o - 8o Rev1.2 Mar 27, 2010 P.41/AT8PE53 AT8PE53 8.0 ORDERING INFORMATION OTP Type MCU Package Type Pin Count Package Size AT8PE53EP PDIP 14 300 mil AT8PE53ED SOP 14 150 mil Mask Type MCU Package Type Pin Count Package Size AT8PE53P PDIP 14 300 mil AT8PE53D SOP 14 150 mil Rev1.2 Mar 27, 2010 P.42/AT8PE53