EM78F564N/F664N 8-Bit Microprocessor EM78F564N/664N Errata Document Specification Revision History Doc. Version Revision Description Date 1.0 Initial release version 2009/01/08 1.1 1. Showed the difference between EM78F664N and ICE652N, particularly on the TCC function. 2009/06/03 2. Modified the DC Electrical Characteristics. 1. Deleted ICE652N information and PAGE instruction. 2.0 2. Added CPU operation with Green/Idle mode, LCALL/LJMP/TBRD instructions. 2009/09/08 3. Indicated the use of ICE660N to simulate EM78F664N. 1. Redefined CPU Operation Mode information. 2.1 2. Added IRC mode selection information on Bank1 R8<7,6> and Word1<12>. 2009/11/20 3. Added Comparison between V/U-Package Versions. 2.2 1. Revised the format of the Pin Description and Wake-up signal table. 2. Added Device Characteristics. 2010/04/07 3. Combined the Specs of EM78F564N and EM78F664N. 2.3 1. Modified the maximum supportable baud rate of the SPI function. 2013/05/07 2. Added LVR specifications. 2.4 1. Added HLP in Bit 9 of Code Option Word 1. 2. Added power consumption for EEPROM. 2014/11/06 Version 2.3 to Version 2.4 A. Attached Items N.A. Errata Document (V2.4) 11.06.2014 •1 EM78F564N/F664N 8-Bit Microprocessor B. Modified Items 1 6.17.2 Code Option Register (Word 1) Page 107 6.17.2 Code Option Register (Word 1) Word 1 Bit Bit 12 Bit 11 Bit 10 Bit 9 Mne COBS0 TCEN monic – Bit 8 HLP C4 Bit 7 Bit 6 Bit 5 Bit 4 C3 C2 C1 C0 Bit 3 Bit 2 Bit 1 Bit 0 RCM1 RCM0 LVR1 LVR0 1 Register TCC – Enable High High High High High High High High High 0 Option P77 – Disable Low Low Low Low Low Low Low Low Low Bit 12 (COBS0): IRC mode select bit. 0: IRC frequency select from code option (default) 1: IRC frequency select from register. Bit 11 (TCEN): TCC enable bit. 0: P77/TCC is set as P77 (default) 1: P77/TCC is set as TCC. Bit 10: Not used, set to “1” at all time. Bit 9 (HLP): Power consumption select bit. 0: Disable, Normal power consumption (default) 1: Enable, Low power consumption. Bit 8 ~ Bit 4 (C4 ~ C0): Internal RC mode calibration bits. C4 ~ C0 must be set to “0” only (auto-calibration). Bit 3 ~ Bit 2 (RCM1 ~ RCM0): RC mode selection bits RCM1 RCM0 *Frequency (MHz) 0 0 4 (default) 0 1 16 1 0 8 1 1 455kHz Bit 1 ~ Bit 0 (LVR1 ~ LVR0): Low Voltage Reset Enable bits LVR1 LVR0 Reset Level Release Level 0 0 NA NA 0 1 2.7V 2.9V 1 0 3.7V 3.9V 1 1 4.1V 4.3V LVR1, LVR0=“0, 0” : LVR disable, power-on reset point of EM78Fx64N is 2.0~2.2V (default) 2• Errata Document (V2.4) 11.06.2014 EM78F564N/F664N 8-Bit Microprocessor LVR1, LVR0=“0, 1” : If Vdd < 2.7V, the EM78Fx64N will be reset. LVR1, LVR0=“1, 0” : If Vdd < 3.7V, the EM78Fx64N will be reset. LVR1, LVR0=“1, 1” : If Vdd < 4.1V, the EM78Fx64N will be reset. Errata Document (V2.4) 11.06.2014 •3 EM78F564N/F664N 8-Bit Microprocessor 2 9 Page 119 9 DC Electrical Characteristics DC Electrical Characteristics Data EEPROM Electrical Characteristics (only for EM78F664N) Symbol Tprog Data Retention Tendu Endurance time Iread Condition Min. Typ. Max. Unit − 4.5 − ms − 10 − years − 1000K − cycles Vdd <= 3.3V − 0.6 − mA Vdd ≤ 5.5V − 1.0 − mA Vdd ≤ 3.3V − 1.0 − mA Vdd ≤ 5.5V − 2.5 − mA Erase/Write cycle time Treten Iprg 4• Parameter Programming Read Vdd = 2.5~ 5.5V Temperature = -40°C ~ 85°C Errata Document (V2.4) 11.06.2014 EM78F564N/F664N 8-Bit Microprocessor C. Deleted Items N.A. Errata Document (V2.4) 11.06.2014 •5