CE2766 Microelectronics 6-Channel Audio DAC, 24-bit, 192kHz DESCRIPTION FEATURES The CE2766 is a mixed signal CMOS monolithic audio digital to analog converter. It contains six multi-bit sigma delta DAC. The system consists of 128-time interpolation filters, 4th order Σ∆ modulators, switch capacitors and analog reconstruction filters. The one bit Σ∆ converter offers superior differential linearity, with no distortion due to component mis-match. high tolerance to clock jitter. • Six Channel Audio DAC. - 101 dB SNR (A Weighted). - -86 dB THD + N Ratio (A Weighted). - 32K - 192 KHz. Sampling Rates. - Independent Digital Volume Control. - I2S, Left and Right Justified Digital Input Formats. - On -chip Reconstruction Filters. • 2-wire Serial Control Interface. • Single 3.3 Volt Power Supply. The CE2766 support data conversion from 32K to 192KHz. The chip is operated at 3.3 volt to simplify the power requirement. The CE2766 is ideal for DVD player, AV receiver and set-top box application. The CE2766 support 32, 24, 20 and 16-bit input data. It also support multiple sampling frequency data. Each DAC has its own individual volume control. DIN1 80 DIN2 80 DIN3 77 LRCK 77 BCK 78 • Digital Surround Sound For Home Theatre • DVD • Car Audio. CE2766 PLL XCK Applications Σ∆ Mod. DIGITAL AUDIO INPUT Σ∆ Mod. INTERPOLATION FILTER Σ∆ Mod. Clock Rate Detect'n Control SDA CEI Microelectronics Co. Ltd. 1-19 D/A AR1 D/A AL1 D/A AR2 D/A AL2 D/A AR3 D/A AL3 Interface SCL 15 15 RST VCM June 25, 2005 CE2766 DAC Performance Item PERFORMANCE SPECIFICATIONS Spec. 1 Audio Output Level 1 Vrms 2 Audio Bandwidth 20Hz - 20 KHz +/- 0.1 dB 3 SNR (A-weight) >101 dB 4 THD + NOISE (A-weight, 0 dB input) < -82 dB 5 Dynamic Range 90 dB 6 Channel Separation < -90 dB 7 Nonlinear Distortion < 0.25 dB 8 Channel Gain Error < 0.1 dB All Measurement were taken with only one channel active. 2-19 June 25, 2005 CE2766 XCK REQUIREMENT The CE2766 supports 384 and 256 times sampling clock for 32, 44.1, 48, 96 and 192K audio; 192 or 128 times for the 96 K audio.; and 96 and 64 times for the 192K audio. XCK Requirement Sampling Rate XCK Freq. CREG1[5:4]=[0 0] CREG1[5:4]=[0 1] CREG1[5:4]=[1 0] Normal XCK 2 times XCK 4 times XCK fs 384*fs 256*fs 2*384*fs 2*256*fs 32 K 12.288 MHz 8.192 MHz 44.1 16.934 Mhz 11.29 Mhz. 48 K 18.432 MHz 12.288 Mhz. 96 K 18.432 MHz 12.288 Mhz. 36.864 MHz 24.576 Mhz. 192 K 18.432 Mhz 12.288 Mhz. 36.864 Mhz 24.576 Mhz. 4*384*fs 4*256*fs 73.728 Mhz 49.152 Mhz. Normal XCK is prefered for all sampling rates. 3-19 June 25, 2005 CE2766 PIN ASSIGNMENT DVDD 28 AVDD XCK 2 27 AR1 BCK 3 26 GR1 LRCK 4 25 AL1 DIN1 5 24 AGND DIN2 6 23 AR2 DIN3 7 22 GR2 TST 8 21 AL2 RSTZ 9 20 AGND 10 19 AR3 11 18 GR3 12 17 AL3 SDA 13 16 VCM SCL 14 15 AVDD N/C DGND TSTOUT CE2766 1 PIN DESCRIPTION Pin Name Pin # Type Description DVDD 1 +3.3V XCK 2 I External Master Clock Input. BCK 3 I Audio Serial Data Clock Input. LRCk 4 I Left/Right Channel Clock pin. Please refer to Figure 1, Input data format for its definition DIN1 5 I Channel 1 or TDM Serial Audio Data Input. DIN2 6 I Channel 2 Serial Audio Data Input. DIN3 7 I Channel 3 Serial Audio Data Input. TST 8 I Test pin. This pin should be connected to ground. RSTZ 9 I/O N/C 10 DGND 11 DIGITAL Digital power supply, 3.3 Volt. Active Low Reset Pin. Not used. can connected to ground. GND Digital ground 4-19 June 25, 2005 CE2766 PIN DESCRIPTION (Continued) Pin Name Pin # Type T Description TSTOUT 12 Tri-state output pin, This pin can be connected to ground or leave open SDA 13 I/O SCL 14 I AVDD 28 +3.3V AR1 27 O GR0 26 GND AL1 25 O AGND 24 GND AR2 23 O GR1 22 GND AL2 21 O AGND 20 GND AR3 19 O GR2 18 GND AL3 17 O Analog right channel 3 output VCM 16 I/O Common voltage De-coupling Pin Should be Connected to a 20 uF capacitor in parallel with a 1 uF. AVDD 15 +3.3V Analog circuits power supply.Should be Connected to a a 100 uF. in parallel with a 1 uF. I2C data bus. Open drain output. Externally this pin should tie to a 680 ohm pull up resistor. I2C clock input. Analog Analog circuits power supply.Should be Connected to a 100 uF capacitor in parallel with a 1 uF. Analog right channel 1 output Analog circuits ground Analog left channel 1 output Analog circuits ground Analog right channel 2 output Analog circuits ground Analog left channel 2 output Analog circuits ground Analog right channel 3 output Analog circuits ground 5-19 June 25, 2005 CE2766 DIGITAL AUDIO SERIAL INTERFACE The digital serial interface consists of 3 serial input pins, DIN1, DIN2, DIN3, and one serial clock input pin, BCK, and one left/right indicator input pin, LRCK. The data are 2’s complement MSB first numbers. The CE2766 supports four resolution, which are selected programming the control register CREG0[5:4] via the I2C serial control port. Table 1 describes these four resolution. Table (1): Audio Serial Data Input Resolution, Format CREG0[5:4] DIN[3:1] 0 00 16-bit (default) 1 01 20-bit 2 10 24-bit 3 11 32-bit The DIN3, DIN2 and DIN1 can be either 24-bit or 32-bit per frame as well as left justified, right justified or I2S. The CE2766 counts the number of BCK per frame to determine whether the input is 24 or 32 bits format. Table (2): Audio Serial Data Input Modes Mode CREG0[7:6] DIN[3:1] 0 00 Right Justified 1 01 Left Justified 2 10 I2S (default) 3 11 TDM TDM Input Format The CE2766 support Time Division Multiplexed data input. In this format only one data input pin is required. The six channel data are sent in serial order, channel 1 first, followed by channel 2 and so forth. The number of bits per channel is defined by CREG0[5:4]. 6-19 June 25, 2005 CE2766 Figure 1. Audio Serial Input Data Format 1/fs left Channel right channel LRCK BCK MSB LSB n DIN[1:3] 3 2 MSB LSB n 1 3 2 1 Right Justified Input Format left Channel right channel LRCK BCK MSB MSB LSB DIN[1:3] 3 2 LSB 1 3 2 1 Left Justified Input Format left Channel right channel LRCK BCK MSB LSB DIN[1:3] 3 2 MSB LSB 1 3 2 1 2 I S Input Format LRCK BCK MSB DIN[1] n LSB MSB 3 2 Channel 0 1 LSB n 3 2 1 Channel 1 MSB n LSB 2 1 data = 0 Last Channel TDM Input Format 7-19 June 25, 2005 CE2766 INFINITE ZERO DETECTION The CE2766 has an Infinite Zero Detection circuit which detects zero in the Audio Serial Port that lasts for approximately 0.1 sec. By default, the zero detection circuit is on. Serial Command Port The user can select the chip operation mode by programming the internal control registers through serial I2C port. The Chip Address for the CE2766 is 35H. The protocol for write operation consists of sending 3 byte data to CE2766, following each byte is the acknowledges generated by CE2766. The first byte is the 7-bit Chip Address followed by the read/write bit (read is high, write is low). The second byte is the control register address. The third byte is the control register data. Upon power up, all programmable registers are set to default values. Figure 2 describes the serial command port timing relationship. Figure 2. Serial Command Port Timing I 2 C Bus Control Register Write Example: first byte Start second byte CA0 CA6 R/W ACK A7 third byte A0 ACK D7 D0 SDA 1 1 1 1 SCL Example Set channel 1L volume to 30H: first byte: [CA R/W] = 6AH ( Note: Chip adrress: CA<6:0> = 35H, R/W =0.) second byte: register address: A<7:0> = 02H third byte: data D<7:0> = 30H 8-19 June 25, 2005 ACK Stop CE2766 SERIAL PORT CONTROL REGISTER ASSIGNMENT There are 8 registers dedicated to the CE2766 for chip functional programming, The register addresses assignments are Address (decimal) Register Default Value Register Function 0 CREG0[7:0] 80 Data input format, de-emphasis filter selection 1 CREG1[7:0] 80 Input format and PLL output frequency selection 2 VOLREG0[7:0] 80 Volume control for channel 1, left 3 VOLREG1[7:0] 80 Volume control for channel 1, right 4 VOLREG2[7:0] 80 Volume control for channel 2, left 5 VOLREG3[7:0] 80 Volume control for channel 2, right 6 VOLREG4[7:0] 80 Volume control for channel 3, left 7 VOLREG5[7:0] 80 Volume control for channel 3, right 9-19 June 25, 2005 CE2766 CONTROL REGISTERS DESCRIPTION Control Register 0(ADRS=hex00, default=hex80) CREG0[7:0] ADDR[3:0] Hex 00 Default Value BIT 7 BIT 6 I2S LF 1 0 BIT 5 BIT 4 NBIT[1:0] 0 0 BIT 3 BIT 2 AMUTE DEEMP 0 0 BIT 1 BIT 0 FSMPL[1:0] 0 0 [I2S, LF] Digital Serial Bus Format Select 00: - Normal or Right Justified Format. 01: -Left Justified Format. 10: - I2S Format.(default) 11: - TDM, Multi-channel Time Division Multiplexed Format NBIT[1:0]: - These two bits define the serial audio input resolution for right justified and TDM mode 00: - 16-bit resolution. (default) 01: - 20-bit resolution. 10: - 24-bit resolution. 11: - 32-bit resolution. AMUTE: - Auto-mute detection enable. 0: - Auto-mute enabled. (default) 1: - No auto-mute. DEEMP: - Enable de-emphasis 0: - Normal. (default) 1: - enable de-emphasis. FSMPL: - Interpolation filter selection. These two bits are recognized only when “AUTODET” bit of the CREG1 is set to ‘0’. 00: - 44.1 or 48K sampling.(default) 01: - 44.1 or 48K sampling. 10: - 96K sampling. 11: - 192K sampling. 10-19 June 25, 2005 CE2766 Control Register 1 (ADRS=hex01, default=hex80) CREG1[7:0] ADDR[3:0] Hex 01 Default Value BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 AUTODET FS384 CKDIV4 CKDIV2 CKdet MUTE56 MUTE34 MUTE12 1 0 0 0 0 0 0 0 AUTODET Automatically detects the serial audio input data sampling rate clock frequency. 0: - do not use auto-detect 1: - automatically detects the serial audio input data sampling rate and clock frequency. FS384: 384 fs or 256 fs control for the PLL clock output. This bit is recognized only when “AUTODET” bit is set to ‘0’ otherwise the input format is automatically detected. 0: the PLL takes the reference clock and multiplies it by 2 to generate a 512 bit clock 1: the PLL takes the reference clock and multiplies it by 4/3 to generate a 512 bit clock CKDIV4: Clock divider enable control.This bit is recognized only when “AUTODET” bit is set to ‘0’ otherwise the input format is automatically detected. 0: do not enable input clock divided by 4 1: enable input clock divided by 4 CKDIV2: Clock divider enable control . This bit is recognized only when “AUTODET” bit is set to ‘0’ otherwise the input format is automatically detected. 0: do not enable input clock divided by 2 1: enable input clock divided by 2 CKdet: turn off clock detection. 0: enable clock detection. The chip will be in reset mode when there are no clock. 1: disable clock detection. MUTE56: Mute control for channels 5 and 6 0: do not mute channels 5 and 6 1: simultaneously mute channels 5 and 6 MUTE34: Mute control for channels 3 and 4 0: do not mute channels 3 and 4 1: simultaneously mute channels 3 and 4 MUTE12: Mute control for channels 1 and 2 0: do not mute channels 1 and 2 1: simultaneously mute channels1 and2 11-19 June 25, 2005 CE2766 Volume Registers for channel 1 to channel 3, (ADRS=hex02 - hex07, default=hex80) Volume Registers ADDR[3:0] BIT 7 BIT 6 BIT 5 BIT 4 Hex 02 Channel 1 left volume register, VOLREGL1[7:0] Hex 03 Channel 1 right volume register, VOLREGR1[7:0] Hex 04 Channel 2 left volume register, VOLREGL2[7:0] Hex 05 Channel 2 right volume register, VOLREGR2[7:0] Hex 06 Channel 3 left volume register, VOLREGL3[7:0] Hex 07 Channel 3 right volume register, VOLREGR3[7:0] Default Value 1 0 0 BIT 3 BIT 2 BIT 1 BIT 0 0 0 0 0 0 VOLREG:- Control the volume of the 6 DAC’s Volume is controlled in linear scale, with 80h corresponding to 0 dB and 01h to -42 dB. The following table showes the typical attenuation settings and their repective register values. Attenuation and VOLREG setting example Attenuation (dB) Reg. value Attenuation (dB) Reg. value Attenuation (dB) Reg. value Attenuation (dB) Reg. value 0 128 -8 51 -16 20 -25 7 -1 114 -9 45 -17 18 -27 6 -2 102 -10 40 -18 16 --28 5 -3 91 -11 36 -20 13 -30 4 -4 81 -12 32 -21 11 -33 3 -5 72 -13 29 -22 10 -36 2 -6 64 -14 26 -23 9 -42 1 -7 57 -15 23 -24 8 -α 0 12-19 June 25, 2005 CE2766 APPLICATION CONNECTION EXAMPLE: 6.8 Ohm 180 Ohm 22 uF Over Sample Clock 2 3 4 Digital Audio Interface 5 6 7 1 15 DVDD AVDD AVDD BCK AR1 LRCK AL1 DIN1 AR2 DIN3 AL2 +3.3 Volt AR3 CE2766 680 ohm 13 I 2 C Serial Interface 14 8 Reset AL3 SDA VCM 28 100 uF 27 25 23 21 19 17 16 SCL 22 uF GR1 26 GR2 22 TST 9 GR3 18 RST DGND All Unmarked Capacitors have values of 0.1 uF 100 uF XCK DIN2 Analog 3.3 Volt 11 13-19 AGND 20 24 June 25, 2005 CE2766 SUGGESTED ANALOG RECONSTRUCTION FILTER A second Sallen Key low pass reconstruction filter is recommend to remove the high frequency sigma delta modulator noise. The filter’s component values and characteristic are shown in the following figures. Sallen Key 2nd order LP filter 1000 pF 4.7 uF 2.7 K 10 K + 100 K 680 pF 10 K 10 K All resistors and capicitors are 5% precision. LP F F requenc y Res pons e 5 0 Amplitude (dB) -5 -10 -15 -20 -25 -30 10 3 10 4 10 5 F req (H z .) 14-19 June 25, 2005 CE2766 TIMING DIAGRAM Figure 3. Audio Serial Interface Timing Requirement tbck tbck tbck H L BCK tkd su DIN[1-3] tkd hd tkr su LRCK tkr hd Figure 4. Serial Command Port Write Timing Requirement tSCL tLOW tHIGH SDA, SCL tF tBF tHD,sta tR tHD,dat tSU,dat tSU,sta tSU,stp SDA SCL stop start start 15-19 stop June 25, 2005 CE2766 ABSOLUTE MAXIMUM RATINGS Symbol Characteristics Min Max Units VDD Power Supply Voltage (Measured to GND) Vi Digital Input Applied Voltage2 GND-0.5 Ai Digital Input Forced Current3,4 -100 100 mA Vo Digital Output Applied Voltage2 GND-0.5 VDD+0.5 V Ao Digital Output Forced Current3,4 -100 100 mA TDsc Digital Short Circuit Duration (single output high state to Vss) 1 Sec TASC Analog Short Circuit Duration (single output to VSS1) infinite Sec Ta Ambient Operating Temperature Range -25 +125 o C Tj Junction Temperature (Plastic Package) -65 +150 o C Tsol Lead Soldering Temperature (10 sec., 1/4” from pin) 280 o C Tvsol Vapor Phase Soldering (1 minute) 220 o C Tstor Storage Temperature +150 o C -0.5 -65 +7.0 V V Notes: 1. Absolute maximum ratings are limiting values applied individually, while all other parameters are within specified operating conditions. 2. Applied voltage must be current limited to specified range, and measured with respect to VSS. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current, flowing into the device. 16-19 June 25, 2005 CE2766 ELECTRICAL CHARACTERISTICS Parameter Characteristics Min Typ Max Units Power Supply AVDD Analog power supply voltage 2.8 3.3 5.5 V DVDD Digital power supply voltage 2.8 3.3 5.5 V IDA Analog Current 40 IDD Digital Current 16 18 mA 1 1.02 Vrms mA Audio DAC Characteristics Full Scale Output Voltage to a 10K load VVCM .98 Reference voltage VDD/2 V Digital Characteristics VIH Digital Input Voltage, Logic HIGH, TTL Compatible Inputs. IOZH 2.0 VDD V Hi-Z Leakage Current, HIGH, VDD=Max, VIN=3.3 Volt 33 µA IOZL Hi-Z Leakage Current, LOW, VDD=Max, VIN=VSS) -10 µA CI Digital Input Capacitance (TA=25oC, f=1Mhz) 8 pF CO Digital Output Capacitance (TA=25oC, f=1Mhz) 10 pF Audio Serial Interface Timing tbck BCK Cycle Time 80 ns tbckH BCK Pulse Width, HIGH 30 ns tbckL BCK Pulse Width, LOW 30 ns tkdsu Audio Data Setup Time With Respect To Rising Edge of BCK 10 ns tkdhd Audio Data Hold Time With Respect to Rising Edge of BCK 15 ns tkrsu Audio LRCK Setup Time With Respect To Rising Edge of BCK 10 ns 17-19 June 25, 2005 CE2766 Parameter tkrhd Characteristics Min Audio LRCK Hold Time With Respect To Rising Edge of BCK Typ Max 15 Units ns Serial Command Port fSCL SCL Clock Frequency tSU,sta Start condition set up time 4.7 us tHD,sta Start condition hold time 4.0 us tSU,stp Stop condition set up time 4.0 us tLOW SCL Low time 4.7 us tHIGH SCL High time 4.0 us tR SCL & SDA rise time 1.0 us tF SCL & SDA fall time 0.3 us tSU,DAT Data set-up time tHD,DAT tBF 100 kHz 250 ns Data hold time 0 ns Bus Free time 4.7 us 18-19 June 25, 2005 CE2766 PACKAGING INFORMATION Dimensions mm. min norm A A1 0.05 b 0.22 C 0.09 D 9.90 0.3 10.20 mm. max min norm max 2.13 E1 5.0 5.3 5.6 0.25 E2 7.4 7.8 8.2 0.38 e 0.20 L 0.65 0.63 0.9 1.03 10.50 28-Pin (SSOP) D E1 E2 A1 A b e c L 19-19 June 25, 2005