PCM1770 PCM1771 SLES011B – SEPTEMBER 2001 – JUNE 2002 LOW-VOLTAGE AND LOW-POWER STEREO AUDIO DIGITAL-TO-ANALOG CONVERTER WITH HEADPHONE AMPLIFIER FEATURES D Multilevel DAC Including Headphone D Amplifier Analog Performance (VCC, VHP = 2.4 V): – Dynamic Range: 98 dB Typ – THD+N at 0 dB: 0.1% Typ – THD+N at –20 dB: 0.04% Typ – Output Power at RL = 16 Ω: 13 mW (Stereo), 26 mW (Monaural) D 1.6-V to 3.6-V Single Power Supply D Low Power Dissipation: 6.5 mW at VCC, VHP = 2.4 V D System Clock: 128fS, 192fS, 256fS, 384fS D Sampling Frequency: 5 kHz to 50 kHz D Software Control (PCM1770): – 16-, 20-, 24-Bit Word Available – Left-, Right-Justified and I2S – Slave/Master Selectable D Digital Attenuation: – – – – – – 0 dB to –62 dB, 1 dB/Step 44.1-kHz Digital De-Emphasis Zero Cross Attenuation Digital Soft Mute Monaural Analog-In With Mixing Monaural Speaker Mode D Hardware Control (PCM1771): – Left-Justified and I2S – 44.1-kHz Digital De-Emphasis – Monaural Analog-In With Mixing D Pop-Noise-Free Circuit D 3.3-V Tolerant D Packages: TSSOP-16 and VQFN-20, Lead Free APPLICATIONS D Portable Audio Player D Cellular Phone D PDA D Other Applications Requiring Low-Voltage Operation DESCRIPTION The PCM1770 and PCM1771 devices are CMOS, monolithic, integrated circuits which include stereo digital-to-analog converters, headphone circuitry, and support circuitry in small TSSOP-16 and VQFN-20 packages. The data converters utilize TI’s enhanced multilevel ∆-Σ architecture, which employs noise shaping and multilevel amplitude quantization to achieve excellent dynamic performance and improved tolerance to clock jitter. The PCM1770 and PCM1771 devices accept several industry standard audio data formats with 16- to 24-bit data, left-justified, I2S, etc., providing easy interfacing to audio DSP and decoder devices. Sampling rates up to 50 kHz are supported. A full set of user-programmable functions are accessible through a 3-wire serial control port, which supports register write functions. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2002, Texas Instruments Incorporated PCM1770 PCM1771 www.ti.com SLES011B – SEPTEMBER 2001 – JUNE 2002 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. PACKAGE/ORDERING INFORMATION PRODUCT PACKGE PACKAGE PACKAGE CODE TA PACKAGE MARKING PCM1770PW TSSOP 16 TSSOP–16 16PW –25°C 25°C to 85°C PCM1770 PCM1771PW TSSOP 16 TSSOP–16 16PW –25°C 25°C to 85°C PCM1771 PCM1770RGA PCM1771RGA VQFN 20 VQFN–20 VQFN 20 VQFN–20 20RGA 20RGA –25°C 25°C to 85°C –25°C 25°C to 85°C PCM1770 PCM1771 ORDERING NUMBER TRANSPORT MEDIA PCM1770PW Tube PCM1770PWR Tape and Reel PCM1771PW Tube PCM1771PWR Tape and Reel PCM1770RGA Tray PCM1770RGAR Tape and Reel PCM1771RGA Tray PCM1771RGAR Tape and Reel ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) PCM1770 PCM1771 Supply voltage: VCC, VHP Supply voltage differences: VCC, VHP Ground voltage differences Digital input voltage Input current (any terminals except supplies) 4V ±0.1 V ±0.1 V –0.3 V to 4.0 V ±10 mA Operatingtemperature –40°C to 125°C Storage temperature –55°C to 150°C Junction temperature Lead temperature (soldering) 150°C 260°C, 5 s Package temperature (IR reflow, peak) 260°C, 10 s (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 PCM1770 PCM1771 www.ti.com SLES011B – SEPTEMBER 2001 – JUNE 2002 ELECTRICAL CHARACTERISTICS all specifications at TA = 25°C, VCC = VHP = 2.4 V, fS = 44.1 kHz, system clock = 256 fS and 24-bit data, RL = 16 Ω, unless otherwise noted PARAMETER TEST CONDITIONS MIN Resolution TYP MAX 24 UNIT Bits DATA FORMAT Audio data interface format (PCM1770) Standard, I2S, left justified (PCM1771) I2S, left justified Audio data bit length 16-, 20-, 24-bits selectable Audio data format MSB first, twos complement Sampling frequency (fS) 5 Internal system clock frequency DIGITAL INPUT/OUTPUT(1) Logic family VIH VIL IIH IIL VOH VOL 50 kHz 128fS, 192fS, 256fS, 384fS CMOS compatible 0.7VCC Input logic level Input logic current VIN = VCC VIN = 0 V Output logic level(2) IOH = –2 mA IOL = 2 mA Vdc 0.3VCC 10 –10 0.7VCC Vdc µA µA Vdc 0.3VCC Vdc DYNAMIC PERFORMANCE HEADPHONE OUTPUT Full scale output voltage 0 dB Dynamic range EIAJ, A-weighted 90 Signal-to-noise ratio EIAJ, A-weighted 90 THD+N 0 dB (13 mW) 0.55VHP 98 VP-P dB 98 dB 0.1% –20 dB (0.1 mW) 0.04% 0.1% Stereo 10 13 mWrms Monaural 20 26 mWrms Channel separation 64 72 dB Load resistance 14 16 Ω Output power dc ACCURACY Gain error ±2 ±8 %FSR Gain mismatch, channel-to-channel ±2 ±8 %FSR ±30 ±75 mV Bipolar zero error VOUT = 0.5VCC at BPZ ANALOG LINE INPUT (MIXING CIRCUIT) Analog input voltage range 0.584VHP Gain (analog input to headphone output) 0.67 Analog input impedance THD+N VP-P 10 AIN = 0.56VHP (peak-to-peak) kΩ 0.1% DIGITAL FILTER PERFORMANCE Passband Stopband 0.454fS 0.546fS ±0.04 Passband ripple Stop band attenuation Group delay 44.1-kHz de-emphasis error –50 dB dB 20/fS ±0.1 dB (1) All logic inputs are 3.3-V tolerant and not terminated internally. (2) LRCK and BCK terminals 3 PCM1770 PCM1771 www.ti.com SLES011B – SEPTEMBER 2001 – JUNE 2002 ELECTRICAL CHARACTERISTICS (continued) all specifications at TA = 25°C, VCC = VHP = 2.4 V, fS = 44.1 kHz, system clock = 256 fS and 24-bit data, RL = 16 Ω, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG FILTER PERFORMANCE Frequency response ±0.2 at 20 kHz dB POWER SUPPLY REQUIREMENTS Voltage range, VCC, VHP ICC IHP ICC + IHP 1.6 Supply current 2.4 3.6 BPZ input 1.5 2.5 BPZ input 1.2 2.5 5 15 µA BPZ input 6.5 12 mW Power down(3) 12 36 µW 85 °C Power down(3) Power dissipation Vdc mA TEMPERATURE RANGE Operationtemperature θJA –25 Thermal resistance PCM1770PW, –71PW: 16-terminal TSSOP 150 PCM1770RGA, –71RGA: 20-terminal VQFN 130 °C/W (1) All logic inputs are 3.3-V tolerant and not terminated internally. (2) LRCK and BCK terminals (3) All input signals are held static. PIN ASSIGNMENTS PCM1770 PW PACKAGE (TOP VIEW) SCKI MS MC MD VCC VHP AIN HOUTL LRCK DATA BCK PD AGND HGND VCOM HOUTR 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1 20 19 18 17 16 15 2 14 3 13 4 12 5 7 8 11 9 10 VCOM HOUTR NC HOUTL 6 NC – No internal connection 4 AIN DATA BCK PD AGND HGND SCKI FMT AMIX DEMP VCC VHP AIN HOUTL LRCK NC NC NC SCKI PCM1771 RGA PACKAGE (TOP VIEW) LRCK NC NC NC SCKI PCM1770 RGA PACKAGE (TOP VIEW) MS MC MD VCC VHP DATA BCK PD AGND HGND 1 20 19 18 17 16 15 2 14 AMIX 3 13 DEMP 4 12 VCC VHP 5 6 7 8 11 9 10 AIN 16 15 14 13 12 11 10 9 VCOM HOUT R NC HOUTL 1 2 3 4 5 6 7 8 LRCK DATA BCK PD AGND HGND VCOM HOUTR PCM1771 PW PACKAGE (TOP VIEW) FMT PCM1770 PCM1771 www.ti.com SLES011B – SEPTEMBER 2001 – JUNE 2002 Terminal Functions PCM1770PW TERMINAL NAME NO. I/O DESCRIPTIONS I/O Left and right clock. Determines which channel is being input on the audio data input, DATA. The frequency of LRCK must be the same as the audio sampling rate. In the slave interface mode, this clock is input from an external device. In the master interface mode, the PCM1770 device generates the LRCK output to an external device. LRCK 1 DATA 2 I BCK 3 I/O Serial bit clock. Clocks the individual bits of the audio data input, DATA. In the slave interface mode, this clock is input from external device. In the master interface mode, the PCM1770 device generates the BCK output to external device. PD 4 I Reset input. When low, the PCM1770 device is powered down and all mode control registers are reset to default settings. AGND 5 – Analog ground. This is a return for VCC. HGND 6 – Analog ground. This is a return for VHP. VCOM 7 – Decoupling capacitor connection. An external 10-µF capacitor connected from this terminal to analog ground is required for noise filtering. Voltage level of this terminal is 0.5VHP nominal. HOUTR HOUTL 8 O R-channel analog signal output of the headphone amplifiers 9 O L-channel analog signal output of the headphone amplifiers AIN 10 I Monaural analog signal mixer input. The signal can be mixed with the output of L- and R-channel DACs. VHP VCC 11 – Analog power supply for the headphone amplifier circuits. The voltage level must be the same as VCC. 12 – Analog power supply for all analog circuits except the headphone amplifier. MD 13 I Mode control port serial data input. Controls the operation mode on the PCM1770 device. MC 14 I Mode control port serial bit clock input. Clocks the individual bits of the control data input, MD. MS 15 I Mode control port select. The control port is active when this terminal is low. SCKI 16 I System clock input Serial audio data input PCM1770RGA TERMINAL NAME NO. I/O DESCRIPTIONS DATA 1 I BCK 2 I/O Serial bit clock. Clocks the individual bits of the audio data input, DATA. In the slave interface mode, this clock is input from external device. In the master interface mode, the PCM1770 device generates the BCK output to external device. PD 3 I Reset input. When low, the PCM1770 device is powered down and all mode control registers are reset to default settings. AGND 4 – Analog ground. This is a return for VCC. HGND 5 – Analog ground. This is a return for VHP. VCOM 6 – Decoupling capacitor connection. An external 10-µF capacitor connected from this terminal to analog ground is required for noise filtering. Voltage level of this terminal is 0.5VHP nominal. HOUTR NC HOUTL AIN Serial audio data input 7 O R-channel analog signal output of the headphone amplifiers 8, 17, 18, 19 – No connect 9 O L-channel analog signal output of the headphone amplifiers 10 I Monaural analog signal mixer input. The signal can be mixed with output of L- and R-channel DACs. VHP VCC 11 – Analog power supply for the headphone amplifier circuits. The voltage level must be the same as VCC. 12 – Analog power supply for all analog circuits except the headphone amplifier. MD 13 I Mode control port serial data input. Controls the operation mode on the PCM1770 device. MC 14 I Mode control port serial bit clock input. Clocks the individual bits of the control data input, MD. MS 15 I Mode control port select. The control port is active when this terminal is low. SCKI 16 I System clock input LRCK 20 I/O Left and right clock. Determines which channel is being input on the audio data input, DATA. The frequency of LRCK must be the same as the audio sampling rate. In the slave interface mode, this clock is input from an external device. In the master interface mode, the PCM1770 device generates the LRCK output to an external device.d 5 PCM1770 PCM1771 www.ti.com SLES011B – SEPTEMBER 2001 – JUNE 2002 Terminal Functions PCM1771PW TERMINAL NAME NO. I/O DESCRIPTIONS LRCK 1 I Left and right clock. Determines which channel is being input on the audio data input, DATA. The frequency of LRCK must be the same as the audio sampling rate. DATA 2 I Serial audio data input BCK 3 I Serial bit clock. Clocks the individual bits of the audio data input, DATA. PD 4 I Reset input. When low, the PCM1771 device is powered down and all mode control registers are reset to default settings. AGND 5 – Analog ground. This is a return for VCC. HGND 6 – Analog ground. This is a return for VHP. VCOM 7 – Decoupling capacitor connection. An external 10-µF capacitor connected from this terminal to analog ground is required for noise filtering. Voltage level of this terminal is 0.5VHP nominal. HOUTR HOUTL 8 O R-channel analog signal output of the headphone amplifiers 9 O L-channel analog signal output of the headphone amplifiers AIN 10 – Monaural analog signal mixer input. The signal can be mixed with the output of L- and R-channel DACs. VHP VCC 11 – Analog power supply for the headphone amplifier circuits. The voltage level must be the same as VCC. 12 – Analog power supply for all analog circuits except the headphone amplifier. DEMP 13 I De-emphasis control AMIX 14 I Analog mixing control FMT 15 I Data format select SCKI 16 I System clock input PCM1771RGA TERMINAL NAME NO. I/O DESCRIPTIONS DATA 1 I Serial audio data input BCK 2 I Serial bit clock. Clocks the individual bits of the audio data input, DATA. PD 3 I Reset input. When low, the PCM1771 device is powered down and all mode control registers are reset to default settings. AGND 4 – Analog ground. This is a return for VCC. HGND 5 – Analog ground. This is a return for VHP. VCOM 6 – Decoupling capacitor connection. An external 10-µF capacitor connected from this terminal to analog ground is required for noise filtering. Voltage level of this terminal is 0.5VHP nominal. HOUTR NC HOUTL AIN 7 O R-channel analog signal output of the headphone amplifiers 8, 17, 18, 19 – No connect 9 O L-channel analog signal output of the headphone amplifiers 10 – Monaural analog signal mixer input. The signal can be mixed with the output of L- and R-channel DACs. VHP VCC 11 – Analog power supply for the headphone amplifier circuits. The voltage level must be the same as VCC. 12 – Analog power supply for all analog circuits except the headphone amplifier DEMP 13 I De-emphasis control AMIX 14 I Analog mixing control FMT 15 I Data format select SCKI 16 I System clock input LRCK 20 I Left and right clock. Determines which channel is being input on the audio data input, DATA. The frequency of LRCK must be the same as the audio sampling rate. 6 PCM1770 PCM1771 www.ti.com SLES011B – SEPTEMBER 2001 – JUNE 2002 FUNCTIONAL BLOCK DIAGRAM AIN Digital Attenuator LRCK ×8 Digital Filter Audio Interface DATA Headphone Amplifier ∆Σ DAC HOUTR + BCK VCOM (FMT) MS ×8 Digital Filter SPI Port (AMIX) MC ∆Σ DAC VCOM HOUTL + (DEMP) MD Clock Manager Power Supply SCKI PD ( ) : PCM1771 AGND VCC HGND VHP TYPICAL CHARACTERISTICS DIGITAL FILTER Digital Filter (De-Emphasis Off) AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY 0 0.05 VCC = 2.4 V fS = 44.1 kHz TA = 25°C RL = 16 Ω –20 0.04 0.03 0.02 Amplitude – dB Amplitude – dB –40 VCC = 2.4 V fS = 44.1 kHz TA = 25°C RL = 16 Ω –60 –80 0.01 0.00 –0.01 –0.02 –100 –0.03 –120 –0.04 –140 0 1 2 f – Frequency [ fS] Figure 1 3 4 –0.05 0.0 0.1 0.2 0.3 0.4 0.5 f – Frequency [ fS] Figure 2 Electrical characteristics, all specifications at TA = 25°C, VCC = VHP = 2.4 V, fS = 44.1 kHz, System clock = 256 fS and 24-bit data, RL = 16 Ω, unless otherwise noted. 7 PCM1770 PCM1771 www.ti.com SLES011B – SEPTEMBER 2001 – JUNE 2002 TYPICAL CHARACTERISTICS De-Emphasis Curves DE-EMPHASIS ERROR vs FREQUENCY DE-EMPHASIS LEVEL vs FREQUENCY 0.5 0 VCC = 2.4 V fS = 44.1 kHz TA = 25°C RL = 16 Ω –1 0.3 De-emphasis Error – dB De-emphasis Level – dB –2 –3 –4 –5 –6 –7 0.2 0.1 –0.0 0.0 –0.1 –0.2 –8 –0.3 –9 –0.4 –10 0.0 VCC = 2.4 V fS = 44.1 kHz TA = 25°C RL = 16 Ω 0.4 –0.5 0.1 0.2 0.3 0.4 0.5 0 0.6 2 4 6 10 12 14 16 18 20 f – Frequency – kHz f – Frequency – kHz Figure 3 Figure 4 TOTAL HARMONIC DISTORTION + NOISE vs SUPPLY VOLTAGE DYNAMIC RANGE vs SUPPLY VOLTAGE 1.00 1 104 VCC = 2.4 V fS = 44.1 kHz TA = 25°C RL = 16 Ω 102 Dynamic Range – dB THD+N – Total Harmonic Distortion + Noise – % 8 0 dB 0.10 0.1 –20 dB VCC = 2.4 V fS = 44.1 kHz TA = 25°C RL = 16 Ω 100 98 96 94 0.01 1.2 1.6 2.0 2.4 2.8 3.2 VCC – Supply Voltage – V Figure 5 3.6 4.0 92 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 VCC – Supply Voltage – V Figure 6 Electrical characteristics, all specifications at TA = 25°C, VCC = VHP = 2.4 V, fS = 44.1 kHz, System clock = 256 fS and 24-bit data, RL = 16 Ω, unless otherwise noted. 8 PCM1770 PCM1771 www.ti.com SLES011B – SEPTEMBER 2001 – JUNE 2002 TYPICAL CHARACTERISTICS SNR vs SUPPLY VOLTAGE CHANNEL SEPARATION vs SUPPLY VOLTAGE 104 76 Channel Separation – dB 102 78 VCC = 2.4 V fS = 44.1 kHz TA = 25°C RL = 16 Ω SNR – dB 100 98 96 94 92 1.2 VCC = 2.4 V fS = 44.1 kHz TA = 25°C RL = 16 Ω 74 72 70 68 1.6 2.0 2.4 2.8 3.2 3.6 66 1.2 4.0 1.6 VCC – Supply Voltage – V 2.0 Figure 7 2.8 3.2 3.6 4.0 80 100 Figure 8 TOTAL HARMONIC DISTORTION + NOISE vs FREE-AIR TEMPERATURE DYNAMIC RANGE vs FREE-AIR TEMPERATURE 1.00 1 102 VCC = 2.4 V fS = 44.1 kHz TA = 25°C RL = 16 Ω 101 100 Dynamic Range – dB THD+N – Total Harmonic Distortion + Noise – % 2.4 VCC – Supply Voltage – V 0 dB 0.10 0.1 –20 dB VCC = 2.4 V fS = 44.1 kHz TA = 25°C RL = 16 Ω 99 98 97 96 95 0.01 –40 –20 0 20 40 60 TA – Free-Air Temperature – °C Figure 9 80 100 94 –40 –20 0 20 40 60 TA – Free-Air Temperature – °C Figure 10 Electrical characteristics, all specifications at TA = 25°C, VCC = VHP = 2.4 V, fS = 44.1 kHz, System clock = 256 fS and 24-bit data, RL = 16 Ω, unless otherwise noted. 9 PCM1770 PCM1771 www.ti.com SLES011B – SEPTEMBER 2001 – JUNE 2002 TYPICAL CHARACTERISTICS SNR vs FREE-AIR TEMPERATURE CHANNEL SEPARATION vs FREE-AIR TEMPERATURE 102 100 SNR – dB 99 98 97 96 74 73 72 71 70 95 94 –40 VCC = 2.4 V fS = 44.1 kHz TA = 25°C RL = 16 Ω 75 Channel Separation – dB 101 76 VCC = 2.4 V fS = 44.1 kHz TA = 25°C RL = 16 Ω 69 –20 0 20 40 60 80 68 –40 100 –20 TA – Free-Air Temperature – °C 0 20 40 60 80 100 TA – Free-Air Temperature – °C Figure 11 Figure 12 SUPPLY CURRENT vs SUPPLY VOLTAGE ICC – Supply Current, Operational – mA 4.5 4.0 VCC = 2.4 V fS = 44.1 kHz TA = 25°C RL = 16 Ω 18 16 3.5 14 Operational 3.0 12 2.5 10 2.0 8 1.5 6 Power Down 1.0 4 0.5 2 0.0 1.2 ICC – Supply Current, Power Down – µA 20 5.0 0 1.6 2.0 2.4 2.8 3.2 3.6 4.0 VCC – Supply Current – V Figure 13 Electrical characteristics, all specifications at TA = 25°C, VCC = VHP = 2.4 V, fS = 44.1 kHz, System clock = 256 fS and 24-bit data, RL = 16 Ω, unless otherwise noted. 10 PCM1770 PCM1771 www.ti.com SLES011B – SEPTEMBER 2001 – JUNE 2002 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs SAMPLING FREQUENCY ICC – Supply Current, Operational – mA VCC = 2.4 V fS = 44.1 kHz TA = 25°C RL = 16 Ω 4.5 4.0 18 16 3.5 14 3.0 12 Operational 2.5 10 2.0 8 Power Down 1.5 6 1.0 4 0.5 2 0.0 ICC – Supply Current, Power Down – µA 20 5.0 0 0 10 20 30 40 50 fS – Sampling Frequency – kHz Figure 14 DYNAMIC RANGE vs JITTER 100 VCC = 2.4 V fS = 44.1 kHz TA = 25°C RL = 16 Ω Dynamic Range – dB 99 98 97 96 95 94 0 100 200 300 400 500 600 700 Jitter – ps Figure 15 Electrical characteristics, all specifications at TA = 25°C, VCC = VHP = 2.4 V, fS = 44.1 kHz, System clock = 256 fS and 24-bit data, RL = 16 Ω, unless otherwise noted. 11 PCM1770 PCM1771 www.ti.com SLES011B – SEPTEMBER 2001 – JUNE 2002 TYPICAL CHARACTERISTICS OUTPUT SPECTRUM (–60 dB, N = 8192) OUTPUT SPECTRUM (–60 dB, N = 8192) 0 0 VCC = 2.4 V fS = 44.1 kHz TA = 25°C RL = 16 Ω –20 –20 –40 Amplitude – dB –40 Amplitude – dB VCC = 2.4 V fS = 44.1 kHz TA = 25°C RL = 16 Ω –60 –80 –60 –80 –100 –100 –120 –120 –140 –140 0 5 10 f – Frequency – kHz Figure 16 15 20 0 20 40 60 80 100 120 f – Frequency – kHz Figure 17 Electrical characteristics, all specifications at TA = 25°C, VCC = VHP = 2.4 V, fS = 44.1 kHz, System clock = 256 fS and 24-bit data, RL = 16 Ω, unless otherwise noted. 12 PCM1770 PCM1771 www.ti.com SLES011B – SEPTEMBER 2001 – JUNE 2002 APPLICATION INFORMATION CONNECTION DIAGRAMS POWER SUPPLIES AND GROUNDING Figure 18 shows the basic connection diagram with the necessary power supply bypassing and decoupling components. It is recommended that the component values shown in Figure 18 be used for all designs. The PCM1770 and PCM1771 devices require a 2.4-V typical analog supply for VCC and VHP. These 2.4-V supplies power the DAC, analog output filter, and other circuits. For best performance, these 2.4-V supplies must be derived from the analog supply using a linear regulator, as shown in Figure 18. The use of series resistors (22 Ω to 100 Ω) are recommended for the MCKI, LRCK, BCK, and DATA inputs. The series resistor combines with the stray PCB and device input capacitance to form a low-pass filter that reduces high frequency noise emissions and helps to dampen glitches and ringing present on the clock and data lines. Figure 18 shows the proper power supply bypassing. The 10-µF capacitors must be tantalum or aluminum electrolytic, while the 0.1-µF capacitors are ceramic (X7R type is recommended for surface-mount applications). 1.6 V to 3.6 V Audio DSP Controller 10 µF 1 LRCK SCKI 16 2 DATA MS 15 3 BCK MC 14 4 PD MD 13 VCC 12 PCM1770 5 AGND 6 HGND VHP 11 7 VCOM AIN 10 8 HOUTR HOUTL 10 µF 10 µF Analog In 9 10 µF 220 µF 0.022 µF 16 Ω 220 µF Headphone RL = 16 Ω 0.022 µF 16 Ω Figure 18. Basic Connection Diagram 13 PCM1770 PCM1771 www.ti.com SLES011B – SEPTEMBER 2001 – JUNE 2002 DETAILED DESCRIPTION Figure 19 shows the timing requirements for the system clock input. For optimal performance, it is important to use a clock source with low phase jitter and noise. SYSTEM CLOCK, RESET, AND FUNCTIONS System Clock Input The PCM1770 and PCM1771 devices require a system clock for operating the digital interpolation filters and multilevel ∆-Σ modulators. The system clock is applied at terminal 16 (SCKI). Table 1 shows examples of system clock frequencies for common audio sampling rates. Table 1. System Clock Frequency for Common Audio Sampling Frequencies SAMPLING FREQUENCY, LRCK SYSTEM CLOCK FREQUENCY, SCKI (MHz) 48 kHz 128fS 6.144 192fS 9.216 256fS 12.288 384fS 18.432 44.1 kHz 5.6448 8.4672 11.2896 16.9344 32 kHz 4.096 6.144 8.192 12.288 24 kHz 3.072 4.608 6.144 9.216 22.05 kHz 2.8224 4.2336 5.6448 8.4672 16 kHz 2.048 3.072 4.096 6.144 12 kHz 1.536 2.304 3.072 4.608 11.025 kHz 1.4112 2.1168 2.8224 4.2336 8 kHz 1.024 1.536 2.048 3.072 t(SCKH) 0.7 VCC SCKI 0.3 VCC t(SCKL) System Clock Pulse Cycle Time† † 1/(128fS), 1/(192fS), 1/(256fS), and 1/(384fS) PARAMETERS System clock pulse width high System clock pulse width low Figure 19. System Clock Timing 14 SYMBOL MIN UNIT t(SCKH) t(SCKL) 7 ns 7 ns PCM1770 PCM1771 www.ti.com SLES011B – SEPTEMBER 2001 – JUNE 2002 POWER ON/OFF RESET Setting terminal 4 (PD) to high must be performed once after power on. The internal logic state is kept in reset when PD is low and during the 1024 system clock count after PD is high. Then the power-on sequence is started. In this sequence, terminals 9 (HOUTL) and 8 (HOUTR) increase gradually from ground level and output corresponding VCC, VHP input data after 9334/fS. When power is off, the PD terminal is reset to low first. Then HOUTL and HOUTR gradually decrease to ground level. In order not to generate pop noise when power is switched on or off, the power-on and power-off sequences shown in Figure 20 and Figure 21 are recommended. Any other power-on or power-off sequence may generate pop noise. 0V 1024 Internal System Clocks LRCK, BCK, SCKI PD Internal Reset 9334/fS HOUTL, HOUTR 0V Figure 20. Power-On Sequence VCC, VHP 0V LRCK, BCK, SCKI 9334/fS PD HOUTL, HOUTR 0V Figure 21. Power-Off Sequence 15 PCM1770 PCM1771 www.ti.com SLES011B – SEPTEMBER 2001 – JUNE 2002 POWER-UP/-DOWN SEQUENCE AND RESET The PCM1770 device has two kinds of power-up/-down methods: the PD terminal through hardware control and PWRD (register 4, B0) through software control. The PCM1771 device has only the PD terminal through hardware control for the power-up/-down sequence. The power-up or power-down sequence operates the same as the power-on or power-off sequence. When powering up or down using the PD terminal, all digital circuits are reset. When powering up or down using PWRD, all digital circuits are reset except for maintaining the logic states of the registers. Figure 22 shows the power-up/power-down sequence. 2.4 V VCC, VHP 9334/fS 9334/fS LRCK, BCK, SCKI PD HOUTL, HOUTR 0V Figure 22. Power-Down and Power-Up Sequences AUDIO SERIAL INTERFACE The audio serial interface for the PCM1770 and PCM1771 devices is comprised of a 3-wire synchronous serial port. It includes terminals 1 (LRCK), 2 (DATA), and 3 (BCK). BCK is the serial audio bit clock, and it clocks the serial data present on DATA into the audio interface serial shift register. Serial data is clocked into the PCM1770 and PCM1771 devices on the rising edge of BCK. LRCK is the serial audio left/right word clock. It latches serial data into the serial audio interface internal registers. Both LRCK and BCK of the PCM1770 device support the slave and master modes which are set by FMT (register 3). LRCK and BCK are outputs during the master mode and inputs during the slave mode. In slave mode, BCK and LRCK are synchronous to the audio system clock, SCKI. Ideally, it is recommended that LRCK and BCK be derived from SCKI. LRCK is operated at the sampling frequency, fS. BCK can be operated at 32, 48, and 64 times the sampling frequency. In master mode, BCK and LRCK are derived from the system clock and these terminals are outputs. The BCK and LRCK are synchronous to SCKI. LRCK is operated at the sampling frequency, fS. BCK can be operated at 64 times the sampling frequency. 16 The PCM1770 and PCM1771 devices operate under LRCK synchronized with the system clock. The PCM1770 and PCM1771 devices do not need a specific phase relationship between LRCK and the system clock, but do require the synchronization of LRCK and the system clock. If the relationship between the system clock and LRCK changes more than ±3BCK during one sample period, internal operation of the PCM1770 and PCM1771 devices halt within 1/fS, and the analog output is kept in last data until resynchronization between system clock and LRCK is completed. AUDIO DATA FORMATS AND TIMING The PCM1770 device supports industry-standard audio data formats, including standard, I2S, and left justified. The PCM1771 device supports the I2S and left-justified data formats. Figure 23 shows the data formats. Data formats are selected using the format bits, FMT[2:0] of control register 3 in case of the PCM1770 device, and are selected using the FMT terminal in case of the PCM1771 device. The default data format is 24-bit, left-justified, slave mode. All formats require binary twos complement, MSB-first audio data. Figure 24 shows a detailed timing diagram for the serial audio interface in slave mode. Figure 25 shows a detailed timing diagram for the serial audio interface in master mode. PCM1770 PCM1771 www.ti.com SLES011B – SEPTEMBER 2001 – JUNE 2002 (1) Standard Data Format; L-Channel = High, R-Channel = Low (Slave Mode) 1/fS LRCK R-Channel L-Channel BCK (= 32 fS, 48 fS or 64 fS) 16-Bit Right-Justified, BCK = 32 fS DATA 14 15 16 1 2 3 14 15 16 1 3 14 15 16 MSB LSB MSB 2 LSB 16-Bit Right-Justified, BCK = 48 fS or 64 fS DATA 14 15 16 1 2 3 1 14 15 16 MSB LSB 2 3 14 15 16 MSB LSB 20-Bit Right-Justified DATA 18 19 20 1 2 3 18 19 20 MSB 1 LSB 2 3 18 19 20 MSB LSB 24-Bit Right-Justified DATA 22 23 24 1 2 3 22 23 24 MSB 1 LSB 2 3 22 23 24 MSB LSB (2) I2S Data Format; L-Channel = Low, R-Channel = High (Slave Mode) 1/fS LRCK L-Channel R-Channel BCK (= 32 fS, 48 fS or 64 fS) DATA 1 2 3 N–2 N–1 MSB N 1 LSB 2 3 N–2 N–1 MSB N 1 2 LSB (3) Left-Justified Data Format; L-Channel = High, R-Channel = Low (Slave Mode) 1/fS LRCK L-Channel R-Channel BCK (= 32 fS, 48 fS or 64 fS) DATA 1 2 3 MSB N–2 N–1 N 1 LSB 2 3 N–2 N–1 MSB N 1 2 N 1 2 LSB (4) Left-Justified Data Format; L-Channel = High, R-Channel = Low (Master Mode) (The frequency of BCK is 64fS and SCKI is 256fS only) 1/fS LRCK L-Channel R-Channel BCK (= 64 fS) DATA 1 2 3 MSB N–2 N–1 LSB N 1 2 3 MSB N–2 N–1 LSB Figure 23. Audio Data Input Formats 17 PCM1770 PCM1771 www.ti.com SLES011B – SEPTEMBER 2001 – JUNE 2002 50% of VDD LRCK (Input) t(BCL) t(BCH) t(LB) 50% of VDD BCK (Input) t(BCY) t(BL) 50% of VDD DATA t(DS) t(DH) PARAMETERS BCK pulse cycle time BCK high-level time BCK low-level time BCK rising edge to LRCK edge LRCK edge to BCK rising edge DATA set-up time DATA hold time (1) fS is the sampling frequency. SYMBOL t(BCY) t(BCH) MAX UNIT 32fS/48fS/64fS (1) 35 ns t(BCL) t(BL) 35 ns 10 ns t(LB) t(DS) t(DH) 10 ns 10 ns 10 ns Figure 24. Audio Interface Timing (Slave Mode) 18 MIN PCM1770 PCM1771 www.ti.com SLES011B – SEPTEMBER 2001 – JUNE 2002 t(SCY) 50% of VCC SCKI t(DL) 50% of VCC LRCK (Output) t(BCL) t(BCH) t(DB) t(DB) 50% of VCC BCK (Output) t(BCY) 50% of VCC DATA t(DS) t(DH) PARAMETERS SCKI pulse cycle time LRCK edge from SCKI rising edge BCK edge from SCKI rising edge BCK pulse cycle time SYMBOL BCK low-level time DATA set-up time UNIT 256fS only (1) 0 40 ns t(DB) 0 40 ns t(DS) t(DH) DATA hold time MAX t(SCY) t(DL) t(BCY) t(BCH) t(BCL) BCK high-level time MIN 64fS only (1) 146 ns 146 ns 10 ns 10 ns (1) fS is up to 48 kHz. fS is the sampling frequency. Figure 25. Audio Interface Timing (Master Mode) 19 PCM1770 PCM1771 www.ti.com SLES011B – SEPTEMBER 2001 – JUNE 2002 The software control interface is a 3-wire serial port that operates asynchronously to the serial audio interface. The serial control interface is utilized to program the on-chip mode registers. MD is the serial data input, used to program the mode registers. MC is the serial bit clock, used to shift data into the control port. MS is the mode control port select signal. HARDWARE CONTROL (PCM1771) The digital functions of the PCM1771 device are capable of hardware control. Table 2 shows selectable formats, Table 3 shows de-emphasis control, and Table 4 shows analog mixing control. Table 2. Data Format Select FMT REGISTER WRITE OPERATION (PCM1770) DATA FORMAT Low 16- to 24-bit, left-justified format High 16- to 24-bit, I2S format All write operations for the serial control port use 16-bit data words. Figure 26 shows the control data word format. The most significant bit must be 0. There are seven bits, labeled IDX[6:0], that set the register index (or address) for the write operation. The eight least significant bits, D[7:0], contain the data to be written to the register specified by IDX[6:0]. Table 3. De-Emphasis Control DEMP DE-EMPHASIS FUNCTION Low 44.1-kHz de-emphasis OFF High 44.1-kHz de-emphasis ON Figure 27 shows the functional timing diagram for writing to the serial control port. To write data into the mode register, data is clocked into an internal shift register on the rising edge of the MC clock. Serial data can change on the falling edge of the clock and must be stable on the rising edge of the clock. The MS signal must be low during the write mode and the rising edge of the MS signal must be aligned with the falling edge of the last MC clock pulse in the 16-bit frame. The MC clock can run continuously between transactions while the MS signal is low. Table 4. Analog Mixing Control AMIX ANALOG MIXING Low Analog mixing OFF High Analog mixing ON SOFTWARE CONTROL (PCM1770) The PCM1770 device has many programmable functions that can be controlled in the software control mode. The functions are controlled by programming the internal registers using MS, MC, and MD. LSB MSB 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 D7 D6 D5 Register Index (or Address) D4 D3 D2 Register Data Figure 26. Control Data Word Format for MD (1) Single Write Operation 16-Bits MS MC MD MSB LSB MSB (2) Continuous Write Operation 16-Bits x N Frames MS MC MD MSB LSB MSB LSB MSB N Frames Figure 27. Register Write Operation 20 LSB D1 D0 PCM1770 PCM1771 www.ti.com SLES011B – SEPTEMBER 2001 – JUNE 2002 CONTROL INTERFACE TIMING REQUIREMENTS (PCM1770) Figure 28 shows a detailed timing diagram for the serial control interface. These timing parameters are critical for proper control port operation. t(MHH) MS 50% of VDD t(MLS) t(MCL) t(MCH) t(MLH) MC 50% of VDD t(MCY) LSB MD 50% of VDD t(MDS) t(MDH) SYMBOL PARAMETERS MC pulse cycle time t(MCY) t(MCL) MC low-level time MC high-level time t(MCH) t(MHH) MS high-level time MS falling edge to MC rising edge t(MLS) t(MLH) MS hold time MIN 100(1) TYP MAX UNITS ns 50 ns 50 ns (2) ns 20 ns 20 ns MD hold time t(MDH) 15 MD set-up time t(MDS) 20 (1) When MC runs continuously between transactions, MC pulse cycle time is specified as 3/(128fS), where fS is sampling rate. (2) 3/(128fS) s (min), where fS is sampling rate. ns ns Figure 28. Control Interface Timing MODE CONTROL REGISTERS (PCM1770) User-Programmable Mode Controls The PCM1770 device has a number of user- programmable functions that can be accessed via mode control registers. The registers are programmed using the serial control interface. Table 5 lists the available mode control functions, along with their reset default conditions and associated register index. Register Map Table 6 shows the mode control register map. Each register includes an index (or address) indicated by the IDX[6:0] bits. Table 5. User-Programmable Mode Controls FUNCTION RESET DEFAULT REGISTER NO. BIT(S) Disabled 01 MUTL, MUTR 0 dB 01, 02 ATL[5:0], ATR[5:0] 128fS oversampling Not inverted 03 OVER Polarity control for analog output for R-channel DAC 03 RINV Analog mixing control for analog in, AIN (terminal 14) Disabled 03 AMIX Soft mute control, L/R independently Digital attenuation level setting, 0 dB to –63 dB in 1.0-dB steps, L/R independently Oversampling rate control (128fS, 192fS, 256fS, 384fS) 44.1-kHz de-emphasis control Disabled 03 DEM 24-bit, left-justified format 03 FMT[2:0] Zero cross attenuation Disabled 04 ZCAT Power down control Disabled 04 PWRD Audio data format select 21 PCM1770 PCM1771 www.ti.com SLES011B – SEPTEMBER 2001 – JUNE 2002 Table 6. Mode Control Register Map REGISTER IDX [6:0] (B14–B8) B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Register 01 01h 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 MUTR MUTL ATL5 ATL4 ATL3 ATL2 ATL1 ATL0 Register 02 02h 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV ATR5 ATR4 ATR3 ATR2 ATR1 ATR0 Register 03 03h 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 OVER RSV RINV AMIX DEM FMT2 FMT1 FMT0 Register 04 04h 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV RSV ZCAT RSV RSV RSV PWRD NOTE: RSV: Reserved for test operation. It must be set to 0 during regular operation. Register Definitions Register 01 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 MUTL MUTR ATL5 ATL4 ATL3 ATL2 ATL1 ATL0 IDX[6:0]: 0000 0001b MUTx: Soft Mute Control Where, x = L or R, corresponding to the headphone output HOUTL and HOUTR. Default Value: 0 MUTL, MUTR = 0 MUTL, MUTR = 1 Mute disabled (default) Mute enabled The mute bits, MUTL and MUTR, enable or disable the soft mute function for the corresponding headphone outputs, HOUTL and HOUTR. The soft mute function is incorporated into the digital attenuators. When mute is disabled (MUTx = 0), the attenuator and DAC operate normally. When mute is enabled by setting MUTx = 1, the digital attenuator for the corresponding output are decreased from the current setting to the infinite attenuation, one attenuator step (1.0 dB) at a time. This provides pop-free muting of the headphone output. By setting MUTx = 0, the attenuator is increased one step at a time to the previously programmed attenuation level. ATL[5:0]: Digital Attenuation Level Setting for Headphone Output, HOUTL Default value: 11 1111b Headphone output, HOUTL includes a digital attenuation function. The attenuation level can be set from 0 dB to –62 dB, in 1.0-dB steps. Changes in attenuator levels are made by incrementing or decrementing by one step (1.0 dB) for every 8/fS time internal until the programmed attenuator setting is reached. Alternatively, the attenuation level may be set to infinite attenuation (or mute). Table 7 shows the attenuation levels for various settings: Table 7. Attenuation Level Settings ATL[5:0] 22 ATTENUATION LEVEL SETTING 11 1111b 11 1110b 0 dB, no attenuation (default) –1.0 dB 11 1101b : –2.0 dB : 00 0010b 00 0001b –61.0 dB –62.0 dB 00 0000b Mute PCM1770 PCM1771 www.ti.com SLES011B – SEPTEMBER 2001 – JUNE 2002 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV Register 02 IDX[6:0]: B5 B4 B3 ATR5 ATR4 ATR3 B2 B1 ATR2 ATR1 B0 ATR0 0000 0010b ATR[5:0]: Digital Attenuation Level Setting for Headphone Output, HOUTR Default Value: 11 1111b Headphone output, HOUTR includes a digital attenuation function. The attenuation level can be set from 0 dB to –62 dB, in 1.0-dB steps. Changes in attenuator levels are made by incrementing or decrementing by one step (1.0 dB) for every 8/fS time internal until the programmed attenuator setting in reached. Alternatively, the attenuation level can be set to infinite attenuation (or mute). To set the attenuation levels for ATR[5:0], refer to the table above in ATL[5:0]. B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV RINV AMIX DEM FMT2 FMT1 FMT0 Register 03 IDX[6:0]: 0000 0011b OVER: Over Sampling Control Default Value: 0 OVER = 0 OVER = 1 128fS oversampling 192fS, 256fS, 384fS oversampling The OVER bit controls the oversampling rate of the ∆-Σ D/A converters. When it operates at a low sampling rate, less than 24 kHz, this function is recommended. RINV: Polarity Control for Headphone Output, HOUTR Default Value: 0 RINV = 0 RINV = 1 Not iinverted Inverted output The RINV bits allow the user to control the polarity of the headphone output, HOUTR. This function can be used to connect the monaural speaker with BTL connection method. This bit is recommended to be 0 during the power-up/-down sequence for minimizing audible pop noise. AMIX: Analog Mixing Control for External Analog Signal, AIN Default Value: 0 AMIX = 0 AMIX = 1 Disabled (not mixed) Enabled (mixing to the DAC output) AMIX bit allows the user to mix analog input (AIN) with headphone outputs (HOUTL/HOUTR) internally. DEM: 44.1-kHz De-emphasis Control Default Value: 0 DEM = 0 DEM = 1 Disabled Enabled The DEM bit enables or disables the digital de-emphasis filter for 44.1-kHz sampling rate. 23 PCM1770 PCM1771 www.ti.com SLES011B – SEPTEMBER 2001 – JUNE 2002 FMT[2:0]: Audio Interface Data Format Default Value: 000 The FMT[2:0] bits select the data format for the serial audio interface. Table 8 shows the available format options. Table 8. Audio Data Format Selection FMT[2:0] Audio Data Format Selection 000 001 010 011 100 101 110 111 16- to 24-bit, left-justified format (default) 16- to 24-bit, I2S format 24-bit right-justified data 20-bit right-justified data 16-bit right-justified data 16- to 24-bit, left-justified format, master mode Reserved Reserved Register 04 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV RSV ZCAT RSV RSV RSV PWRD IDX[6:0]: 0000 0100b ZCAT: Zero Cross Attenuation Default Value: 0 ZCAT = 0 ZCAT = 1 Normal attenuation (default) Zero cross attenuation This bit enables the change signal level on zero crossing during attenuation control or muting. If the signal does not cross BPZ beyond 512/fS (11.6 ms at 44.1-kHz sampling rate), the signal level is changed similar to normal attenuation control. This function is independently monitored for each channel; moreover, change of signal level is alternated between both channels. Figure 29 shows an example of zero cross attenuation. ATT CTRL START L-Channel (2 kHz) R-Channel (1 kHz) Level change point Figure 29. Example of Zero Cross Attenuation PWRD: Power Down Control Default Value: 0 PWRD = 0 PWRD = 1 Normal operation (default) Power-down state This bit is used to enter into low-power mode. Note that PWRD has no reset function. When this bit is set to 1, the PCM1770 device enters low-power mode and all digital circuits are reset except the register states which remain unchanged. 24 PCM1770 PCM1771 www.ti.com SLES011B – SEPTEMBER 2001 – JUNE 2002 ANALOG IN/OUT HEADPHONE OUTPUT (STEREO) The PCM1770 and PCM1771 devices have two independent headphone amplifiers and each amplifier output is provided at the HOUTL and HOUTR terminals. Since the capability of the headphone output is designed for driving a 16-Ω impedance headphone, less than a 16-Ω impedance headphone is not recommended. A resistor and a capacitor must be connected to HOUTL and HOUTR to ensure proper output loading. Monaural Output (BTL Mode/Monaural Speaker) The monaural output can be created by summing left and right headphone outputs. When in the BTL mode, the user must set each headphone output levels to –3 dB using ATL[5:0] bits on register 01 and ATR[5:0] bits on register 02. Moreover, invert the polarity of the right headphone output by using the RINV bit on control register 03. The RINV bit is recommended to be 0 during power-up/-down sequence for minimizing audible pop noise. Analog Input The PCM1770 and PCM1771 devices have an analog input, AIN (terminal 10). The AMIX bit (PCM1770) or the AMIX terminal (PCM1771) allows the user to mix AIN with the headphone outputs (HOUTL and HOUTR) internally. When in the MIXING mode, an ac-coupling capacitor is needed for AIN. But if AIN is not used, AIN must be open and the AMIX bit (PCM1770) must be disabled or the AMIX terminal (PCM1771) must be low. Since AIN does not have an internal low pass filter, it is recommended that the bandwidth of the input signal into AIN is limited to less than 100 kHz. The source of signals connected to AIN must be connected by low impedance. Although the maximum input voltage on AIN is designed to be as large as 0.584VHP [peak-to-peak], the user must attenuate the input voltage on AIN and control digital input data so that each headphone output (HOUTL and HOUTR) does not exceed 0.55VHP [peak-to-peak] during mixing mode. VCOM Output One unbuffered common-mode voltage output terminal, VCOM is brought out for decoupling purposes. This terminal is nominally biased to a dc voltage level equal to 0.5VHP and connected to a 10-µF capacitor. In the case of a capacitor smaller than 10 µF, pop noise can be generated during the power-on/-off or power-up/-down sequences. 25 PCM1770 PCM1771 www.ti.com SLES011B – SEPTEMBER 2001 – JUNE 2002 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°–ā8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES:A. B. C. D. 26 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 PCM1770 PCM1771 www.ti.com SLES011B – SEPTEMBER 2001 – JUNE 2002 RGA (S-PQFP-N20) PLASTIC QUAD FLATPACK 4,05 3,95 4,30 4,10 0,50 NOM/2 A “A” 4,30 4,10 B DETAIL “A” 4,05 3,95 0,50 NOM 20 1,00 NOM C0,70 Index “C” 0,25 0,09 S 1,00 0,95 MAX 0,50 1 0,50 NOM 1,00 NOM 0,75 0,45 0,05 0,00 S 0,05 S DETAIL “B” “B” 0,05 M S AB 0,27 0,17 0,21 0,09 0,05 0,00 0,35 ± 0,11 0,23 0,17 0,69 ± 0,11 0,25 0,09 0,27 0,17 DETAIL “C” 0,22 ± 0,05 4202802/B 08/01 NOTES:A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. These dimensions include package bend. Falls within EIAJ: EDR-7324. 27 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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