PRELIMINARY CM3202 DDR VDDQ and Termination Voltage Regulator Features Product Description • The CM3202 is a dual-output low noise linear regulator designed to meet SSTL-2 and SSTL-3 specifications for DDR-SDRAM VDDQ supply and termination voltage VTT supply. With integrated power MOSFET’s, the CM3202 can source up to 2A of VDDQ continuous cur rent, and source or sink up to 2A VTT continuous cur rent. The typical dropout voltage for VDDQ is 500 mV at 2A load current. • • • • • • • • • • • • • Two linear regulators -Maximum 2A current from VDDQ -Source and sink up to 2A VTT current 1.7V to 2.8V adjustable VDDQ output voltage 500mV typical VDDQ dropout voltage at 2A VTT tracking at 50% of VDDQ Excellent load and line regulation, low noise Fast transient response Meet JEDEC DDR-I and DDR-II memory power spec. Linear regulator design requires no inductors and has low external component count Integrated power MOSFETs Dual purpose ADJ/Shutdown pin Built-in over-current limit with short-circuit foldback and thermal shutdown for VDDQ and VTT Fast transient response 5mA quiescent current TDFN-8, RoHS Compliant Lead-free package The CM3202 provides fast response to transient load changes. Load regulation is excellent, from no load to full load. It also has built-in over-current limits and ther mal shutdown at 170°C. The CM3202 is packaged in an easy-to-use TDFN-8. Low thermal resistance allows it to withstand high power dissipation at 85°C ambient. It can operate over the industrial ambient temperature range of –40°C to 85°C. Applications • • • • • • • DDR memory and active termination buses Desktop Computers, Servers Residential and Enterprise Gateways DSL Modems, Routers and Switchers DVD recorders 3D AGP cards LCD TV and STB Typical Application VIN = 3.3V to 3.6V VDDQ = 2.5V/2A CIN 220u/ 10V 1 2 VTT = 1.25V/2A 220uF/ 10V CTT 3 4.7uF/ 10V cer 4.7uF/10V cer CDDQ 220u/ 10V VIN VDDQ NC ADJSD CM3202 VTT 4 NC GND GND 4.7uF/10V, cer C hip S et 8 DL0 RT0 R1 10k 7 DLn 6 5 S/D VDDQ VDDQ RTn R2 10k DDR REF Memory 1. 25V , 2.5A VTT 1k 1u/10V cer VREF © 2006 California Micro Devices Corp. All rights reserved. 07/06/06 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 l Tel: 408.263.3214 l Fax: 408.263.7846 l www.cmd.com 1 PRELIMINARY CM3202 Package Pinout PACKAGE / PINOUT DIAGRAM TOP VIEW Bottom VIEW (Pins Down View) (Pins Up View) Pin 1 Marking 1 NC 2 VTT 3 NC 4 CM320 200DE VIN 8 VDDQ 8 7 ADJSD 7 6 GND 6 5 GND 5 1 GND PAD 2 3 4 CM3202-00DE 8-Lead TDFN Package (3mmx3mm) Note: This drawing is not to scale. PIN DESCRIPTIONS LEAD(s) NAME 1 VIN DESCRIPTION Input supply voltage pin. Bypass with a 220μF capacitor to GND. 2 NC Not internally connected. For better heat flow, connect to GND (exposed pad). 3 VTT VTT regulator output pin, which is preset to 50% of VDDQ. 4 NC Not internally connected. For better heat flow, connect to GND (exposed pad). 5 GND Ground pin (analog). 6 GND Ground pin (power). This pin is for VDDQ output voltage adjustment. The VDDQ output voltage is set using an external resistor divider connected to ADJSD: 7 ADJSD R1 + R2 V DDQ = 1.25V × --------------------R2 where R1 is the upper resistor and R2 is the ground-side resistor. In addition, the ADJSD pin functions as a Shutdown pin. When ADJSD voltage is higher than 2.7V, the circuit is in Shutdown mode. Bellow 1.5V, both VDDQ and VTT outputs are restored. A low-leakage Schottky diode in series with ADJSD pin is recommended to avoid interference with the voltage adjustment setting. 8 VDDQ EPad GND VDDQ regulator output voltage pin. The backside exposed pad which serves as the package heatsink. Connect to GND. Ordering Information PART NUMBERING INFORMATION Lead-free Finish Pins Package Ordering Part Number1 Part Marking 8 TDFN CM3202-00DE CM320 200DE Note 1: Parts are shipped in Tape & Reel form unless otherwise specified. © 2006 California Micro Devices Corp. All rights reserved. 2 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 l Tel: 408.263.3214 l Fax: 408.263.7846 l www.cmd.com 07/06/06 PRELIMINARY CM3202 Specifications ABSOLUTE MAXIMUM RATINGS RATING UNITS VIN to GND PARAMETER [GND - 0.3] to +6.0 V Pin Voltages VDDQ, VTT to GND ADJSD to GND [GND - 0.3] to +6.0 [GND - 0.3] to +6.0 V V 2.0 / ±2.0 2.8 / ±2.8 3 A A A -40 to +85 -40 to + 170 -40 to +150 °C °C °C 55 °C/W 2.6 / 1.5 W ESD Protection (HBM) 2000 V Lead Temperature (Soldering, 10sec) 300 °C Output Current VDDQ / VTT, continuous (Note 1) VDDQ / VTT, peak VDDQ Source + VTT Source Temperature Operating Ambient Operating Junction Storage Thermal Resistance, RJA (Note 2) Continuous Power Dissipation (Note 2) TA = 25°C / 85°C Note 2: Despite the fact that the device is designed to handle large continuous/peak output currents it is not capable of handling these under all conditions. Limited by the package thermal resistance, the maximum output current of the device can’t exceeds the limit imposed by the maximum power dissipation value. Note 3: Measured with the package using a 4 sq. inch / 2 layers PCB with thermal vias. STANDARD OPERATING CONDITIONS PARAMETER RATING UNITS Ambient Operating Temperature Range -40 to +85 °C VDDQ Regulator DDR-1 Supply Voltage, VIN Load Current, Continuous Load Current, Peak (1 s) CDDQ 3.1 to 3.6 0 to 2.0 2.5 220 V A A μF VTT Regulator DDR-1 Supply Voltage, VIN Load Current, Continuous Load Current, Peak (1 s) CTT 3.1 to 3.6 0 to 2.0 2.5 220 V A A μF VDDQ Source + VTT Source Load Current, Continuous Load Current, Peak (1 s) 2.5 3.5 A A -40 to +150 °C Junction Operating Temperature Range © 2006 California Micro Devices Corp. All rights reserved. 07/06/06 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 l Tel: 408.263.3214 l Fax: 408.263.7846 l www.cmd.com 3 PRELIMINARY CM3202 Specifications (cont’d) ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1) SYMBOL General VIN PARAMETER CONDITIONS Supply Voltage Range MIN TYP MAX UNITS 3.10 3.30 3.60 V 8 15 mA 0.1 0.5 mA 1.50 2.90 V V V °C IQ Quiescent Current IDDQ = 0, ITT = 0 ISHDN Shutdown Current VADJSD = 3.3V (shutdown) SHDN_H SHDN_L UVLO TOVER Shutdown Logic High Shutdown Logic Low Undervoltage Lockout Thermal SHDN Threshold (Note 2) THYS Thermal SHDN Hysteresis 50 °C VDDQ, VTT TEMPCO 150 ppm/°C TEMPCO 2.7 Hysteresis = 100mV (Note 3) (Note 3) VDDQ Regulator VDDQ Output Voltage VDDQ DEF IDDQ = 100mA 2.40 150 2.70 170 2.450 2.500 2.550 V VDDQ LOAD VDDQ Load Regulation 10mA ≤ IDDQ ≤ 2A (Note 4) 10 25 mV VDDQ LINE VDDQ Line Regulation 3.1V ≤ VIN ≤ 3.6V, IDDQ= 0.1A 5 25 mV VDROP VDDQ Dropout Voltage IDDQ = 2A (Note 5) 500 IADJ ADJSD Bias Current (Note 3) 0.8 IDDQ LIM VDDQ Current Limit VTT Regulator VTT DEF VTT LOAD VTT LINE ITT LIM VTT Output Voltage ITT = 100mA VTT Load Regulation Source, 0 ≤ ITT ≤ 2A (Note 4) Sink, -2A ≤ ITT ≤ 0 (Note 4) VTT Line Regulation 3.1V ≤ VIN ≤ 3.6V, ITT = 0.1A ITT Current Limit Source / Sink (Note 4) mV 3 μA 2.0 2.5 A 1.225 1.250 1.275 V 10 -10 30 -30 mV mV 5 15 mV ±2.0 ±2.5 A Note 1: VIN = 3.3V, VDDQ = 2.50V, VTT = 1.25V (default values), CDDQ=CTT=47μF, TA = 25°C unless otherwise specified. Note 2: The SHDN Logic High value is normally satisfied for full input voltage range by using a low leakage current (bellow 1μA). Schottky diode at ADJSD control pin. Note 3: Guaranteed by design. Note 4: Load and line regulation are measured at constant junction temperature by using pulse testing with a low duty cycle. Changes in output voltage due to heating effects must be taken into account separately. Load and line regulation values are guaranteed up to the maximum power dissipation. Note 5: Dropout voltage is input to output floorage differential at which output voltage has dropped 100mV from the nominal value obtained at 3.3V input. It depends on load current and junction temperature. Guaranteed by design. © 2006 California Micro Devices Corp. All rights reserved. 4 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 l Tel: 408.263.3214 l Fax: 408.263.7846 l www.cmd.com 07/06/06 PRELIMINARY CM3202 Typical Operating Characteristics VDDQ vs. Temperature VTT vs. VDDQ 2.510 1.65 1.55 VDDQ (V) VTT (V) 1.45 1.35 1.25 1.15 1.05 2.505 2.500 2.495 0.95 0.85 2.490 0.75 1.5 1.75 2 2.25 2.5 2.75 3 -40 -20 3.25 0 40 60 80 100 120 140 Temperature VDDQ (V) VDDQ vs. Load Current o C VDDQ Dropout vs. IDDQ Dropout Voltage (mV) VDDQ (V) 20 Ta=25 oC Vin=3.3V Ta=25 oC IDDQ (A) IDDQ (A) Startup into Full Load Vin UVLO VDDQ VTT 1ms/div 1V/div © 2006 California Micro Devices Corp. All rights reserved. 07/06/06 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 l Tel: 408.263.3214 l Fax: 408.263.7846 l www.cmd.com 5 PRELIMINARY CM3202 Typical Operating Characteristics (cont’d) VDDQ Transient Response VTT Transient Response IOUT IOUT VDDQ VTT VIN = 3.3V IOUT Step: 15mA ~ 1.5A VIN = 3.3V IOUT Step: 750mA ~ +750mA Functional Block Diagram 9,1 89/2 %DQGJDS 9''4 $'-6' 1.22V &XUUHQW /LPLW 273 6KXWGRZQ &XUUHQW /LPLW 9''4 977 9''4 &XUUHQW /LPLW *1' CM3202 © 2006 California Micro Devices Corp. All rights reserved. 6 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 l Tel: 408.263.3214 l Fax: 408.263.7846 l www.cmd.com 07/06/06 PRELIMINARY CM3202 Application Information Powering DDR Memory Double-Data-Rate (DDR) memory has provided a huge step in performance for personal computers, servers and graphic systems. As is apparent in its name, DDR operates at double the data rate of earlier RAM, with two memory accesses per cycle versus one. DDR SDRAM's transmit data at both the rising falling edges of the memory bus clock. DDR’s use of Stub Series Terminated Logic (SSTL) topology improves noise immunity and power-supply rejection, while reducing power dissipation. To achieve this performance improvement, DDR requires more complex power management architecture than previ ous RAM technology. Unlike the conventional DRAM technology, DDR SDRAM uses differential inputs and a reference volt age for all interface signals. This increases the data bus bandwidth, and lowers the system power con sumption. Power consumption is reduced by lower operating voltage, a lower signal voltage swing associ ated with Stub Series Terminated Logic (SSTL_2) and by the use of a termination voltage, VTT. SSTL_2 is an industry standard, defined in JEDEC document JESD8-9. SSTL_2 maintains high-speed data bus sig nal integrity by reducing transmission reflections. JEDEC further defines the DDR SDRAM specification in JESD79C. DDR memory requires three tightly regulated voltages: VDDQ, VTT, and VREF (see Figure 1). In a typical SSTL_2 receiver, the higher current VDDQ supply volt age is normally 2.5V with a tolerance of ±200-mV. The active bus termination voltage, VTT, is half of VDDQ. VREF is a reference voltage that tracks half of VDDQ, ± 1%, and is compared with the VTT terminated signal at the receiver. VTT must be within ±40-mV of VREF. VTT (=VDDQ/2) VDDQ VDDQ Rt = 25 Rs = 25 Line Transmitter Receiver VREF (=VDDQ/2) Figure 1. Typical DDR terminations, Class II The VTT power requirement is proportional to the num ber of data lines and the resistance of the termination resistor, but does not vary with memory size. In a typi cal DDR data bus system each data line termination may momentarily consume 16.2-mA to achieve the 405-mV minimum over VTT needed at the receiver: 405mV - = 16.2mA I terminaton = --------------------Rt ( 25Ω) A typical 64 Mbyte SSTL-2 memory system, with 128 terminated lines, has a worst-case maximum VTT sup ply current up to ± 2.07A. However, a DDR memory system is dynamic, and the theoretical peak currents only occur for short durations, if they ever occur at all. These high current peaks can be handled by the VTT external capacitor. In a real memory system, the con tinuous average VTT current level in normal operation is less than ± 200 mA. The VDDQ power supply, in addition to supplying cur rent to the memory banks, could also supply current to controllers and other circuitry. The current level typi cally stays within a range of 0.5A to 1A, with peaks up to 2A or more, depending on memory size and the computing operations being performed. The tight tracking requirements and the need for VTT to sink, as well as source, current provide unique chal lenges for powering DDR SDRAM. CM3202 Regulator The CM3202 dual output linear regulator provides all of the power requirements of DDR memory by combining two linear regulators into a single TDFN-8 package. VDDQ regulator can supply up to 2A current, and the two-quadrant VTT termination regulator has current sink and source capability to ±2A. The VDDQ linear regulator uses a PMOS pass element for a very low dropout voltage, typically 500mV at a 2A output. The output voltage of VDDQ can be set by an external volt age divider. The second output, VTT, is regulated at VDDQ/2 by an internal resistor divider. The VTT regula tor can source, as well as sink, up to 2A current. The CM3202 is designed for optimal operation from a nom inal 3.3VDC bus, but can work with VIN as high as 5V. When operating at higher VIN voltages, attention must © 2006 California Micro Devices Corp. All rights reserved. 07/06/06 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 l Tel: 408.263.3214 l Fax: 408.263.7846 l www.cmd.com 7 PRELIMINARY CM3202 Application Information (cont’d) be given to the increased package power dissipation and proportionally increased heat generation. VREF is typically routed to inputs with high impedance, such as a comparator, with little current draw. An ade quate VREF can be created with a simple voltage divider of precision, matched resistors from VDDQ to ground. A small ceramic bypass capacitor can also be added for improved noise performance. Input and Output Capacitors The CM3202 requires that at least a 220μF electrolytic capacitor be located near the VIN pin for stability and to maintain the input bus voltage during load transients. An additional 4.7μF ceramic capacitor between the VIN and the GND, located as close as possible to those pins, is recommended to ensure stability. A minimum of a 220μF electrolytic capacitor is recom mended for the VDDQ output. An additional 4.7μF ceramic capacitor between the VDDQ and GND, located very close to those pins, is recommended. A minimum of a 220μF, electrolytic capacitor is recom mended for the VTT output. This capacitor should have low ESR to achieve best output transient response. SP or OSCON capacitors provide low ESR at high fre quency, and thus are a good choice. In addition, place a 4.7μF ceramic capacitor between the VTT pin and GND, located very close to those pins. The total ESR must be low enough to keep the transient within the VTT window of 40mV during the transition for source to sink. An average current step of ± 0.5A requires: where VADJ = 1.25V. For best regulator stability, we recommend that R1 and R2 not exceed 10kΩ each. Shutdown ADJSD also serves as a shutdown pin. When this is pulled high, > SHDN_H, both VDDQ and VTT outputs tri-states and could sink/source less than 10μA. During shutdown, the quiescent current is reduced to less than 0.5mA, independent of output load. It is recommended that a low leakage Schottky diode be placed between ADJSD Pin and an external shut down signal to prevent interference with the ADJ pin’s normal operation. When the diode anode is pulled low, or left open, the CM3202 is again enabled. Current Limit, Foldback and Over-temperature Pro tection The CM3202 features internal current limiting with ther mal protection. During normal operation, VDDQ limits the output current to approximately 2.8A and VTT limits the output current to approximately ±2.8A. While cur rent limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipa tion ratings of the package. If the junction temperature of the device exceeds 170°C (typical), the thermal pro tection circuitry tri-states both VDDQ and VTT outputs. Once the junction temperature has cooled to below about 120°C, the CM3202 returns to normal operation. Thermal Considerations Typical Thermal Characteristics 40mV ESR < --------------- = 40mΩ 1A Both outputs will remain stable and in regulation even during light or no load conditions. Adjusting VDDQ Output Voltage The CM3202 internal bandgap reference is set at 1.25V. The VDDQ voltage is adjustable by using a resis tor divider, R1 and R2: The overall junction to ambient thermal resistance (θJA) for device power dissipation (PD) primarily con sists of two paths in the series. The first path is the junction to the case (θJC) which is defined by the pack age style and the second path is case to ambient (θCA) thermal resistance which is dependent on board layout. The final operating junction temperature for any condi tion can be estimated by the following thermal equa tion: R1 + R2 V DDQ = V ADJ × -------------------R2 © 2006 California Micro Devices Corp. All rights reserved. 8 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 l Tel: 408.263.3214 l Fax: 408.263.7846 l www.cmd.com 07/06/06 PRELIMINARY CM3202 Application Info (cont’d) T JUNC = T AMB + P D × (θ JC ) + P D × (θ CA ) = T AMB + P D × (θ CA ) When a CM3202 is mounted on a double-sided printed circuit board with four square inches of copper allo cated for “heat spreading,” the θJA is approximately 55°C/W. Based on the over temperature limit of 170°C with an ambient of 85°C, the available power of the package will be: 170°C – 85 °C- = 1.5W P D = ---------------------------------55°C ⁄ W PCB Layout Considerations TheCM3202 has a heat spreader attached to the bot tom of the TDFN-8 package in order for the heat to be transferred more easily from the package to the PCB. The heat spreader is a copper pad of dimensions just smaller than the package itself. By positioning the matching pad on the PCB top layer to connect to the spreader during the manufacturing, the heat will be transferred between the two pads. See the Figure 2, the CM3202 shows the recommended PCB layout. Please be noted that there are four vias on either side to allow the heat to dissipate into the ground and power planes on the inner layers of the PCB. Vias can be placed underneath the chip, but this can be resulted in blocking of the solder. The ground and power planes need to be at least 2 square inches of copper by the vias. It also helps dissipation if the chip is positioned away from the edge of the PCB, and not near other heat-dissipating devices. A good thermal link from the PCB pad to the rest of the PCB will assure the best heat transfer from the CM3202 to ambient, θJA, of approximately 55°C/W. Top View Bottom Layer Ground Plane Top Layer Copper Connects to Heat Spreader Pin Solder Mask Thermal PAD Solder Mask Vias (0.3mm Diameter) Note: This drawing is not to scale Figure 2. Thermal Layout © 2006 California Micro Devices Corp. All rights reserved. 07/06/06 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 l Tel: 408.263.3214 l Fax: 408.263.7846 l www.cmd.com 9 PRELIMINARY CM3202 Mechanical Details TDFN-08 Mechanical Specifications Mechanical Package Diagrams The CM3202-00DE is supplied in an 8-lead, 0.65mm pitch TDFN package. Dimensions are presented below. For complete information on the TQFN16, see the Cal ifornia Micro Devices TQFN Package Information doc ument. D 8 7 6 5 PACKAGE DIMENSIONS TDFN JEDEC No. MO-229 (Var. WEEC-1)+ Leads 8 Dim. Millimeters E Package Pin 1 Marking Inches Min Nom Max Min Nom Max A 0.70 0.75 0.80 0.028 0.030 0.031 A1 0.00 0.02 0.05 0.000 0.001 0.002 A2 0.45 0.55 0.65 0.018 0.022 0.026 A3 b 0.20 0.25 0.30 0.35 0.010 0.012 3.00 0.118 D1 1.95 REF 0.077 D2 2.10 E E2 2.20 0.084 0.092 1.60 0.056 0.060 3.00 1.40 e 1.50 0.20 L 0.20 4 TOP VIEW 0.014 0.08 C A1 A SIDE VIEW 0.088 0.064 A3 A2 D1 0.026 5 0.008 0.30 3 0.118 0.65 K 0.40 0.008 0.012 6 7 8 0.016 3000 pieces D2 GND PAD E2 # per tape and reel 2.30 2 0.10 C 0.008 D 1 C0.35 Controlling dimension: millimeters L +This package is compliant with JEDEC standard MO-229, variation VEEC-1 with exception of the "D2", "E2" and "b" dimensions as called out in the table above. 4 K 3 2 1 b e 8X BOTTOM VIEW 0.10 M CAB Dimensions for 8-Lead TDFN (3x3) Package © 2006 California Micro Devices Corp. All rights reserved. 10 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 l Tel: 408.263.3214 l Fax: 408.263.7846 l www.cmd.com 07/06/06