DDR VDDQ and VTT Termination Voltage Regulator TJ3212 FEATURES z Two linear regulators - Maximum 2A current from VDDQ - Source and sink up to 2A VTT current z 1.7V to 2.8V adjustable VDDQ output voltage z 0.85V to 1.4V VTT output voltage (tracking at 50% of VDDQ) z Buffered VREF output z 500mV typical VDDQ dropout voltage at 2A z Excellent load and line regulation, low noise z Meets JEDEC DDR-I and DDR-II memory power spec z Linear regulator design requires no inductors and has low external component count z Integrated power MOSFETs z Dual purpose ADJ/Shutdown pin z Enable VTT pin for sleep or suspend to RAM function z Built-in over-current limit and thermal shutdown for VDDQ and VTT z Fast transient response z Low quiescent current TDFN-8 PKG SOP-8 PKG SOP-16 PKG ORDERING INFORMATION APPLICATION z z z z z z z DDR memory and active termination buses Desktop computers, servers Residential and enterprise gateways DSL modems Routers and switches DVD recorders, LCD TV and STB 3D AGP cards Device Package TJ3212Q TDFN-8 TJ3212DP SOP-8 TJ3212D SOP-16 DESCRIPSION The TJ3212 is a dual-output low noise linear regulator designed to meet SSTL-2 and SSTL-3 specifications for DDR-SDRAM VDDQ supply and termination voltage VTT supply. With integrated power MOSFETs the TJ3212 can source up to 2A of VDDQ continuous current, and source or sink up to 2A VTT continuous current. The typical dropout voltage for VDDQ is 500mV at 2A load current. The TJ3212 provides excellent full load regulation and fast response to transient load changes. It also has builtin over-current limits and thermal shutdown at 170°C. The TJ3212 supports Suspend-To-RAM (STR) and ACPI compliance with Shutdown Mode which tri-states VTT to minimize quiescent system current. The TJ3212 is available in a space saving TDFN-8 and SOIC-8 surface mount packages. Low thermal resistance allows them to withstand high power dissipation at 85°C ambient. The TJ3212 can operate over the industrial ambient temperature range of –40°C to 85°C. Mar. 2011 - Preliminary -1 - HTC DDR VDDQ and VTT Termination Voltage Regulator TJ3212 Ordering Information Package Order No. Description Supplied As Status TDFN-8 TJ3212Q Reel Contact us SOP-8 TJ3212DP Reel Contact us SOP-16 TJ3212D Tube Contact us Absolute Maximum Ratings CHARACTERISTIC SYMBOL VIN to GND Pin Voltage VDDQ, VTT to GND ADJSD to GND VDDQ / VTT, continuous Output Current (Note 1) VDDQ / VTT, peak VDDQ Source + VTT Source RATINGS UNIT [GND - 0.3] to +6.0 V [GND - 0.3] to +6.0 V [GND - 0.3] to +6.0 V 2.0 / ± 2.0 A 2.8 / ± 2.8 A 3 A Operating Ambient Temperature TA –40 to 85 °C Operating Junction Temperature TJ –40 to 170 °C TSTG –40 to 150 °C Storage Temperature Thermal Resistance TDFN-8 SOP-8 SOP-16 (Note 2) RJA Continuous Power Dissipation (Note 2) TA = 25°C / 85°C TDFN-8 SOP-8 SOP-16 PD(Cont.) Lead Temperature (Soldering, 10sec) TSOL ESD Protection (HBM) Mar. 2011 - Preliminary -2 - 55 120 90 2.6 / 1.5 1.2 / 0.7 1.6 / 0.9 °C / W W 300 °C 2000 V HTC DDR VDDQ and VTT Termination Voltage Regulator TJ3212 Operating Ratings CHARACTERISTIC SYMBOL Ambient Operating Temperature Range TOPR RATINGS –40 to 85 UNIT °C VDDQ Regulator Supply Voltage, VIN Load Current, Continuous Load Current, Peak (1 sec) CDDQ 3.0 to 3.6 0 to 2 2.5 220 V A A uF VTT Regulator Supply Voltage, VIN Load Current, Continuous Load Current, Peak (1 sec) CTT 3.0 to 3.6 0 to ±2.0 ±2.50 220 V A A uF RATINGS UNIT 3.0 to 3.6 V 2.5 3.5 A A –40 to +150 °C Operating Ratings (Continued) CHARACTERISTIC SYMBOL VIN Supply Voltage Range VDDQ Source + VTT Source Load Current, Continuous Load Current, Peak (1 sec) Junction Operating Temperature Range Mar. 2011 - Preliminary TJOPR -3 - HTC DDR VDDQ and VTT Termination Voltage Regulator TJ3212 PIN CONFIGURATION 8 7 6 5 8 7 6 5 16 15 14 13 12 11 10 9 1 2 3 4 1 2 3 4 1 2 3 4 5 6 7 8 TDFN-8 SOP-8 SOP-16 PIN DESCRIPTION TDFN-8 / SOP-8 PKG SOP-16 PKG Pin No. Name Function Name Function 1 VIN Input Supply VIN Input Supply 2 VTT Output Voltage for Connection to Termination Resistors VIN Input Supply 3 GND Ground VIN Input Supply 4 GND Ground N.C Not internally connected. 5 EN Chip Enable N.C Not internally connected. 6 ADJ VDDQ Adjust VTT Output Voltage for Connection to Termination Resistors 7 VREF Reference Voltage GND Ground 8 VDDQ VDDQ Regulator Output Voltage GND Ground 9 - - EN Chip Enable 10 - - SENSE Feedback for Regulating VTT 11 - - VREF Reference Voltage 12 - - VDDQ VDDQ Regulator Output Voltage 13 - - VDDQ VDDQ Regulator Output Voltage 14 - - ADJ VDDQ Adjust 15 - - GND Ground 16 - - VIN Input Supply Mar. 2011 - Preliminary -4 - HTC DDR VDDQ and VTT Termination Voltage Regulator TJ3212 TYPICAL APPLICATION VIN = 3.0V ~3.6V 220 uF 4.7uF (opt.) VTT = 1.25V/2A 220 uF 4.7uF (opt.) 1 VIN VDDQ 2 VTT VREF GND ADJ 3 4 EN GND -5 7 R1 13k 6 1.2V 5 R2 12k 220 uF 4.7uF (opt.) S/D TJ3212 Mar. 2011 - Preliminary VDDQ = 2.5V/2A 8 - HTC DDR VDDQ and VTT Termination Voltage Regulator TJ3212 ELECTRICAL CHARACTERISTICS Parameters Symbol Supply Voltage Range VIN Quiescent Current IQ ADJSD Voltage VADJSD Condition Min. Typ. 3.0 IDDQ = 0, ITT =0 ISHDN ADJSD Logic High SHDN_H (2) ADJSD Logic Low SHDN_L (3) Unit 3.6 V 2 (3) Shutdown Current Max. 1.225 VADJSD = 3.3V (shutdown) 1.250 mA 1.275 0.1 V mA 2.7 V 1.5 V 2.90 V Under-voltage Lockout UVLO Hysteresis = 100mV (3) 2.40 2.70 Thermal SHDN Threshold TOVER (3) 150 170 °C Thermal SHDN Hysteresis THYS 50 °C 100 ppm/°C VDDQ, VTT TEMPCO TEMPCO IOUT = 1A (3) VDDQ Regulator VDDQ Output Voltage VDDQ EDF IDDQ = 100mA VDDQ Load Regulation VDDQ LOAD VDDQ Line Regulator VDDQ LINE VDDQ Dropout Voltage VDROP ADJSD Bias Current IADJ VDDQ Current Limit IDDQ LIM 2.450 2.500 2.550 V 10mA ≤ IDDQ ≤ 2A (4) 10 25 mV 3.0V ≤ VIN ≤ 3.6V, IDDQ = 0.1A 5 25 mV IDDQ = 2A (5) 500 (3) 0.8 2.0 2.5 1.225 1.250 -30 mV 3 uA A VTT Regulator VTT Output Voltage VTT DEF ITT = 100mA VTT Load Regulation VTT LOAD Source, 10mA ≤ ITT ≤ 2A (4) (4) Sink, -2A ≤ ITT ≤ 10mA VTT Line Regulator VTT LINE 3.0V ≤ VIN ≤ 3.6V, ITT = 0.1A ITT Current Limit VTT Shutdown Leakage Current Reference Voltage ITT LIM Source / Sink (4) ± 2.0 IVTT OFF VEN_VTT = 0.4V (shutdown) VREF CREF = 0.1uF, IREF = 100uA 1.225 1.275 V 10 -10 30 mV mV 5 15 mV ± 2.5 1.250 A 10 uA 1.275 V Note 1. VIN = 3.3V, VDDQ = 2.50V, VTT = 1.25V (default values), CDDQ=CTT=47F, TA = 25°C unless otherwise specified. Note 2. The ADJSD Logic High value is normally satisfied for full input voltage range by using a low leakage current (below 1A). Schottky diode at ADJSD control pin. Note 3. Guaranteed by design. Note 4. Load and line regulation are measured at constant junction temperature by using pulse testing with a low duty cycle. For high current tests, correlation method can be used. Changes in output voltage due to heating effects must be taken into account separately. Load and line regulation values are guaranteed by design up to the maximum power dissipation. Note 5. Dropout voltage is the input to output voltage differential at which output voltage has dropped 100mV from the nominal value obtained at 3.3V input. It depends on load current and junction temperature. Guaranteed by design. Mar. 2011 - Preliminary -6 - HTC DDR VDDQ and VTT Termination Voltage Regulator TJ3212 TYPICAL OPERATING CHARACTERISTICS VTT vs. VDDQ VDDQ vs. IDDQ VDDQ Dropout vs. IDDQ Mar. 2011 - Preliminary VTT vs. Load Current -7 - HTC DDR VDDQ and VTT Termination Voltage Regulator TJ3212 TYPICAL OPERATING CHARACTERISTICS (Continued) VDDQ Transient Response VTT Transient Response Softstart into full load Mar. 2011 - Preliminary -8 - HTC DDR VDDQ and VTT Termination Voltage Regulator TJ3212 APPLICATION INFORMATION Powering DDR Memory Double-Data-Rate (DDR) memory has provided a huge step in performance for personal computers, servers and graphic systems. As is apparent in its name, DDR operates at double the data rate of earlier RAM, with two memory accesses per cycle versus one. DDR SDRAMs transmit data at both the rising and falling edges of the memory bus clock. DDR’s use of Stub Series Terminated Logic (SSTL) topology improves noise immunity and power-supply rejection, while reducing power dissipation. To achieve this performance improvement, DDR requires more complex power management architecture than previous RAM technology. Unlike the conventional DRAM technology, DDR SDRAM uses differential inputs and a reference voltage for all interface signals. This increases the data bus bandwidth, and lowers the system power consumption. Power consumption is reduced by lower operating voltage, a lower signal voltage swing associated with Stub Series Terminated Logic (SSTL_2), and by the use of a termination voltage, VTT. SSTL_2 is an industry standard defined in JEDEC document JESD8-9. SSTL_2 maintains high-speed data bus signal integrity by reducing transmission reflections. JEDEC further defines the DDR SDRAM specification in JESD79C. DDR memory requires three tightly regulated voltages: VDDQ, VTT, and VREF (see Figure 1). In a typical SSTL_2 receiver, the higher current VDDQ supply voltage is normally 2.5V with a tolerance of ±200mV. The active bus termination voltage, VTT, is half of VDDQ. VREF is a reference voltage that tracks half of VDDQ ±1%, and is compared with the VTT terminated signal at the receiver. VTT must be within ± 40mV of VREF. Figure 1. Typical DDR terminations, Class II The VTT power requirement is proportional to the number of data lines and the resistance of the termination resistor, but does not vary with memory size. In a typical DDR data bus system each data line termination may momentarily consume 16.2mA to achieve the 405mV minimum over VTT needed at the receiver: I terminatio n = 405mV = 16.2mA R t (25Ω) A typical 64Mbyte SSTL-2 memory system, with 128 terminated lines, has a worst-case maximum VTT supply current up to ± 2.07A. However, a DDR memory system is dynamic, and the theoretical peak currents only occur for short durations, if they ever occur at all. These high current peaks can be handled by the VTT external capacitor. In a real memory system, the continuous average VTT current level in normal operation is less than ± 200mA. Mar. 2011 - Preliminary -9 - HTC DDR VDDQ and VTT Termination Voltage Regulator TJ3212 The VDDQ power supply, in addition to supplying current to the memory banks, could also supply current to controllers and other circuitry. The current level typically stays within a range of 0.5A to 1A, with peaks up to 2A or more, depending on memory size and the computing operations being performed. The tight tracking requirements and the need for VTT to sink, as well as source, current provide unique challenges for powering DDR SDRAM. TJ3212 Regulator The TJ3212 dual output linear regulator provides all of the power requirements of DDR memory by combining two linear regulators into a single package. VDDQ regulator can supply up to 2A current, and the two quadrant VTT termination regulator has current sink and source capability to ± 2A. The VDDQ linear regulator uses a PMOS pass element for a very low dropout voltage, typically 500mV at a 2A output. The output voltage of VDDQ can be set by an external voltage divider. The use of regulators for both the upper and lower side of the VDDQ output allows a fast transient response to any change of the load, from high current to low current or inversely. The second output, VTT, is regulated at VDDQ / 2 by an internal resistor divider. Same as VDDQ, VTT has the same fast transient response to load change in both directions. The VTT regulator can source, as well as sink, up to 2A current. The TJ3212 is designed for optimal operation from a nominal 3.3V DC bus, but can work with VIN up to 5V. When operating at higher VIN voltages, attention must be given to the increased package power dissipation and proportionally increased heat generation. Limited by the package thermal resistance, the maximum output current of the device at higher VIN cannot exceed the limit imposed by the maximum power dissipation value. VREF is typically routed to inputs with high impedance, such as a comparator, with little current draw. An adequate VREF can be created with a simple voltage divider of precision, matched resistors from VDDQ to ground. A small ceramic bypass capacitor can also be added for improved noise performance. Input and Output Capacitors The TJ3212 requires that at least a 220uF electrolytic capacitor be located near the VIN pin for stability and to maintain the input bus voltage during load transients. An additional 4.7uF ceramic capacitor between the VIN and GND, located as close as possible to those pins, is recommended to ensure stability. At a minimum, a 220uF electrolytic capacitor is recommended for the VDDQ output. An additional 4.7uF ceramic capacitor between the VDDQ and GND, located very close to those pins, is recommended. At a minimum, a 220uF electrolytic capacitor is recommended for the VTT output. This capacitor should have low ESR to achieve best output transient response. SP or OSCON capacitors provide low ESR at high frequency, and thus are a good choice. In addition, place a 4.7uF ceramic capacitor between the VTT pin and GND, located very close to those pins. The total ESR must be low enough to keep the transient within the VTT window of 40mV during the transition for source to sink. An average current step of ± 0.5A requires: ESR < 40mV = 40mΩ 1A Both outputs will remain stable and in regulation even during light or no load conditions. The general recommendation for circuit stability for the TJ3212 requires the following: 1) CIN = CDDQ = CTT = 220uF / 4.7uF for the full temperature range of –40 to +85°C. 2) CIN = CDDQ = CTT = 100uF / 2.2uF for the temperature range of –25 to +85°C. Mar. 2011 - Preliminary - 10 - HTC DDR VDDQ and VTT Termination Voltage Regulator TJ3212 Adjusting VDDQ Output Voltage The TJ3212 internal bandgap reference is set at 1.25V. The VDDQ voltage is adjustable by using a resistor divider, R1 and R2: VDDQ = V ADJ × R1 + R2 R2 where VADJ = 1.25V. The recommended divider value is R1 = R2 = 10k for DDR-1 application, and R1 = 4.42k, R2 = 10k for DDR-2 application (VDDQ = 1.8V, VTT = 0.9V). Shutdown ADJSD also serves as a shutdown pin. When this is pulled high (SHDN_H), both the VDDQ and the VTT outputs tristate and could sink/source less than 10uA. During shutdown, the quiescent current is reduced to less than 0.5mA, independent of output load. It is recommended that a low leakage Schottky diode be placed between the ADJSD Pin and an external shutdown signal to prevent interference with the ADJ pin’s normal operation. When the diode anode is pulled low, or left open, the TJ3212 is again enabled. For Shutdown operation, observe the following: Under ADJSD shutdown condition, VDDQ should go to tri-state. VDDQ Under EN_VTT shutdown condition, VDDQ should keep state (2.5V). Under ADJSD or EN_VTT shutdown condition, VTT should go to tri-state and should sink or source less than 10uA. VTT Under ADJSD shutdown condition, VREF should go to zero. VREF Under EN_VTT shutdown condition, VREF should keep state (1.2V or VDDQ/2). Current Limit and Over-temperature Protection The TJ3212 features internal current limiting with thermal protection. During normal operation, VDDQ limits the output current to approximately 2A and VTT limits the output current to approximately ± 2A. When VTT is current limiting into a hard short circuit, the output current folds back to a lower level (~1A) until the over-current condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the junction temperature of the device exceeds 170°C(typical), the thermal protection circuitry triggers and tri-states both VDDQ and VTT outputs. Once the junction temperature has cooled to below about 120°C the TJ3212 returns to normal operation. Typical Thermal Characteristics The overall junction to ambient thermal resistance (θJA) for device power dissipation (PD) primarily consists of two paths in the series. The first path is the junction to the case (θJC) which is defined by the package style and the second path is case to ambient (θCA) thermal resistance which is dependent on board layout. The final operating junction temperature for any condition can be estimated by the following thermal equation: TJ = TA + PD x (θJC) + PD x (θCA) = TA + PD x (θCA) Mar. 2011 - Preliminary - 11 - HTC