ETC CR81200

CR81P200
TM
8-Bit Microcontroller
DATA SHEET
======== CR81P200 ========
Crescenic Technology Corporation
All rights reserved .
FR18033B
2004/11/Ver. 0.0.02/All rights reserved.
1
CR81P200
TM
Caution!
The information in this document is subject to change without notice
and does not represent a commitment on part of the vendor, who assumes
no liability or responsibility for any errors that may appear in this data
sheet.
No warranty or representation, either expressed or implied, is made
with respect to the quality, accuracy, or fitness for any particular part of
this document. In no event shall the manufacturer be liable for direct,
indirect, special, incidental or consequential damages arising from any
defect or error in this data sheet or product. Product names appearing in
this data sheet are for identification purpose only, and trademarks and
product names or brand names appearing in this document are property of
their respective owners.
All rights reserved. No part of this data sheet may be reproduced,
transmitted, or transcribed without the expressed written permission of the
manufacturer and authors of this data sheet.
FR18033B
2004/11/Ver. 0.0.02/All rights reserved.
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CR81P200
TM
1. General Description
The CR81P200 is an EPROM microcontroller with 8 bits, which takes advantage of a
thorough CMOS technology improved with low cost, high speed, and high noise immunity.
Preferably, integrated into this single chip are up to 6 channels 8-bit ADC, 2 channels PWM, a
Watchdog Timer, a RAM, a EPROM, a tri-state I/O port, a power-down mode, power on reset
with low voltage detection and a real time programmable clock/counter. CR81P200 works
with 48 instructions. The number of cycle per instruction can be chosen from three options, 4
/ 2 /1 cycle through firmware, so the user can use a crystal at a lower frequency to achieve a
high-speed performance easily. Moreover, CR81P200 stays in power-saving mode during
instruction execution for lower frequency and power application.
1.1 Features
z Full CMOS static design.
z Better noise immunity
z Additional the instructions BCTR and BRTC for easy use of transferring between
Carry bit and Register bit
z Operating voltage ranging from 3.0V to 6.5V
z 1 instruction cycle takes 4/2/1 system clocks controlled by register OPT bit 3,2.
z Operating frequency at 0 up to 15M Hz, Vdd =5V for one cycle option
Operating frequency at 0 up to 25M Hz, Vdd =5V for two cycles option
Operating frequency at 0 up to 40M Hz, Vdd =5V for four cycles option
z 8-bit data bus
z Internal EPROM with 2K words in size
z 72-byte internal RAM with Bank control and extra one hidden register.
z 22 special purpose registers
z Both 22 general purpose I/O pins and 1 counter input pin for I/O pins
z 5-level stacks of program counter
z Four types of interrupt vectors
z Four interrupt sources , including a Timer/counter interrupt, a PortA interrupt, ADC
interrupt, and a Watchdog timer time-out interrupt
z 6 channels 8-bit ADC
z Two 8-bit PWM modules. They can serve as DACs by connecting a low-pass filter.
z Power on reset with 2 levels adjustable low voltage detection.
z Power-saving mode for the lower frequency application based on a low power
requirement
z Config options:
-- 4 oscillator types selected by config option:
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CR81P200
TM
RC -- RC oscillator
LFXT -- Low frequency crystal oscillator
XTAL -- Crystal oscillator
HFXT -- High frequency crystal oscillator
-- 4 oscillator start-up time selected by config option:
172µs, 22ms, 44ms, and 88ms
-- Watchdog timer enabled/disabled by config option
2. Pins Assignment
CR81P200N28
CNTI
VDD
PB5/ADCI
VSS
PB4/ADCI
PB0/ADCI
PB1/ADCI
PB2/ADCI
PB3/ADCI/ADvref
PA0
PA1
PA2/PWMO
PA3/PWMO
PA4
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
/ERST
OSC1
OSC2
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PA7
PA6
PA5
2.1 Pins Description
NO.
I/O Type
PA0
10
I/O
TTL
PA1
11
I/O
TTL
PA2/PWMO
12
I/O
TTL
PA3/PWMO
13
I/O
TTL
PA4
14
I/O
TTL
PA5
15
I/O
TTL
PA6
16
I/O
TTL
PA7
17
I/O
TTL
PB0/ADCI
6
I/O
TTL
Name
Input Level Description
Bi-directional and can serve as Port A
interrupt input.
Bi-directional , PWM output and can
serve as Port A interrupt input.
Bi-directional and can serve as Port A
interrupt input.
Bi-directional and ADC input
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CR81P200
TM
PB1/ADCI
7
I/O
TTL
PB2/ADCI
8
I/O
TTL
PB3/ADCI/
ADVref
9
I/O
TTL
Bi-directional and ADC input or ADC
Vref-in
PB4/ADCI
5
I/O
TTL
Bi-directional and ADC input
PB5/ADCI
3
I/O
TTL
PC0
18
I/O
TTL
PC1
19
I/O
TTL
PC2
20
I/O
TTL
PC3
21
I/O
TTL
PC4
22
I/O
TTL
PC5
23
I/O
TTL
PC6
24
I/O
TTL
PC7
25
I/O
TTL
CNTI
1
I
Schmitt
Trigger
A clock input to TCR; in order to avoid
the leakage current, this pin must be tied
to pull-high or pull-low.
/ERST
28
I
Schmitt
Trigger
An external reset input pin; this pin is
an active low reset to the device.
OSC1
27
I
-
An input pin of oscillator crystal
input/external clock source
OSC2
26
O
-
Oscillator crystal output
VDD
2
P
-
Power supply
VSS
4
P
-
Ground
Bi-directional
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CR81P200
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3. Block Diagram of Structure
New RISC 2K Structure Block Diagram
OSC1 OSC2 /ERST
CNTI
WTC
Stack
Stack
Stack
Stack
Stack
PC
Oscillator/Timing
Control
WDT
Timer
ROM
8bit Prescaler
Instruction
Register
8Bit Prescaler
WDT
Time_out
ALU
Mux
Instruction
Decode
ACC
TCC
TCC
Sleep/Wakeup
control
Special
Register &
RAM
R1
TCR
Timer interrupt
TCC
WTC
R2
Interrupt
DATA & CONTROL BUS
CPA
IPA
PWM_Cntl
PWM
RPA
CPB
OPT
ADC_Cntl
RPA
CPC
RPC
ADC
PC7~PC0
PA7~PA0
PA7~PA0
4. Memory mapping
4.1 Special Register & Internal RAM
00
01
02
03
04
05
06
07
INDirect addressing register ( IND )
{CTRLR 00/h => Watchdog Timer Control register WTC}
Timer/Counter Register ( TCR )
{CTRLR 01/h => Timer/Counter Control register TCC}
Program Counter, Low byte ( PCL )
{CTRLR 02/h => Port A Interrupt control register IPA}
Status Flag Register ( SFR )
{CTRLR 03/h => I/O P and RAM Bank control register OPT}
Memory Index Register (MIR)
{CTRLR 04/h => Hidden generial purpose register HGR}
Port A data Register ( RPA )
{CTRLR 05/h => Port A Control register CPA}
Port B data Register ( RPB )
{CTRLR 06/h => Port B Control register CPB}
Port C data Register ( RPC )
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CR81P200
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{ CTRLR 07/h
=>
Port C Control register CPC }
Note: CTRLR is one of the RISC instructions for writing or reading these special
control registers.
08
09
0A
0B
0C
0D
0E
0F
10∼1F
Internal RAM
Internal RAM
Internal RAM
Internal RAM
Internal RAM
Internal RAM
Internal RAM
Internal RAM
Internal RAM
20∼2F
Internal RAM ( Bank Disabled )
/
Mapping to 00∼0F( Bank
30∼3F
40∼4F
Enabled )
Internal RAM
Internal RAM ( Bank Disabled )
/
Mapping to 00∼0F( Bank
50∼5F
60∼6F
Enabled )
None ( Bank Disabled )
60∼67 : None (Bank Disable)
/ Internal RAM ( Bank Enabled )
/ Mapping to 00∼07( Bank
70∼7F
Enabled )
68 : None ( Bank Disable or Bank Enable )
69 ~ 6F : the control registers and Data registers of PWM and ADC
None ( Bank Disabled )
/ Internal RAM ( Bank Enabled )
Hint:
If you don’t understand the description above very well, please refer to the memory map
shown below and the special function registers in chapter 5.1.
˙No Memory Bank ( OPT bit7=0)
Memory address = 00~4FH (continuous memory addressing mode) + 69 ~ 6F
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CR81P200
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˙Memory Bank ( OPT bit7=1), illustrated in the form of table below:
Address
Description
FSR<6:5>
Bank 0
00
Bank 1
01
Bank 2
10
Bank 3
11
00h
IND
01h
TCR
02h
PCL
03h
SFR
69h
P2D
04h
MIR
6Ah
P3D
05h
RPA
PWC
06h
RPB
07h
RPC
Address map
6Bh
back to address in 6Ch
bank 0
6Dh
6Eh
ADH
6Fh
ADC
08h~0FH General Purpose
Register
ADF
ADD
10h~1Fh
30h~3Fh
50h~5Fh
70h~7Fh
General Purpose General Purpose General Purpose General Purpose
Register
Register
Register
Register
5. Function Control Registers
5.1 Special Function Control Registers
Address Name
00h
IND
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Use contents of MIR to address data memory(not a physical register)
01h
TCR
8 bits of real-time clock/counter
02h
PCL
Program counter with low byte
03h
SFR
04h
MIR
05h
RPA
RPA7
RPA6
RPA5
RPA4
RPA3
06h
RPB
-
-
RPB5
RPB4
07h
RPC
RPC7
RPC6
RPC5
69h
P2D
P2D7
P2D6
6Ah
P3D
P3D7
6Bh
PWC
--
6Ch
ADF
ARDY AINTF
6Dh
ADD
ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
6Eh
ADH
6Fh
ADC ADEN
GB
PP1
PP0
/WD
/SP
Z
AC
C
RPA2
RPA1
RPA0
RPB3
RPB2
RPB1
RPB0
RPC4
RPC3
RPC2
RPC1
RPC0
P2D5
P2D4
P2D3
P2D2
P2D1
P2D0
P3D6
P3D5
P3D4
P3D3
P3D2
P3D1
P3D0
--
--
--
PEN3
PEN2
PCK1
PCK0
--
--
--
--
--
--
Indirect data memory address pointer
APB5
AIEN AREN
APB4
APB3
--
--
FR18033B
APB2
APB1
APB0
ACK2 ACK1 ACK0
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CR81P200
TM
Note:
1. Access of these control registers can be executed in normal direct or indirect addressing
mode.
2. Legend: GB = General memory Bit
PP1, PP0 = Program memory page bits
/WD = WatchDog flag
AC = Auxiliary Carry flag
Z = Zero flag
/SP = SleeP flag
C = Carry flag
3. P2D7~P2D0 : set duty cycle of 8-bit PWM at PA2
P3D7~P3D0 : set duty cycle of 8-bit PWM at PA3
PEN2: Enable PWM function at PA2
PEN3: Enable PWM function at PA3
PCK1, PCK0: set PWM clock
4. ARDY: ADC process Done flag
AINTF: ADC interrupt flag
ADD7~ADD0: 8-bit ADC data
APB5~APB0: Define PB5 PB4 PB3 PB2 PB1 PB0 respectively as ADC input
ADEN: Enable ADC function
AIEN: Enable ADC interrupt
AREN: Choose PB3 as VRef of ADC instead of Vdd.
ACK2~ACK0: set ADC clock
5.2 Implicit Function Control Registers
CTRLR Name Bit7
Address
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
00h
WTC CNTI WDTI TCLK EGTY PSCA
PSC2
PSC1
PSC0
01h
TCC TCEI TCEN PSCS
PSC2
PSC1
PSC0
02h
IPA
PSCC
TPSC
Port A interrupt control register
A ‘1’ in this register will allow a low pulse applied to the
corresponding pin of port A to generate an interrupt and wake up
the MPU. The interrupt and wake up function are valid only while
the pin is not defined as an output pin.
03h
OPT
RAMB IOWM PWSV PSEX_ ONE-C TURB LVD-S LVD-E
_EN
EN
YC O-EN EL
N
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CR81P200
TM
<RAMB> RAM Bank enable bit
“0” for disabling RAM bank function
“1” for enabling RAM bank function (default)
<IOWM> I/O port write mode for read-then-write instruction.
“0” for reading the latch → operation → write (default)
“1” for reading the interface → operation → write
<PWSV_EN> enable bit for power-saving mode
0
Disable power-saving mode during instruction
execution. This bit should be reset to 0 if the application
belongs to the higher frequency ones. (default)
1
Enable power-saving mode for lower frequency
application caring about power consumption.
<PSEX_EN> enable bit for solving prescaler exchange issue
between watchdog timer and Timer.
0
Disable just for compatibility with Mask version.
1
Enable (default)
<ONE-CYC> enable bit for one cycle per instruction option.
0
Disable one cycle option. If TURBO-EN is set to 1, the
number of cycles it takes per instruction is 2. If
TURBO-EN is reset to 0, the number of cycles it takes per
instruction is 4. (default)
1
Enable one cycle option. TURBO-EN should be set 1
when users want to use One-cycle option.
<TURBO-EN> enable bit for turbo option.
0
Disable turbo option. Then ONE-CYC bit should be 0,
too. The number of cycles it takes per instruction is 4.
1
Enable turbo option. If ONE-CYC is set to 1, the number
of cycles it takes per instruction is 1. If ONE-CYC is reset
to 0, the number of cycles it takes per instruction is 2.
<LVD_SEL> Select the voltage level of Low Voltage detector
“0” Lower : 1.4 ~ 1.8V (default)
“1” Higher: 2.1 ~ 2.8V
<LVD_EN> Enable Low Voltage Reset
“0” Disable: Low voltage reset is disabled
“1” Enable: Low voltage reset is enabled (default)
If we want to make the sleep current minimum, the Low
voltage reset should be turned off before entering sleep mode.
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CR81P200
TM
04h
HGR
HGR7 HGR6 HGR5 HGR4 HGR3 HGR2 HGR1 HGR0
Hidden generial purpose register. The register will be reset while
power-on reset or external reset occurs, which is different from the
feature of RAM.
05h
Port A control register
CPA
A ’0’ in this register will set the corresponding pin of port A to an
output.
06h
CPB
-
-
Port B control register
A ’0’ in this register will set the corresponding pin of port B to an
output.
Bit[7:6] are unimplemented and always read as ‘0’.
07h
CPC
Port C control register
A ’0’ in this register will set the corresponding pin of port C to an
output.
Note:
Access of these control registers is only executed by the instruction “CTRLR”.
5.3 Program Memory and Reset&Interrupt Vectors
000-7FB for program memory
7FC for port A interrupt and ADC interrupt starting address
7FD for timer/counter interrupt starting address
7FE for watchdog timer time-out interrupt starting address
7FF for power-on or external reset starting address
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CR81P200
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6. Program Memory Map and Stack
PC<10:0>
11
Stack Level 1
Stack Level 2
Stack Level 3
Stack Level 4
Stack Level 5
000h
On-chip Program Memory
(Page 0)
0FFh
100h
1FFh
200h
User Memory Space
On-chip Program Memory
(Page 1)
2FFh
300h
3FFh
400h
On-chip Program Memory
(Page 2)
4FFh
500h
5FFh
600h
On-chip Program Memory
(Page 3)
6FFh
700h
7FBh
Port A interrupt and ADC interrupt starting address
Timer/Counter interrupt starting address
WDT time-out interrupt starting address
Power on or external reset starting address
7FCh
7FDh
7FEh
7FFh
6.1 Special Registers
1) 00H [7:0] < IND > INDirect addressing register {RW}
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CR81P200
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Description:
Not serving as a physical register, this register is used as an indirect address pointer.
Reading or writing this address will have access to the register of the address defined by the
04H (MIR).
MIR (04H) = 0 indicates that the result=00H will appear if IND (00H) is read, and the
operation will be being executed as a NOP (No OPeration), maybe affecting C, AC, or Z flag,
if IND (00H) is written in.
2) 01H [7:0] < TCR > Timer/Counter Register {RW}
Description:
If a timer/counter is enabled, after powered on, the counter will start to count up. An
interrupt, if enabled, will be generated while the counter reaches 255; unless otherwise an
interrupt is disabled, the counter will continue to count till a new value is loaded.
3) 02H [7:0] < PCL > Program Counter Low byte {RW}
Description:
This register is a low byte of the PC (program counter). Writing this register will change
the PC.
4) 03H [7:0] < SFR > Status Flag Register {RW}
Description:
[0] = < C > Carry flag
Carry flag represents the operational results of addition and subtraction, wherein “0”
indicates that the result of operation does not generate a carryout in the MSB and “1”
indicates that the result of operation generates a carryout in the MSB. A subtraction is
executed by adding the 2's complement of the operand. By the way, please refer to instruction
set for other affected flags.
C
Yes
No
Carry (Addition)
1
0
Borrow (Subtraction)
0
1
[1]= < AC > Auxiliary Carry flag
“0” indicates that the result of operation does not generate a carryout in bit3;
“1” indicates that the result of operation generates a carryout in bit3.
Auxiliary Carry flag feature about operates addition and subtraction
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CR81P200
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AC
Yes
No
Carry from b3 (Addition)
1
0
Borrow for b3 (Subtraction)
0
1
[2]= < Z > Zero flag
“0” indicates that the result of operation is not zero;
“1” indicates that the result of operation is zero.
[3]= < /SP > SleeP flag
“0” for a bit coming after SLEEP or STDBY instruction. (The status bit can’t be recovered
to ‘1’ automatically, so you have to set this bit manually after SLEEP or STDBY.);
“1” for power-up or the execution of CLRWT instruction.
[4]= < /WT > Watchdog Timer flag
“0” for watchdog timer timeout;
“1” for power-up or the execution of CLRWT, SLEEP, and STDBY instructions.
[6:5] = <PP1:PP0 > Program memory Page bits
[7] = < GB > General register Bit
EVENT
SLEEP、STDBY
/WT /SP
1
0
CLRWT instruction
1
1
Power up
1
1
Watchdog timeout
0
*
*: unaffected
/WT /SP
0
0
DESCRIPTION
Watchdog timer timeout reset or interrupt during SLEEP、STDBY
0
1
Watchdog timer timeout reset or interrupt not during SLEEP、STDBY
1
0
External reset､PortA ､ADC､Timer/Counter interrupt during SLEEP、STDBY
1
1
Power-on reset
u
u
External reset､PortA ､ADC､Timer/Counter interrupt not during SLEEP、STDBY
u: unchanged
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CR81P200
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PP0,PP1:
Below shown is a table illustrating PP0 and PP1 status
PP1
PP0
Program segment address
0
0
000∼7FFH == 000∼7FFH
0
1
000∼1FFH == 200∼3FFH
1
0
000∼1FFH == 400∼5FFH
1
1
000∼1FFH == 600∼7FFH
(1) [PP1:PP0] == 00 (default)
☉ JUMP aADDR
;
aADDR = A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓
PC = A10 A9 A8
A7 A6 A5 A4
A3 A2 A1 A0
☉ CALL aADDR ; aADDR = A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓
PC = A10 A9 A8
☉ WRITE
PCL ;
PC = A10 A9 A8
A7 A6 A5 A4
Data 8 Bits =
Operation result =
A3 A2 A1 A0
A3 A2 A1 A0
B7 B6 B5 B4 B3 B2 B1 B0
D7 D6 D5 D4 D3 D2 D1 D0
PP1 PP0
↓ ↓
PC =
A7 A6 A5 A4
0
FR18033B
0
0
↓ ↓ ↓ ↓
↓ ↓ ↓ ↓
D7 D6 D5 D4
D3 D2 D1 D0
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CR81P200
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JUMP or CALL Instruction
10
9
8
7
0
PCL
PC
Instruction Word
WRITE Instruction
10
9
8
7
0
PC
PCL
Instruction Word
2
Reset to '0'
0
7
PP1 PP0
SFR
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CR81P200
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(2) [PP1:PP0] ≠ 00
☉ JUMP aADDR
;
aADDR = A10 A9 A8
A7 A6 A5 A4
A3 A2 A1 A0
PP1 PP0
↓ ↓ ↓
↓ ↓ ↓ ↓
↓ ↓ ↓ ↓
PC = PP1 PP0 A8
A7 A6 A5 A4
A3 A2 A1 A0
☉ CALL aADDR ; aADDR = A10 A9 A8 A7 A6 A5 A4
A3 A2 A1 A0
PP1 PP0
↓ ↓
PC = PP1 PP0
☉ WRITE
PCL ;
0
PC = A10 A9 A8
↓ ↓ ↓ ↓
↓ ↓ ↓ ↓
A7 A6 A5 A4
A3 A2 A1 A0
A7 A6 A5 A4
Data 8 Bits =
Operation result =
A3 A2 A1 A0
B7 B6 B5 B4 B3 B2 B1 B0
D7 D6 D5 D4 D3 D2 D1 D0
PP1 PP0
↓ ↓
PC = PP1 PP0
FR18033B
↓ ↓ ↓ ↓
0
D7 D6 D5 D4
↓ ↓ ↓ ↓
D3 D2 D1 D0
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CR81P200
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JUMP Instruction
10
9
8
7
0
PC
PCL
Instruction Word
2
0
7
PP1 PP0
SFR
CALL or WRITE Instruction
10
9
8
7
0
PC
PCL
Instruction Word
2
Reset to '0'
0
7
PP1 PP0
SFR
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CR81P200
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5) 04H [7:0] < MIR > Memory Index Register {RW}
Description:
[6:0] indicates that this register used in the indirect addressing mode defines which register
will be selected during the instruction to read/write 00H.
[7]=< unimplemented > read as ‘1’
(1) [RAMB](b7 of OPT) == 0
☉ [6:0] → 00∼4FH ≡ 00∼4FH
[RAMB] ( b7 of OPT) == 1 (default)
☉ [6:5] = < MB1:MB0 > Memory Bank select bit
☉ ALL Case except MIR[6:3]=1100/b → MIR[4:0]
00∼0FH ≡ 00∼0FH
(Addresses mapping back to the addresses in Bank 0 )
MIR[6:5] == 3 && MIR[4:0]= 09~ 0FH
( ADC and
☉
☉
☉
☉
MIR [6:5] == 0
MIR [6:5] == 1
MIR [6:5] == 2
MIR [6:5] == 3
&&
&&
&&
&&
MIR [4:0]=
MIR [4:0]=
MIR [4:0]=
MIR [4:0]=
10∼1FH
10∼1FH
10∼1FH
10∼1FH
=>
=>
=>
=>
=>
Physical Registers
PWM-related register )
Physical RAM
Physical RAM
Physical RAM
Physical RAM
that is,
Direct Addressing
(MIR)
6 5
Indirect Addressing
4 (opcode) 0
6 5
4
(MIR)
0
bank select location select
Bank select location select
00
01
11
10
00h
Data Memory
Addresses map
back to addresses
in Bank 0.
0Fh
10h
1Fh 3Fh 5Fh 7Fh
Bank 0 Bank 1 Bank 2 Bank 3
* 69/h to 6F/h don’t map to Bank0. These addresses are related to the registers of Data and
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CR81P200
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control registers of ADC and PWM.
6) 05H [7:0] < RPA > Port A data Register {RW}
Description:
This register is an 8-bit I/O register.
7) 06H [5:0] < RPB > Port B data Register {RW}
Description:
Bits 5-0 are I/O register, while bits 7-6 are always read as ‘0’.
8) 07H [7:0] < RPC > Port C data register {RW}
Description:
This register is an 8-bit I/O register.
9) 69H [7:0]
Description:
P2D7~P2D0
10) 6AH [7:0]
Description:
P3D7~P3D0
<P2D> PWM data register for PA2 {RW}
00/h => duty cycle= 0/256
01/h => duty cycle= 1/256
02/h => duty cycle= 2/256
……………………
FE/h => duty cycle= 254/256
FF/h => duty cycle= 255/256
<P3D> PWM data register for PA3 {RW}
00/h => duty cycle= 0/256
01/h => duty cycle= 1/256
02/h => duty cycle= 2/256
……………………
FE/h => duty cycle= 254/256
FF/h => duty cycle= 255/256
Note:
The corresponding PWM register controls the PWM duty cycle. Duty cycle range is from
0/256 to 255/256.
LSB 3-bit of PWM register determines which frame will be extended one period of PWM
clock.
000:no extended pulse.
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CR81P200
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001:extend one PWM clock cycle in frame 4.
010:extend one PWM clock cycle in frame 2 and 6.
011:extend one PWM clock cycle in frame 2, 4 and 6.
100:extend one PWM clock cycle in frame 1, 3, 5 and 7.
101:extend one PWM clock cycle in frame 1, 3, 4, 5 and 7
110:extend one PWM clock cycle in frame 1, 2, 3, 5, 6
and 7.
111:extend one PWM clock cycle in frame 1, 2, 3, 4, 5, 6
and 7.
MSB 5-bit of PWM register determines 0/32 to 31/32 duty cycle in each frame.
11) 6BH [3:0] <PWC> PWM control register {RW}
Description:
Bit 3 PEN3: 1: Enable PWM function of PA3.( PA3 is forced to be Output
mode )
0: Disable PWM function of PA3
Bit 2 PEN2: 1: Enable PWM function of PA2.( PA2 is forced to be Output
mode )
0: Disable PWM function of PA2
Bit 1, 0 :
select PWM clock
PCK1, PCK0
0 0
0 1
1 0
1 1
PWM clock
system clock
system clock/2
system clock/4
system clock/8
12) 6CH [7:6] <ADF> ADC flag register {R}
Description:
Bit 7 ARDY : ADC conversion process “Finish” flag
1: The ADC conversion process has been done, and the valid ADC data is
stored in ADD ( 6D/h).
0: The process hasn’t been done yet. Whenever the ADC process is initiated,
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21
CR81P200
TM
this bit will be cleared automatically.
Bit 6 AINTF : ADC interrupt flag
When ADC interrupt is enabled and ADC conversion process is finished,
the bit will be set and ADC interrupt will occur. The bit is cleared only after
RETI or CLRIF is executed. If we don’t clear this bit after ADC interrupt,
next ADC interrupt and port A interrupt won’t happen again.
13) 6DH [7:0] <ADD> ADC data register {R}
Description:
bit 7 ~0 ADD7 ~ ADD0 : ADC data
14) 6EH [3:0] <ADH> ADC channel register {RW}
Description:
Select ADC channel
Bit 5 APB5: PB5 becomes ADC analog input when we set the bit.
Bit 4 APB4: PB4 becomes ADC analog input when we set the bit.
Bit 3 APB3: PB3 becomes ADC analog input when we set the bit.
Bit 2 APB2: PB2 becomes ADC analog input when we set the bit.
Bit 1 APB1: PB1 becomes ADC analog input when we set the bit.
Bit 0 APB0: PB0 becomes ADC analog input when we set the bit.
The ADC has four selectable input channels. When an input channel is selected, it will start
converting. After the conversion is done, the ARDY bit is set and valid data is stored in
ADD7~ADD0 bits. If program want to make a new conversion, write ADH register again and
it will start another conversion.
15) 6FH [7:0] <ADC> ADC control register {RW}
Description:
Bit 7 ADEN:
1 : Enable ADC function.
0 : Disable ADC function.
Bit 6 AIEN:
1 : Enable ADC interrupt.
0 : Disable ADC interrupt.
Bit 5 AREN:
1: PB3 serves as Vref input for ADC voltage reference (corresponding to
FF/h at Digital side ).
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22
CR81P200
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0:
Just uses Vdd as ADC voltage reference (corresponding to FF/h at
Digital side).
Bit 4, 3: Not used
Bit 2~0 ACK2~ ACK0: select ADC clock.
ACK2 ACK1 ACK0
0
0
0
=>
system clock/2
0
0
1
=>
system clock/4
0
1
0
=>
system clock/8
0
1
1
=>
system clock/16
1
0
0
=>
system clock/32
1
0
1
=>
system clock/64
1
1
0
=>
system clock/128
1
1
1
=> WDT clock (offered by a built-in RC
oscillator for watch-dog, and Watch-dog
must be enabled, and
frequency is about 20 kHz )
This RISC can’t run ADC conversion process under power-down mode or sleep
mode directly and automatically, but we can do it manually through “firmware
solution” to reduce the influence of Digital portion noise and then will get a more
precise data of ADC.
FR18033B
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23
CR81P200
TM
Timing diagram for 8-bit SAR ADC
6.2 Implicit Registers
16) 00H [7:0] < WTC > Watchdog Timer Control register {RW}
[2:0] = < PSC2:PSC1:PSC0 > TCR | WDT PreSCaler rate bits
PSC2 PSC1 PSC0
TCR rate
WDT rate
0
0
0
1:2
1:1
0
0
1
1:4
1:2
0
1
0
1:8
1:4
0
1
1
1:16
1:8
1
0
0
1:32
1:16
1
0
1
1:64
1:32
1
1
0
1:128
1:64
1
1
1
1:256
1:128
[3] = < PSCA > PreSCaler Assigned bit
“0” is assigned to TCR;
“1” is assigned to WDT (default).
If one bit of the prescaler is assigned to WDT, it will be reset after the execution of
FR18033B
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24
CR81P200
TM
CLRWT instruction.
[4] = < EGTY > CNTI input edge select
“0” for an increment of counter at a rising edge on CNTI pin
“1” for an increment of counter at a falling edge on CNTI pin (default)
[5] = < TCLK > Timer/Counter CLocK source
“0” for internal clock (instruction cycle clock , i.e. System clock /4 )
“1” for transition on CNTI pin (default)
[6]= < WDTI > WatchDog Timer time-out Interrupt control in the case of the enabled
WDT in code option configuration
“0” indicates that reset MPU without interrupt in the case of WatchDog Timer timeout
(default);
“1” indicates that enable WatchDog Timer timeout Interrupt.
[7] = < CNTI > State on CNTI pin {Ro}
17) 01H [7:0]
< TCC > Timer/Counter Control register {RW}
Description:
[2:0] = < TPS2: TPS1: TPS0 > TCR PreScaler rate bits
TPS2 TPS1 TPS0
TCR rate
0
0
0
1:2
0
0
1
1:4
0
1
0
1:8
0
1
1
1:16
1
0
0
1:32
1
0
1
1:64
1
1
0
1:128
1
1
1
1:256
[3] = < TPSC > Control Timer/Counter prescaler of TCC register
“0” for disable (default)
“1” for enable
[4]= < PSCC > Clear prescaler of Timer/Counter automatically when changing TCR or
prescaler rate.
“0” for disable
“1” for enable (default)
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CR81P200
TM
[5] = < PSCS > Timer/Counter prescaler selection
“0” for TCR rate Controlled by WTC register [3] (default)
“1” for Timer/Counter using its own prescaler defined by TCC register [4:0].
[6] = < TCEN > Timer/Counter ENable control
“0” indicates that the Timer/Counter is disabled.
“1” indicates that the Timer/Counter (default) is enabled.
[7] = < TCEI > Timer/Counter Interrupt control
“0” indicates that the Timer/Counter interrupt (default) is disabled.
“2” indicates that the Timer/Counter interrupt is enabled.
TCLK
Data Bus
Fosc/2
PSCA
PSCS
8
0
CNTI
Pin
MUX
1
0
1
MUX
1
0
Timer Interrupt
Sync 2
Cycle
MUX
TCR
EGTY
TCEN TCEI
PSCA
0
Watchdog
Timer
1 MUX
8 to 1 MUX
WDTI
8 bit Prescaler
8 bit Prescaler
0
PSC[2:0]
8 to 1 MUX
TCC[2:0]
1
1
MUX
PSCA
MUX
0
TPSC
WDT Time-out
TCR Prescale control
18) 02H [7:0]
< IPA > Port A Interrupt control register {RW}
Description:
A ‘1’ in this register will allow a low pulse applied to the corresponding pin of port A to
generate an interrupt and wake up the MPU, wherein the interrupt and wake-up functions are
valid only while the pin is defined as an input pin.
19) 03H [7:6]
< OPT > Option control register {RW}
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26
CR81P200
TM
Description:
[0]=<LVD_EN> Enable Low Voltage Reset
“0” Disable: Low voltage reset is disabled
“1” Enable: Low voltage reset is enabled (default)
If we want to make the sleep current minimum, the Low voltage reset should be turned
off before entering sleep mode.
[1]=<LVD_SEL> Select the voltage level of Low Voltage detector
“0” Lower : 1.4 ~ 1.8V (default)
“1” Higher: 2.1 ~ 2.8V
If we want to make the sleep current minimum, the Low voltage reset should be turned off
before entering sleep mode.
The number of system
clock for executing
one instruction
Bit 3
ONE-CYC
Bit 2
TURBO-EN
Note
4 cycles
0
0
Default setting
2 cycles
0
1
1 cycle
1
1
Not allowed
1
0
Not allowed
[2] = <TURBO-EN> enable bit for turbo option.
0
Disable turbo option. Then ONE-CYC bit should be 0, too. The number of cycles
it takes per instruction is 4.
1
Enable turbo option. If ONE-CYC is set to 1, the number of cycles it takes per
instruction is 1. If ONE-CYC is reset to 0, the number of cycles it takes per instruction is
2.
[3] = <ONE-CYC> enable bit for one cycle per instruction option.
0
Disable one cycle option. If TURBO-EN is set to 1, the number of cycles it takes per
instruction is 2. If TURBO-EN is reset to 0, the number of cycles it takes per instruction is
4. (default)
1
Enable one cycle option. TURBO-EN should be set to 1 when users want to use
One-cycle option.
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27
CR81P200
TM
[4]= <PSEX_EN> enable bit for solving prescaler exchange issue between watchdog timer
and Timer.
0
Disable just for compatibility with Mask version.
1
Enable (default)
[5]= <PWSV_EN> enable bit for power-saving mode
0
Disable power-saving mode during instruction execution. This bit should be reset
to 0 if the application belongs to the higher frequency ones. (default)
1
Enable power-saving mode for lower frequency application caring about power
consumption.
[6] = < IOWM > I/O port Write Mode for read-then-write instructions.
“0” for reading the latches → operation → write (default)
“1” for reading the interface → operation → write
[7] = < RAMB > RAM Bank enable bit.
“0” for disabling RAM bank function
“1” for enabling RAM bank function (default)
20) 04H [7:0]
<HGR> Hidden general purpose register.
21) 05H [7:0]
< CPA > Port A Control register {RW}
Description:
A ‘0’ in this register will set the corresponding pin of port A to an output. In the conditions
of power-on and reset, all default “1” is input. If the program enables the comparator function,
you must set the corresponding Port A pins to an input.
22) 06H [5:0]
< CPB > Port B Control register {RW}
Description:
A ‘0’ in this register will set the corresponding pin of port B to an output. In the conditions
of power-on and reset, all [5:0] default “1” is input. Bits 7-6 are not implemented and always
read as ‘0’. If the program enables the comparator function, you must set the corresponding
PB pins to an input.
23) 07H [7:0]
< CPC > Port C Control register {RW}
Description:
A ‘0’ in this register will set the corresponding pin of port C to an output. All default ‘1’ is
input.
FR18033B
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28
CR81P200
TM
7. Absolute maximum ratings:
Operating temperature ......................................................................………….. .-40 to 85℃
Storage temperature .................................................................………………. -65 to 150℃
Supply voltage ...............................................................................................…….. 7.5 V
Input voltage ...........................................................................…………… -0.6 to Vdd+0.6 V
Total power dissipation .........................................................................………….. 500 mW
Max. current out of VSS pin .................................................................…………. 100 mA
Max. current into VDD pin .....................................................................………….100 mA
Max. output current sourcing from a single port ............................................…… 50 mA
Max. output current sunk to a single port ..............................................………… 50 mA
8. Electrical characteristics (operating temperature at 25℃):
Sym
Description
Conditions
2.8
3.0
Typ.
3.2
Max.
Unit
Vdd
Operating voltage
Vref
Reference voltage of ADC
ViH
High level input voltage
PA , PB, PC
CNTI , /ERST
Vdd = 3 V
High level input voltage
PA , PB
CNTI , /ERST
Vdd = 5 V
Low level input voltage
PA , PB
CNTI , /ERST
Vdd = 3 V
Low level input voltage
PA , PB
CNTI , /ERST
Vdd = 5 V
VoH
High level output voltage
Vdd=3V, IoH = -8.66 mA
Vdd=5V, IoH = -23.7mA
2.0
3.0
V
V
VoL
Low level output voltage
Vdd=3V, IoL= 2.92 mA
Vdd=5V, IoL=8.6mA
0.5
1.0
V
V
IiL
Input low leakage current
PA,PB, CNTI
/ERST
Vdd=3V
ViL
Without using ADC
Using ADC
Min.
7.0
7.0
V
V
2.5
Vdd
V
1.6
2.0
Vdd
Vdd
V
V
2.2
3.5
Vdd
Vdd
V
V
Vss
Vss
0.7
0.7
V
V
Vss
Vss
1.1
1.1
V
V
-1
-6.5
FR18033B
µA
µA
2004/11/Ver. 0.0.02/All rights reserved.
29
CR81P200
TM
Sym
Description
Input low leakage current
PA,PB, CNTI
/ERST
IiH
Conditions
Min.
Typ.
Max.
Unit
Vdd=5V
-1
-18
µA
µA
Input high leakage current Vdd=3V
PA,PB, CNTI
/ERST
+1
+1
µA
µA
Input low leakage current
PA,PB, CNTI
/ERST
+1
+1
µA
µA
2.5
4.0
V
V
Vdd=5V
LVD Low voltage detect voltage Lower level
Higher level
1.9
3.4
Tost
Basic time-out period
for watchdog timer
Vdd=3.0V
Vdd=5.0V
26
22.6
mS
mS
Idds
Sleep current
(WDT disable)
Vdd=3.0 V
LVD disable
LVD enable low
LVD enable high
1
8
--
3
15
--
µA
µA
µA
Vdd = 5.0 V
LVD disable
LVD enable low
LVD enable high
1
35
35
5
60
60
µA
µA
µA
All input pins level =Vdd or
Vss
No loading current for all
output ports
FR18033B
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30
CR81P200
TM
Sym
Idds
Description
Sleep current
(WDT enable)
Conditions
Min.
Typ.
Max.
Unit
Vdd=3.0 V
LVD disable
LVD enable low
LVD enable high
5
13
--
10
30
--
µA
µA
µA
Vdd=5.0 V
LVD disable
LVD enable low
LVD enable high
15
50
45
25
90
90
µA
µA
µA
All input pins level =Vdd or
Vss
No loading current for all
output ports
Idd
Operating Current
LVD disable , WDT enable
4 cycle mode
Vdd=3.0V, XT mode, 4MHz
Vdd=5.0V, XT mode, 4MHz
2 cycle mode
Vdd = 3.0 V, XT mode , 4
MHz
Vdd = 5.0 V, XT mode, 4 MHz
1 cycle mode
Vdd = 3.0 V, XT mode , 4
MHz
Vdd = 5.0 V, XT mode, 4 MHz
No loading current for all
output ports
The current will vary if a load
is changed.
FR18033B
0.5
1.2
mA
mA
0.8
mA
1.8
mA
1.2
mA
3.2
mA
2004/11/Ver. 0.0.02/All rights reserved.
31
CR81P200
TM
Sym
Description
Conditions
FMX Maximum
operation 5V
frequency of 4/2/1 cycle
3V
PSF
Min.
Typ.
4 cycle
2 cycle
1 cycle
4 cycle
2 cycle
1 cycle
Power-saving mode ON LF mode Crystal =32768
/OFF current consuming 4-cycle
factor
No I/O loading
FR18033B
Max.
48
27
16
27
20
8
50
Unit
MHz
%
2004/11/Ver. 0.0.02/All rights reserved.
32
CR81P200
TM
8.1. RC frequency curve
4 Cycle RC Oscillator ( Vdd = 3V )
12.00
10.00
Fosc (MHz)
8.00
5pf
10pf
6.00
15pf
20pf
4.00
2.00
0.00
1.8k 2.0k 2.2k 2.4k 2.7k 3.0k 3.3k 4.3k 4.7k 5.1k 6.2k 7.5k 8.2k 9.1k 10k 12k 15k 18k 20k 24k 30k
Resistor (Ω)
4 Cycle RC Oscillator ( Vdd = 5V )
16.00
14.00
12.00
Fosc (MHz)
10.00
5pf
10pf
8.00
15pf
20pf
6.00
4.00
2.00
0.00
1.8k 2.0k 2.2k 2.4k 2.7k 3.0k 3.3k 4.3k 4.7k 5.1k 6.2k 7.5k 8.2k 9.1k 10k 12k 15k 18k 20k 24k 30k
Resistor (Ω)
FR18033B
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33
CR81P200
TM
8.2. ADC curve
Vdd=3V Vref=Vdd
CR81P200 3V ADC
300
250
#3V ADC
Digital Value ( Decimal )
#01 ADC
200
#02 ADC
#03 ADC
#04 ADC
150
#05 ADC
#06 ADC
#07 ADC
100
#08 ADC
#09 ADC
#10 ADC
50
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
Vin
Vdd=5V Vref=Vdd
CR81P200 5V ADC
300
250
#5V ADC
Digital Value ( Decimal )
#01 ADC
200
#02 ADC
#03 ADC
#04 ADC
150
#05 ADC
#06 ADC
#07 ADC
100
#08 ADC
#09 ADC
#10 ADC
50
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Vin
FR18033B
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CR81P200
TM
9. Instruction Set
Binary Code
Syntax
Description
Operation
Status Affected
000 000 00000000
NOP
No Operation
None
None
000 000 00000010
SLEEP
Sleep mode
SP=0
000 000 00000011
CLRWT
Clear watchdog timer
Stop OSC
0→WT
SP=1
000 000 00000100
RETI
Return from interrupt
Stack→PC
IF=1
000 000 00000101
RET
Return from
subroutine
Stack→PC
None
000 000 00000110
CLRIF
Clear interrupt flag
None
IF=1
000 000 00000111
STDBY
Stand-by mode
SP=0
000 000 00001000
CLRA
Clear Acc.
Stop Clock
0 → A
000 000 00001001
|
000 000 01111111
None
None
None
None
000 000 1 rrrrrrr
STAR r
Store Acc. in Reg..
A → r
None
000 001 0xxxdrrr
CTRLR r,d
Store Acc in Reg. or
store Reg. in Acc..
r = WTC(00h),
TCC(01h)
IPA(02h)
OPT(03h)
CMP(04h)
CPA(05h)
CPB(06h)
CPC(07h)
d=0r → A
d=1A → r
CTRLR r,d
000 001 1 rrrrrrr
CLRR r
Clear Reg.
0 → r
Z
Z
000 010 d rrrrrrr
IORAR r,d Incl. OR Acc. and
Reg.
rˇA → d
Z
000 011 d rrrrrrr
XORAR r,d Excl. OR Acc. and
Reg.
r♁A → d
Z
000 100 d rrrrrrr
ANDAR r,d
AND Acc. and Reg.
r&A → d
Z
000 101 d rrrrrrr
ADDAR r,d
Add Acc. and Reg.
A+ r → d
C,AC,Z
000 110 d rrrrrrr
SUBAR r,d Subtract Acc. from
Reg.
r–A → d
C,AC,Z
Z
000 111 d rrrrrrr
LDR r,d
Load Reg. into Acc.
r → d
001 0bb b rrrrrrr
BCR r,b
Clear bit of Reg.
0 → r[b]
FR18033B
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35
CR81P200
TM
001 1bb b rrrrrrr
BTRSC r,b
Test bit of Reg., skip
if cleared
Skip if r[b]=0
010 000 d rrrrrrr
COMR r,d
Complement Reg.
/R → d
Z
010 001 d rrrrrrr
DECR r,d
Decrement Reg.
r-1 → d
Z
010 010 d rrrrrrr
DRSZ r,d
Decrement Reg., skip
if zero
r-1 → d
None
010 011 d rrrrrrr
INCR r,d
Increment Reg.
r+1→ d
Z
010 100 d rrrrrrr
IRSZ r,d
Increment Reg., skip
if zero
r+1 → d
None
010 101 d rrrrrrr
SWAPR r,d
Swap halves Reg.
r[0:3] <—> r[4:7]
→ d
None
010 110 d rrrrrrr
RLR r,d
Rotate Reg. left
r[n] → r[n+1] C
→ r[0]
r[7] → C
C
010 111 d rrrrrrr
RRR r,d
Rotate reg. right
r[n] → r[n-1] C
→ r[7]
r[0] → C
C
011 0bb b rrrrrrr
BSR r,b
Set bit of Reg.
1 → r[b]
None
011 1bb b rrrrrrr
BTRSS r,b
Test bit of Reg., skip
if set
Skip if r[b]=1
None
100 i i i i i i i i i i i
JUMP i
Jump to address
n → PC
None
101 i i i i i i i i i I i
CALL i
Call subroutine
n → PC
PC+1→ stack
None
110 000 d rrrrrrr
ADCAR r,d Add Acc, Reg., and
carry
A+r+C → d
C,AC,Z
110 001 d rrrrrrr
SBCAR r,d
Subtract Acc from
Reg. with borrow
r-A-/C → A
C,AC,Z
110 010 d rrrrrrr
SRR r,d
Shift Reg. right
r[n] → r[n-1]
r[0] → C
0 → r[7]
C
110 011 d rrrrrrr
SLR r,d
Shift Reg. left
r[n] → r[n+1]
r[7] → C
0 → r[0]
C
110 100 d rrrrrrr
DAR r,d
Decimal Adjustment
if r[3:0]>9 or
AC=1, then
r[7:0]+6→d[7:0]
C,AC
FR18033B
2004/11/Ver. 0.0.02/All rights reserved.
36
CR81P200
TM
if r[7:4]>9 or
C=1, then
r[7:4]+6→d[7:4]
110 101 0 rrrrrrr
XCHAR r
Exchange Reg. and
Acc
r <—> A
None
110 101 1 rrrrrrr
CMPAR r
Compare Acc with
Reg.
r-A
C,Z
110 110 bbbrrrrr
BCTR r,b
Carry flag written
into Bit [b] of Reg.
C → r[b]
None
110 111 bbbrrrrr
BRTC r,b
Bit[b] of Reg. written
into carry flag
r[b] → C
C
111 000 i i i i i i i i
LDIA i
Load immediate into
Acc.
i → A
None
111 001 i i i i i i i i
CMPIA i
Compare immediate
with Acc
i-A
C,Z
111 010 i i i i i i i i
IORIA i
Incl. OR Acc and
immediate
iˇA→ A
Z
111 011 i i i i i i i i
XORIA i
Excl. OR Acc and
immediate
i♁A → A
Z
111 100 i i i i i i i i
RTIA i
Return and place
immediate into Acc
Stack → PC
i → Acc
None
111 101 i i i i i i i i
ADCIA i
Add Acc and
immediate and carry
A+i+C → A
C,AC,Z
111 110 i i i i i i i i
SBCIA i
Subtract Acc from
immediate with borrow
i-A-/C → A
C,AC,Z
111 111 i i i i i i i i
ANDIA i
AND Acc and
immediate
i & A→ A
Z
Notes to syntax:
ACC: Accumulator
A: Accumulator
Reg.: General register
WT: watchdog timer
X: Don’t care
SP: Sleep flag
Incl.: Inclusive
Excl.: Exclusive
r: General register address
d: Destination
1: General register
0: Accumulator
b: Bit position
i: Immediate data; 8 bits
C: Carry flag
AC: Auxiliary
FR18033B
2004/11/Ver. 0.0.02/All rights reserved.
37
CR81P200
TM
Z: Zero flag
/: Complement
IF: Interrupt flag
9. Special Register Condition
Registers
Power-on Reset
External or
Watchdog reset
Watchdog
interrupt
Timer/Counter
or Port Interrupt
01H ( TCR )
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
02H ( PCL )
1111 1111
1111 1111
1111 1110
By starting address
03H ( SFR )
0001 1xxx
000? ?uuu
uuu0 ?uuu
uuuu ?uuu
04H ( MIR )
xxxx xxxx
1uuu uuuu
1uuu uuuu
1uuu uuuu
05H ( RPA )
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
06H ( RPB )
-- xx xxxx
-- uu uuuu
-- uu uuuu
-- uu uuuu
07H
(RPC)
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
69H
(P2D)
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
6AH
(P3D)
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
6BH
(PWC)
---- 0000
---- 0000
---- uuuu
---- uuuu
6CH
(ADF)
00-- ----
00-- ----
uu-- ----
uu-- ----
6DH
(ADD)
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
6EH
(ADH)
--00 0000
--00 0000
--uu uuuu
--uu uuuu
6FH (ADC)
000- -111
000- -111
uuu- -uuu
uuu- -uuu
00H
( WTC )
*011 1111
*u11 1111
*uuu uuuu
*uuu uuuu
01H
( TCC )
0101 0111
0101 0111
uuuu uuuu
uuuu uuuu
02H
( IPA )
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
03H
( OPT )
1001 0001
1001 0001
uuuu uuuu
uuuu uuuu
04H
( HGR)
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
05H
( CPA )
1111 1111
1111 1111
uuuu uuuu
uuuu uuuu
06H
( CPB )
-- 11 1111
-- 11 1111
--uu uuuu
--uu uuuu
07H
( CPC )
1111 1111
1111 1111
uuuu uuuu
uuuu uuuu
Note:
x: unknown
u: unchanged
-: unimplemented, read as ‘0’
*: state of CNTI pin
?: states of /WT and /SP, illustrated in the form of a table below
FR18033B
2004/11/Ver. 0.0.02/All rights reserved.
38
CR81P200
TM
/WT /SP
DESCRIPTION
0
0 Watchdog timer timeout reset or interrupt during SLEEP、STDBY
0
1 Watchdog timer timeout reset or interrupt not during SLEEP、STDBY
1
0 External reset､Port A､ADC､Timer/Counter interrupt during SLEEP、STDBY
1
1 Power-on reset
u
u External reset､Port A ､ADC､Timer/Counter interrupt not during SLEEP、STDBY
Annex 1
Interrupt function:
Timer/counter interrupt: Timer/counter reaching 255 will generate an interrupt and
go directly to the address 7FD/h and can jump to the Timer Interrupt Service Routine
(e.g. by JUMP instruction…).
If the interrupt happened during the ISR (Interrupt Service Routine) of other
interrupt (Port A interrupt or watchdog timer time-out interrupt), this interrupt will be
held and then execute its own ISR after the end of the previous ISR generated by
other source.
Port A interrupt: A low pulse (at least one instruction cycle long) applied to the
corresponding pin (which is in an input mode) will generate an interrupt and go
directly to the address 7FC/h and can jump to the Port A Interrupt Service Routine. If
the interrupt happened during the ISR of other interrupt (timer/counter interrupt or
watchdog timer time-out interrupt), this interrupt will be held and then execute its
own ISR after the end of the previous ISR generated by other source.
Watchdog timer time-out interrupt: Watchdog timer time-out will generate an
interrupt and go directly to the address 7FE/h (in the case of <WTC> Watchdog
timer Control register bit 6=”1”) and can jump to the WDT Interrupt Service Routine.
This interrupt has the highest priority and can execute its ISR immediately, whether
or not having happened during another ISR (generated by timer/counter or Port A). If
both timer/counter interrupt and port A interrupt happened during the execution
period of watchdog timer time-out ISR, timer/counter ISR will be executed first after
the return of watchdog timer time-out ISR.
FR18033B
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39
CR81P200
TM
The interrupt structure is two-level deep. But only watchdog timer time-out could
be the most recently generated interrupt.
In interrupt service routine, the programmer has to save the accumulator and status
registers first and restore the accumulator and status registers before exit. The
following instructions are recommended.
In the beginning of ISR:
STAR
SAVE_A
LDR
03H,A
STAR
SAVE_S
z
Before exit from ISR:
LDR
SAVE_S,A
STAR
03H,R
XCHAR SAVE_A
RETI
The priority of ADC interrupt is the same as that of Port A interrupt.
Watchdog timer:
The basic time-out period of watchdog timer is Twdt (about 22 ms). By setting the
post-scaler rate, a 2.8 seconds time-out period can be present. The CLRWT, SLEEP, or
STDBY instruction will reset the watchdog timer and the post-scaler.
To clear interrupt flag:
Normally, the interrupt routine must be returned by RETI. If returning to the original
address is not wanted, then CLRIF must be executed once. Otherwise, a next interrupt will not
be allowed. The CLRIF instruction only clear the implicit interrupt enable flag and all the
other register will not be affected.
Instruction cycle:
One instruction cycle consists of 1/2/4 ( firmware control ) oscillator periods. All
instructions are executed within one instruction cycle except that a condition test is true or the
program counter is changed into a result of an instruction. In this case, the instruction takes
two instruction cycles.
Start-up Vector:
FR18033B
2004/11/Ver. 0.0.02/All rights reserved.
40
CR81P200
TM
After a power-on or reset condition is applied, the program counter will first go to the
start-up vector “ 7FF/h“ to execute the instruction at said address.
Configuration byte (EPROM options):
Bit
1-0 for Watchdog timer control
=x0 for watchdog timer disabled all the time
=01 for watchdog timer disabled during sleep or stand-by mode
=11 for watchdog timer enabled all the time
3-2 for oscillator type
=00 for RC oscillator
=01 for LFXT oscillator
=10 for XTAL oscillator
=11 for HFXT oscillator
5-4 for Oscillator start-up time select
=00 for Twdt/128 (about 172µs)
=01 for Twdt x 1 (about 22ms)
=10 for Twdt x 2 (about 44ms)
=11 for Twdt x 4 (about 88ms)
This start-up time is generated by an internal RC oscillator and will vary from chip to chip.
The operating voltage and temperature also will affect it. The above values are measured at
Vdd=5V.
Annex 2
Package type avaliable
Device number
Package type
Pin count
FR18033B
Package size
2004/11/Ver. 0.0.02/All rights reserved.
41
CR81P200
TM
Annex 3
宜特科技股份有限公司
Integrated Service Technology Inc.
No.:A8799
TEL : (03) 578-2266
RA No: 9301377-E
FAX : (03) 578-2299
Date : 05/24/2004
Email: [email protected]
Test Site Address: 1F, No.22, Pu-Ding Rd., Hsin-Chu, Taiwan, R.O.C.
可靠度測試報告
RELIABILITY TEST REPORT
Applicant/Department: Syntek Semiconductor Co., Ltd.
Address
: 3F,NO.24-2,INDUSTRY E.RD.,IV, Science-Based Industrial
Park,Hsin-Chu,Taiwan,R.O.C.
Product
: KS5854AG(CR81P200)
Testing Item
: ESD-HBM
Package/Pin Count: P-DIP / 28
Application Date
: 05/24/2004
Date Finished
Test Method
: MIL-STD-883E Method 3015.7
Failure Criteria
: FOR V CHANGE AT 1µA ±30%
Test Voltage
: 500V ~ 4000V (±), Step：500V (±)
: 05/24/2004
Testing Item
Random ESD-HBM Test…………………………………………………………………………………P2
Remark:
●This report refers only to the specimen submitted to testing, and be invalid as separately
used.
Testing Engineer:
Report Review:
Laboratory Head:
FR18033B
2004/11/Ver. 0.0.02/All rights reserved.
42
CR81P200
TM
宜特科技股份有限公司
Integrated Service Technology Inc.
No.:A8799
TEL : (03) 578-2266
RA No: 9301377-E
FAX : (03) 578-2299
Date : 05/24/2004
Email: [email protected]
Test Site Address: 1F, No.22, Pu-Ding Rd., Hsin-Chu, Taiwan, R.O.C.
ESD-HBM Testing Report
Test Equipment:
KEYTEK ZAPMASTER
Environmental Condition of Laboratory:
Temperature: 25ºC±5ºC
Humidity: 55%±10% RH
Test Condition:
VSS (+)
VSS (-)
VCC (+)
VCC (-)
VCC-VSS (+)
VCC-VSS (-)
Test Result:
MODEL: HBM
PIN
COMBINATION
ESD SENSITIVITY PASS : ±4000 V
SAMPLE
PASSED VOLTS
SIZE
VSS (+)
3
+4000 V
VSS (-)
3
-4000 V
VCC (+)
3
+4000 V
VCC (-)
3
-4000 V
VCC-VSS (+)
3
+4000 V
FR18033B
V CLASS:
3
NOTE:
FOR MIL-STD
CLASS1: 0V-1999V
CLASS2: 2000V-3999V
CLASS3: 4000V-TO ABOVE
2004/11/Ver. 0.0.02/All rights reserved.
43
CR81P200
TM
VCC-VSS (-)
3
-4000 V
I/O:3,5-25
I/P:1,27-28
O/P:26
VCC:2
VSS:4
VSS (+)
(UNIT: V)
Test
FAIL
Pin VOLTAGE
#1
#2
#3
1
PASS
PASS
PASS
3
PASS
PASS
PASS
5
PASS
PASS
PASS
6
PASS
PASS
PASS
7
PASS
PASS
PASS
8
PASS
PASS
PASS
9
PASS
PASS
PASS
10
PASS
PASS
PASS
11
PASS
PASS
PASS
12
PASS
PASS
PASS
13
PASS
PASS
PASS
14
PASS
PASS
PASS
15
PASS
PASS
PASS
16
PASS
PASS
PASS
17
PASS
PASS
PASS
18
PASS
PASS
PASS
19
PASS
PASS
PASS
20
PASS
PASS
PASS
21
PASS
PASS
PASS
22
PASS
PASS
PASS
23
PASS
PASS
PASS
24
PASS
PASS
PASS
25
PASS
PASS
PASS
26
PASS
PASS
PASS
27
PASS
PASS
PASS
28
PASS
PASS
PASS
FR18033B
2004/11/Ver. 0.0.02/All rights reserved.
44
CR81P200
TM
VSS (-)
(UNIT: V)
Test
FAIL
Pin VOLTAGE
#1
#2
#3
1
PASS
PASS
PASS
3
PASS
PASS
PASS
5
PASS
PASS
PASS
6
PASS
PASS
PASS
7
PASS
PASS
PASS
8
PASS
PASS
PASS
9
PASS
PASS
PASS
10
PASS
PASS
PASS
11
PASS
PASS
PASS
12
PASS
PASS
PASS
13
PASS
PASS
PASS
14
PASS
PASS
PASS
15
PASS
PASS
PASS
16
PASS
PASS
PASS
17
PASS
PASS
PASS
18
PASS
PASS
PASS
19
PASS
PASS
PASS
20
PASS
PASS
PASS
21
PASS
PASS
PASS
22
PASS
PASS
PASS
23
PASS
PASS
PASS
24
PASS
PASS
PASS
25
PASS
PASS
PASS
26
PASS
PASS
PASS
27
PASS
PASS
PASS
28
PASS
PASS
PASS
FR18033B
2004/11/Ver. 0.0.02/All rights reserved.
45
CR81P200
TM
VCC (+)
(UNIT: V)
Test
FAIL
Pin VOLTAGE
#1
#2
#3
1
PASS
PASS
PASS
3
PASS
PASS
PASS
5
PASS
PASS
PASS
6
PASS
PASS
PASS
7
PASS
PASS
PASS
8
PASS
PASS
PASS
9
PASS
PASS
PASS
10
PASS
PASS
PASS
11
PASS
PASS
PASS
12
PASS
PASS
PASS
13
PASS
PASS
PASS
14
PASS
PASS
PASS
15
PASS
PASS
PASS
16
PASS
PASS
PASS
17
PASS
PASS
PASS
18
PASS
PASS
PASS
19
PASS
PASS
PASS
20
PASS
PASS
PASS
21
PASS
PASS
PASS
22
PASS
PASS
PASS
23
PASS
PASS
PASS
24
PASS
PASS
PASS
25
PASS
PASS
PASS
26
PASS
PASS
PASS
27
PASS
PASS
PASS
28
PASS
PASS
PASS
FR18033B
2004/11/Ver. 0.0.02/All rights reserved.
46
CR81P200
TM
VCC (-)
(UNIT: V)
Test
FAIL
Pin VOLTAGE
#1
#2
#3
1
PASS
PASS
PASS
3
PASS
PASS
PASS
5
PASS
PASS
PASS
6
PASS
PASS
PASS
7
PASS
PASS
PASS
8
PASS
PASS
PASS
9
PASS
PASS
PASS
10
PASS
PASS
PASS
11
PASS
PASS
PASS
12
PASS
PASS
PASS
13
PASS
PASS
PASS
14
PASS
PASS
PASS
15
PASS
PASS
PASS
16
PASS
PASS
PASS
17
PASS
PASS
PASS
18
PASS
PASS
PASS
19
PASS
PASS
PASS
20
PASS
PASS
PASS
21
PASS
PASS
PASS
22
PASS
PASS
PASS
23
PASS
PASS
PASS
24
PASS
PASS
PASS
25
PASS
PASS
PASS
26
PASS
PASS
PASS
27
PASS
PASS
PASS
28
PASS
PASS
PASS
FR18033B
2004/11/Ver. 0.0.02/All rights reserved.
47
CR81P200
TM
VCC-VSS (+)
(UNIT: V)
Test
FAIL
Pin VOLTAGE
#1
#2
#3
2
PASS
PASS
PASS
VCC-VSS (-)
(UNIT: V)
Test
FAIL
Pin VOLTAGE
#1
#2
#3
2
PASS
PASS
PASS
宜特科技股份有限公司
Integrated Service Technology Inc.
TEL : (03) 578-2266
RA No: 9301377-E
FAX : (03) 578-2299
Date : 05/24/2004
Email: [email protected]
Test Site Address: 1F, No.22, Pu-Ding Rd., Hsin-Chu, Taiwan, R.O.C.
可靠度測試報告
RELIABILITY TEST REPORT
Applicant/Department: Syntek Semiconductor Co., Ltd.
Address
: 3F,NO.24-2,INDUSTRY E.RD.,IV, Science-Based Industrial
Park,Hsin-Chu,Taiwan,R.O.C.
Product
: KS5854AG(CR81P200)
Testing Item
: LATCH-UP
Package/Pin Count: P-DIP / 28
Application Date
: 05/24/2004
Date Finished
Test Condition
: JEDEC STANDARD NO.78 MARCH 1997
Failure Criteria
Trigger Current
: 05/24/2004
< 25mA 10mA + I normal
> 25mA 1.4 x I normal
: 25mA ~ 200mA (±), Step: 25mA (±)
Vsupply OVERVOLTAGE TEST : 5V(+)~8V(+) , Step : 1V(+)
FR18033B
2004/11/Ver. 0.0.02/All rights reserved.
48
CR81P200
TM
Testing Item
Random LATCH-UP Test…………………………………………………………………………………P2
Remark:
●Ground pins are not latch-up tested.
●The positive or negative current pulse (I-Test) or voltage pulse (Vsupply overvoltage test)
applied to any pin under test in an attempt to induce latch-up.
●This report refers only to the specimen submitted to testing, and be invalid as separately used.
Testing Engineer:
Report Review:
Laboratory Head:
宜特科技股份有限公司
Integrated Service Technology Inc.
TEL : (03) 578-2266
RA No: 9301377-E
FAX : (03) 578-2299
Date : 05/24/2004
Email: [email protected]
Test Site Address: 1F, No.22, Pu-Ding Rd., Hsin-Chu, Taiwan, R.O.C.
LATCH-UP Testing Report
Test Equipment:
KEYTEK ZAPMASTER
Environmental Condition of Laboratory:
Temperature: 25ºC±5ºC
Humidity: 55%±10% RH
Test Condition:
POSITIVE I
NEGATIVE I
FR18033B
2004/11/Ver. 0.0.02/All rights reserved.
49
CR81P200
TM
Vsupply OVERVOLTAGE TEST
Test Result:
TRIGGER
MODEL
TEST
PIN
SAMPLE
SIZE
TRIGGER SOURCE
INDUCE LATCH-UP
I/O
+IT
-IT
I/P
3
PASS
CLASS1:
+IT:0mA~39mA
-IT:0mA~ -39mA
CLASS2:
+IT: 40mA~+99mA
-IT: -40mA~-99mA
CLASS3:
+IT:>100mA
-IT:<-100mA
I/O
PASS
PASS
O/P
Vsupply
OVER
VOLTAGE
TEST
NOTE:
PASS
3
VCC
PASS
3
3
PASS
O/P
I/P
IT CLASS:
PASS
I/O:3,5-25
I/P:1,27-28
O/P:26
VCC:2
VSS:4
POSITIVE I
Test TRIGGER
Pin CURRENT
1
3
5
6
7
8
9
10
11
12
13
14
15
#1
#2
Test TRIGGER
pin CURRENT
16
17
18
19
20
21
22
23
24
25
26
27
28
#3
PASS PASS PASS
PASS PASS PASS
PASS PASS PASS
PASS PASS PASS
PASS PASS PASS
PASS PASS PASS
PASS PASS PASS
PASS PASS PASS
PASS PASS PASS
PASS PASS PASS
PASS PASS PASS
PASS PASS PASS
PASS PASS PASS
NEGATIVE I
FR18033B
(UNIT: mA)
#1
#2
#3
PASS PASS PASS
PASS PASS PASS
PASS PASS PASS
PASS PASS PASS
PASS PASS PASS
PASS PASS PASS
PASS PASS PASS
PASS PASS PASS
PASS PASS PASS
PASS PASS PASS
PASS PASS PASS
PASS PASS PASS
PASS PASS PASS
(UNIT: mA)
2004/11/Ver. 0.0.02/All rights reserved.
50
CR81P200
TM
Test TRIGGER
Pin CURRENT
1
3
5
6
7
8
9
10
11
12
13
14
15
#1
#2
Test TRIGGER
pin CURRENT
16
17
18
19
20
21
22
23
24
25
26
27
28
#3
PASS PASS PASS
PASS PASS PASS
PASS PASS PASS
PASS PASS PASS
PASS PASS PASS
PASS PASS PASS
PASS PASS PASS
PASS PASS PASS
PASS PASS PASS
PASS PASS PASS
PASS PASS PASS
PASS PASS PASS
PASS PASS PASS
Vsupply OVERVOLTAGE TEST
Test
Pin
TRIGGER
VOLTAGE
2
#2
#1
PASS PASS PASS
PASS PASS PASS
PASS PASS PASS
PASS PASS PASS
PASS PASS PASS
PASS PASS PASS
PASS PASS PASS
PASS PASS PASS
PASS PASS PASS
PASS PASS PASS
PASS PASS PASS
PASS PASS PASS
PASS PASS PASS
(UNIT: V)
#1
#2
#3
PASS
PASS
PASS
FR18033B
#3
2004/11/Ver. 0.0.02/All rights reserved.
51
CR81P200
TM
EFT test report
FR18033B
2004/11/Ver. 0.0.02/All rights reserved.
52
CR81P200
TM
FR18033B
2004/11/Ver. 0.0.02/All rights reserved.
53
CR81P200
TM
FR18033B
2004/11/Ver. 0.0.02/All rights reserved.
54
CR81P200
TM
FR18033B
2004/11/Ver. 0.0.02/All rights reserved.
55
CR81P200
TM
FR18033B
2004/11/Ver. 0.0.02/All rights reserved.
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TM
FR18033B
2004/11/Ver. 0.0.02/All rights reserved.
57