EUA2101 10-W Stereo Class-D Audio Power Amplifier DESCRIPTION FEATURES The EUA2101 is a high efficiency, 2 channel bridged-tied load (BTL), class-D audio power amplifier. Operating from a 12V power supply, EUA2101 is capable of delivering 10W/ channel of continuous output power to a 8Ω load with 10% THD+N. The EUA2101 features a differential input architecture offering improved noise immunity over a single-ended (SE) input amplifier. Amplifier gain is internally configured and can be selected to 20, 26, 32 or 36dB utilizing the Go and G1 gain select pins. The EUA2101 also features short-circuit and thermal protection preventing the device from being damaged during a fault condition. The EUA2101 is available in thermally efficient 48-pin TQFP package. z z z z z z z z z z z Wide Supply Voltage: 8V to 15V Unique Modulation Scheme Reduces EMI Emission 10-W/ch into an 8-Ω Load From a 12-V Supply 15-W/ch into an 4-Ω Load From a 12-V Supply 90% Efficient Class-D Operation Eliminates Need for Heat Sinks Four Selectable, Gain Settings Differential Inputs Thermal and Short-Circuit Protection Clock Output for Synchronization With Multiple Class-D Devices 7mm × 7mm, 48-pin TQFP Package RoHS compliant and 100% lead(Pb)-free APPLICATIONS z Televisions Typical Application Circuit Figure1. DS2101 Ver 1.0 1 June 2008 深圳市速学王科技 0755-82924118 [email protected] www.mcu104.com EUA2101 Pin Configurations Package Type Pin Configurations (TOP VIEW) TQFP-48 Pin Description PIN TQFP-48 I/O SHUTDOWN 44 I RINN 2 I Negative audio input for right channel. Biased at VREG/2. RINP 3 I Positive audio input for right channel. Biased at VREG/2. LINN 6 I Negative audio input for left channel. Biased at VREG/2. LINP 5 I Positive audio input for left channel. Biased at VREG/2. GAIN0 8 I Gain select least significant bit. TTL logic levels with compliance to VREG. GAIN1 9 I Gain select most significant bit. TTL logic levels with compliance to VREG. MUTE 45 I FAULT 46 O BSLP 18 I/O Mute signal for quick disable/enable of outputs (HIGH = outputs high-Z, LOW = outputs enabled). TTL logic levels with compliance to AVCC. TTL compatible output. HIGH = short-circuit fault. LOW = no fault. Only reports short-circuit faults. Thermal faults are not reported on this terminal. Bootstrap I/O for left channel, positive high-side FET. PVCCL 26,27 LOUTP 19,20 O Power supply for left channel H-bridge, not internally connected to PVCCR or AVCC. Class-D 1/2-H-bridge positive output for left channel. PGNDL 28,29 LOUTN 21,22 O Class-D 1/2-H-bridge negative output for left channel. BSLN 23 I/O Bootstrap I/O for left channel, negative high-side FET. VCLAMPL 30 Internally generated voltage supply for left channel bootstrap capacitor. VCLAMPR 31 Internally generated voltage supply for right channel bootstrap capacitor. DS2101 Ver 1.0 DESCRIPTION Shutdown signal for IC (LOW = disabled, HIGH = operational). TTL logic levels with compliance to AVCC. Power ground for left channel H-bridge. 2 June 2008 深圳市速学王科技 0755-82924118 [email protected] www.mcu104.com EUA2101 Pin Description (Continued) PIN TQFP-48 I/O DESCRIPTION BSRN 38 I/O Bootstrap I/O for right channel, negative high-side FET. ROUTN 39,40 O Class-D 1/2-H-bridge negative output for right channel. PGNDR 32,33 ROUTP 41,42 PVCCR 34,35 BSRP 43 AGND 4,17 ROSC 14 I/O MSTR/ SLV 10 I SYNC 11 I/O VBYP 16 O VREG 15 O AVCC 48 NC 1,7,12, 13,24,25, 36,37,47 Power ground for right channel H-bridge. O Class-D 1/2-H-bridge positive output for right channel. Power supply for right channel H-bridge, not connected to PVCCL or AVCC. I/O Bootstrap I/O for right channel, positive high-side FET. Analog ground for digital/analog cells in core. I/O for current setting resistor of ramp generator. Master/Slave select for determining direction of SYNC terminal. HIGH=Master mode, SYNC terminal is an output; LOW = slave mode, SYNC terminal accepts a clock input. TTL logic levels with compliance to VREG. Clock input/output for synchronizing multiple class-D devices. Direction determined by MSTR/ SLV terminal. Input signal not to exceed VREG. Reference for preamplifier. Nominally equal to 1.39V. Also controls start-up time via external capacitor sizing. 4-V regulated output for use by internal cells, GAINx, MUTE, and MSTR/ SLV pins only. Not specified for driving other external circuitry. High-voltage analog power supply. Not internally connected to PVCCR or PVCCL. Not internally connected. Ordering Information Order Number Package Type Marking Operating Temperature Range EUA2101TIR1 TQFP-48 xxxxx EUA2101 -40 °C to 85°C EUA2101 □ □ □ □ Lead Free Code 1: Lead Free 0: Lead Packing R: Tape & Reel Operating temperature range I: Industry Standard Package Type T:TQFP DS2101 Ver 1.0 3 June 2008 深圳市速学王科技 0755-82924118 [email protected] www.mcu104.com EUA2101 Absolute Maximum Ratings ▓ ▓ ▓ ▓ ▓ ▓ ▓ ▓ ▓ Supply Voltage, AVCC,PVCC -------------------------------------------------------------------------- -0.3 V to 15V Input Voltage, SHUTDOWN ,MUTE--------------------------------------------------------- -0.3 V to VCC +0.3V Input Voltage,GAIN0,GAIN1,RINN,RINP,LINN,LINP, MSTR/ SLV ,SYNC------- -0.3 V to VREG +0.5V Continuous Total Power Dissipation-------------------------------------------------- See Dissipation Rating Table Free-air Temperature Range, TA ---------------------------------------------------------------------- -40°C to 85°C Junction Temperature Range, TJ --------------------------------------------------------------------- -40°C to 150°C Storage Temperature Rang, Tstg ------------------------------------------------------------------- -65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ----------------------------------------260°C Load Resistance, RLOAD ---------------------------------------------------------------------------------- 3.2Ω Minimum Recommended Operating Conditions Supply voltage, VCC PVCC,AVCC High-level input voltage, VIH Low-level input voltage, VIL SHUTDOWN ,MUTE,GAIN0,GAIN1, MSTR/ SLV ,SYNC SHUTDOWN ,MUTE,GAIN0,GAIN1, MSTR/ SLV ,SYNC Min Max Unit 8 15 V 2 V 0.8 SHUTDOWN ,VI=VCC,VCC=12V 125 MUTE,VI=VCC, VCC=12V 75 GAIN0,GAIN1, MSTR/ SLV ,SYNC,VI=VREG, VCC=12V 2 SHUTDOWN ,VI=0V,VCC=12V 2 1 High-level output voltage, VOH SYNC,MUTE,GAIN0,GAIN1,MSTR/ SLV ,VI=0V, VCC=12V FAULT, IOH=1mA Low-level output voltage, VOL FAULT, IOL= -1mA Oscillator frequency, fOSC ROSC Resistor=100 kΩ High-level input current, IIH Low-level input current, IIL Operating free-air temperature, TA V µA µA VREG-0.6 V AGND+0.4 V 200 300 kHz -40 85 °C DC Characteristics TA = 25°C ,VCC=12V, RL=8Ω (Unless otherwise noted) Symbol VOS PSRR DS2101 Parameter Conditions Min EUA2101 Unit Typ Max. Class-D output offset voltage (measured differentially) VI= 0 V, Gain = 36 dB Bypass reference for input amplifier VBYP, no load 1.30 1.40 1.50 V 4-V internal supply voltage VREG, no load, VCC= 10V to 15V 3.70 4 4.30 V DC Power supply rejection ratio VCC = 12 V to 15 V, inputs ac coupled to AGND, Gain = 32 dB Ver 1.0 mV -60 4 June 2008 深圳市速学王科技 5 0755-82924118 [email protected] www.mcu104.com dB EUA2101 DC Characteristics (Continued) Symbol ICC Parameter Conditions Quiescent supply current ICC(SD) Quiescent supply current in shutdown mode Min SHUTDOWN =2V, MUTE=0V, no load 30 40 mA SHUTDOWN =0.8V, no load 500 1000 µA 6 10 mA ICC(MUTE) Quiescent supply current in mute mode MUTE=2V, no load Drain-source on-state resistance rDS(on) VCC=12V, IO=500mA, TJ=25°C GAIN1=0.8V G EUA2101 Unit Typ Max. Gain GAIN1=2V High Side 300 Low Side 300 Total 600 800 mΩ GAIN0=0.8V 19 20 21 GAIN0=2V 25 26 27 GAIN0=0.8V 31 32 33 GAIN0=2V 35 36 37 dB dB tON Turn-on time C(VBYP)=1µF, SHUTDOWN =2V 10 ms tOFF Turn-off time C(VBYP)=1µF, SHUTDOWN =0.8V 20 ms AC Characteristics TA = 25°C ,VCC=12V, RL=8Ω (Unless otherwise noted) Symbol KSVR PO Parameter Conditions 200mVPP ripple from 20 Hz-1 kHz, Gain= 20dB, Inputs ac-coupled to AGND Supply ripple rejection Continuous output power THD+N Total harmonic distortion +noise Vn SNR DS2101 Min EUA2101 Unit Typ Max. -53 THD+N=7%, f=1kHz 9.20 THD+N=10%, f=1kHz 9.80 THD+N=7%, f=1kHz, RL=4Ω 15.70 THD+N=10%, f=1kHz,RL=4Ω (thermally limited) 16.60 RL=8Ω, f=1 kHz, PO=5W (half-power) 0.2% RL=4Ω, f=1 kHz, PO=8W (half-power) 0.096% dB W Output integrated noise 20Hz to 22kHz, A-weighted filter, Gain=20dB 200 µV -74 dBV Crosstalk PO=1 W, Gain=20dB, f=1 kHz Maximum output at THD+N< 1%, f=1kHz,Gain=20dB, A-weighted -90 dB 90 dB Thermal trip point 150 ℃ Thermal hysteresis 40 ℃ Signal-to-noise ratio Ver 1.0 5 June 2008 深圳市速学王科技 0755-82924118 [email protected] www.mcu104.com EUA2101 Block Diagram Figure2. DS2101 Ver 1.0 6 June 2008 深圳市速学王科技 0755-82924118 [email protected] www.mcu104.com EUA2101 Typical Characteristics Figure3. DS2101 Ver 1.0 Figure4. Figure5. Figure6 Figure7. Figure8. 7 June 2008 深圳市速学王科技 0755-82924118 [email protected] www.mcu104.com EUA2101 Figure9. DS2101 Ver 1.0 Figure10. Figure11. Figure12. Figure13. Figure14. 8 June 2008 深圳市速学王科技 0755-82924118 [email protected] www.mcu104.com EUA2101 DS2101 Ver 1.0 Figure15. Figure16. Figure17. Figure18. Figure19. Figure20. 9 June 2008 深圳市速学王科技 0755-82924118 [email protected] www.mcu104.com EUA2101 Figure21. Figure22. Figure23. DS2101 Ver 1.0 10 June 2008 深圳市速学王科技 0755-82924118 [email protected] www.mcu104.com EUA2101 Application Information Differential Input The differential input stage of the amplifier cancels any common-mode noise that appears on both input lines of the audio channel. To use the EUA2101 with a differential source, connect the positive signal of the audio source to the INP pin and the negative signal from the audio source to the INN pin (Figure 24). Figure 24. Differential Input (EUA2101 should be tested/worked with 4Ω or 8Ω load for guaranteeing 8~15V VCC operation) DS2101 Ver 1.0 11 June 2008 深圳市速学王科技 0755-82924118 [email protected] www.mcu104.com EUA2101 Application Information (continued) Single-Ended Input When using an audio source with a single-ended “out”, it is important to connect the RINN and LINN pins to the GND of the audio source with coupling capacitors. (Figure 25). Figure 25. Single Ended Input (EUA2101 should be tested/worked with 4Ω or 8Ω load for guaranteeing 8~15V VCC operation) DS2101 Ver 1.0 12 June 2008 深圳市速学王科技 0755-82924118 [email protected] www.mcu104.com EUA2101 Gain Selection The gain of the EUA2101 is set by two input terminals, GAIN0 and GAIN1. The gains listed in Table 1 are realized by changing the taps on the input resistors and feedback resistors inside the amplifier. This causes the input impedance (ZI) to be dependent on the gain setting. The actual gain settings are controlled by ratios of resistors, so the gain variation from part-to-part is small. However, the input impedance from part-to-part at the same gain may shift by ±20% due to shifts in the actual resistance of the input resistors. For design purposes, the input network should be designed assuming an input impedance of 40 kΩ, which is the absolute minimum input impedance of the EUA2101. At the lower gain settings, the input impedance could increase as high as 120 kΩ. Table.1 Gain Setting GAIN1 GAIN0 0 0 1 1 0 1 0 1 AMPLIFIER INPUT GAIN (dB) IMPEDANCE (kΩ) TYP TYP 20 100 26 50 32 50 36 50 The EUA2101 features an internal 4V regulator output (VREG), is the output of an internally, used for the oscillator, preamplifier, and gain control circuitry. It requires a 10nF capacitor, placed close to the pin, to keep the regulator stable. This regulated voltage can also be used to control GAIN0, GAIN1, MSTR/ SLV , and MUTE, but should not be used to drive external circuitry. Short-Circuit Protection and Automatic Recovery Feature The EUA2101 has short-circuit protection circuitry on the outputs that prevents damage to the device during output-to-output shorts, output-to-GND shorts, and output-to-VCC shorts. When a short circuit is detected on the outputs, the part immediately disables the output drive. The FAULT flag must be reset by cycling the voltage on the SHUTDOWN pin or MUTE pin. If the short was not removed, the protection circuitry again activates. MUTE Operation The MUTE pin only control the output state and does not shutdown the EUA2101. A logic high on this terminal disables the outputs. A logic low on this pin enables the outputs. This terminal may be used as a quick disable/enable of outputs when changing channels on a television or transitioning between different audio sources. Do not leave MUTE terminal floating. Ver 1.0 Thermal Protection Thermal protection on the EUA2101 prevents damage to the device when the internal die temperature exceeds 150oC. There is a 10oC tolerance on this trip point from device to device. Once the die temperature exceeds the thermal set point, the device enters into the shutdown state and the outputs are disabled. This is not a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 40oC. The device begins normal operation at this point with no external system interaction. 13 June 2008 深圳市速学王科技 synchronize the frequency of the class-D output switching. When MSTR/ SLV is high, the output switching frequency is determined by the selection of the resistor connected to the ROSC pin. The SYNC becomes an output in this mode, and the frequency of this output is also determined by the selection of the ROSC resistor. This TTL compatible, push-pull output can be connected to another EUA2101, configured in the slave mode. The output switching is synchronized to avoid any beat frequencies that could occur in the audio band when two class-D amplifiers in the same system are switching at slightly different frequencies. When MSTR/ SLV is low, the output switching frequency is determined by the incoming square wave on the SYNC input. The SYNC becomes an input in this mode and accepts a TTL compatible square wave from another EUA2101 configured in the master mode or from an external GPIO. If connecting to an external GPIO, recommended frequencies are 200kHz to 300kHz for proper device operation, and the maximum amplitude is 4V. Internal Regulated 4V Supply (VREG) SHUTDOWN Operation Connect SHUTDOWN to a logic high for normal operation. Pulling SHUTDOWN low causes the outputs to mute and the amplifier to enter a low-current state. Never leave SHUTDOWN unconnected, because amplifier operation would be unpredictable. For the best power-off pop performance, place the amplifier in the shutdown or mute mode prior to removing the power supply voltage. DS2101 MSTR/SLV and SYNC Operation The MSTR/ SLV and SYNC pins can be used to 0755-82924118 [email protected] www.mcu104.com EUA2101 Input Resistance Changing the gain setting can vary the input resistance of the amplifier from its smallest value, 50 kΩ ±20%, to the largest value, 100 kΩ ±20%. As a result, if a single capacitor is used in the input high-pass filter, the -3 dB or cutoff frequency may change when changing gain steps. Power Supply Decoupling, CS The EUA2101 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure that the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is achieved by using two capacitors of different types that target different types of noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low quivalent-series-resistance (ESR) ceramic capacitor, typically 0.1µF to 1µF placed as close as possible to the device VCC lead works best. For filtering lower frequency noise signals, a larger aluminum electrolytic capacitor of 220µF or greater placed near the audio power amplifier is recommended. The 220µF capacitor also serves as local storage capacitor for supplying current during large signal transients on the amplifier outputs. The PVCC terminals provide the power to the output transistors, so a 220µF or larger capacitor should be placed on each PVCC terminal. A 10µF capacitor on the AVCC terminal is adequate. BSN and BSP Capacitors The full H-bridge output stages use only NMOS transistors, that require bootstrap capacitors for the high side of each output to turn on correctly. A 220nF ceramic capacitor, rated for at least 25V, must be connected from each output to its corresponding bootstrap input. (See application circuit diagram in Figure 24,25.) The bootstrap capacitors connected between the BSxx pins and corresponding output function as a floating power supply for the high-side N-channel power MOSFET gate drive circuitry. During each high-side switching cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs turned on. The -3dB frequency can be calculated using Equation 1. Use the ZI values given in Table 1. f = 1 2 πZ C i i ---------------- (1) Input Capacitor, CI In the typical application, an input capacitor (CI) is required to allow the amplifier to bias the input signal to the proper dc level for optimum operation. In this case, CI and the input impedance of the amplifier (ZI) form a high-pass filter with the corner frequency determined in Equation 2. 1 f = c 2 πZ C i i -----------------(2) VCLAMP Capacitors The EUA2101 also features two regulators used for gate voltage clamping in order to ensure the maximum gate-to-source voltage for the NMOS output transistors is not exceeded. Two 1µF capacitors must be connected from VCLAMPL (pin 30) and VCLAMPR (pin 31) to ground and must be rated for at least 16V. The voltages at the VCLAMP terminals may vary with VCC and may not be used for powering any other circuitry. The value of CI is important, as it directly affects the bass (low-frequency) performance of the circuit. Consider the example where ZI is 50 kΩ and the specification calls for a flat bass response down to 20 Hz. Equation 2 is reconfigured as Equation 3. 1 C = i 2 πZ f i c -----------------(3) In this example, CI is 0.16µF; so, one would likely choose a value of 0.22µF as this value is commonly used. If the gain is known and is constant, use ZI from Table 1 to calculate CI. DS2101 Ver 1.0 14 June 2008 深圳市速学王科技 0755-82924118 [email protected] www.mcu104.com EUA2101 VBYP Capacitor The internal bias generator (VBYP) nominally provides a 1.25V internal bias for the preamplifier stages. The external input capacitors and this internal reference allow the inputs to be biased within the optimal common-mode range of the input preamplifiers. The selection of the capacitor value on the VBYP terminal is critical for achieving the best device performance. During power up or recovery from the shutdown state, the VBYP capacitor determines the rate at which the amplifier starts up. The charge rate of the capacitor is calculated using the standard charging formula for a capacitor, I = C x dV/dT. The charge current is nominally equal to 125µA and dV is equal to VBYP. For example, a 1µF capacitor on VBYP would take 10 ms to reach the value of VBYP and turn on outputs. The turn-on time will <30 ms for a 1µF capacitor on the VBYP terminal. A secondary function of the VBYP capacitor is to filter high-frequency noise on the internal 1.4V bias generator. A value of at least 1µF is recommended for the VBYP capacitor. For the best power-up and shutdown pop performance, the VBYP capacitor should be greater than or equal to the input capacitors. Output Filter Most applications require a ferrite bead filter. The ferrite filter reduces EMI around 1 MHz and higher (FCC and CE only test radiated emissions greater than 30 MHz). When selecting a ferrite bead, choose one with high impedance at high frequencies, but low impedance at low frequencies. Use an LC output filter if there are low frequency (<1 MHz) EMI-sensitive circuits and/or there are long wires from the amplifier to the speaker. When both an LC filter and a ferrite bead filter are used, the LC filter should be placed as close as possible to the IC followed by the ferrite bead filter. Figure.26 Using Low-ESR Capacitors Use capacitors with an ESR less than 100mΩ for optimum performance. Low-ESR ceramic capacitors minimize the output resistance. For best performance over the extended temperature range, select X7R capacitors. Figure.27 DS2101 Ver 1.0 15 June 2008 深圳市速学王科技 0755-82924118 [email protected] www.mcu104.com EUA2101 Package Information TQFP-48 DETAIL A B A DETAIL A Thermal Pad Opation SYMBOLS A A1 b D D1 D2 E E1 E2 e L DS2101 Ver 1.0 MILLIMETERS MIN. MAX. 1.20 0.05 0.15 0.17 0.27 8.80 9.20 7.00 2.00 8.80 9.20 7.00 2.00 0.50 0.45 0.75 MAX. 0.047 0.006 0.011 0.362 0.275 0.079 0.346 0.362 0.275 0.079 0.020 0.018 0.030 16 June 2008 深圳市速学王科技 INCHES MIN. 0.002 0.007 0.346 0755-82924118 [email protected] www.mcu104.com