UX 2105 155Mbps Limiting Amplifier General Description The UX2105 is a high gain limiting amplifier CMOS Level designed for SDH/SONET fiber optical receiver systems, accepting a wide range of input AC voltages and providing voltage swings with constant-amplitude some Alarm Level Compatible with PECL, TTL and Pin Compatible with the Mindspeed MC2045 and MAXIM MAX3645 Pin Configuration temperature compensation. It integrates a signal detector, with programmable LOS threshold, an optional output disable function and automatic squelch function. It is available in TSSOP 16-pin packages. Features +3.3V or +5V Power Supply 1mV Differential Input Sensitivity (BER=10-10) OUTP/OUTN are CMOS Configuration, Figure 1. Pin Configuration TSSOP 16 Simply AC-coupling Typical Application Circuit Figure 2. Typical Application Circuit 2007 Preliminary Datasheet www.uxfastic.com 1 UX 2105 155Mbps Limiting Amplifier Pin Description Pin No. Name Function Auto-zero capacitor pin. A capacitor connected between this pin and AZ2 sets the 1 AZ1 time constant of the offset correction loop. The offset correction is disabled when the AZ1 and AZ2 pins are shorted together. See AZ1. 2 AZ2 3 GNDA 4 INP Positive data input 5 INN Negative data input 6 VCCA 7 CF 8 JAM Analog Supply Ground. Must be at same potential as GNDE pin. Analog Supply Voltage. Must be at the same potential as the VCCE pin. Level-detect filter capacitor pin. Connect a capacitor between this pin and VCCA. The squelch function is disabled when JAM is connected to ground. The automatic squelch function is enabled when JAM is connected to the LOSP. Positive Loss-of-Signal output, CMOS level, compatible with PECL and TTL. LOSP is 9 LOSP low when the level of the input signal is above the preset threshold set by the VSET input. LOSP is high when the signal level drops below the threshold. Normally connected to JAM pin to enable automatic squelch function to operate. Negative Loss-of-signal output, CMOS level, compatible with PECL and TTL. LOSN is 10 LOSN high when the level of the input signal is above the preset threshold set by the VSET input. LOSN is low when the signal level drops below the threshold. Indicates Input signal level status. 11 GNDE Digital Supply Ground. Must be the same potential as the GNDA pin. 12 OUTN Negative data output, the output buffer is CMOS structure. 13 OUTP Positive data output, the output buffer is CMOS structure. 14 VCCE Digital Supply Voltage. Must be at the same potential as the VCCA pin. 15 V3V 5V to 3V conversion output pin.No connection or can connect a capacitor between this pin and GND. Loss-of-Signal Threshold Pin. Resistor (RSET) to ground sets the LOS threshold. This 16 VSET pin can be left open if the LOS detect function is not required and JAM is connected to ground, otherwise connect VSET to ground. Absolute Maximum Ratings Symbol Parameter Rating Units 6 V VCC Power supply(Note 1) TA Operating ambient -40 to +85 °C Storage temperature -65 to +150 °C TSTG 2007 Preliminary Datasheet www.uxfastic.com 2 UX 2105 155Mbps Limiting Amplifier Recommended Operating Conditions Symbol Parameter Rating Units VCC Power supply(Note 1) 3.0 to 5.5 V TA Operating ambient -40 to +85 °C Note 1: Related to Ground DC Characteristics Symbol Parameter Min VOS Equivalent input Offset Voltage VTH LOS Sensitivity Range 2 HYS LOS Hysteresis (Note 2) 1 ICC Typ 2 Power-Supply Current (Note 3) Max Units 50 μV 20 mVP-P 4 dB 43.5 mA Note 2: Optical, 10log (VDEASSERT/VASSERT). Note 3: LOSN is at CMOS level, no load terminated to the outputs, with I/O current in the output buffer. AC Characteristics (VCC=+3.0V to +5.5V, Typical values are at VCC = +5V, TA = +25°C, unless otherwise noted.) Symbol Parameter Min Typ BW Input Bandwidth@upper -3dB point: Gain>70dB 190 242 FLFC Low-Frequency Cutoff VIN Input signal voltage VAMP Output Amplitude (Note 4) RIN Input Resistance CIN Input Capacitance CAZ = open 169 CAZ = 0.1μF 21 Single ended Differential Max Units MHz KHz 0.5 800 1 1600 600 880 20 mV mV KΩ 2 pF TR,TF Data Output Transition Time (Note 5) 600 1000 ps TPWD Pulse-Width Distortion(Note 6) 100 300 ps TLOS LOS Assert/Deassert Time 100 μs Note 4: Single ended; the output buffer is CMOS structure, shown in Figure3. Note 5: 20% to 80% Note 6: TPWD= [(width of wider pulse)-(width of narrower pulse)]/2. 2007 Preliminary Datasheet www.uxfastic.com 3 UX 2105 155Mbps Limiting Amplifier Applications Information CMOS Output Buffer CMOS structure, please refer to Figure3. Current sources are integrated internal in the output buffer circuit. Different from PECL output, no 50Ω to (VCC-2V) termination here. The output common mode voltage is at half of VCC. The current flows through the chip partly from the current sources, so it corresponds to that of other similar products with ECL load. AC coupling is required at OUTN and OUTP, and the external capacitors are employed to insulate the DC level with external circuits, as shown in Typical Application Circuit. Figure 3. Output Buffer Circuit terminated by a pull up resistor (4.7～10KΩ), see LOS Output Terminations In UX2105, the LOS interface operates three logic states with different termination techniques respectively. When LOSN is connected directly to external circuits, it operates CMOS level; When Figure4, it compatible with TTL level; When terminated by 50Ω to (VCC-2V), see Figure5, it compatible with PECL level. The corresponding logic states list in table LOS Level Status. Figure 4. Equivalent TTL Termination Circuit Figure 5. Equivalent PECL Termination at LOSN Circuit at LOSN 2007 Preliminary Datasheet www.uxfastic.com 4 UX 2105 155Mbps Limiting Amplifier LOS level status Logic State CMOS PECL TTL High VCC VCC-0.9V VCC Low Ground VCC-2.2V Ground to 0.5V Package Outline Details of ‘A’ part Figure 6. TSSOP16 Package 2007 Preliminary Datasheet www.uxfastic.com 5