APA2069 Stereo 2.6W Audio Power Amplifier (with DC_Volume Control) Features • • General Description Low Operating Current with 9mA APA2069 is a monolithic integrated circuit, which pro- Improved Depop Circuitry to Eliminate Turn-on vides precise DC volume control, and a stereo bridged audio power amplifiers capable of producing 2.6W and Turn-off Transients in Outputs • • (2W) into 4Ω with less than 10% (1.0%) THD+N. The attenuator range of the volume control in APA2069 is from High PSRR 32 Steps Volume Adjustable by DC Voltage with 20dB (DC_Vol=0V) to -80dB (DC_Vol=3.54V) with 32 steps. The advantage of internal gain setting can be less Hysteresis • 2.6W per Channel Output Power into 4Ω Load components and PCB area. Both of the depop circuitry and the thermal shutdown protection circuitry are inte- at 5V, BTL Mode • Two Output Modes Allowable with BTL and SE grated in APA2069, that reduce pops and clicks noise during power up or shutdown mode operation. It also Modes Selected by SE/BTL Pin • improves the power off pop noise and protects the chip from being destroyed by over temperature and short cur- Low Current Consumption in Shutdown Mode (1µA) • • • • • rent failure. To simplify the audio system design, APA2069 combines a stereo bridge-tied loads (BTL) mode for Short Circuit Protection Thermal Shutdown Protection and Over-Current Protection Circuitry speaker drive and a stereo single-end (SE) mode for headphone drive into a single chip, where both modes are The OUT+ Signal and the IN- Signal are Outphase easily switched by the SE/BTL input control pin signal. Power Enhanced Package (DIP-16 / DIP-16A) Lead Free and Green Devices Available Pin Configuration (RoHS Compliant) Applications • • SHUTDOWN BYPASS RINGND NoteBook PC LCD Monitor or TV 1 2 3 4 GND 5 LIN- 6 VOLUME 7 SE/BTL 8 APA2069 16 15 14 13 ROUTVDD ROUT+ GND 12 11 10 9 GND LOUT+ VDD LOUT- ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.9 - Jul., 2011 1 www.anpec.com.tw APA2069 Ordering and Marking Information Package Code J : DIP-16 / DIP-16A Operating Ambient Temperature Range I : - 40 to 85 oC Handling Code TU : Tube Assembly Material L : Lead Free Device G : Halogen and Lead Free Device APA2069 Assembly Material Handling Code Temperature Range Package Code APA2069 J : APA2069 XXXXX XXXXX - Date Code Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings (Note 1) (Over operating free-air temperature range unless otherwise noted.) Symbol VDD Parameter Rating Supply Voltage Range VIN Input Voltage Range, SE/BTL, SHUTDOWN TA Operating Ambient Temperature Range TJ Maximum Junction Temperature TSTG Storage Temperature Range TSDR Maximum Lead Soldering Temperature, 10 Seconds PD Power Dissipation Unit -0.3 to 6 V -0.3 to VDD+0.3 V -40 to 85 °C 150 °C -65 to +150 °C 260 °C Internal Limited W Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol Parameter θJA Thermal Resistance from Junction to Ambient in Free Air θJC Thermal Resistance from Junction to Case in Free Air Typical Value Unit 45 °C/W 10 °C/W (Note 2) DIP-16 / DIP-16A DIP-16 / DIP-16A Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. Recommended Operating Conditions Parameter Symbol VDD Supply Voltage VIH High Level Threshold Voltage VIL Low Level Threshold Voltage VICM Common Mode Input Voltage Copyright ANPEC Electronics Corp. Rev. A.9 - Jul., 2011 Range Unit 4.5 ~ 5.5 V SHUTDOWN 2.0 ~ SE/BTL 4.0 ~ V SHUTDOWN ~ 1.0 SE/BTL ~ 3.0 ~ VDD-0.5 2 V V www.anpec.com.tw APA2069 Electrical Characteristics VDD=5V, TA=25°C (unless otherwise noted) Symbol IDD Parameter APA2069 Test Conditions Unit Min. Typ. Max. SE/BTL=0V - 9 20 SE/BTL=5V - 4 10 - 1 - µA mA Supply Current SE/BTL=0V ISD Supply Current in Shutdown Mode IIH High Input Current - 900 - nA IIL Low Input Current - 900 - nA Output Offset Voltage - 5 - mV VOS SHUTDOWN=0V Operating Characteristics, BTL mode. VDD=5V, TA=25OC, RL=4Ω, A V=6dB (unless otherwise noted) Symbol Parameter APA2069 Test Conditions Unit Min. Typ. THD+N=10%, RL=3Ω, fin=1kHz - 2.9 - THD+N =10%, RL=4Ω, fin=1kHz - 2.6 - THD+N =10%, RL=8Ω, fin=1kHz - 1.6 - THD+N =1%, RL=3Ω, fin=1kHz - 2.4 - THD+N =1%, RL=4Ω, fin=1kHz - 2 - THD+N =0.5%, RL=8Ω, fin=1kHz 1 1.3 - PO=1.2W, RL=4Ω, fin=1kHz - 0.07 - PO=0.9W, RL=8Ω, fin=1kHz - 0.08 - Power Ripple Rejection Ratio VIN=0.1Vrms, RL=8Ω, CB=1µF, fin=120Hz - 60 - dB Crosstalk Channel Separation CB=1µF, RL=8Ω, fin=1kHz - 90 - dB S/N Signal to Noise Ratio PO=1.1W, RL=8Ω, A_weighting - 95 - dB PO THD+N PSRR Maximum Output Power Total Harmonic Distortion Plus Noise Max. W % Operating Characteristics, SE mode. VDD=5V, TA=25°C, AV=0dB (unless otherwise noted) Symbol PO Parameter Maximum Output Power APA2069 Test Conditions Unit Min. Typ. Max. THD+N=10%, RL=16Ω, fin=1kHz - 220 - THD+N =10%, RL=32Ω, fin=1kHz - 120 - THD+N =1%, RL=16Ω, fin=1kHz - 160 - mW THD+N =1%, RL=32Ω, fin=1kHz - 95 - PO=125mW, RL=16Ω, fin=1kHz - 0.09 - PO=65mW, RL=32Ω, fin=1kHz - 0.09 - Power Ripple Rejection Ratio VIN=0.1Vrms, RL=32Ω, CB=1µF, fin=120Hz - 60 - dB Crosstalk Channel Separation CB=1µF, RL=32Ω, fin=1kHz - 60 - dB S/N Signal to Noise Ratio PO=75mW, SE, RL=32Ω, A_weighting - 100 - dB THD+N PSRR Total Harmonic Distortion Plus Noise Copyright ANPEC Electronics Corp. Rev. A.9 - Jul., 2011 3 % www.anpec.com.tw APA2069 Typical Operating Characteristics THD+N vs. Output Power THD+N vs. Output Power 10 10 VDD = 5V AV =14dB fin = 1kHz SE RL = 4Ω 1 RL = 3Ω RL = 8Ω THD+N(%) THD+N(%) VDD = 5V AV =20dB fin= 1kHz BTL RL = 32Ω 0.01 0 0.5 1 1.5 2 2.5 3 3.5 0 40m Output Power (W) THD+N vs. Output Power Output Noise Voltage vs. Frequency 10 VDD = 5V fin =1kHz RL =3Ω BTL 1 THD+N(%) THD+N(%) 10 AV = 20dB VDD = 5V AV =20dB RL =3Ω BTL 1 fin= 20kHz fin= 20Hz 0.1 AV = 6dB 0.01 0 1 0.5 0.1 1.5 2 2.5 3 fin = 1kHz 0.05 10m 3.5 100m Output Power (W) 1 5 Output Power (W) THD+N vs. Frequency THD+N vs. Frequency 10 VDD = 5V RL =3Ω PO = 1.8W BTL 1 THD+N(%) THD+N(%) 160m 200m 240m 80m 120m Output Power (W) 10 RL = 16Ω 0.1 0.1 0.01 1 AV = 20dB 0.1 VDD = 5V AV = 6dB RL =3Ω BTL 1 0.1 PO = 0.9W AV = 6dB PO = 1.8W 0.01 20 100 1k 0.01 20 10k 20k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.9 - Jul., 2011 100 1k 10k 20k Frequency (Hz) 4 www.anpec.com.tw APA2069 Typical Operating Characteristics (Cont.) THD+N vs. Output Power THD+N vs. Output Power 10 10 VDD = 5V fin =1kHz RL =4Ω BTL THD+N(%) THD+N(%) 1 AV = 20dB 0.1 fin = 20kHz 1 fin = 20Hz 0.1 0.01 0 0.5 1 1.5 2 2.5 3 0.01 10m 3.5 100m Output Power (W) VDD = 5V RL=4Ω PO=1.5W BTL 1 THD+N(%) THD+N(%) VDD = 5V AV= 6dB RL=4Ω BTL AV = 6dB 0.1 PO = 0.8W 0.1 PO = 1.5W AV = 20dB 0.01 20 100 1k Frequency (Hz) 0.01 20 10k 20k 100 1k THD+N vs. Output Power 10 VDD = 5V fin= 1kHz RL=8Ω BTL 1 VDD = 5V AV = 20dB RL=8Ω BTL THD+N(%) 1 AV = 6dB 0.1 fin = 20kHz fin = 20Hz 0.1 fin = 1kHz AV = 20dB 0 0.5 1 1.5 10k 20k Frequency (Hz) THD+N vs. Output Power 10 THD+N(%) 5 THD+N vs. Frequency 10 1 0.01 1 Output Power (W) THD+N vs. Frequency 10 fin = 1kHz VDD = 5V AV =20dB RL =4Ω BTL AV = 6dB 2 2.5 3 0.01 10m 3.5 Output Power (W) Copyright ANPEC Electronics Corp. Rev. A.9 - Jul., 2011 100m 1 5 Output Power (W) 5 www.anpec.com.tw APA2069 Typical Operating Characteristics (Cont.) THD+N vs. Frequency THD+N(%) 10 THD+N vs. Frequency 10 VDD = 5V AV = 6dB RL=8Ω BTL THD+N(%) 1 PO = 0.5W 0.1 VDD=5V RL=8Ω PO=0.9W BTL 1 AV = 6dB 0.1 PO = 0.9W 0.01 20 100 1k Frequency (Hz) AV = 20dB 0.01 10k 20k 20 THD+N vs. Output Power 1k Frequency (Hz) 10 THD+N(%) VDD=5V fin=1kHz RL=16Ω SE 1 VDD=5V AV=14dB RL=16Ω CO=1000µf 1 SE fin = 20Hz fin = 20kHz AV = 0dB 0.1 0.1 AV = 14dB 0.01 0 80m 40m fin= 1kHz 0.01 120m 160m 200m 240m 10m Output Power (W) 50m THD+N vs. Frequency THD+N vs. Frequency 10 VDD=5V RL=16Ω PO=125mW CO=1000µf 1 SE THD+N(%) VDD=5V AV=0dB RL=16Ω CO=1000µf 1 SE AV = 0dB 0.1 PO = 125mW 0.1 AV = 14dB 0.01 20 100 100m 200m 300m Output Power (W) 10 THD+N(%) 10k 20k THD+N vs. Output Power 10 THD+N(%) 100 1k PO = 60mW 0.01 20 10k 20k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.9 - Jul., 2011 100 1k 10k 20k Frequency (Hz) 6 www.anpec.com.tw APA2069 Typical Operating Characteristics (Cont.) THD+N vs. Output Power VDD=5V AV=14dB RL=32Ω CO=1000µf 1 SE VDD=5V fin=1kHz RL=32Ω SE THD+N(%) THD+N(%) THD+N vs. Output Power 10 10 1 AV = 0dB fin= 20kHz 0.1 0.1 AV = 14dB 0.01 40m 0 fin= 1kHz 0.01 10m 80m 120m 160m 200m 240m THD+N vs. Frequency THD+N vs. Frequency THD+N(%) THD+N(%) 10 VDD=5V RL=32Ω PO=65mW CO=1000µf 1 SE AV = 0dB VDD=5V AV=14dB RL=32Ω CO=1000µf 1 SE PO = 30mW 0.1 0.1 AV = 14dB 20 100 PO = 65mW 1k 0.01 10k 20k 20 100 Frequency Response 10k 20k Frequency Response +20 +330 +20 +330 Gain( 20dB) Gain( 20dB) +320 +16 +320 +300 +190 +8 Phase( 6dB) VDD=5V RL=4Ω PO=0.8W BTL 10 100 Gain( 6dB) +180 Copyright ANPEC Electronics Corp. Rev. A.9 - Jul., 2011 +310 +12 +300 +190 +8 Phase( 6dB) +180 +4 +170 +160 1k 10k Frequency (Hz) Phase( 20dB) VDD=5V RL=8Ω PO=0.5W BTL +0 10 100k 200k 100 Phase(Degrees) +12 Phase(Degrees) Phase( 20dB) Amplitude(dB) +16 +310 Amplitude(dB) 1k Frequency (Hz) Frequency (Hz) +0 200m 300m Output Power (W) 10 0.01 100m 50m Output Power (W) +4 fin = 20Hz Gain( 6dB) +170 1k 10k +160 100k 200k Frequency (Hz) 7 www.anpec.com.tw APA2069 Typical Operating Characteristics (Cont.) Frequency Response +14 Gain(14dB) +220 Gain(14dB) +280 +10 +10 +210 +260 +220 +2 Gain(0dB) +200 +180 -2 VDD=5V RL=16Ω CO=1000µf PO=60mW SE -6 -10 20 100 Phase(0dB) Amplitude(dB) +240 Phase(14dB) +6 +200 +2 -2 +160 -6 +140 1k 10k Frequency (Hz) +120 100k 200k -10 20 Crosstalk(dB) Crosstalk(dB) -50 -60 -70 -120 Left to Right 20 100 1k Frequency (Hz) VDD=5V RL=4Ω PO=1.5 W BTL -30 -40 -50 -60 -70 -80 -90 -100 -110 Right to Left -110 -120 10k 20k Right to Left Left to Right 20 Crosstalk vs. Frequency Crosstalk(dB) -20 -30 VDD=5V RL=16Ω CO=1000µf PO=125mW SE -40 -50 Right to Left -60 Left to Right -50 -80 -80 -90 -90 -100 -100 Copyright ANPEC Electronics Corp. Rev. A.9 - Jul., 2011 10k 20k 10k 20k 8 Right to Left -60 -70 100 1k Frequency (Hz) 1k Frequency (Hz) +0 VDD=5V -10 R =32Ω L -20 CO=1000µf PO=65mW -30 SE -40 -70 20 100 Crosstalk vs. Frequency Crosstalk(dB) +0 -10 +170 +165 100k 200k 10k 1k Frequency (Hz) 100 +180 Crosstalk vs. Frequency +0 -10 -20 VDD=5V RL=8Ω PO=0.9 W BTL -80 -90 -100 Phase(0dB) VDD=5V RL=32Ω CO=1000µf PO=30mW SE Crosstalk vs. Frequency +0 -10 -20 -30 -40 +190 Gain(0dB) Phase(Degrees) Phase(14dB) +6 Phase(Degrees) Amplitude(dB) Frequency Response +14 +300 Left to Right 20 100 1k Frequency (Hz) 10k 20k www.anpec.com.tw APA2069 Typical Operating Characteristics (Cont.) Output Noise Voltage vs. Frequency Output Noise Voltage vs. Frequency 100µ Output Noise Voltage(V) Output Noise Voltage(V) 100µ Filter BW<22kHz 20µ A-Weighting 10µ VDD=5V AV=6dB RL=4Ω BTL 1µ 20 1k 100 Frequency (Hz) 10k 20k 20µ 10µ VDD=5V RL=4Ω VIN=200mV AV=20dB BTL -50 VDD=5V -10 R =32Ω L -20 VIN=200mV AV=14dB -30 SE -40 -50 -60 -60 -70 -70 -80 -80 -90 -90 20 100 1k -100 20 10k 20k 100 Frequency (Hz) -110 -120 1k Frequency (Hz) 10k 20k Gain vs. Volume Voltage 20 VDD=5V RL=8Ω VIN=1Vrms AV=6dB BTL 10 0 -10 Gain(dB) Shutdown Attenuation(dB) Shutdown Attenuation vs. Frequency +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 10k 20k PSRR vs. Frequency -40 -100 1k Frequency (Hz) +0 PSRR(dB) PSRR(dB) -20 -30 A-Weighting VDD=5V AV=0dB RL=32Ω SE 1µ 20 100 PSRR vs. Frequency +0 -10 Filter BW<22kHz Down -20 Up -30 -40 -50 -60 -70 20 100 1k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.9 - Jul., 2011 VDD=5V No Load BTL -80 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 10k 20k DC Volume(V) 9 www.anpec.com.tw APA2069 Typical Operating Characteristics (Cont.) Power Dissipation vs. Output Power Supply Current vs. Supply Voltage 2.0 10.0 No Load BTL Power Dissipation(W) Supply Current(mA) RL=3Ω 1.8 9.0 8.0 7.0 6.0 5.0 SE 4.0 1.6 RL=4Ω 1.4 1.2 1.0 RL=8Ω 0.8 0.6 0.4 3.0 VDD=5V THD+N<1% BTL 0.2 2.0 3.0 3.5 4.0 4.5 Supply Voltage (V) 5.0 0.0 0.00 5.5 0.50 1.00 1.50 2.00 Output Power (W) 2.50 Power Dissipation vs. Output Power 200 RL=8Ω Power Dissipation(W) 180 160 140 120 RL=16Ω 100 80 RL=32Ω 60 VDD=5V THD+N<1% SE 40 20 0 0 50 100 150 Output Power (W) Copyright ANPEC Electronics Corp. Rev. A.9 - Jul., 2011 200 250 10 www.anpec.com.tw APA2069 Pin Description PIN CONFIG FUNCTION NO. NAME 1 SHUTDOWN 2 BYPASS I Bias voltage generator 3 RIN- I Right channel input terminal 4,5,12,13 GND - Ground connection, Connected to thermal pad. 6 LIN- I Left channel input terminal 7 VOLUME I Input signal for internal volume gain setting. 8 SE/BTL I Output mode control input, high for SE output mode and low for BTL mode. 9 LOUT- O Left channel negative output in BTL mode and high impedance in SE mode. 10,15 VDD - Supply voltage 11 LOUT+ O Left channel positive output in BTL mode and SE mode. 14 ROUT+ O Right channel positive output in BTL mode and SE mode. 16 ROUT- O Right channel negative output in BTL mode and high impedance in SE mode. I It will be into shutdown mode when pull low. ISD = 1µA Block Diagram LOUT+ LINVolume Control LOUT- RINBYPASS BYPASS ROUT+ VOLUME ROUTSE/BTL SHUTDOWN SE/BTL VDD Power and Depop Circuit Shutdown ckt GND APA2069_Block Copyright ANPEC Electronics Corp. Rev. A.9 - Jul., 2011 11 www.anpec.com.tw APA2069 Typical Application Circuit VDD 100µF 0.1µF VDD GND GND LOUT+ 220 µF 1 µF LIN- L-CH Input 4Ω Volume Control 1kΩ SE/BTL Signal LOUT- 1 µF RIN- R-Ch Input BYPASS Sleeve Tip Headphone Jack BYPASS 2.2 µF ROUT+ VDD VDD 100k Ω 1k Ω 4Ω 100k Ω Shutdown Signal 220 µF VOLUME 50kΩ Control Pin Ring SE/BTL SHUTDOWN ROUT- SE/BTL Shutdown ckt A2069_AppCkt Volume Control Table_BTL Mode Supply Voltage VDD=5V Av(dB) 20 18 16 14 12 10 8 6 4 2 0 -2 -4 -6 -8 High(V) 0.12 0.23 0.34 0.46 0.57 0.69 0.80 0.91 1.03 1.14 1.25 1.37 1.48 1.59 1.71 Copyright ANPEC Electronics Corp. Rev. A.9 - Jul., 2011 Low(V) 0.00 0.17 0.28 0.39 0.51 0.62 0.73 0.84 0.96 1.07 1.18 1.29 1.41 1.52 1.63 Hysteresis(mV) Recommended Voltage(V) 0 52 0.20 51 0.31 50 0.43 49 0.54 47 0.65 46 0.77 45 0.88 44 0.99 43 1.10 41 1.22 40 1.33 39 1.44 38 1.56 37 1.67 12 www.anpec.com.tw APA2069 Volume Control Table_BTL Mode (Cont.) Supply Voltage VDD=5V Av(dB) -10 -12 -14 -16 -18 -20 -22 -24 -26 -28 -30 -32 -34 -36 -38 -40 -80 High(V) 1.82 1.93 2.05 2.16 2.28 2.39 2.50 2.62 2.73 2.84 2.96 3.07 3.18 3.30 3.41 3.52 5.00 Copyright ANPEC Electronics Corp. Rev. A.9 - Jul., 2011 Low(V) 1.74 1.85 1.97 2.08 2.19 2.30 2.42 2.53 2.64 2.75 2.87 2.98 3.09 3.20 3.32 3.43 3.54 Hysteresis(mV) Recommended Voltage(V) 35 1.78 34 1.89 33 2.01 32 2.12 30 2.23 29 2.35 28 2.46 27 2.57 26 2.69 24 2.80 23 2.91 22 3.02 21 3.14 20 3.25 18 3.36 17 3.48 16 5 13 www.anpec.com.tw APA2069 Application Information BTL Operation need for an output coupling capacitor which is required in a single supply, SE configuration. The APA2069 output stage (power amplifier) has two pairs of operational amplifiers internally, which allows Single-Ended Operation different amplifier configurations. To consider the single-supply SE configuration shown in the Application Circuit, a coupling capacitor is required to OUT+ Volume Control amplifier output signal block the DC offset voltage from reaching the load. These capacitors can be quite large (approximately 33µF to OP1 1000µF) so they tend to be expensive, occupy valuable PCB area, and have the additional drawback of limiting RL low-frequency performance of the system (refer to the Output Coupling Capacitor).The rules described still hold OUTVbias Circuit with the addition of the following relationship: OP2 1 CB x 150kΩ ≤ 1 << 1 RiC i RLCC (1) Figure 1: APA2069 Internal Configuration (each channel) Output SE/BTL Operation The power amplifier’s OP1 gain is set by internal unitygain and input audio signal comes from internal vol- The best cost saving feature of APA2069 is that it can be switched easily between BTL and SE modes. This ume control amplifier. While the second amplifier OP2 is internally fixed in a unity-gain, inverting configuration. feature eliminates the requirement for an additional headphone amplifier in applications where internal Figure 1 shows that the output of OP1 is connected to the input to OP2, which results in the output signals of stereo speakers are driven in BTL mode but external headphone or speakers must be accommodated. Internal to the APA2069, two separate amplifiers drive OUT+ and OUT- (see Figure 1). The SE/BTL input con- with both amplifiers with identical in magnitude, but out of phase 180°. Consequently, the differential gain for each channel is 2 x (Gain of SE mode). trols the operation of the follower amplifier that drives LOUT- and ROUT-. By driving the load differentially through outputs OUT+ and OUT-, an amplifier configuration is commonly referred • When SE/BTL keeps low, the OP2 turns on and the to the bridged mode is established. BTL mode operation is different from the classical single-ended SE amplifier APA2069 is in the BTL mode. configuration where one side of its load is connected to the ground. • When SE/BTL keeps high, the OP2 is in a high output A BTL amplifier design has a few distinct advantages over impedance state, which configures the APA2069 as SE driver from OUT+. IDD is reduced by approximately one- the SE configuration, as it provides differential drive to the load, thus, doubles the output swing for aspecified sup- half in the SE mode. ply voltage. The Control of the SE/BTL input can be a logic-level TTL source or a resistor divider network or the stereo head- When placed under the same conditions, a BTL amplifier has four times the output power of a SE amplifier. A BTL phone jack with switch pin as shown in the Application Circuit. configuration, such as the one used in APA2069, also creates a second advantage over SE amplifiers. Since the differential outputs, ROUT+, ROUT-, LOUT+, and LOUT-, are biased at half-supply, it’s not necessary for DC voltage to be across the load. This eliminates the Copyright ANPEC Electronics Corp. Rev. A.9 - Jul., 2011 14 www.anpec.com.tw APA2069 Application Information (Cont.) APA2069 DC Volume Control Curve (BTL) Output SE/BTL Operation (Cont.) 20 10 0 1kΩ 100kΩ Forward -10 Control Pin Gain (dB) VDD Ring SE/BTL Tip -20 Backward -30 -40 Sleeve -50 Headphone Jack -60 -70 Figure 2: SE/BTL Input Selection by Readphone Plug -80 0.0 In Figure 2, input SE/BTL operates as below : 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 DC volume (V) When the Readphone plug is inserted, the 1kΩ resistor is disconnected and the SE/BTL input is pulled high and Figure 3: Gain Setting vs. DC Volume Pin Voltage enables the SE mode. When the input goes high, the OUT- amplifier is shutdown which causes the speaker to For the highest accuracy, the voltage shown in the ‘recommended voltage’column of the table is used to select mute. The OUT+ amplifier then drives through the output capacitor (CO) into the headphone jack. When there is no a desired gain. This recommended voltage is exactly halfway between the two nearest transitions. The gain levels headphone plugged into the system, the contact pin of the headphone jack is connnected from the signal pin, are 2dB/step from 20dB to -40dB in the BTL mode, and the last step at -80dB as mute mode. the voltage divider set up by resistors 100kΩ and 1kΩ. Resistor 1kΩ then pulls low the SE/BTL pin, enabling the Input Resistance, Ri The gain for each audio input of the APA2069 is set by the internal resistors (Ri and RF) of volume control amplifier BTL function. Volume Control Function in inverting configuration. The APA2069 has an internal stereo volume control whose setting is the function of the DC voltage applied to the SE Gain = A V = − VOLUME input pin. The APA2069 volume control consists of 32 steps that are individually selected by a variable DC BTL Gain = -2 × voltage level on the VOLUME control pin. The range of the steps, controlled by the DC voltage, are from 20dB RF Ri (2) (3) BTL mode operation brings the factor of 2 in the gain equation due to the inverting amplifier mirroring the volt- to -80dB. Each gain step corresponds to a specific input voltage range, as shown in the table. To minimize the age swing across the load. For varying gain settings, the APA2069 generates each input resistance on the figure 4. effect of noise on the volume control pin, which can affect the selected gain level, hysteresis and clock delay are The input resistance will affect the low frequency performance of audio signal. The minmum input resistance is implemented. The amount of hysteresis corresponds to half of the step width, as shown in the volume control 25kΩ when gain setting is 20dB and the resistance will ramp up when close loop gain below 20dB. The input graph. Copyright ANPEC Electronics Corp. Rev. A.9 - Jul., 2011 RF Ri resistance has wide variation (+/-10%) caused by process variation. 15 www.anpec.com.tw APA2069 Application Information (Cont.) Input Resistance, Ri (Cont.) source DC level. Please note that it is important to confirm the capacitor polarity in the application. Ri vs. Gain (BTL) 160 140 Effective Bypass Capacitor, CB 120 A power amplifier, proper supply bypassing, is critical for low noise performance and high power supply rejection. The capacitor location on the BYPASS pin should be as close to the device as possible. The effect of a larger supply bypass capacitor is to improve PSRR due to increased half-supply stability. Two critical criteria of bypass capacitor (CB): 1st, it depends upon desired PSRR requirements and click-and-pop performance; 2 nd, the leakage current of CB will induce the voltage drop of VBYPASS (voltage of BYPASS pin), and if the VBYPASS is less than 0.49VDD, APA2069 will enter mute condition. The value of VBYPASS can be calculated as below: Ri (kΩ) 100 80 60 40 20 0 -40 -30 -20 -10 0 Gain (BTL) 10 20 Figure 4: Input resistance vs. Gain setting VBYPASS = 0.5VDD - ILeakage × 150k Ω Input Capacitor, Ci In the typical application, an input capacitor, Ci, is required to allow the amplifier to bias the input signal to the proper Where ILeakage =Leakage current of CB DC level for optimum operation. In this case, Ci and the minimum input impedance Ri (25kΩ) form a high-pass Therefore, it is recommended that CB leakage current should be no more then 0.4µA for properly work of APA2069. filter with the corner frequency determined in the following equation : FC (highpass) = 1 2π × 25kΩ × Ci To avoid the start-up pop noise, the bypass voltage should rise slower than the input bias voltage and the relation- (4) The value of Ci is important to consider as it directly affects the low frequency performance of the circuit. Con- ship shown in equation should be maintained. sider the example where Ri is 25kΩ and the specification calls for a flat bass response down to 50Hz. Equation is 1 1 << ( C B X150k Ω ) C i X150k Ω reconfigured as below : Ci = 1 2π × 25kΩ × FC (6) (7) The capacitor is fed from a 150kΩ resistor inside of the amplifier and the 150kΩ is the maximum input resistance of (Ri+RF). Bypass capacitor, CB, values of 2.2µF to (5) 10µF ceramic or tantalum low-ESR capacitors are recommended for the best THD+N and noise performance. When the input resistance variation is considered, the value of Ci is 0.13µF, a value in the range 0.22µF to 1.0µF would be chosen. A further consideration for this capacitor The bypass capacitance also affects the start up time. It is determined in the following equation: is the leakage path from the input source through the input network (Ri+RF, Ci) to the load. This leakage current Tstart up = 5X(C B X150k Ω ) (8) creates a DC offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications as the DC level there is held at VDD/2, which is likely higher than the Copyright ANPEC Electronics Corp. Rev. A.9 - Jul., 2011 16 www.anpec.com.tw APA2069 Application Information (Cont.) Output Coupling Capacitor, CO The value of Ci will also affect turn-on pops (Refer to In the typical single-supply SE configuration, an output Effective Bypass Capacitance). The bypass voltage ramp up should be slower than input bias voltage. Although the coupling capacitor (CO) is required to block the DC bias at the output of the amplifier thus preventing DC currents in bypass pin current source cannot be modified, the size of CB can be changed to alter the device turn-on time and the the load. As with the input coupling capacitor, the output coupling capacitor and impedance of the load form a high- amount of clicks and pops. By increasing the value of CB , turn-on pop can be reduced. However, the tradeoff for pass filter governed by the following equation: FC (highpass) = 1 2πRL CO using a larger bypass capacitor is to increase the turn-on time for this device. There is a linear relationship be- (9) tween the size of C B and the turn-on time. In a SE configuration, the output coupling capacitor, CO, is of par- For example, a 330µF capacitor with an 8Ω speaker would attenuate low frequencies below 60.6Hz. The main disadvantage, from a performance standpoint, is the load ticular concern. impedance is typically small, which drives the low-frequency corner higher degrading the bass response. resistors. Depending on the size of CO, the time constant can be relatively large. To reduce transients in the SE Large values of CO are required to pass low frequencies into the load. mode, an external 1kΩ resistor can be placed in parallel with the internal 10kΩ resistor. The tradeoff for using this Power Supply Decoupling, CS resistor is an increase in quiescent current. In most cases, choosing a small value of C i in the range of This capacitor discharges through the internal 10kΩ The APA2069 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to 0.33µF to 1µF, CB being equal to 4.7µF and an external 1kΩ resistor should be placed in parallel with the inter- ensure the output total harmonic distortion (THD+N) is as low as possible. Power supply decoupling also pre- nal 10kΩ resistor should produce a virtually clickless and popless turn-on. vents the oscillations being caused by long lead length between the amplifier and the speaker. The optimum A high gain amplifier intensifies the problem as the small delta in voltage is multiplied by the gain, therefore, it is decoupling is achieved by using two different types of capacitors that target on different types of noise on the advantageous to use low-gain configurations. power supply leads. For higher frequency transients, spikes, or digital hash Shutdown Function on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1µF, is placed as close In order to reduce power consumption while not in use, the APA2069 contains a shutdown pin to externally turn as possible to the device VDD lead works the best. For filtering lower-frequency noise signals, it is recom- off the amplifier bias circuitry. This shutdown feature turns the amplifier off when a logic low is placed on the mended to place a large aluminum electrolytic capacitor of 10µF or greater near the audio power amplifier SHUTDOWN pin. The trigger point between a logic high and logic low level is typically 2.0V. It is best to switch Optimizing Depop Circuitry between the ground and the supply VDD to provide maximum device performance. Circuitry has been included in the APA2069 to minimize the amount of popping noise at power-up and when coming By switching the SHUTDOWN pin to low, the amplifier enters a low-current state, IDD<1µA. APA2069 is in the shutdown mode. Under normal operation, SHUTDOWN out of shutdown mode. Popping occurs whenever a voltage step is applied to the speaker. In order to eliminate pin pull to high level to keep the IC out of the shutdown mode. The SHUTDOWN pin should be tied to a defi- clicks and pops, all capacitors must be fully discharged before turn-on. Rapid on/off switching of the device or nite voltage to avoid unwanted state changing. the shutdown function will cause the clicks and pops. Copyright ANPEC Electronics Corp. Rev. A.9 - Jul., 2011 17 www.anpec.com.tw APA2069 Application Information (Cont.) BTL Amplifier Efficiency An easy-to-use equation to calculate efficiency starts out PO (W) Efficiency (%) IDD (A) VPP(V) PD (W) as being equal to the ratio of power from the power supply to the power delivered to the load. 0.25 31.25 0.16 2.00 0.55 0.50 47.62 0.21 2.83 0.55 1.00 66.67 0.30 4.00 0.5 1.25 78.13 0.32 4.47 0.35 The following equations are the basis for calculating amplifier efficiency. Efficiency = PO PSUP (10) Where PO = Vorms × Vorms ( VP × VP ) = RL 2RL Vorms = VP Table 1. Efficiency vs. Output Power in 5-V/8Ω BTL Sys- (11) 2 PSUP = VDD × lDDAVG = VDD × **High peak voltages cause the THD+N to increase. 2VP πRL tems (12) Power Dissipation Efficiency of a BTL configuration : PO PSUP VP × VP ) 2RL πVP = = 2VP 4VDD ( VDD × ) πRL Whether the power amplifier is operated in BTL or SE mode, power dissipation is the major concern. Equa- ( (13) tion14 states the maximum power dissipation point for a SE mode operating at a given supply voltage and driving a specified load. Table 1 calculates efficiencies for four different output power levels. 2 SE mode : PD,MAX = Note that the efficiency of the amplifier is quite low for lower power levels and rises sharply as power to the load is increased resulting in a nearly flat internal power dissi- (14) VDD 2π 2R L In BTL mode operation, the output voltage swing is doubled as in SE mode. Thus, the maximum power dissipation point for a BTL mode operating at the same given pation over the normal operating range. Note that the internal dissipation at full output power is less than the conditions is 4 times as in SE mode. dissipation in the half power range. Calculating the efficiency for a specific system is the key to proper power 2 BTL mode : PD,MAX = 4VDD 2π 2R L (15) supply design. For a stereo 1W audio system with 8Ω loads and a 5V supply, the maximum draw on the power Since the APA2069 is a dual channel power amplifier, the supply is almost 3W. A final point to remember about linear amplifiers (either maximum internal power dissipation is 2 times that both of equations depend on the mode of operation. Even with SE or BTL) is how to manipulate the terms in the efficiency equation to the utmost advantage when possible. this substantial increase in power dissipation, the APA2069 does not require extra heatsink. The power dis- Note that in equation, VDD is in the denominator. This indicates that as VDD goes down, efficiency goes up. In other sipation from equation14, assuming a 5V-power supply and an 8Ω load, must not be greater than the power dissipation that results from the equation16: words, use the efficiency analysis to choose the correct supply voltage and speaker impedance for the application. PD,MAX = TJ,MAX - TA θ JA (16) For DIP16-A package with thermal pad, the thermal resistance (θJA) is equal to 45οC/W. Copyright ANPEC Electronics Corp. Rev. A.9 - Jul., 2011 18 www.anpec.com.tw APA2069 Application Information (Cont.) Power Dissipation (Cont.) Since the maximum junction temperature (TJ,MAX ) of APA2069 is 150οC and the ambient temperature (TA) is defined by the power system design, the maximum power dissipation which the IC package is able to handle can be obtained from equation16. Once the power dissipation is greater than the maximum limit (P D,MAX ), either the supply voltage (V DD) must be decreased, the load impedance (RL) must be increased or the ambient temperature should be reduced. Thermal Consideration Linear power amplifiers dissipate a significant amount of heat in the package under normal operating conditions. To calculate maximum ambient temperatures, first consideration is that the numbers from the Power Dissipation vs. Output Power graphs are per channel values, therefore, the dissipation of the IC heat needs to be doubled for two-channel operation. Given θJA, the maximum allowable junction temperature (TJMAX), and the total internal dissipation (PD), the maximum ambient temperature can be calculated with the following equation. The maximum recommended junction temperature for the APA2069 is 150°C. The internal dissipation figures are taken from the Power Dissipation vs. Output Power graphs. TAMax = TJMax -θJAPD (16) 150 - 45(0.8*2) = 78°C The APA2069 is designed with a thermal shutdown protection that turns the device off when the junction temperature surpasses 150°C to prevent damaging the IC. Copyright ANPEC Electronics Corp. Rev. A.9 - Jul., 2011 19 www.anpec.com.tw APA2069 Package Information DIP-16 E1 D 0.38 A L A1 A2 E b D1 b2 e c eA eB S Y M B O L DIP-16 MILLIMETERS MIN. INCHES MIN. MAX. A MAX. 0.210 5.33 A1 0.38 A2 2.92 0.015 4.95 0.115 0.195 b 0.36 0.56 0.014 0.022 b2 1.14 1.78 0.045 0.070 c 0.20 0.35 0.008 0.014 D 18.6 20.31 0.732 0.800 D1 0.13 E 7.62 8.26 0.300 0.325 E1 6.10 7.11 0.240 0.280 0.005 e 2.54 BSC 0.100 BSC eA 7.62 BSC 0.300 BSC eB L 0.430 10.92 2.92 0.115 3.81 0.150 Note : 1. Followed from JEDEC MS-001AB 2. Dimension D, D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 10 mil. Copyright ANPEC Electronics Corp. Rev. A.9 - Jul., 2011 20 www.anpec.com.tw APA2069 Package Information DIP-16A E1 D 0.38 A L A1 A2 E b D1 b2 e c eA eB S Y M B O L DIP-16A MILLIMETERS MIN. INCHES MAX. A MIN. MAX. 5.33 A1 0.38 A2 2.92 0.210 0.015 4.95 0.115 0.195 b 0.36 0.56 0.014 0.022 b2 1.14 1.78 0.045 0.070 c 0.20 0.35 0.008 0.014 D 18.6 20.31 0.732 0.800 0.005 D1 0.13 E 7.62 8.26 0.300 0.325 E1 6.10 7.11 0.240 0.280 e 2.54 BSC 0.100 BSC eA 7.62 BSC 0.300 BSC eB L 0.430 10.92 2.92 0.115 3.81 0.150 Note : 1. Followed from JEDEC MS-001AB 2. Dimension D, D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 10 mil. Copyright ANPEC Electronics Corp. Rev. A.9 - Jul., 2011 21 www.anpec.com.tw APA2069 Classification Profile Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Copyright ANPEC Electronics Corp. Rev. A.9 - Jul., 2011 22 www.anpec.com.tw APA2069 Classification Reflow Profiles (Cont.) Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) 3 Package Thickness <2.5 mm Volume mm <350 235 °C Volume mm ≥350 220 °C ≥2.5 mm 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Description 5 Sec, 245°C 1000 Hrs, Bias @ 125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.9 - Jul., 2011 23 www.anpec.com.tw