54ACTQ827 Quiet Series 10-Bit Buffer/Line Driver with TRI-STATE ® Outputs General Description The ’ACTQ827 10-bit bus buffer provides high performance bus interface buffering for wide data/address paths or buses carrying parity. The 10-bit buffers have NOR output enables for maximum control flexibility. The ’ACTQ827 utilizes NSC Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series™ feature GTO™ output control and undershoot corrector in addition to a split ground bus for superior performance. n Inputs and outputs on opposite sides of package allow easy interface with microprocessors n Improved latch-up immunity n Outputs source/sink 24 mA n Functionally and pin-compatible to AMD’s AM29827 n ’ACTQ827 has TTL-compatible inputs n 4 kV minimum ESD immunity n Standard Microcircuit Drawing (SMD) 5962-92199 Features n Guaranteed simultaneous switching noise level and dynamic threshold performance Logic Symbols Connection Diagrams Pin Assignment for DIP and Flatpak DS100249-1 IEEE/IEC DS100249-3 Pin Assignment for LCC DS100249-2 Pin Names Description OE1, OE2 Output Enable D0–D9 Data Inputs O0–O9 Data Outputs DS100249-4 GTO™ is a trademark of National Semiconductor Corporation. TRI-STATE ® is a registered trademark of National Semiconductor Corporation. FACT ® is a registered trademark of Fairchild Semiconductor Corporation. FACT Quiet Series™ is a trademark of Fairchild Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100249 www.national.com 54ACTQ827 Quiet Series 10-Bit Buffer/Line Driver with TRI-STATE Outputs August 1998 Functional Description Function Table The ’ACTQ827 line driver is designed to be employed as memory address driver, clock driver and bus-oriented transmitter/receiver. The devices have TRI-STATE outputs controlled by the Output Enable (OE) pins. When the OE is LOW, the device is transparent. When OE is HIGH, the device is in TRI-STATE mode. Inputs Outputs Function OE Dn On L H H L L L Transparent H X Z High Z Transparent H = HIGH Voltage Level L = LOW Voltage Level Z = HIGH Impedance X = Immaterial Logic Diagram DS100249-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 2 Absolute Maximum Ratings (Note 1) DC Latch-Up Source or Sink Current Junction Temperature (TJ) CDIP If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) −0.5V to +7.0V ± 300 mA 175˚C Recommended Operating Conditions −20 mA +20 mA −0.5V to VCC + 0.5V Supply Voltage (VCC) ’ACTQ Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54ACTQ Minimum Input Edge Rate ∆V/∆t ’ACTQ Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V −20 mA +20 mA −0.5V to VCC + 0.5V ± 50 mA ± 50 mA −65˚C to +150˚C 4.5V to 5.5V 0V to VCC 0V to VCC −55˚C to +125˚C 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT ® circuits outside databook specifications. Note 2: All commercial packaging is not recommended for applications requiring greater than 2000 temperature cycles from −40˚C to +125˚C. DC Electrical Characteristics for ’ACTQ Family Devices Symbol VIH VIL VOH VOL IIN Parameter VCC (V) 54ACTQ TA = −55˚C to +125˚C Minimum High Level 4.5 2.0 Input Voltage 5.5 2.0 Maximum Low Level 4.5 0.8 Input Voltage 5.5 0.8 Minimum High Level 4.5 4.4 Output Voltage 5.5 5.4 4.5 3.70 5.5 4.70 Maximum Low Level 4.5 0.1 Output Voltage 5.5 0.1 Maximum Input Units Conditions Guaranteed Limits V VOUT = 0.1V V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V IOUT = −50 µA V (Note 3) VIN = VIL or VIH IOH = −24 mA V IOH = −24 mA IOUT = 50 µA V (Note 3) VIN = VIL or VIH IOL = 24 mA IOL = 24 mA VI = VCC, GND 4.5 0.50 5.5 0.50 5.5 ± 1.0 µA 5.5 ± 10.0 µA VI = VIL, VIH VO = VCC, GND VI = VCC − 2.1V VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC Leakage Current IOZ Maximum TRI-STATE Current ICCT Maximum ICC/Input 5.5 1.6 mA IOLD (Note 4) Minimum Dynamic 5.5 50 mA IOHD Output Current 5.5 −50 mA ICC Maximum Quiescent 5.5 160.0 µA Supply Current or GND (Note 5) 3 www.national.com DC Electrical Characteristics for ’ACTQ Family Devices Symbol VOLP Parameter Quiet Output VCC (V) 54ACTQ TA = −55˚C to +125˚C (Continued) Units 5.0 1.5 V 5.0 −1.2 V Maximum Dynamic VOL VOLV Quiet Output Conditions Guaranteed Limits (Notes 6, 7) Minimum Dynamic VOL (Notes 6, 7) Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: ICC for 54ACTQ @ 25˚C is identical to 74ACTQ @ 25˚C. Note 6: Plastic DIP package. Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND. Note 8: Max number of data inputs (n−1) inputs switching 0V to 3V (’ACTQ). Input-under-test switching: 3V to threshold (VILD), 0V to threshold. (VIHD), f = 1 MHz. AC Electrical Characteristics 54ACTQ TA = −55˚C VCC Symbol Parameter (V) to +125˚C CL = 50 pF (Note 9) tPHL, tPLH Propagation Delay Units Min Max 5.0 2.0 9.0 ns Data to Output tPZL, tPZH Output Enable Time 5.0 2.0 12.5 ns tPHZ, tPLZ Output Disable Time 5.0 1.0 9.0 ns Note 9: Voltage Range 5.0 is 5.0V ± 0.5V. Capacitance Symbol CIN CPD Typ Units Input Capacitance Parameter 4.5 pF Power Dissipation 82 pF Capacitance www.national.com 4 Conditions VCC = OPEN VCC = 5.0V AC Loading DS100249-10 DS100249-9 FIGURE 2. Test Input Signal Levels *Includes jig and probe capacitance FIGURE 1. Standard AC Test Load Amplitude Rep. Rate tw tr tf 3.0V 1 MHz 500 ns 2.5 ns 2.5 ns FIGURE 3. Test Input Signal Requirements AC Waveforms DS100249-11 DS100249-12 FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 5. TRI-STATE Output HIGH and LOW Enable and Disable Time 5 www.national.com 6 Physical Dimensions inches (millimeters) unless otherwise noted 28-Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E28A 24-Lead Slim (0.300" Wide) Ceramic Dual-In-Line Package (SD) NS Package Number J24F 7 www.national.com 54ACTQ827 Quiet Series 10-Bit Buffer/Line Driver with TRI-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24 Lead Ceramic Flatpak (F) NS Package Number W24C LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. 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