54ACQ373 • 54ACTQ373 Quiet Series Octal Transparent Latch with TRI-STATE ® Outputs General Description Features The ’ACQ/’ACTQ373 consists of eight latches with TRI-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state. The ’ACQ/’ACTQ373 utilizes NSC Quiet Series technology to guarantee quiet output switching and improve dynamic threshold performance. FACT Quiet Series™ features GTO™ output control and undershoot corrector in addition to a split ground bus for superior performance. n ICC and IOZ reduced by 50% n Guaranteed simultaneous switching noise level and dynamic threshold performance n Improved latch up immunity n Eight latches in a single package n TRI-STATE outputs drive bus lines or buffer memory address registers n Outputs source/sink 24 mA n Faster prop delays than the standard ’AC/’ACT373 n 4 kV minimum ESD immunity (’ACQ) n Standard Military Drawing (SMD) — ’ACTQ373: 5962-92188 — ’ACQ373: 5962-92178 Logic Symbols IEEE/IEC DS100238-1 DS100238-2 Pin Names Description D0–D7 Data Inputs LE Latch Enable Input OE Output Enable Input O0–O7 TRI-STATE Latch Outputs GTO™ is a trademark of National Semiconductor Corporation. TRI-STATE ® is a registered trademark of National Semiconductor Corporation. FACT ® is a registered trademark of Fairchild Semiconductor Corporation. FACT Quiet Series™ is a trademark of Fairchild Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100238 www.national.com 54ACQQ373 • 54ACTQ373 Quiet Series Octal Transparent Latch with TRI-STATE Outputs September 1998 Connection Diagrams Pin Assignment for DIP and Flatpak Pin Assignment for LCC DS100238-4 DS100238-3 Truth Table Functional Description The ’ACQ/’ACTQ373 contains eight D-type latches with TRI-STATE standard outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The TRI-STATE standard outputs are controlled by the Output Enable (OE) input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. Inputs Outputs LE OE Dn On X H X Z H L L L H L H H L L X O0 H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH to Low transition of Latch Enable Logic Diagram DS100238-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 2 Absolute Maximum Ratings (Note 1) Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) DC Latchup Source or Sink Current Junction Temperature (TJ) CDIP Supply Voltage (VCC) ’ACQ ’ACTQ Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54ACQ/ACTQ Minimum Input Edge Rate ∆V/∆t ’ACQ Devices VIN from 30% to 70% of VCC VCC @ 3.0V, 4.5V, 5.5V Minimum Input Edge Rate ∆V/∆t ’ACTQ Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ± 50 mA ± 50 mA −65˚C to +150˚C 2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC −55˚C to +125˚C 125 mV/ns 125 mV/ns Note: All commercial packaging is not recommended for applications requiring greater than 2000 temperature cycles from −40˚C to +125˚C. Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT ® circuits outside databook specifications. ± 300 mA 175˚C DC Characteristics for ’ACQ Family Devices Symbol Parameter VCC 54ACQ TA = (V) −55˚C to +125˚C Units Conditions Guaranteed Limits VIH VIL VOH VOL IIN Minimum High Level 3.0 2.1 Input Voltage 4.5 3.15 5.5 3.85 Maximum Low Level 3.0 0.9 Input Voltage 4.5 1.35 5.5 1.65 Minimum High Level 3.0 2.9 Output Voltage 4.5 4.4 5.5 5.4 3.0 2.4 4.5 3.7 5.5 4.7 Maximum Low Level 3.0 0.1 Output Voltage 4.5 0.1 5.5 0.1 Maximum Input 3.0 0.50 4.5 0.50 5.5 0.50 5.5 ± 1.0 Leakage Current VOUT = 0.1V V or VCC − 0.1V V or VCC − 0.1V VOUT = 0.1V IOUT = −50 µA V (Note 2) VIN = VIL or VIH IOH = −12 mA V IOH = −24 mA IOH = −24 mA IOUT = 50 µA V (Note 2) VIN = VIL or VIH IOL = 12 mA V IOL = 24 mA µA IOL = 24 mA VI = VCC, GND (Note 4) 3 www.national.com DC Characteristics for ’ACQ Family Devices Symbol Parameter (Continued) VCC 54ACQ TA = (V) −55˚C to +125˚C Units Conditions Guaranteed Limits IOLD Minimum Dynamic (Note 3) IOHD Output Current ICC Maximum Quiescent 50 mA VOLD = 1.65V Max 5.5 −50 mA 5.5 80.0 µA VOHD = 3.85V Min VIN = VCC 5.5 Supply Current IOZ VOLP Maximum TRI-STATE Leakage Current 5.5 ± 5.0 µA Quiet Output 5.0 1.5 V 5.0 −1.2 V Maximum Dynamic VOL VOLV Quiet Output or GND (Note 4) VI(OE) = VIL, VIH VI = VCC, GND VO = VCC, GND (Notes 5, 6) Maximum Dynamic VOL (Notes 5, 6) Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. ICC for 54ACQ @ 25˚C is identical to 74ACQ @ 25˚C. Note 5: Plastic DIP package. Note 6: Max number of outputs defined as (n). Data inputs are driven 0V to 5V. One output @ GND. Note 7: Max number of data inputs (n) switching. (n−1) inputs switching 0V to 5V (’ACQ). Input-under-test switching: 5V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz. DC Characteristics for ’ACTQ Family Devices Symbol Parameter VCC 54ACTQ TA = (V) −55˚C to +125˚C Units Conditions Guaranteed Limits VIH VIL VOH VOL IIN Minimum High Level 4.5 2.0 Input Voltage 5.5 2.0 Maximum Low Level 4.5 0.8 Input Voltage 5.5 0.8 Minimum High Level 4.5 4.4 Output Voltage 5.5 5.4 4.5 3.70 5.5 4.70 Maximum Low Level 4.5 0.1 Output Voltage 5.5 0.1 Maximum Input V VOUT = 0.1V V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V IOUT = −50 µA V (Note 8) VIN = VIL or VIH IOH = −24 mA V IOH = −24 mA IOUT = 50 µA V (Note 8) VIN = VIL or VIH IOL = 24 mA IOL = 24 mA VI = VCC, GND 4.5 0.50 5.5 0.50 5.5 ± 1.0 µA 5.5 ± 5.0 µA Leakage Current IOZ Maximum TRI-STATE Leakage Current www.national.com 4 VI = VIL, VIH VO = VCC, GND DC Characteristics for ’ACTQ Family Devices Symbol Parameter (Continued) VCC 54ACTQ TA = (V) −55˚C to +125˚C Units Conditions Guaranteed Limits ICCT Maximum 5.5 1.6 mA VI = VCC − 2.1V ICC/Input IOLD Minimum Dynamic 5.5 50 mA IOHD Output Current (Note 9) 5.5 −50 mA VOLD = 1.65V Max VOHD = 3.85V Min ICC Maximum Quiescent 5.5 80.0 µA VIN = VCC 5.0 1.5 V 5.0 −1.2 V Supply Current VOLP or GND (Note 10) Quiet Output Maximum Dynamic VOL VOLV Quiet Output (Notes 11, 12) Minimum Dynamic VOL (Notes 11, 12) Note 8: All outputs loaded; thresholds on input associated with output under test. Note 9: Maximum test duration 2.0 ms, one output loaded at a time. Note 10: ICC for 54ACTQ @ 25˚C is identical to 74ACTQ @ 25˚C. Note 11: Plastic DIP package. Note 12: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND. AC Electrical Characteristics 54ACQ TA = −55˚C VCC (V) (Note 13) Symbol Parameter Min Max tPHL, tPLH Propagation Delay 3.3 1.0 15.0 Dn to On 5.0 1.0 9.5 tPHL, tPLH tPZL, tPZH tPHZ, tPLZ to +125˚C CL = 50 pF Units Propagation Delay 3.3 1.0 16.0 LE to On 5.0 1.0 9.5 Output Enable Time 3.3 1.0 14.5 5.0 1.0 10.5 3.3 1.0 12.0 5.0 1.0 10.5 Output Disable Time ns ns ns ns Note 13: Voltage Range 5.0 is 5.0V ± 0.5V. Voltage Range 3.3 is 3.3V ± 0.3V. 5 www.national.com AC Operating Requirements 54ACQ TA = −55˚C Parameter VCC (V) (Note 14) Setup Time, HIGH or LOW 3.3 3.0 Dn to LE 5.0 3.0 Hold Time, HIGH or LOW 3.3 1.5 Dn to LE 5.0 1,5 LE Pulse Width, HIGH 3.3 5.0 5.0 5.0 Symbol to +125˚C CL = 50 pF Units Guaranteed Minimum ts th tw ns ns ns Note 14: Voltage Range 5.0 is 5.0V ± 0.5V. Voltage Range 3.3 is 3.3V ± 0.3V. AC Electrical Characteristics Symbol Parameter tPHL, tPLH Propagation Delay 54ACTQ TA = −55˚C VCC (V) (Note 15) to +125˚C CL = 50 pF Units Min Max 5.0 1.5 10.5 ns 5.0 1.5 11.5 ns Dn to On tPHL, tPLH Propagation Delay LE to On tPZL, tPZH Output Enable Time 5.0 1.5 11.0 ns tPHZ, tPLZ Output Disable Time 5.0 1.5 10.5 ns Note 15: Voltage Range 5.0 is 5.0V ± 0.5V. AC Operating Requirements 54ACTQ TA = −55˚C Parameter VCC (V) (Note 16) Setup Time, HIGH or LOW 5.0 3.5 ns 5.0 1.5 ns 5.0 5.0 ns Symbol to +125˚C CL = 50 pF Units Guaranteed Minimum ts Dn to LE th Hold Time, HIGH or LOW Dn to LE tw LE Pulse Width, HIGH Note 16: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Symbol CIN CPD Typ Units Input Capacitance Parameter 4.5 pF Power Dissipation 44.0 pF Capacitance www.national.com 6 Conditions VCC = OPEN VCC = 5.0V Physical Dimensions inches (millimeters) unless otherwise noted 20-Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E20A 20-Lead Ceramic Dual-In-Line Package (D) NS Package Number J20A 7 www.national.com 54ACQQ373 • 54ACTQ373 Quiet Series Octal Transparent Latch with TRI-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Ceramic Flatpak (F) NS Package Number W20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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