54ACQ374 • 54ACTQ374 Quiet Series Octal D Flip-Flop with TRI-STATE ® Outputs General Description The ’ACQ/’ACTQ374 is a high-speed, low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and TRI-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flip-flops. The ’ACQ/’ACTQ374 utilizes Quiet Series technology to guarantee quiet output switching and improve dynamic threshold performance. FACT Quiet Series™ features GTO™ output control and undershoot corrector in addition to a split ground bus for superior performance. n Guaranteed simultaneous switching noise level and dynamic threshold performance n Improved latch-up immunity n Buffered positive edge-triggered clock n TRI-STATE outputs drive bus lines or buffer memory address registers n Outputs source/sink 24 mA n Faster prop delays than the standard ’AC/’ACT374 n 4 kV minimum ESD immunity n Standard Military Drawing (SMD) — ’ACTQ374: 5962-92189 — ’ACQ374: 5962-92179 Features n ICC and IOZ reduced by 50% Logic Symbols Connection Diagrams Pin Assignment for DIP and Flatpak DS100239-1 IEEE/IEC DS100239-3 Pin Assignment for LCC DS100239-2 DS100239-4 GTO™ is a trademark of National Semiconductor Corporation. TRI-STATE ® is a registered trademark of National Semiconductor Corporation. FACT ® is a registered trademark of Fairchild Semiconductor Corporation. FACT Quiet Series™ is a trademark of Fairchild Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100239 www.national.com 54ACQ374 • 54ACTQ374 Quiet Series Octal D Flip-Flop with TRI-STATE Outputs August 1998 Connection Diagrams (Continued) Pin Names Description D0–D7 Data Inputs CP Clock Pulse Input OE TRI-STATE Output Enable Input O0–O7 TRI-STATE Outputs Functional Description Truth Table The ’ACQ/’ACTQ374 consists of eight edge-triggered flip-flops with individual D-type inputs and TRI-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. Inputs Outputs Dn CP OE On H N L H L N L L X X H Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance N = LOW-to-HIGH Transition Logic Diagram DS100239-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 2 Absolute Maximum Ratings (Note 1) Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) DC Latch-Up Source or Sink Current Junction Temperature (TJ) CDIP Supply Voltage (VCC) ’ACQ ’ACTQ Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54ACQ/ACTQ Minimum Input Edge Rate ∆V/∆t ’ACQ Devices VIN from 30% to 70% of VCC VCC @ 3.0V, 4.5V, 5.5V Minimum Input Edge Rate ∆V/∆t ’ACTQ devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ± 50 mA ± 50 mA −65˚C to +150˚C ± 300 mA 2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC −55˚C to +125˚C 125 mV/ns 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT ® circuits outside databook specifications. 175˚C Note 2: All commercial packaging is not recommended for applications requiring greater than 2000 temperature cycles from −40˚C to +125˚C. DC Characteristics for ’ACQ Family Devices Symbol VIH VIL VOH VOL IIN Parameter VCC 54ACQ TA = −55˚C to +125˚C (V) Guaranteed Limits Minimum High Level 3.0 2.1 Input Voltage 4.5 3.15 5.5 3.85 Maximum Low Level 3.0 0.9 Input Voltage 4.5 1.35 5.5 1.65 Minimum High Level 3.0 2.9 Output Voltage 4.5 4.4 5.5 5.4 3.0 2.4 4.5 3.7 5.5 4.7 Maximum Low Level 3.0 0.1 Output Voltage 4.5 0.1 5.5 0.1 3.0 0.50 4.5 0.50 5.5 0.50 5.5 ± 1.0 Maximum Input Units VOUT = 0.1V V or VCC − 0.1V V or VCC − 0.1V VOUT = 0.1V IOUT = −50 µA V (Note 3) VIN = VIL or VIH IOH = −12 mA V IOHD (Note 4) Minimum Dynamic Output Current IOH = −24 mA IOH = −24 mA IOUT = 50 µA V V µA Leakage Current IOLD Conditions (Note 3) IOL = 12 mA IOL = 24 mA IOL = 24 mA VI = VCC, GND (Note 5) 5.5 50 mA 5.5 −50 mA 3 VOLD = 1.65V Max VOHD = 3.85V Min www.national.com DC Characteristics for ’ACQ Family Devices Symbol ICC Parameter Maximum Quiescent (Continued) VCC 54ACQ TA = −55˚C to +125˚C (V) Guaranteed Limits 5.5 80.0 Units µA VIN = VCC or GND (Note 5) VI(OE) = VIL, VIH VI = VCC, GND Supply Current IOZ Conditions Maximum TRI-STATE Leakage Current 5.5 ± 5.0 µA Quiet Output 5.0 1.5 V 5.0 −1.2 V VO = VCC, GND VOLP Maximum Dynamic VOL VOLV Quiet Output (Notes 6, 7) Minimum Dynamic VOL (Notes 6, 7) Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. ICC for 54ACQ @ 25˚C is identical to 74ACQ @ 25˚C. Note 6: Plastic DIP Package. Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 5V. One output @ GND. Note 8: Max number of data inputs (n) switching. (n−1) inputs switching 0V to 5V (’ACQ). Input-under-test switching: 5V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz. DC Characteristics for ’ACTQ Family Devices Symbol VIH VIL VOH VOL IIN Parameter VCC 54ACTQ TA = −55˚C to +125˚C (V) Guaranteed Limits Minimum High Level 4.5 2.0 Input Voltage 5.5 2.0 Maximum Low Level 4.5 0.8 Input Voltage 5.5 0.8 Minimum High Level 4.5 4.4 Output Voltage 5.5 5.4 4.5 3.70 5.5 4.70 Maximum Low Level 4.5 0.1 Output Voltage 5.5 0.1 Maximum Input Units Conditions V VOUT = 0.1V V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V IOUT = −50 µA V (Note 9) VIN = VIL or VIH IOH = −24 mA V IOH = −24 mA IOUT = 50 µA V (Note 9) VIN = VIL or VIH IOL = 24 mA IOL = 24 mA VI = VCC, GND 4.5 0.50 5.5 0.50 5.5 ± 1.0 µA 5.5 ± 5.0 µA VI = VIL, VIH VO = VCC, GND 5.5 1.6 mA VI = VCC − 2.1V 5.5 50 mA VOLD = 1.65V Max 5.5 −50 mA VOHD = 3.85V Min Leakage Current IOZ Maximum TRI-STATE Current ICCT Maximum ICC/Input (Note 9) IOLD Minimum Dynamic Output Current IOHD www.national.com 4 DC Characteristics for ’ACTQ Family Devices Symbol ICC Parameter Maximum Quiescent (Continued) VCC 54ACTQ TA = −55˚C to +125˚C (V) Guaranteed Limits 5.5 80.0 µA 5.0 1.5 V 5.0 −1.2 V Units Supply Current VOLP VIN = VCC or GND (Note 11) Quiet Output Maximum Dynamic VOL VOLV Conditions Quiet Output (Notes 12, 13) Minimum Dynamic VOL (Notes 12, 13) Note 9: All outputs loaded; thresholds on input associated with output under test. Note 10: Maximum test duration 2.0 ms, one output loaded at a time. Note 11: ICC for 54ACTQ @ 25˚C is identical to 74ACTQ @ 25˚C. Note 12: Plastic DIP package. Note 13: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND Note 14: Max number of data inputs (n) switching. (n−1) inputs switching 0V to 3V (’ACTQ). Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz. AC Electrical Characteristics 54ACQ TA = −55˚C VCC Symbol Parameter (V) to +125˚C CL = 50 pF (Note 15) Min fmax tPLH, tPHL tPZL, tPZH tPHZ, tPLZ Maximum Clock 3.3 95 Frequency 5.0 95 No. Max MHz Propagation Delay 3.3 1.0 16.5 CP to On 5.0 1.0 11.0 Output Enable Time 3.3 1.0 16.5 5.0 1.0 11.5 3.3 1.0 12.0 5.0 1.0 10.5 Output Disable Time Fig. Units ns ns ns Note 15: Voltage Range 5.0 is 5.0V ± 0.5V Voltage Range 3.3 is 3.3V ± 0.3V AC Operating Requirements VCC Symbol Parameter (V) (Note 16) 54ACQ TA = −55˚C to +125˚C CL = 50 pF Fig. Units No. Guaranteed Minimum ts th tw Setup Time, HIGH or LOW 3.3 3.0 Dn to CP 5.0 3.0 Hold Time, HIGH or LOW 3.3 2.0 Dn to CP 5.0 1.5 CP Pulse Width, 3.3 5.0 HIGH or LOW 5.0 5.0 ns ns ns Note 16: Voltage Range 5.0 is 5.0V ± 0.5V Voltage Range 3.3 is 3.3V ± 0.3V 5 www.national.com AC Electrical Characteristics 54ACTQ TA = −55˚C VCC Symbol Parameter (V) to +125˚C CL = 50 pF (Note 17) Min fmax Maximum Clock Fig. Units No. Max 5.0 95 MHz 5.0 2.0 11.5 ns Frequency tPLH, tPHL Propagation Delay CP to On tPZL, tPZH Output Enable Time 5.0 2.0 11.5 ns tPHZ, tPLZ Output Disable Time 5.0 1.5 10.5 ns Note 17: Voltage Range 5.0 is 5.0V ± 0.5V AC Operating Requirements 54ACTQ TA = −55˚C VCC Symbol Parameter (V) to +125˚C CL = 50 pF (Note 18) Fig. Units Guaranteed Minimum ts Setup Time, HIGH or LOW 5.0 3.5 ns 5.0 2.0 ns 5.0 5.0 ns Dn to CP th Hold Time, HIGH or LOW Dn to CP tw CP Pulse Width, HIGH or LOW Note 18: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Typ Units CIN Symbol Input Capacitance 4.5 pF CPD Power Dissipation Capacitance 42.0 pF www.national.com Parameter 6 Conditions VCC = OPEN VCC = 5.0V No. Physical Dimensions inches (millimeters) unless otherwise noted 20-Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E20A 20-Lead Ceramic Dual-In-Line Package (D) NS Package Number J20A 7 www.national.com 54ACQ374 • 54ACTQ374 Quiet Series Octal D Flip-Flop with TRI-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Ceramic Flatpak (F) NS Package Number W20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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