NSC 54ACQ573L

54ACQ573 • 54ACTQ573
Quiet Series Octal Latch with TRI-STATE ® Outputs
General Description
The ’ACQ/’ACTQ573 is a high-speed octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs. The ’ACQ/’ACTQ573 is functionally
identical to the ’ACQ/’ACTQ373 but with inputs and outputs
on opposite sides of the package. The ’ACQ/’ACTQ utilizes
NSC Quiet Series technology to guarantee quiet output
switching and improved dynamic threshold performance.
FACT Quiet Series™ features GTO™ output control and undershoot corrector in addition to a split ground bus for superior performance.
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Improved latch-up immunity
n Inputs and outputs on opposite sides of package allow
easy interface with microprocessors
n Outputs source/sink 24 mA
n Faster prop delays than standard ’ACT573
n 4 kV minimum ESD immunity
n Standard Microcircuit Drawing (SMD)
— ’ACTQ573: 5962-92194
— ’ACQ573: 5962-92180
Features
n ICC and IOZ reduced by 50%
Logic Symbols
IEEE/IEC
DS100242-1
DS100242-2
Pin Names
Description
D0–D7
Data Inputs
LE
Latch Enable Input
OE
TRI-STATE Output Enable Input
O0–O7
TRI-STATE Latch Outputs
GTO™ is a trademark of National Semiconductor Corporation.
TRI-STATE ® is a registered trademark of National Semiconductor Corporation.
FACT ® is a registered trademark of Fairchild Semiconductor Corporation.
FACT Quiet Series™ is a trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100242
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54ACQ573 • 54ACTQ573 Quiet Series Octal Latch with TRI-STATE Outputs
August 1998
Connection Diagrams
Functional Description
The ’ACQ/’ACTQ573 contains eight D-type latches with
TRI-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this
condition the latches are transparent, i.e., a latch output will
change state each time its D input changes. When LE is
LOW the latches store the information that was present on
the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The TRI-STATE buffers are controlled by the
Output Enable (OE) input. When OE is LOW, the buffers are
enabled. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new
data into the latches.
Pin Assignment for DIP
and Flatpak
Truth Table
DS100242-3
Inputs
Pin Assignment for LCC
Outputs
OE
LE
D
On
L
H
H
H
L
H
L
L
L
L
X
O0
H
X
X
Z
H = HIGH Voltage
L = LOW Voltage
Z = High Impedance
X = Immaterial
O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable
DS100242-4
Logic Diagram
DS100242-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings (Note 2)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI = −0.5V
VI = VCC + 0.5V
DC Input Voltage (VI)
DC Output Diode Current (IOK)
VO = −0.5V
VO = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source
or Sink Current (IO)
DC VCC or Ground Current
per Output Pin (ICC or IGND)
Storage Temperature (TSTG)
DC Latchup Source
or Sink Current
Junction Temperature (TJ)
CDIP
Supply Voltage (VCC)
’ACQ
’ACTQ
Input Voltage (VI)
Output Voltage (VO)
Operating Temperature (TA)
54ACQ/ACTQ
Minimum Input Edge Rate ∆V/∆t
’ACQ Devices
VIN from 30% to 70% of VCC
VCC @ 3.0V, 4.5V, 5.5V
Minimum Input Edge Rate ∆V/∆t
’ACTQ Devices
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
−0.5V to +7.0V
−20 mA
+20 mA
−0.5V to VCC + 0.5V
−20 mA
+20 mA
−0.5V to VCC + 0.5V
± 50 mA
± 50 mA
−65˚C to +150˚C
2.0V to 6.0V
4.5V to 5.5V
0V to VCC
0V to VCC
−55˚C to +125˚C
125 mV/ns
125 mV/ns
Note 1: All commercial packaging is not recommended for applications requiring greater than 2000 temperature cycles from −40˚C to +125˚C.
± 300 mA
Note 2: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recommend operation of FACT ® circuits outside databook specifications.
175˚C
DC Characteristics for ’ACQ Family Devices
Symbol
VIH
VIL
VOH
VOL
IIN
Parameter
VCC
54ACQ
TA = −55˚C to +125˚C
(V)
Guaranteed Limits
Minimum High Level
3.0
2.1
Input Voltage
4.5
3.15
5.5
3.85
Maximum Low Level
3.0
0.9
Input Voltage
4.5
1.35
5.5
1.65
Minimum High Level
3.0
2.9
Output Voltage
4.5
4.4
5.5
5.4
3.0
2.4
4.5
3.7
5.5
4.7
Maximum Low Level
3.0
0.1
Output Voltage
4.5
0.1
5.5
0.1
Maximum Input
3.0
0.50
4.5
0.50
5.5
0.50
5.5
± 1.0
Leakage Current
Units
Conditions
VOUT = 0.1V
V
or VCC − 0.1V
V
or VCC − 0.1V
VOUT = 0.1V
IOUT = −50 µA
V
(Note 3)
VIN = VIL or VIH
IOH = −12 mA
V
IOH = −24 mA
IOH = −24 mA
IOUT = 50 µA
V
(Note 3)
VIN = VIL or VIH
IOL = 12 mA
V
µA
IOL = 24 mA
IOL = 24 mA
VI = VCC, GND
(Note 5)
3
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DC Characteristics for ’ACQ Family Devices
Symbol
IOLD
IOHD
ICC
Parameter
(Continued)
VCC
54ACQ
TA = −55˚C to +125˚C
(V)
Guaranteed Limits
5.5
50
mA
VOLD = 1.65 VMax
Units
(Note 4)
Minimum Dynamic
Output Current
5.5
−50
mA
Maximum Quiescent
5.5
80.0
µA
VOHD = 3.85 VMin
VIN = VCC
or GND (Note 5)
VI(OE) = VIL, VIH
VI = VCC, GND
Supply Current
IOZ
Conditions
Maximum TRI-STATE
Leakage Current
5.5
± 5.0
µA
Quiet Output
5.0
1.75
V
5.0
−1.2
V
VO = VCC, GND
VOLP
Maximum Dynamic VOL
VOLV
Quiet Output
(Notes 6, 7)
Minimum Dynamic VOL
(Notes 6, 7)
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
ICC for 54ACQ @ 25˚C is identical to 74ACQ @ 25˚C.
Note 6: Plastic DIP package.
Note 7: Max number of outputs defined as (n). Data Inputs are driven 0V to 5V. One output @ GND.
DC Characteristics for ’ACTQ Family Devices
Symbol
VIH
VIL
VOH
VOL
IIN
Parameter
VCC
54ACTQ
TA = −55˚C to +125˚C
(V)
Guaranteed Limits
Minimum High Level
4.5
2.0
Input Voltage
5.5
2.0
Maximum Low Level
4.5
0.8
Input Voltage
5.5
0.8
Minimum High Level
4.5
4.4
Output Voltage
5.5
5.4
4.5
3.70
5.5
4.70
Maximum Low Level
4.5
0.1
Output Voltage
5.5
0.1
Maximum Input
Units
Conditions
V
VOUT = 0.1V
V
or VCC − 0.1V
VOUT = 0.1V
V
or VCC − 0.1V
IOUT = −50 µA
V
(Note 8)
VIN = VIL or VIH
IOH = −24 mA
V
IOH = −24 mA
IOUT = 50 µA
V
(Note 8)
VIN = VIL or VIH
IOL = 24 mA
IOL = 24 mA
VI = VCC, GND
4.5
0.50
5.5
0.50
5.5
± 1.0
µA
5.5
± 5.0
µA
5.5
1.6
mA
Leakage Current
IOZ
Maximum TRI-STATE
Leakage Current
ICCT
Maximum
ICC/Input
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4
VI = VIL, VIH
VO = VCC, GND
VI = VCC − 2.1V
DC Characteristics for ’ACTQ Family Devices
Symbol
IOLD
IOHD
ICC
Parameter
(Continued)
VCC
54ACTQ
TA = −55˚C to +125˚C
(V)
Guaranteed Limits
5.5
50
mA
VOLD = 1.65V Max
Units
(Note 9)
Minimum Dynamic
Output Current
5.5
−50
mA
Maximum Quiescent
5.5
80.0
µA
VOHD = 3.85V Min
VIN = VCC
5.0
1.5
V
(Notes 11, 12)
5.0
−1.2
V
(Notes 11, 12)
Supply Current
VOLP
Conditions
or GND (Note 10)
Quiet Output
Maximum Dynamic VOL
VOLV
Quiet Output
Minimum Dynamic VOL
Note 8: All outputs loaded; thresholds on input associated with output under test.
Note 9: Maximum test duration 2.0 ms, one output loaded at a time.
Note 10: ICC for 54ACTQ @ 25˚C is identical to 74ACTQ @ 25˚C.
Note 11: Plastic DIP package.
Note 12: Max number of outputs defined as (n). Data Inputs are driven 0V to 3V. One output @ GND.
AC Electrical Characteristics
54ACQ
TA = −55˚C
VCC
Symbol
Parameter
(V)
Fig.
to +125˚C
CL = 50 pF
(Note 13)
Min
Units
Max
tPHL,
Propagation Delay
3.3
1.5
16.0
tPLH
Dn to On
5.0
1.5
11.0
tPLH,
Propagation Delay
3.3
1.5
15.0
tPHL
LE to On
5.0
1.5
11.0
tPZL,
Output Enable Time
tPZH
tPHZ,
Output Disable Time
tPLZ
No.
3.3
1.5
13.5
5.0
1.5
10.0
3.3
1.5
13.0
5.0
1.0
10.5
ns
ns
ns
ns
Note 13: Voltage Range 5.0 is 5.0V ± 0.5V
Voltage Range 3.3 is 3.3V ± 0.3V
AC Operating Requirements
VCC
Symbol
Parameter
(V)
(Note 14)
54ACQ
TA = −55˚C
to +125˚C
CL = 50 pF
Units
Guaranteed
Minimum
tS
tH
tW
Setup Time, HIGH or LOW
3.3
4.0
Dn to LE
5.0
4.0
Hold Time, HIGH or LOW
3.3
2.0
Dn to LE
5.0
2.0
LE Pulse Width, HIGH
3.3
5.0
5.0
5.0
ns
ns
ns
Note 14: Voltage Range 5.0 is 5.0V ± 0.5V
Voltage Range 3.3 is 3.3V ± 0.3V
5
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AC Electrical Characteristics
54ACTQ
TA = −55˚C
VCC
Symbol
Parameter
(V)
to +125˚C
CL = 50 pF
(Note 15)
tPHL,
Propagation Delay
tPLH
Dn to On
Fig.
Units
Min
Max
5.0
1.5
10.0
ns
5.0
1.5
11.0
ns
tPLH,
Propagation Delay
tPHL
LE to On
tPZL, tPZH
Output Enable Time
5.0
1.5
11.0
ns
tPHZ, tPLZ
Output Disable Time
5.0
1.5
11.0
ns
No.
Note 15: Voltage Range 5.0 is 5.0V ± 0.5V
AC Operating Requirements
54ACTQ
TA = −55˚C
VCC
Symbol
Parameter
(V)
to +125˚C
CL = 50 pF
(Note 16)
Fig.
Units
Guaranteed Minimum
tS
Setup Time, HIGH or LOW
5.0
3.5
ns
5.0
1.5
ns
5.0
5.0
ns
Dn to LE
tH
Hold Time, HIGH or LOW
Dn to LE
tW
LE Pulse Width, HIGH
Note 16: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Symbol
CIN
CPD
Typ
Units
Input Capacitance
Parameter
4.5
pF
Power Dissipation
42.0
pF
Capacitance
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6
Conditions
VCC = OPEN
VCC = 5.0V
No.
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
20-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
7
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54ACQ573 • 54ACTQ573 Quiet Series Octal Latch with TRI-STATE Outputs
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
20-Lead Ceramic Flatpak (F)
NS Package Number W20A
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