ICS9250-50 Integrated Circuit Systems, Inc. Frequency Generator & Integrated Buffers for PIII & Tualatin™ Block Diagram 48MHz 24_48MHz /2 XTAL OSC PLL1 Spread Spectrum FS(4:0) PD# Vtt_PWRGD SEL24_48# SDATA SCLK 0594A—07/08/02 REF0 CPU DIVDER 2 CPUCLK (1:0) SDRAM DIVDER 12 SDRAM (11:0) SDRAM_F Control Logic Config. Reg. VDDA X1 X2 GNDA GND3V66 3V66-0 3V66-1 3V66-2 VDD3V66 VDDPCI 1 *FS0/PCICLK0 1 *FS1/PCICLK1 1 *SEL24_48#/PCICLK2 GNDPCI PCICLK3 PCICLK4 PCICLK5 VDDPCI PCICLK6 PCICLK7 GNDPCI Vtt_PWRGD/PD# SCLK SDATA VDDSDR SDRAM11 SDRAM10 GNDSDR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1 REF0/FS4* VDDLAPIC IOAPIC VDDLCPU CPUCLK0 CPUCLK1 GNDLCPU GNDSDR SDRAM0 SDRAM1 SDRAM2 VDDSDR SDRAM3 SDRAM4 SDRAM5 GNDSDR SDRAM6 SDRAM7 SDRAM_F VDDSDR GND48 1 24_48MHz/FS2 * 1 48MHz/FS3* VDD48 VDDSDR SDRAM8 SDRAM9 GNDSDR 56-Pin 300 mil SSOP 1. These pins will have 1.5 to 2X drive strength. * 120K ohm pull-up to VDD on indicated inputs. Functionality PLL2 X1 X2 Pin Configuration ICS9250-50 Recommended Application: 815B Solano B step style chipset Output Features: • 2 - CPUs @ 2.5V, up to 133MHz. • 13 - SDRAM @ 3.3V, up to 133MHz. • 3 - 3V66 @ 3.3V, 2x PCI MHz. • 8 - PCI @ 3.3V • 1 - 48MHz, @ 3.3V fixed • 1 - 24/48MHz @ 3.3V • 1 - REF @ 3.3V, 14.318MHz. • 1 - IOAPIC @ 2.5V 16.67MHz. Features: • Support PC133 SDRAM. • Up to 133MHz frequency support • Support power management through PD# • Spread spectrum for EMI control (± 0.25% Center Spread or 0 to -0.5% down spread) • Uses external 14.318MHz crystal • FS pins for frequency select Key Specifications: • CPU Output Jitter: <250ps • CPU Output Skew: <175ps • PCI Output Skew: <500ps • 3V66 Output Skew <175ps • For group skew timing, please refer to the Group Timing Relationship Table. IOAPIC DIVDER IOAPIC PCI DIVDER 8 3V66 DIVDER 3 PCICLK (7:0) 3V66 (2:0) FS4 FS3 FS2 FS1 FS0 CPU SDRAM 0 0 0 0 0 66.67 100.00 0 1 0 0 0 100.00 100.00 1 0 0 0 0 133.33 133.33 1 1 0 0 0 133.33 100.00 3V66 66.67 66.67 66.67 66.67 PCI 33.33 33.33 33.33 33.33 For other hardware/I2C selectable frequencies please refer to Byte 0 frequency select register. Power Groups VDD48 = Fixed PLL power GND48 = Fixed PLL GND VDDA = Power for CPU PLL GNDA = GND for CPU PLL ICS9250-50 General Description The ICS9250-50 is a single chip clock solution for desktop designs using the 810/810E, Solano and Solano B- Step style chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS925050 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Serial programming I2C interface allows changing functions, stop clock programming and frequency selection. Pin Configuration PIN NUMBER 1 PIN NAME VDDA 9, 10, 18, 25, VDD 32, 33, 37, 45 TYPE PWR PWR DESCRIPTION 3.3V analog power supply for fixed PLL 3 . 3 V p ow e r s u p p l y Cr ystal input, has inter nal load cap (33pF) and feedback resistor from X2 2 X1 IN 3 X2 OUT Cr ystal output, nominally 14.318MHz. Has inter nal load cap (33pF) 4 GNDA PWR Analog Ground pin for 3.3V supply for fixed PLL PWR Ground pins for 3.3V supply 5, 14, 21, 28, GND 29, 36, 41, 49 8, 7, 6 3V66 (2:0) 11 12 20, 19, 17, 16, 15 OUT 3.3Vclock outputs for HUB @ 2X PCI frequency PCICLK0 FS0 OUT IN 3 . 3 V P C I c l o ck o u t p u t s L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n . PCICLK1 OUT 3 . 3 V P C I c l o ck o u t p u t s . FS1 IN L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n . PCICLK (7:3) OUT 3 . 3 V P C I c l o ck o u t p u t s . PCICLK2 OUT 3 . 3 V P C I c l o ck o u t p u t . 13 Input logic select. When logic "0" is selected pin 35 = 48MHz When logic "1" is selected pin 35 = 24MHz. This pin acts as a dual function input pin for Vtt_PWRGD and PD# signal. When Vtt_PWRGD g o e s h i g h t h e f r e q u e n c y s e l e c t w i l l b e l a t c h e d a t p ow e r o n t h e r e a f t e r t h e p i n i s a n a s y n c h r o n o u s active low power down pin. Asynchronous active low input pin used to power down the device into a low power state. The i n t e r n a l c l o ck s a r e d i s a b l e d a n d t h e V C O a n d t h e c r y s t a l a r e s t o p p e d . T h e l a t e n c y o f t h e p o w e r d ow n w i l l n o t b e g r e a t e r t h a n 3 m s. SEL24_48# IN Vtt_PWRGD IN PD# IN 23 SCLK IN Clock input of I2C serial input. 24 SDATA IN Data input for I2C serial input. 48MHz OUT 22 34 35 FS3 FS2 3.3V Fixed 48MHz clock output for USB. IN L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n . IN L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n . 24_48MHz OUT 3.3V 24 or 48MHz output. 38 SDRAM_F 48, 47, 46, 44, S AM 43, 42, 40, 39, (1D1R :0) 31, 30, 27, 26 OUT 3.3V free r unning 100MHz SDRAM not affected by I2C OUT 3.3V output r unning 100MHz. All SDRAM outputs can be tur ned off through I2C. GNDL PWR Ground for 2.5V power supply for CPU & APIC. 51, 52 50 CPUCLK (1:0) OUT 2.5V Host bus clock output. Output frequency der ived from FS pins. 53, 55 54 VDDL IOAPIC FS4 PWR OUT IN 2.5V power suypply for CPU, IOAPIC. 2.5V clock outputs r unning at 16.67MHz. L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n . REF0 OUT 3.3V, 14.318MHz reference clock output. 56 0594A—07/08/02 2 ICS9250-50 Group Timing Relationship Table 1 Group CPU 66MHz SDRAM 100MHz CPU 100MHz SDRAM 100MHz CPU 133MHz SDRAM 100MHz CPU 133MHz SDRAM 133MHz Offset Offset Offset Tolerance Offset Tolerance Tolerance Tolerance CPU to SDRAM 2.5ns 500ps 5.0ns 500ps 0.0ns 500ps 3.75ns 500ps CPU to 3V66 7.5ns 500ps 5.0ns 500ps 0.0ns 500ps 0.0ns 500ps SDRAM to 3V66 0.0ns 500ps 0.0ns 500ps 0.0ns 500ps 3.75ns 500ps 3V66 to PCI 1.5-3.5ns 500ps 1.5-3.5ns 500ps 1.5-3.5ns 500ps 1.5 -3.5ns 500ps PCI to PCI 0.0ns 1.0ns 0.0ns 1.0ns 0.0ns 1.0ns 0.0ns 1.0ns USB & DOT Asynch N/A Asynch N/A Asynch N/A Asynch N/A Byte 0: Functionality and frequency select register (Default=0) (1 = enable, 0 = disable) Bit Description Bit 2 Bit 7 Bit 6 Bit 5 Bit 4 CPUCLK MHz FS4 FS3 FS2 FS1 FS0 Bit (2, 7:4) Bit 3 Bit 1 Bit 0 SDRAM MHz 3V66 MHz 0 0 0 0 0 66.67 100.01 66.67 0 1 0 0 0 100.00 100.00 66.67 1 0 0 0 0 133.33 133.33 66.67 1 1 0 0 0 133.33 100.00 66.67 0-Frequency is selected by hardware select, latched inputs 1- Frequency is selected by Bit 2,7:4 0- Normal 1- Spread spectrum enable 0- Running 1- Tristate all outputs PWD PCICLK IOAPIC MHz 33.34 33.33 33.33 33.33 16.67 16.67 16.67 16.67 Spread Precentage 0 0 0 0 to to to to -0.5% -0.5% -0.5% -0.5% Down Down Down Down Spread Spread Spread Spread Notes: 1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3. 2. The I2C readback for Bit 2, 7:4 indicate the revision code. 0594A—07/08/02 3 00001 Note 1 0 1 0 ICS9250-50 Byte 2: Control Register (1 = enable, 0 = disable) Byte 1: Control Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 35 34 38 PWD X X X 0 1 1 1 1 Description FS3# FS0# FS2# 24_48MHz # (Reser ved) 48MHz (Reser ved) SDRAM_F Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 3: Control Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bi t 0 Pin# 20 19 17 16 15 13 12 11 PWD 1 1 1 1 1 1 1 1 Pin# 26 27 30 31 PWD 1 1 1 X 1 1 1 1 PWD 1 1 1 1 1 1 1 1 Description SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1 SDRAM0 Byte 4: Control Register (1 = enable, 0 = disable) Description PCICLK7 PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 5: Control Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 39 40 42 43 44 46 47 48 Pin# 8 6 7 54 51 52 PWD 1 1 1 X 1 X 1 1 Description 3V66_2 3V66_0 3V66_1 FS4# IOAPIC FS1# CPUCLK1 CPUCLK0 Byte 6: Peripheral , Active/Inactive Register (1= enable, 0 = disable) Description (Reser ved) (Reser ved) (Reser ved) 24_48MHz# SDRAM11 SDRAM10 SDRAM9 SDRAM8 Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Pin# - PWD 0 0 0 0 0 1 1 0 Description Reser ved (Note) Reser ved (Note) Reser ved (Note) Reser ved (Note) Reser ved (Note) Reser ved (Note) Reser ved (Note) Reser ved (Note) Note: Don’t write into this register, writing into this register can cause malfunction Notes: 1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. PWD = Power on Default 0594A—07/08/02 4 ICS9250-50 Absolute Maximum Ratings Core Supply Voltage . . . . . . . . . . . . . . . . . . . . I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . 4.6 V 3.6V GND –0.5 V to VDD +0.5 V 0°C to +70°C –65°C to +150°C 115°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input / Supply / Common Output Parameters TA = 0 - 70°C; Supply Voltage V DD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX Input High Voltage (Latched Inputs) VIH Input Low Voltage (Latched Inputs) VIL Input High Voltage (Real-Time Inputs) VIH Input Low Voltage (Real Time Inputs) VIL VDD3.3 Supply Power2 VDD <= 2.5 V 0.9 0.75 V DD = 3.15 - 3.45 V 1.15 0.85 VDD + 0.3 VDD <= 2.5 V VSS - 0.3 0.72 0.60 V DD = 3.15 - 3.45 V 0.82 0.65 VDD <= 2.5 V 1.4 1.05 V DD = 3.15 - 3.45 V 2 1.45 VDD + 0.3 VDD <= 2.5 V VSS - 0.3 0.95 0.60 V DD = 3.15 - 3.45 V 1.35 0.80 I RAMP V DD = 0 to 2.0 V 50 Input High Current I IH -5 Input Low Current IIL1 Input Low Current IIL2 VIN = V DD V IN = 0 V; Inputs with no pull-up resistors V IN = 0 V; Inputs with pull-up resistors Cl = max cap loads; Select @ 66MHz Cl = max cap loads; Select @ 66MHz Cl = 0 pF; With Input to Vdd or Gnd V DD = 3.3 V IDD3.3OP Operating Supply Current I DDL2.5OP Power Down Current IDD3.3PD Input frequency Pin Inductance Transition Time1 Fi Lpin CIN Cout CINX TTrans Settling Time1 TS Clk Stabilization1 TStab Delay 1 TPZH, TPZL TPHZ, TPLZ Input Capacitance1 Logic Inputs Output pin capacitance X1 & X2 pins To 1st crossing of target Freq. From 1st crossing to 1% target Freq. From VDD = 3.3 V to 1% target Freq. output enable delay(all outputs) output disable delay(all outputs) 1 0594A—07/08/02 5 V V V V µs 5 mA -5 mA -200 mA 350 400 13 20 275 600 µA 7 5 6 45 3 MHz nH pF pF pF ms 3 ms 3 ms 10 10 ns ns mA 14.32 27 1 1 Guaranteed by design, not 100% tested in production. When 2.5V and PD# pins are high before or simultaneous with VDD3.3 reaching 2V. 2 UNITS ICS9250-50 Electrical Characteristics - CPU TA = 0 - 70°C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN Output Impedance Output Impedance1 Output High Voltage Output Low Voltage RDSP2B RDSN2B V OH2B VOL2B 13.5 13.5 2 Output High Current I OH2B Output Low Current I OL2B Rise Time1 Fall Time1 Duty Cycle1 Skew window1 Jitter, Cycle-to-cycle1 tr2B tf2B dt2B tsk2B V O = V DD*(0.5) V O = V DD*(0.5) IOH = -1 mA IOL = 1 mA V OH @ MIN = 1.0 V VOH @ MAX = 2.375 V V OL @ MIN = 1.2 V VOL @ MAX = 0.3 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V, 66, 100 MHz V T = 1.25 V V T = 1.25 V 1 tjcyc-cyc2B TYP MAX UNITS 45 45 Ω Ω V V 0.4 -27 -27 27 mA mA 0.4 0.4 45 0.8 0.9 51 98 115 30 1.6 1.6 55 175 250 MIN 12 TYP 17 MAX 55 UNITS Ω V O = V DD*(0.5) 12 18 55 Ω IOH = -1 mA IOL = 1 mA V OH @ MIN = 1.0 V VOH @ MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V 2.4 0.55 V V ns ns % ps ps 1 Guaranteed by design, not 100% tested in production. Electrical Characteristics - 3V66 TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER Output Impedance SYMBOL Output Impedance RDSP11 RDSN11 Output High Voltage Output Low Voltage VOH1 V OL1 Output High Current I OH1 Output Low Current IOL1 Rise Time1 Fall Time1 Duty Cycle1 Skew window1 Jitter, Cycle-to-cycle1 tr1 tf1 dt1 tsk1 tjcyc-cyc1 CONDITIONS V O = V DD*(0.5) 1 Guaranteed by design, not 100% tested in production. 0594A—07/08/02 6 -33 30 0.4 0.4 45 -108 -9 95 29 1 1 50 75 155 -33 38 1.6 1.6 55 175 500 mA mA ns ns % ps ps ICS9250-50 Electrical Characteristics - IOAPIC TA = 0 - 70°C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER Output Impedance Output Impedance1 Output High Voltage Output Low Voltage SYMBOL RDSP4B RDSN4B V OH4B VOL4B Output High Current IOH4B Output Low Current IOL4B Rise Time1 Fall Time1 Duty Cycle1 Jitter, Cycle-to-cycle1 tr4B tf4B dt4B 1 tjcyc-cyc4B CONDITIONS V O = V DD*(0.5) V O = V DD*(0.5) IOH = -1 mA IOL = 1 mA V OH @ MIN = 1.0 V VOH @ MAX = 2.375 V V OL @ MIN = 1.2 V VOL @ MAX = 0.3 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V V T = 1.25 V V T = 1.25 V MIN 9 9 2 TYP 21.5 23 MAX 30 30 0.4 -27 27 0.4 0.4 45 -68 -9 54 11 1.2 1.3 50.6 210 30 1.6 1.6 55 500 TYP 14 18 MAX 24 24 -27 UNITS Ω Ω V V mA mA ns ns % ps 1 Guaranteed by design, not 100% tested in production. Electrical Characteristics - SDRAM TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 20-30 pF (unless otherwise specified) PARAMETER Output Impedance Output Impedance1 Output High Voltage Output Low Voltage SYMBOL RDSP3 RDSN3 VOH3 V OL3 Output High Current IOH3 Output Low Current IOL3 Rise Time1 Fall Time1 Duty Cycle1 Skew window1 tr3 tf3 dt3 tsk3 CONDITIONS V O = V DD*(0.5) V O = V DD*(0.5) IOH = -1 mA IOL = 1 mA V OH @ MIN = 2.0 V VOH @ MAX = 3.135 V V OL @ MIN = 1.0 V VOL @ MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V Jitter, Cycle-to-cycle1 tjcyc-cyc3 VT = 1.5 V, 66, 100 MHz 1 1 Guaranteed by design, not 100% tested in production. 0594A—07/08/02 7 MIN 10 10 2.4 0.4 -54 54 0.4 0.4 45 -92 -16 68 29 1 1.5 52.5 58 53 1.6 1.6 55 250 170 250 -46 UNITS Ω Ω V V mA mA ns ns % ps ps ICS9250-50 Electrical Characteristics - PCI TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified) CONDITIONS PARAMETER SYMBOL MIN Output Impedance1 RDSP1 V O = V DD*(0.5) 12 Output Impedance1 RDSN1 V O = V DD*(0.5) 12 IOH = -1 mA 2.4 Output High Voltage V OH1 Output Low Voltage V OL1 IOL = 1 mA V OH @ MIN = 1.0 V -33 Output High Current I OH1 VOH @ MAX = 3.135 V 30 VOL @ MIN = 1.95 V Output Low Current I OL1 VOL @ MAX = 0.4 V Rise Time1 tr1 VOL = 0.4 V, VOH = 2.4 V 0.5 Fall Time1 tf1 VOH = 2.4 V, VOL = 0.4 V 0.5 1 Duty Cycle Skew window1 Jitter, Cycle-to-cycle1 dt1 VT = 1.5 V tsk1 tjcyc-cyc1 VT = 1.5 V VT = 1.5 V TYP MAX 14 55 UNITS Ω 18 55 Ω 0.55 V V -106 -14 94 29 -33 38 mA mA 1.5 2 ns 1.6 51.9 2 55 ns % 328 500 ps 170 500 ps MIN 12 12 2.4 TYP 17 18 MAX 55 55 UNITS Ω Ω V V -33 -108 -9 95 29 1.2 1.2 52 310 720 45 1 Guaranteed by design, not 100% tested in production. Electrical Characteristics - REF, 24,48MHz TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER Output Impedance1 Output Impedance1 Output High Voltage Output Low Voltage SYMBOL RDSP5 RDSN5 VOH15 V OL5 Output High Current IOH5 Output Low Current IOL5 Rise Time1 Fall Time1 Duty Cycle1 Jitter, Cycle-to-cycle1 Jitter, Cycle-to-cycle1 tr5 tf5 dt5 tjcyc-cyc5 tjcyc-cyc5 CONDITIONS V O = V DD*(0.5) V O = V DD*(0.5) IOH = -1 mA IOL = 1 mA V OH @ MIN = 1.0 V V OH @ MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V V T = 1.5 V VT = 1.5 V, Fixed clocks VT = 1.5 V, Ref clocks 1 Guaranteed by design, not 100% tested in production. 0594A—07/08/02 8 0.55 30 0.4 0.4 45 -33 38 4 4 55 500 1000 mA mA ns ns % ps ps ICS9250-50 General I2C serial interface information The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note. How to Write: How to Read: • • • • • • • • • • • • • • • • Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 • ICS clock will acknowledge each byte one at a time. • Controller (host) sends a Stop bit Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit How to Write: Controller (Host) Start Bit Address D2(H) ICS (Slave/Receiver) How to Read: Controller (Host) Start Bit Address D3(H) ACK Dummy Command Code ACK ICS (Slave/Receiver) ACK Byte Count Dummy Byte Count ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK Stop Bit Byte 0 Byte 0 Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Byte 4 Byte 4 Byte 5 Byte 5 Stop Bit Notes: 1. 2. 3. 4. 5. 6. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. 0594A—07/08/02 9 ICS9250-50 Shared Pin Operation Input/Output Pins Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor. The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Via to VDD Programming Header 2K Via to Gnd Device Pad 8.2K Clock trace to load Series Term. Res. Fig. 1 0594A—07/08/02 10 ICS9250-50 Power Down Waveform Note 1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the output clocks are driven Low on their next High to Low tranistiion. 2. Power-up latency <3ms. 3. Waveform shown for 100MHz 0594A—07/08/02 11 ICS9250-50 Group Offset Waveforms 0594A—07/08/02 12 ICS9250-50 c N L E1 INDEX AREA E 1 2 h x 45° D A In Millimeters SYMBOL COMMON DIMENSIONS MIN MAX A 2.41 2.80 A1 0.20 0.40 b 0.20 0.34 c 0.13 0.25 D SEE VARIATIONS E 10.03 10.68 E1 7.40 7.60 e 0.635 BASIC h 0.38 0.64 L 0.50 1.02 SEE VARIATIONS N 0° 8° α In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0° 8° A1 -Ce SEATING PLANE b .10 (.004) C N 56 VARIATIONS D mm. MIN MAX 18.31 18.55 D (inch) MIN .720 Ref erence Do c.: JED EC Pub licat io n 9 5, M O-118 10 -0 0 3 4 Ordering Information ICS9250yF-50-T Example: ICS XXXX y F - PPP - T Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS, AV = Standard Device 0594A—07/08/02 13 MAX .730