ICS9248-78 Integrated Circuit Systems, Inc. Preliminary Product Preview Frequency Timing Generator for Pentium II Systems General Description The ICS9248-78 is a single chip clock for Intel Pentium II. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces EMI by 8dB to 10 dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-78 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Features Generates the following system clocks: - 2 - CPUs @ 2.5V, up to 150MHz. - 1 - IOAPIC @ 2.5V, PCI/2MHz. - 9 SDRAMs (3.3V), up to150MHz. -2 - 3V66 @ 3.3V, 2x PCIMHz. - 8 - PCIs @ 3.3V. - 1 - 48MHz, @ 3.3V fixed. - 2 - REF @ 3.3V, 14.318Hz. - 1 - 24MHz, @ 3.3V fixed. Supports spread spectrum modulation , down spread 0 to -0.5%, ±0.25% center spread. I2C support for power management. Efficient power management scheme through PD#. Uses external 14.138 MHz crystal. Block Diagram Pin Configuration 48-Pin 300 mil SSOP Power Groups GNDREF, VDDREF = REF, Crystal GND3V66, VDD3V66 = 3V66 GNDPCI, VDDPCI = PCICLKs GNDCOR, VDDCOR = PLLCORE GND48, VDD48 = 48 GNDSDR, VDDSDR = SDRAM GNDLCPU, VDDLCPU = CPUCLK GNDLPCI, VDDLAPIC = IOAPIC 9248-78 Rev A 7/21/99 1. These pins will have 2X drive strength. * 120K ohm pull-up to VDD on indicated inputs. Pentium II is a trademark of Intel Corporation I2C is a trademark of Philips Corporation PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. ICS9248-78 Preliminary Product Preview Pin Descriptions PIN NUMBER 1 2, 9, 10, 18, 25, 29, 37 P I N NA M E TYPE REF1 OUT 3.3V, 14.318MHz reference clock output. VDD PWR 3.3V power supply 3 X1 IN 4 X2 OUT 5, 6, 14, 21, 28, GND 33, 41 7, 8 3V66 (1:0) 11 12 13, 15, 16, 17, 19, 20 DESCRIPTION Crystal input, has internal load cap (33pF) and feedback resistor from X2 Crystal output, nominally 14.318MHz. Has internal load cap (33pF) PWR Ground pins for 3.3V supply OUT 3.3V clock outputs for HUB running at 2XPCI MHz 1 OUT IN 3.3V PCI clock outputs, with Synchronous CPUCLKS Logic input frequency select bit. Input latched at power on. PCICLK11 OUT 3.3V PCI clock outputs, with Synchronous CPUCLKS PCICLK0 FS0 FS1 PCICLK (2:7) IN OUT Logic input frequency select bit. Input latched at power on. 3.3V PCI clock outputs, with Synchronous CPUCLKS 22 PD# IN Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. 23 SCLK IN Clock input of I2C input 24 SDATA IN Data input for I2C serial input. 48MHz OUT 26 27 3 . 3 V F i xe d 4 8 M H z c l o c k o u t p u t f o r U S B FS3 IN Logic input frequency select bit. Input latched at power on. FS2 IN Logic input frequency select bit. Input latched at power on. 24MHz OU T 3 . 3 V fi x e d 2 4 M H z o u t p u t SDRAM_F OUT 3.3V free running SDRAM not affected by I2C SDRAM (7:0) OUT 3.3V outputs GNDL PWR Ground for 2.5V power supply for CPU & APIC 43, 44 CPUCLK (1:0) OUT 2 . 5 V H o s t bu s c l o c k o u t p u t . 45, 47 46 VDDL IOAPIC SEL_3V66 PWR OUT IN 2.5V power suypply for CPU, IOAPIC 2.5V clock outputs running at PCI/2 MHz This pin selects the 3V66 output frequency. REF01 OUT 3.3V, 14.318MHz reference clock output. 30 40, 39, 38, 36, 35, 34, 32, 31 42 48 Note: 1. These pins will have 2X drive strength. 2 ICS9248-78 Preliminary Product Preview Frequency Selection FS3 FS2 FS1 FS0 CPU SDRAM PCI MHz MHz MHz 3V66 MHz IOAPIC MHz SEL_3V66=0 SEL_3V66=1 0 0 0 0 100.23 100.23 33.41 66.82 66.82 16.70 0 0 0 1 100.90 100.90 33.63 67.26 67.26 16.81 0 0 1 0 105.00 105.00 35.00 70.00 70.00 17.50 0 0 1 1 66.89 100.33 33.44 66.89 66.89 16.72 0 1 0 0 120.00 120.00 40.00 64.00* 80.00 20.00 0 1 0 1 124.00 124.00 41.33 64.00* 82.66 20.67 0 1 1 0 133.30 133.30 44.43 64.00* 88.86 22.21 0 1 1 1 133.30 133.30 33.32 66.65 66.65 16.66 1 0 0 0 140.00 140.00 35.00 70.00 70.00 17.50 1 0 0 1 150.00 150.00 37.50 64.00* 75.00 18.75 1 0 1 0 114.99 114.99 38.33 64.00* 76.66 19.16 1 0 1 1 70.00 105.00 35.00 70.00 70.00 17.50 1 1 0 0 75.00 112.50 37.50 64.00* 75.00 18.75 1 1 0 1 83.31 124.96 41.65 64.00* 83.31 20.83 1 1 1 1 1 1 0 1 90.00 95.00 90.00 95.00 30.00 31.67 60.00 63.33 60.00 63.33 15.00 15.83 Note: * These output frequencies are not synchronous to CPUCLK and do not have spread spectrum modulation. Clock Enable Configuration PD# CPUCLK SDRAM IOAPIC 66MHz PCICLK REF, 48MHz Osc VCOs 0 LOW LOW LOW LOW LOW LOW OFF OF F 1 ON ON ON ON ON ON ON ON 3 ICS9248-78 Preliminary Product Preview Power Down Waveform Note 1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the output clocks are driven Low on their next High to Low tranistiion. 2. Power-up latency <3ms. 3. Waveform shown for 100MHz 4 ICS9248-78 Preliminary Product Preview General I2C serial interface information The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note. How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit How to Write: Controller (Host) Start Bit Address D2(H) ICS (Slave/Receiver) How to Read: Controller (Host) Start Bit Address D3(H) ACK Dummy Command Code ACK ICS (Slave/Receiver) ACK Byte Count Dummy Byte Count ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK Stop Bit Byte 0 Byte 0 Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Byte 4 Byte 4 Byte 5 Byte 5 Stop Bit Notes: 1. 2. 3. 4. 5. 6. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. 5 ICS9248-78 Preliminary Product Preview Byte 0: Functionality and frequency select register (Default=0) (1 = enable, 0 = disable) Description Bit Bit 7 0 - ±0.25% Center Sperad Spectrum Bit 3 Bit 1 Bit 0 0 1-Down Spread Spectrum 0 to -0.5% Bit CPUCLK SDRAM PCICLK (2, 6:4) MHz MHz MHz Bit (2, 6:4) PWD 3V66 MHz IOAPIC MHz 0000 0001 0010 0011 0100 0101 100.23 100.90 105.00 66.89 120.00 124.00 100.23 100.90 105.00 100.33 120.00 124.00 33.41 33.63 35.00 33.44 40.00 41.33 SEL_3V66=0 66.82 67.26 70.00 66.89 64.00* 64.00* SEL_3V66=1 66.82 67.26 70.00 66.89 80.00 82.66 16.70 16.81 17.50 16.72 20.00 20.67 0110 133.30 133.30 44.43 64.00* 88.86 22.21 0111 133.30 133.30 33.32 66.65 66.65 16.66 1000 140.00 140.00 35.00 70.00 70.00 17.50 1001 150.00 150.00 37.50 64.00* 75.00 18.75 1010 114.99 114.99 38.33 64.00* 76.66 19.16 1011 70.00 105.00 35.00 70.00 70.00 17.50 1100 75.00 112.50 37.50 64.00* 75.00 18.75 1101 83.31 124.96 41.65 64.00* 83.31 20.83 1110 90.00 90.00 30.00 60.00 60.00 15.00 63.33 15.83 1111 95.00 95.00 31.67 63.33 0 - Frequency is selected by hardware select, latched inputs 1 - Frequency is selected by Bit 2, 6:4 0 - Normal 1 - Spread spectrum enable 0 - Running 1 - Tristate all outputs Notes: 1. Default at power-up will be for latched logic inputs to define frequency, Bit 2, 6:4 are default to 0000. * These output frequencies are not synchronous to CPUCLK and do not have spread spectrum modulation. 6 Note 1 0 1 0 ICS9248-78 Preliminary Product Preview Byte 2: Control Register (1 = enable, 0 = disable) Byte 1: Control Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 27 26 30 PWD X X X 1 1 1 1 1 Description FS3# FS0# FS2# 24MHz (Act/Inact) (Reserved) 48MHz (Act/Inact) (Reserved) SDRAM_F (Act/Inact) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 3: Control Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 20 19 17 16 15 13 12 11 PWD 1 1 1 1 1 1 1 1 Pin# 31 32 34 35 36 38 39 40 PWD 1 1 1 1 1 1 1 1 Description SDRAM7 (Act/Inact) SDRAM6 (Act/Inact) SDRAM5 (Act/Inact) SDRAM4 (Act/Inact) SDRAM3 (Act/Inact) SDRAM2 (Act/Inact) SDRAM1 (Act/Inact) SDRAM0 (Act/Inact) Byte 4: Control Register (1 = enable, 0 = disable) Description PCICLK7 (Act/Inact) PCICLK6 (Act/Inact) PCICLK5 (Act/Inact) PCICLK4 (Act/Inact) PCICLK3 (Act/Inact) PCICLK2 (Act/Inact) PCICLK1 (Act/Inact) PCICLK0 (Act/Inact) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 7 8 46 43 44 PWD 0 1 1 X 1 X 1 1 Description (Reserved) 3V66_0 (Act/Inact) 3V66_1 (Act/Inact) SEL_3V66 IOAPIC (Act/Inact0) FS1# CPUCLK1 (Act/Inact) CPUCLK0 (Act/Inact) Notes: 1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. PWD = Power on Default 7 ICS9248-78 Preliminary Product Preview Absolute Maximum Ratings Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 4.6 V I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 3.6V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70C; Supply Voltage VDD = 3.3 V +5%, VDDL=2.5 V+ 5%(unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Power Down Supply Current Input frequency Pin Inductance Input Capacitance1 Transition Time 1 1 IDD3.3PD CONDITIONS VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = 0 pF; Select @ 66M MIN 2 VSS-0.3 -5 -5 -200 CL = 0 pF; With input address to Vdd or GND Fi Lpin VDD = 3.3 V; CIN Cout CINX Logic Inputs Out put pin capacitance X1 & X2 pins Ttrans To 1st crossing of target Freq. TYP MAX UNITS VDD+0.3 V 0.8 V µA 5 µA 2.0 µA -100 60 100 mA 400 600 µA 7 MHz nH 5 6 45 pF pF pF 3 ms 14.318 27 Settling Time Ts From 1st crossing to 1% target Freq. Clk Stabilization1 TSTAB tPZH,tPZH tPLZ,tPZH From VDD = 3.3 V to 1% target Freq. output enable delay (all outputs) output disable delay (all outputs) Delay 1 SYMBOL VIH VIL IIH IIL1 IIL2 IDD3.3OP Guarenteed by design, not 100% tested in production. 8 ms 1 1 3 10 10 ms ns ns ICS9248-78 Preliminary Product Preview Electrical Characteristics - CPU TA = 0 - 70C, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER SYMBOL Output Impedance RDSP2B1 RDSN2B1 Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current VOH2B VOL2B IOH2B IOL2B CONDITIONS MIN TYP MAX UNITS VO = VDD*(0.5) 13.5 45 Ω VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH @MIN= 1.0V , VOH@ MAX= 2.375V VOL @MIN= 1.2V , VOL@ MAX= 0.3V 13.5 2 45 -27 27 0.4 -27 30 Ω V V mA mA Rise Time tr2B1 VOL = 0.4 V, VOH = 2.0 V 0.4 1.6 ns Fall Time tf2B1 dt2B1 tsk2B1 VOH = 0.4 V, VOL = 2.0 V 0.4 1.6 ns VT = 1.25 V 45 55 ns VT = 1.25 V 175 ps VT = 1.25 V 250 ps Duty Cycle Skew tjcyc-cyc1 50 Jitter 1 Guarenteed by design, not 100% tested in production. Electrical Characteristics - 3V66 TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS RDSP1 1 VO = VDD*(0.5) 12 55 Ω Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current RDSN1 VOH1 VOL1 IOH1 IOL1 1 VO = VDD*(0.5) 12 IOH = -1 mA 2.4 IOL = 1 mA VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V -33 VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 30 55 0.55 -33 38 Ω V V mA mA Rise Time tr11 VOL = 0.4 V, VOH = 2.4 V 0.4 1.6 ns Fall Time 1 VOH = 2.4 V, VOL = 0.4 V 0.4 1.6 ns 1 VT = 1.5 V 45 55 % 1 VT = 1.5 V VT = 1.5 V 175 500 ps ps Output Impedance Duty Cycle Skew Jitter 1 tf1 dt1 tsk1 tjcyc-cyc Guarenteed by design, not 100% tested in production. 9 ICS9248-78 Preliminary Product Preview Electrical Characteristics - IOAPIC TA = 0 - 70C;VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER SYMBOL Output Impedance RDSP4B1 RDSN4B1 Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current MIN TYP MAX UNITS VO = VDD*(0.5) 9 30 Ω VO = VDD*(0.5) IOH = -5.5 mA IOL = 9.0 mA VOH@ min = 1.4 V, VOH@ MAX = 2.5 V VOL@ MIN = 1.0 V, VOL@ MAX= 0.2 9 2 30 -36 36 0.4 -21 31 Ω V V mA mA Rise Time tr4B1 VOL = 0.4 V, VOH = 2.0 V 0.4 1.6 ns Fall Time tf4B1 dt4B1 VOH = 2.0 V, VOL = 0.4 V 0.4 1.6 ns VT = 1.25 V VT = 1.25 V 45 55 500 % ps Duty Cycle Jitter 1 VOH4\B VOL4B IOH4B IOL4B CONDITIONS tjcyc-cyc Guarenteed by design, not 100% tested in production. Electrical Characteristics - SDRAM TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS RDSP3 1 VO = VDD*(0.5) 10 24 Ω Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current RDSN3 VOH3 VOL3 IOH3 IOL3 1 VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH @MIN= 2.0 V, VOH@ MAX=3.135 V VOL@ MIN= 1.0 V, VOL@ MAX=0.4 V 10 2.4 24 -54 54 0.4 -46 53 Ω V V mA mA Rise Time Tr31 VOL = 0.4 V, VOH = 2.4 V 0.4 1.6 ns Fall Time Tf3 1 VOH = 2.4 V, VOL = 0.4 V 0.4 1.6 ns Dt3 1 VT = 1.5 V 45 55 % 250 250 ps ps Output Impedance Duty Cycle Skew Jitter 1 1 Tsk3 tj cyc-cyc VT = 1.5 V VT = 1.5 V Guarenteed by design, not 100% tested in production. 10 ICS9248-78 Preliminary Product Preview Electrical Characteristics - PCI TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS RDSP1 1 VO = VDD*(0.5) 12 55 Ω Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current RDSN1 VOH1 VOL1 IOH1 IOL1 1 VO = VDD*(0.5) 12 IOH = -1 mA 2.4 IOL = 1 mA VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V -33 VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 30 55 0.55 -33 38 Ω V V mA mA Rise Time tr11 VOL = 0.4 V, VOH = 2.4 V 0.5 2 ns Fall Time 1 VOH = 2.4 V, VOL = 0.4 V 0.5 2 ns 1 VT = 1.5 V 45 55 % 1 VT = 1.5 V VT = 1.5 V 500 500 ps ps Output Impedance Duty Cycle Skew Jitter 1 tf1 dt1 tsk1 tjcyc-cyc Guarenteed by design, not 100% tested in production. Electrical Characteristics - 48M, REF TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 -20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS RDSP5 1 VO = VDD*(0.5) 20 60 Ω Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current RDSN5 VOH5 VOL5 IOH5 IOL5 1 VO = VDD*(0.5) IOH = 1 mA IOL = -1 mA VOH @MIN=1 V, VOH@MAX= 3.135 V VOL@MIN=1.95 V, VOL@MIN=0.4 V 20 2.4 60 0.4 -23 27 Ω V V mA mA Rise Time tr51 VOL = 0.4 V, VOH = 2.4 V 1.8 4 ns Fall Time 1 VOH = 2.4 V, VOL = 0.4 V 1.7 4 ns 1 VT = 1.5 V 55 % VT = 1.5 V; Fixed Clocks 500 ps VT = 1.5 V; Ref Clocks VT = 1.5 V 1000 250 ps ps Output Impedance 1 tf5 Duty Cycle dt5 Jitter tjcyc-cyc1 tjcyc-cyc1 Skew Tsk -29 29 45 Guarenteed by design, not 100% tested in production. 11 ICS9248-78 Preliminary Product Preview Group Offset Waveforms Group Skews at Common Transition Edges: CPU & IOAPIC load (lumped) = 20pf; PCI, SDRAM, 3V66 LOAD (LUMPED) = 30pf. GROUP SYMBOL CONDITIONS MIN CPU @ 1.25V, 3V66 @ 1.5V (Note: 180° CPU (at 66MHz) to 0 SCPU1-3V66 offset between CPU & 3V66 3V66 CPU @ 1.25V, SDRAM @ 1.5V (Note: 180° CPU (at 100MHz) to 0 SCPU2-SDRAM offset between CPU & 66MHz SDRAM 1.5 3V66 to PCI S3V66-PCI 3V66 @ 1.5V, PCI @ 1.5V IOAPIC to PCI SIOAPIC-PCI IOAPIC @ 1.25V, PCI @1.5V 0 12 TYP 2.1 MAX UNITS 500 ps 500 ps 4 500 ns ps ICS9248-78 Preliminary Product Preview SSOP Package SYMBOL A A1 A2 B C D E e H h L N ∝ X COMMON DIMENSIONS MIN. NOM. MAX. .095 .101 .110 .008 .012 .016 .088 .090 .092 .008 .010 .0135 .005 .010 See Variations .292 .296 .299 0.025 BSC .400 .406 .410 .010 .013 .016 .024 .032 .040 See Variations 0° 5° 8° .085 .093 .100 VARIATIONS MIN. .620 AC D NOM. .625 N MAX . .630 48 Ordering Information ICS9248yF-78 Example: ICS XXXX y F - PPP Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 13 PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.