155.52 MHz Frequency Synthesizer AD809 a FEATURES Frequency Synthesis to 155.52 MHz 19.44 MHz or 9.72 MHz Input Reference Signal Select Mux Single Supply Operation: +5 V or –5.2 V Output Jitter: 2.0 Degrees RMS Low Power: 90 mW 10 KH ECL/PECL Compatible Output 10 KH ECL/PECL/TTL/CMOS Compatible Input Package: 16-Pin Narrow 150 Mil SOIC 155.52 Mbps ports. The AD809 can be applied to create the transmit bit clock for one or more ports. An input signal multiplexer supports loop-timed applications where a 155.52 MHz transmit bit clock is recovered from the 155.52 Mbps received data. The low jitter VCO, low power and wide operating temperature range make the device suitable for generating a 155.52 MHz bit clock for SONET/SDH/Fiber in the Loop systems. The device has a low cost, on-chip VCO that locks to either 8× or 16× the frequency at the 19.44 MHz or 9.72 MHz input. No external components are needed for frequency synthesis; however, the user can adjust loop dynamics through selection of a damping factor capacitor whose value determines loop damping. PRODUCT DESCRIPTION The AD809 provides a 155.52 MHz ECL/PECL output clock from either a 19.44 MHz or a 9.72 MHz TTL/CMOS/ECL/PECL reference frequency. The AD809 functionality supports a distributed timing architecture, allowing a backplane or PCB 19.44 MHz or 9.72 MHz timing reference signal to be distributed to multiple The AD809 design guarantees that the clock output frequency will drift low (by roughly 20%) in the absence of a signal at the input. The AD809 consumes 90 mW and operates from a single power supply at either +5 V or –5.2 V. FUNCTIONAL BLOCK DIAGRAM CF1 CF2 7 (19.44MHz CLKIN 13 OR 9.72MHz) CLKINN 12 AUTO SELECT PFD 8 LOOP FILTER VCO BW ADJUST TTL/CMOSIN 10 AUTO SELECT DIVIDE BY 8/16 AD809 PECLIN 2 (155MHz) PECLINN 1 MUX 15 MUX 5 CLKOUT 4 CLKOUTN (155MHz PECL OUTPUT) REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 © Analog Devices, Inc., 1997 AD809–SPECIFICATIONS (T = T A Parameter MIN to TMAX, VS = VMIN to VMAX, CD = 22 nF, unless otherwise noted) Condition Min TRACKING AND CAPTURE RANGE ×8 Synthesis ×16 Synthesis 19.42 9.71 OUTPUT JITTER ×8 Synthesis ×16 Synthesis 1.6 1.6 CD = 5.6 nF (ζ = 5) CD = 22 nF (ζ = 10) 200 0.08 0.02 1 JITTER TRANSFER Bandwidth Peaking DUTY CYCLE TOLERANCE INPUT VOLTAGE LEVELS PECL Input Logic High, VIH Input Logic Low, VIL TTL Input Logic High, VIH Input Logic Low, VIL Typ Units 19.46 9.73 MHz MHz 2.9 2.9 Degrees RMS Degrees RMS kHz dB dB ×8 or ×16 Synthesis Output Jitter ≤ 2.9 Degrees RMS 15 85 % @ CLKIN/N and PECLIN/N Inputs 3.8 3.1 VCC 3.6 Volts Volts @ TTL/CMOSIN and MUX Inputs 2.0 0.8 Volts Volts OUTPUT VOLTAGE LEVELS PECL Output Logic High, VOH Output Logic Low, VOL Referenced to VCC SYMMETRY (Duty Cycle) ×8 Synthesis or ×16 Synthesis OUTPUT RISE/FALL TIMES 1.5 Rise Time (tR) Fall Time (tF) 20%–80% 80%–20% POWER SUPPLY VOLTAGE VMIN to VMAX –1.2 –2.0 –1.0 –1.8 –0.7 –1.7 Volts Volts 46 52 62 % % 1.1 1.1 1.5 1.5 ns ns 5.5 Volts 26 mA +85 °C 4.5 POWER SUPPLY CURRENT OPERATING TEMPERATURE RANGE Max 17 TMIN to TMAX –40 NOTES 1 Device design is guaranteed for operation over Capture Ranges and Tracking Ranges, however the device has wider capture and tracking ranges (for both ×8 and ×16 synthesis). Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS* Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +12 V Input Voltage (Pin 12 or Pin 13) . . . . . . . . . . . . . . VCC + 0.6 V Maximum Junction Temperature. . . . . . . . . . . . . . . . . +165°C Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C ESD Rating (Human Body Model) . . . . . . . . . . . . . . . . 1500 V “ON” TIME tON OUTPUT 50% (PINS 4 & 5) PERIOD τ *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics: 16-Pin Narrow Body SOIC Package: θJA = 110°C/W. SYMMETRY = (100 × tON/τ) Figure 1. Symmetry ORDERING GUIDE Model Temperature Range Package Description Package Option AD809BR AD809BR-REEL7 –40°C to +85°C –40°C to +85°C 16-Pin Narrow Body SOIC 750 Pieces, 7" Reel R-16A R-16A –2– REV. A AD809 Table I. PIN DESCRIPTIONS MUX Input Input Selected TTL “0” TTL “1” CLKIN/CLKINN PECLIN/PECLINN Pin No. Mnemonic Description 1 PECLINN Differential 155 MHz Input 2 PECLIN Differential 155 MHz Input 3 VCC2 Digital VCC for PECL Outputs 4 CLKOUTN Differential 155 MHz Output 5 CLKOUT Differential 155 MHz Output Input Reference AD809 Configuration PECL/ECL Differential Apply the valid PECL–level reference frequency to Pins 13 and 12. AD809 frequency synthesizer ignores the input at Pin 10. TTL/CMOS Single-Ended Apply the reference frequency to Pin 10. Connect Pins 13 and 12 to AVEE (Pins 9 and 16). The AD809 senses the common-mode signal at these pins as less than valid PECL and selects the TTL/CMOS input as active. 6 VCC1 Digital VCC for Internal Logic 7 CF1 Loop Damping Capacitor 8 CF2 Loop Damping Capacitor 9 AVEE Analog VEE 10 TTL/CMOSIN TTL/CMOS Reference Clock Input 11 AVCC1 Analog VCC for PLL 12 CLKINN PECL Differential Reference Clock Input 13 CLKIN PECL Differential Reference Clock Input 14 AVCC2 Analog VCC for Input Stage 15 MUX Input Signal Mux Control Input 16 VEE Digital VEE Table II. Applying a PECL/ECL or CMOS/TTL Reference Input to the AD809 AD809 Phase Skew The AD809 output is in phase with the input. The falling edge at Pin 4, CLKOUTN, occurs 700 ps before the rising edge at Pin 10, TTL/CMOSIN at 27°C. The phase skew remains relatively constant over temperature. Refer to Table III for phase skew data. PIN CONFIGURATION PECLINN 1 PECLIN 2 VCC2 3 16 VEE Table III. Phase Skew vs. Temperature 15 MUX 14 AVCC2 AD809 13 CLKIN TOP VIEW CLKOUT 5 (Not to Scale) 12 CLKINN CLKOUTN 4 VCC1 6 11 AVCC1 CF1 7 10 TTL/CMOSIN CF2 8 9 AVEE Temperature (8C) Skew (CLKOUTN, Pin 4, Relative to TTL/CMOSIN, Pin 10 Measured in ps at Package Pins) –35 –20 0 10 30 50 70 80 90 100 –1000 –950 –850 –750 –700 –600 –450 –450 –350 –250 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD809 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. A –3– WARNING! ESD SENSITIVE DEVICE AD809 Maximum, Minimum and Typical Specifications Typical Characteristic Curves Specifications for every parameter are derived from statistical analyses of data taken on multiple devices from multiple wafer lots. Typical specifications are the mean of the distribution of the data for that parameter. If a parameter has a maximum (or a minimum), that value is calculated by adding to (or subtracting from) the mean six times the standard deviation of the distribution. This procedure is intended to tolerate production variations: if the mean shifts by 1.5 standard deviations, the remaining 4.5 standard deviations still provide a failure rate of only 3.4 parts per million. For all tested parameters, the test limits are guardbanded to account for tester variation to thus guarantee that no device is shipped outside of data sheet specifications. AD809 FREQUENCY SYNTHESIZER JITTER DISTRIBUTION MATRIX 75 DEVICES (3 LOTS) [ECL, TTL] × [×8, ×16] × [RISE, FALL] × [+4.5V, +5.0V, +5.5V] × [–40°C, +25°C, +85°C] 1200 100 CUMULATIVE % POPULATION – Devices 1000 90 THIS CHART DESCRIBES THE AD809 OUTPUT JITTER SPECIFICATION OVER MANY CONDITIONS. THE DATA REPRESENTED ARE TAKEN WITH RESPECT TO THE RISING AND FALLING EDGES, FOR EACH FREQUENCY RANGE, LOCKED TO EITHER TTL OR ECL INPUT, OVER ALL TEMPERATURE AND SUPPLY CONDITIONS. 800 600 80 70 60 50 40 400 30 FREQUENCY 20 200 Capture and Tracking Range CUMULATIVE – % DEFINITION OF TERMS 10 This is the range of input data rates over which the AD809 will remain in lock. 0 Jitter 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 More RMS JITTER – Degrees This is the dynamic displacement of digital signal edges from their long term average positions, measured in degrees rms. Jitter on the input clock causes jitter on the synthesized clock. 1.9 Output Jitter 1.8 This is the jitter on the synthesized clock (OUTPUT, OUTPUT), in degrees rms. 1.7 RMS JITTER – Degrees Figure 2. Jitter Histogram Jitter Transfer The AD809 exhibits a low-pass filter response to jitter applied to its input data. Bandwidth This describes the frequency at which the AD809 attenuates sinusoidal input jitter by 3 dB. TA = +25°C VCC = +5V 1.6 1.5 1.4 1.3 19.44MHz 9 72MHz 1.2 Peaking 1.1 This describes the maximum jitter gain of the AD809 in dB. 1.0 Damping Factor, z Damping factor, ζ describes the compensation of the second order PLL. A larger value of ζ corresponds to more damping and less peaking in the jitter transfer function. 0 10 20 30 40 50 60 70 INPUT DUTY CYCLE – % 80 90 100 Figure 3. Jitter vs. Input Duty Cycle Duty Cycle Tolerance The AD809 exhibits a duty cycle tolerance that is measured by applying an input signal (nominal input frequency) with a known duty cycle imbalance and measuring the ×8 or ×16 output frequency. Symmetry-Recovered Clock Duty Cycle Symmetry is calculated as (100× on time)/period, where on time equals the time that the clock signal is greater than the midpoint between its “0” level and its “1” level. –4– REV. A AD809 USING THE AD809 Ground Planes VCC1 Use of one ground plane for connections to both analog and digital grounds is recommended. Synthesizer Input TTL/CMOSIN 2*ITTL 2*ITTL 80µA OR 0µA 80µA OR 0µA Power Supply Connections Use of a 10 µF capacitor between VCC and ground is recommended. Care should be taken to isolate the +5 V power trace to VCC2 (Pin 3). The VCC2 pin is used inside the device to provide the CLKOUT/CLKOUTN signals. 500Ω VEE Use of a trace connecting Pin 14 and Pin 6 (AVCC2 and VCC1 respectively) is recommended. Use of 0.1 µF capacitors between IC power supply and ground is recommended. Power supply decoupling should take place as close to the IC as possible. Refer to the schematic, Figure 5, for advised connections. VCC1 7.5kΩ Synthesizer Input CLKIN/CLKINN PECL INPUT Transmission Lines Use of 50 Ω transmission lines are recommended for PECL inputs. 7.5kΩ 500Ω ITTL 500Ω 40µA 40µA Terminations Termination resistors should be used for PECL input signals. Metal, thick film, 1% tolerance resistors are recommended. Termination resistors for the PECL input signals should be placed as close as possible to the PECL input pins. VEE VCC2 Connections from the power supply to load resistors for input and output signals should be individual, not daisy chained. This will avoid crosstalk on these signals. 460Ω 460Ω PLL Differential Output Stage– CLKOUT/CLKOUTN Loop Damping Capacitor, C D DIFFERENTIAL OUTPUT A ceramic capacitor may be used for the loop damping capacitor. A 22 nF capacitor provides a damping factor of 10. 2.6mA VEE Figure 4. Simplified Schematics C1 0.1µF J5 R6 3.65kΩ J1 C2 0.1µF ECL INN JUMPER W2 50Ω STRIP LINE EQUAL LENGTH R5 301Ω R2 49.9Ω R1 49.9Ω 2 PECLIN J3 C4 0.1µF C7 R7 100Ω J4 C5 0.1µF R8 100Ω R16 301Ω VEE 16 AVCC2 14 4 CLKOUTN CLKIN 13 R17 3.65kΩ JUMPER W3 MUX 15 3 VCC2 5 CLKOUT CLKOUT C12 0.1µF +5V AD809 1 PECLINN ECL IN MUX EXT GND 16-PIN SOIC SOLDERED TO BOARD J2 C3 0.1µF CLKOUTN JUMPER W1 R14 49.9Ω C9 R15 49.9Ω C13 0.1µF J6 C14 0.1µF J7 C15 0.1µF J8 CLKIN CLKINN 12 CLKINN R3 C6 100Ω 0.1µF R4 100Ω R11 154Ω R12 154Ω C8 TP1 CD TP2 VECTOR PINS SPACED FOR THROUGH-HOLE CAPACITOR ON VECTOR CUPS. COMPONENT SHOWN FOR REFERENCE ONLY. 6 VCC1 AVCC1 11 7 CF1 TTL/CMOSIN 10 8 CF2 AVEE 9 C10 CMOS/TTL IN R13 49.9Ω GUARD RING NOTE: C7–C10 ARE 0.1µF BYPASS CAPACITORS C11 10µF TP3 +5V RIGHT ANGLE SMA CONNECTOR OUTER SHELL TO GND PLANE TP4 GND ALL RESISTORS ARE 1% 1/8 WATT SURFACE MOUNT TPx TEST POINTS ARE VECTOR PINS Figure 5. Evaluation Board Schematic REV. A –5– AD809 Figure 6. Evaluation Board: Component Side Figure 7. Evaluation Board: Solder Side –6– REV. A AD809 Figure 8. Evaluation Board: INT2 REV. A –7– AD809 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16 C2045a–2–1/97 16-Lead Small Outline IC Package (R-16A) 9 0.1574 (4.00) 0.1497 (3.80) PIN 1 0.2440 (6.20) 0.2284 (5.80) 8 1 0.3937 (10.00) 0.3859 (9.80) 0.0196 (0.50) x 45 ° 0.0099 (0.25) 0.0688 (1.75) 0.0532 (1.35) 0.0500 (1.27) BSC 0.0192 (0.49) 0.0138 (0.35) 0.0099 (0.25) 0.0075 (0.19) 8° 0° 0.0500 (1.27) 0.0160 (0.41) PRINTED IN U.S.A. 0.0098 (0.25) 0.0040 (0.10) –8– REV. A