Revised November 1999 100311 Low Skew 1:9 Differential Clock Driver General Description Features The 100311 contains nine low skew differential drivers, designed for generation of multiple, minimum skew differential clocks from a single differential input (CLKIN, CLKIN). If a single-ended input is desired, the VBB output pin may be used to drive the remaining input line. A HIGH on the enable pin (EN) will force a LOW on all of the CLKn outputs and a HIGH on all of the CLKn output pins. The 100311 is ideal for distributing a signal throughout a system without worrying about the original signal becoming too corrupted by undesirable delays and skew. ■ Low output-to-output skew ■ 2000V ESD protection ■ 1:9 low skew clock driver ■ Differential inputs and outputs ■ Available to industrial grade temperature range (PLCC package only) Ordering Code: Order Number Package Number Package Description 100311QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 100311QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range (−40°C to +85°C) Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram 28-Pin PLCC Pin Descriptions Truth Table Pin Names Description CLKIN, CLKIN EN CLKIN CLKIN EN Differential Clock Inputs L H Enable H L CLK0–8, CLK0–8 Differential Clock Outputs X X VBB VBB Output NC No Connect © 1999 Fairchild Semiconductor Corporation DS010648 CLKn CLKn L L H L H L H L H www.fairchildsemi.com 100311 Low Skew 1:9 Differential Clock Driver February 1990 100311 Absolute Maximum Ratings(Note 1) Storage Temperature (TSTG) −65°C to +150°C +150°C Maximum Junction Temperature (TJ) Pin Potential to Ground Pin (VEE) Input Voltage (DC) Recommended Operating Conditions −7.0V to +0.5V Case Temperature (TC) VEE to +0.5V Output Current (DC Output HIGH) −50 mA ESD (Note 2) ≥2000V 0°C to +85°C Commercial −40°C to +85°C Industrial −5.7V to −4.2V Supply Voltage (VEE) Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 2: ESD testing conforms to MIL-STD-883, Method 3015. Commercial Version DC Electrical Characteristics (Note 3) VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C Min Typ Max Units VOH Symbol Output HIGH Voltage Parameter −1025 −955 −870 mV VIN = VIH (Max) Loading with VOL Output LOW Voltage −1830 −1705 −1620 mV or VIL (Min) 50Ω to −2.0V VOHC Output HIGH Voltage −1035 mV VIN = VIH Loading with VOLC Output LOW Voltage −1610 mV or VIL (Max) 50Ω to −2.0V VBB Output Reference Voltage −1260 mV IVBB = −300 µA mV Required for Full Output Swing −1380 −1320 Conditions VDIFF Input Voltage Differential 150 VCM Common Mode Voltage VCC − 2.0 VCC − 0.5 V VIH Input HIGH Voltage −1165 −870 mV Guaranteed HIGH Signal for VIL Input LOW Voltage −1830 −1475 mV Guaranteed LOW Signal for IIL Input LOW Current 0.50 IIH Input HIGH Current All Inputs All Inputs µA VIN = VIL (Min) VIN = VIH (Max) CLKIN, CLKIN 100 EN 250 ICBO Input Leakage Current −10 IEE Power Supply Current −115 −57 µA µA VIN = VEE mA Inputs Open Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. www.fairchildsemi.com 2 100311 Commercial Version (Continued) AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol fMAX Parameter Max Toggle Frequency TC = 0°C Min Typ TC = +25°C Max 750 Min Typ TC = +85°C Max 750 Min Typ Units Max 750 Conditions MHz (Note 4) ns Figure 3 ns Figure 2 CLKIN to Qn tPLH Propagation Delay, tPHL CLKINn to CLKn Differential 0.75 0.84 0.95 0.75 0.86 0.95 0.84 0.93 1.04 Single-Ended 0.65 0.90 1.05 0.67 0.93 1.17 0.74 1.06 1.24 tPLH Propagation Delay 0.75 1.03 1.20 0.80 1.05 1.25 0.85 1.12 1.35 tPHL SEL to Output tPS LH–HL Skew 10 30 10 30 10 30 tOSLH Gate–Gate Skew LH 20 50 20 50 20 50 tOSHL Gate–Gate Skew HL 20 50 20 50 20 50 tOST Gate–Gate LH–HL Skew 30 60 30 60 30 60 tS Setup Time (Note 5)(Note 8) ps (Note 6)(Note 8) (Note 6)(Note 8) (Note 7)(Note 8) 250 250 300 ps 0 0 0 ps 300 300 300 ps ENn to CLKINn tH Hold Time ENn to CLKINn tR Release Time ENn to CLKINn tTLH Transition Time tTHL 20% to 80%, 80% to 20% 275 500 750 275 480 750 275 460 750 ps Figure 4 Note 4: fMAX = the highest frequency at which output VOL/V OH levels still meet VIN specifications. The F311 will function @ 1 GHz. Note 5: tPS describes opposite edge skews, i.e. the difference between the delay of a differential output signal pair’s LOW-to-HIGH and HIGH-to-LOW propagation delays. With differential signal pairs, a LOW-to-HIGH or HIGH-to-LOW transition is defined as the transition of the true output or input pin. Note 6: tOSLH describes in-phase gate-to-gate differential propagation skews with all differential outputs going LOW-to-HIGH; tOSHL describes the same conditions except with the outputs going HIGH-to-LOW. Note 7: tOST describes the maximum worst case difference in any of the tPS, tOSLH or tOST delay paths combined. Note 8: The skew specifications pertain to differential I/O paths. Industrial Version DC Electrical Characteristics (Note 9) VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −40°C to +85°C Symbol Parameter TC = −40°C Units Conditions Min Max Output HIGH Voltage −1085 −870 −1025 −870 mV VIN = VIH (Max) Loading with VOL Output LOW Voltage −1830 −1575 −1830 −1620 mV or VIL (Min) 50Ω to −2.0V −1095 mV VIN = VIH Loading with −1610 mV or VIL (Min) 50Ω to −2.0V −1260 mV IVBB = −300 µA mV Required for Full Output Swing VOHC Output HIGH Voltage Output LOW Voltage VBB Output Reference Voltage VDIFF Input Voltage Differential VCM Common Mode Voltage VIH Input HIGH Voltage Max TC = 0°C to +85°C VOH VOLC Min −1035 −1565 −1395 −1255 −1380 150 150 VCC − 2.0 VCC − 0.5 VCC − 2.0 VCC − 0.5 −1170 −870 −1165 −870 V mV Guaranteed HIGH Signal for All Inputs 3 www.fairchildsemi.com 100311 Industrial Version (Continued) DC Electrical Characteristics (Note 9) VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol TC = −40°C Parameter TC = 0°C to +85°C Min Max Min Max −1480 −1830 −1475 VIL Input LOW Voltage −1830 IIL Input LOW Current 0.50 IIH Input HIGH Current Units mV Conditions Guaranteed LOW Signal for All Inputs µA 0.50 VIN = VIL (Min) VIN = VIH (Max) CLKIN, CLKIN 100 100 EN 250 250 ICBO Input Leakage Current −10 IEE Power Supply Current −115 VPP Minimum Input Swing 150 VCMR Common Mode Range VCC−2.0 µA −10 −57 −115 VCC−0.5 VCC−2.0 −57 150 µA VIN = VEE mA Inputs Open mV VCC−0.5 V Note 9: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol TC = −40°C Parameter Min fMAX Max Toggle Frequency Typ TC = +25°C Max 750 Min Typ TC = +85°C Max 750 Min Typ Units Conditions Max 750 MHz (Note 10) ns Figure 3 ns Figure 2 CLKIN to Qn tPLH Propagation Delay, tPHL CLKINn to CLKn Differential 0.72 0.81 0.92 0.77 0.86 0.95 0.84 0.93 1.04 Single-Ended 0.62 0.89 1.02 0.67 0.93 1.17 0.74 1.06 1.24 tPLH Propagation Delay 0.70 0.97 1.20 0.80 1.05 1.25 0.85 1.12 1.35 tPHL SEL to Output tPS LH–HL Skew 10 30 10 30 10 30 tOSLH Gate–Gate Skew LH 20 50 20 50 20 50 tOSHL Gate–Gate Skew HL 20 50 20 50 20 50 tOST Gate–Gate LH–HL Skew 30 60 30 60 30 60 tS Setup Time (Note 11)(Note 14) ps (Note 12)(Note 14) (Note 12)(Note 14) (Note 13)(Note 14) 250 250 300 ps 0 0 0 ps 300 300 300 ps ENn to CLKINn tH Hold Time ENn to CLKINn tR Release Time ENn to CLKINn tTLH Transition Time tTHL 20% to 80%, 80% to 20% 275 500 750 275 480 750 275 460 750 ps Figure 4 Note 10: fMAX = the highest frequency of which output VOL/VOH levels still meet VIN specifications. The F311 will function @ 1 GHz Note 11: tPS describes opposite edge skews, i.e. the difference between the delay of a differential output signal pair's LOW-to-HIGH and HIGH-to-LOW propagation delays. With differential signal pairs, a LOW-to-HIGH or HIGH-to-LOW transition is defined as the transition of the true output or input pin. Note 12: tOSLH describes in-phase gate differential propagation skews with all differential outputs going LOW-to-HIGH; tOSHL describes the same conditions except with the outputs going HIGH-to-LOW. Note 13: tOST describes the maximum worst case difference in any of the tPS, tOSLH or tOST delay paths combined. Note 14: The skew specifications pertain to differential I/O paths. www.fairchildsemi.com 4 100311 Test Circuit Note: Shown for testing CLKIN to CLK1 in the differential mode. L1, L2, L3 and L4 = equal length 50Ω impedance lines. All unused inputs and outputs are loaded with 50Ω in parallel with ≤ 3 pF to GND. Scope should have 50Ω input terminator internally. FIGURE 1. AC Test Circuit Switching Waveforms FIGURE 2. Propagation Delay, EN to Outputs FIGURE 3. Propagation Delay, CLKIN/CLKIN to Outputs FIGURE 4. Transition Times 5 www.fairchildsemi.com 100311 Low Skew 1:9 Differential Clock Driver Physical Dimensions inches (millimeters) unless otherwise noted 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 6