12-Bit, 65 MSPS, Dual ADC AD15252 FUNCTIONAL BLOCK DIAGRAM FEATURES AD15252 12-bit, 65 MSPS dual ADC Differential input with 100 Ω input impedance Full-scale analog input: 296 mV p-p 170 MHz, 3 dB bandwidth SNR (−9 dBFS): 64 dBFS (70 MHz AIN), 64 dBFS (140 MHz AIN) SFDR (−9 dBFS): 77 dBFS (70 MHz AIN), 73 dBFS (140 MHz AIN) 435 mW per channel Dual parallel output buses Out-of-range indicators Independent clocks Duty cycle stabilizer Twos complement or offset binary data format OTR_A PDWNA CLKA INA LPF DATA BUS A OEB_A DFS PDWNB CLKB DATA BUS B INB 05154-001 LPF OEB_B APPLICATIONS OTR_B Figure 1. Antijam GPS receivers Wireless and wired broadband communications Communications test equipment GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD15252 is a dual, 12-bit, 65 MSPS, analog-to-digital converter (ADC). It features a differential front-end amplification circuit followed by a sample-and-hold amplifier and multistage pipeline ADC. It is designed to operate with a 3.3 V analog supply and a 2.5 V/3.3 V digital supply. Each input is fully differential, ac-coupled, and terminated in 100 Ω input impedances. The full-scale differential signal input range is 296 mV p-p. 1. Dual 12-bit, 65 MSPS ADC with integrated analog signal conditioning optimized for antijam global positioning system receiver (AJ-GPS) applications. 2. Operates from a single 3.3 V power supply and features a separate digital output driver supply to accommodate 2.5 V and 3.3 V logic families. 3. Packaged in a space-saving 8 mm × 8 mm chip scale package ball grid array (CSP_BGA) and is specified over the industrial temperature range (–40°C to +85°C). Two parallel, 12-bit digital output buses provide data flow from the ADCs. The digital output data is presented in either straight binary or twos complement format. Out-of-range (OTR) signals indicate an overflow condition, which can be used with the most significant bit to determine low or high overflow. Dual single-ended clock inputs control all internal conversion cycles. A duty cycle stabilizer allows wide variations in the clock duty cycle while maintaining excellent performance. The AD15252 is optimized for applications in antijam global positioning receivers and is well suited for communications applications. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. AD15252 TABLE OF CONTENTS Electrical Characteristics ................................................................. 3 Clock Input and Considerations .............................................. 11 Absolute Maximum Ratings............................................................ 5 Power Dissipation and Standby Mode .................................... 11 ESD Caution.................................................................................. 5 Digital Outputs ........................................................................... 12 Pin Configuration and Function Descriptions............................. 6 Timing ......................................................................................... 12 Typical Performance Characteristics ............................................. 8 Data Format ................................................................................ 12 Theory of Operation ...................................................................... 11 PCB and Evaluation Board............................................................ 13 Analog Input ............................................................................... 11 Outline Dimensions ....................................................................... 19 Voltage Reference ....................................................................... 11 Ordering Guide .......................................................................... 19 REVISION HISTORY 8/05—Revision 0: Initial Version Rev. 0 | Page 2 of 20 AD15252 ELECTRICAL CHARACTERISTICS AVDD = 3.3 V, DRVDD = 2.5 V, encode = 65 MSPS, CLK_A = CLK_B, AIN = −9 dBFS differential input, TA= 25°C, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error MATCHING CHARACTERISTICS Offset Error Gain Error Input Referred Noise ANALOG INPUT Input Range Input Resistance (RIN) 1 Input Capacitance (CIN)1 CLOCK INPUTS High Level Input Voltage (VIH) Low Level Input Voltage (VIL) High Level Input Current (IIH) Low Level Input Current (IIL) Input Capacitance (CIN) LOGIC OUTPUTS High Level Output Voltage (VOH) Low Level Output Voltage (VOL) INTERFACE TIMING Maximum Conversion Rate Minimum Conversion Rate Clock Period (tC) Clock Width High (tCH) Clock Width Low (tCL) Clock to Data (tOD) Pipeline Delay (Latency) POWER SUPPLIES Supply Voltages AVDD DRVDD Supply Currents AVDD DRVDD Total Power Dissipation Temp Test Level 25°C 25°C 25°C Full Full IV I I V V Full Full V V ±9 ±172 ppm/°C ppm/°C Full Full Full V V V ±2.0 ±1.0 0.87 % FSR % FSR LSB rms Full 25°C 25°C IV V V 296 100 1.8 mV p-p Ω pF Full Full Full Full Full IV IV IV IV V Full Full IV IV 2.49 Full Full Full Full Full Full Full VI IV V IV IV IV V 65 Full Full IV IV Full Full Full VI VI VI Rev. 0 | Page 3 of 20 Min −6 −12.5 Typ 12 Guaranteed ±1.7 ±2.0 ±0.35 ±0.8 Max Unit Bits +6 +12.5 % FSR % FSR LSB LSB 2.0 0.8 +10 +10 −10 −10 2 0.2 1 15.4 6.2 6.2 2 6 7 3.0 2.25 V V μA μA pF V V MSPS MSPS ns ns ns ns Cycles 3.3 2.5 3.6 3.6 V V 254 12 0.87 280 15 1.0 mA mA W AD15252 Parameter SIGNAL-TO-NOISE RATIO (SNR) fINPUT = 70 MHz fINPUT = 110 MHz fINPUT = 140 MHz SINAD fINPUT = 70 MHz fINPUT = 110 MHz fINPUT = 140 MHz THD fINPUT = 70 MHz fINPUT = 110 MHz fINPUT = 140 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fINPUT = 70 MHz fINPUT = 110 MHz fINPUT = 140 MHz CROSSTALK 1 Temp Test Level Min Typ 25°C 25°C 25°C I V I 62.7 64.2 64.1 64 dBFS dBFS dBFS 25°C 25°C 25°C I V I 63.9 63.7 63.3 dBFS dBFS dBFS Full Full Full V V V −76 −74 −72 dBFS dBFS dBFS 25°C 25°C 25°C 25°C I V I V 77.8 75.9 73.8 −70 dBFS dBFS dBFS dB 62.5 62.4 61.9 72.7 68 Max Unit Input resistance and capacitance shown as differential. Table 2. Explanation of Test Levels Test Level I II III IV V VI Description 100% production tested. 100% production tested at 25°C, and sample tested at specified temperatures. Sample tested only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. All devices are 100% production tested at 25°C, guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices. Rev. 0 | Page 4 of 20 AD15252 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter AVDD to AGND DRVDD to DRGND DRGND to AGND DRVDD to AVDD Analog Inputs Digital Outputs CLK Operational Case Temperature Storage Temperature Range Lead Temperature: Infrared, 15 sec Rating −0.3 V, +3.9 V −0.3 V, +3.9 V −0.3 V, +0.3 V −3.9 V, +3.9 V −0.3 V, AVDD + 0.3 V −0.3 V, DRVDD + 0.3 V −0.3 V, AVDD + 0.3 V −40°C to 85°C −65°C to 150°C 230°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 5 of 20 AD15252 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 8 7 6 5 4 3 2 1 A B C D E F H BOTTOM VIEW (Not to Scale) 05154-003 G Figure 2. Pin Configuration Table 4. Pin Function Descriptions Pin No. A1 Mnemonic VINA Description Analog Input Pin (+) for Channel A. A2 H1 VINA VINB Analog Input Pin (−) for Channel A. Analog Input Pin (+) for Channel B. H2 VINB Analog Input Pin (−) for Channel B. B4 CLK_A Clock Input Pin for Channel A. G4 CLK_B Clock Input Pin for Channel B. C4 PDWN_A Power-Down Function Selection for Channel A (Active High). F4 PDWN_B Power-Down Function Selection for Channel B (Active High). A4 OTR_A Out-of-Range Indicator for Channel A. E8 OTR_B Out-of-Range Indicator for Channel B. A3 VCM_A Channel A Common Mode. H3 VCM_B Channel B Common Mode. D4 OEB_A Output Enable for Channel A. Logic 0 enables Data Bus A; Logic 1 sets outputs to high-Z. E4 OEB_B Output Enable for Channel B. Logic 0 enables Data Bus B; Logic 1 sets outputs to high-Z. C5 D11_A(MSB) Channel A Data Output Bit 11 (MSB). A5 D10_A Channel A Data Output Bit 10. B5 D09_A Channel A Data Output Bit 9. A6 D08_A Channel A Data Output Bit 8. B6 D07_A Channel A Data Output Bit 7. A7 D06_A Channel A Data Output Bit 6. B7 D05_A Channel A Data Output Bit 5. A8 D04_A Channel A Data Output Bit 4. C6 D03_A Channel A Data Output Bit 3. B8 D02_A Channel A Data Output Bit 2. C7 D01_A Channel A Data Output Bit 1. C8 D00_A(LSB) Channel A Data Output Bit 0 (LSB). E3 DFS Data Output Format Select Bit (Logic 0 for offset binary, Logic 1 for twos complement). E7 D11_B(MSB) Channel B Data Output Bit 11 (MSB). F8 D10_B Channel B Data Output Bit 10. F7 D09_B Channel B Data Output Bit 9. G8 D08_B Channel B Data Output Bit 8. Rev. 0 | Page 6 of 20 AD15252 Pin No. F6 Mnemonic D07_B Description Channel B Data Output Bit 7. H8 D06_B Channel B Data Output Bit 6. G7 D05_B Channel B Data Output Bit 5. H7 D04_B Channel B Data Output Bit 4. G6 D03_B Channel B Data Output Bit 3. H6 D02_B Channel B Data Output Bit 2. G5 D01_B Channel B Data Output Bit 1. H5 D00_B Channel B Data Output Bit 0 (LSB). C1 to C3, F1 to F3 AVDD Analog Power Supply. B1 to B3, D3, G1 to G3 AGND Analog Ground. D6, E6 DRVDD Digital Output Driver Supply. D5, E5 DRGND Digital Output Ground. E1 REFT Differential Reference (+). E2 REFB Differential Reference (−). D1 VREF Voltage Reference. D2 REF_RTN Voltage Reference Return H4, F5, D7, D8 DNC1 to DNC4 No Connect. Rev. 0 | Page 7 of 20 AD15252 TYPICAL PERFORMANCE CHARACTERISTICS 0 90 –1 –2 85 –4 80 SFDR (dBFS) ATTENUATION (dB) –3 –5 –6 –7 –8 75 70 –9 –10 –12 10 60 –15 –14 –13 –12 –11 –10 –9 –8 –7 –6 –5 –4 –3 –2 –1 1000 100 FREQUENCY (MHz) 05154-007 05154-004 65 –11 0 INPUT AMPLITUDE (dBFS) Figure 3. Gain Flatness Figure 6. Single-Tone SFDR vs. AIN with fIN = 70 MHz 0 90 –0.25 85 –0.75 80 –1.00 SFDR (dBFS) –1.25 –1.50 –1.75 75 70 –2.00 –2.25 05154-005 65 –2.50 –2.75 120 125 130 135 140 145 150 155 60 –16 160 05154-008 30MHz FLATNESS (dB) –0.50 –14 –12 FREQUENCY (MHz) –10 –8 –6 –4 –2 0 INPUT AMPLITUDE (dBFS) Figure 4. Gain Flatness fIN =125MHz to 155 MHz Figure 7. Single-Tone SFDR vs. AIN with fIN = 110 MHz 0 90 –10 85 –30 SFDR (dBFS) 80 –40 –50 –60 75 70 –70 –80 –90 1 10 100 60 –16 1000 FREQUENCY (MHz) 05154-009 65 05154-006 CROSSTALK (dBFS) –20 –14 –12 –10 –8 –6 –4 –2 INPUT AMPLITUDE (dBFS) Figure 8. Single-Tone SFDR vs. AIN with fIN = 140 MHz Figure 5. Typical Crosstalk Rev. 0 | Page 8 of 20 0 AD15252 0.4 85 0.3 80 0.1 75 (DNL) SFDR/SNR (dBFS) 0.2 SFDR 70 0 –0.1 –0.2 65 SNR 60 70 110 05154-014 05154-010 –0.3 –0.4 140 0 512 1024 1536 FREQUENCY (MHz) 2048 2560 3072 3584 4096 3072 3584 4096 CODE Figure 9. Single-Tone SNR/SFDR vs. fIN Figure 12. Typical DNL 0.7 64.6 0.6 64.4 0.5 0.4 0.3 0.2 64.0 (INL) SINAD (dBFS) 64.2 63.8 0.1 0 –0.1 63.6 –0.2 –0.3 63.4 –0.4 63.0 70 110 05154-019 –0.5 05154-011 63.2 –0.6 –0.7 0 140 512 1024 1536 FREQUENCY (MHz) Figure 10. Single-Tone SINAD vs. fIN 2048 CODE 2560 Figure 13. Typical INL –68 0 1 –10 –70 –20 –30 MAGNITUDE (dB) –74 –76 –78 –40 –50 –60 –70 –80 2 –90 –80 3 4 5 6 –100 –110 –84 70 110 –120 –130 140 0 FREQUENCY (MHz) Figure 11. Single-Tone THD vs. fIN 05154-023 –82 05154-012 THD (dBFS) –72 3.25 6.50 9.75 13.00 16.25 19.50 22.75 26.00 29.25 32.50 FREQUENCY (MHz) Figure 14. Single-Tone FFT of Channel A Digitizing fIN = 70 MHz @ −9 dBFS While Channel B Digitizes fIN = 70 MHz @ −9 dBFS Rev. 0 | Page 9 of 20 AD15252 0 1 –10 –20 –20 –30 –30 –40 –40 MAGNITUDE (dB) –50 –60 –70 –80 3 2 5 4 –90 6 –60 –70 2 6 –80 4 5 3 –100 05154-024 –120 –130 0 3.25 6.50 05154-021 –110 –110 –120 –130 0 9.75 13.00 16.25 19.50 22.75 26.00 29.25 32.50 FREQUENCY (MHz) Figure 15. Single-Tone FFT of Channel B Digitizing fIN = 70 MHz @ −9 dBFS While Channel A Digitizes fIN = 70 MHz @ −9 dBFS 3.25 6.50 0 1 –30 –40 –40 MAGNITUDE (dB) –20 –30 –50 –60 –70 3 –90 2 6 1 –10 –20 –80 9.75 13.00 16.25 19.50 22.75 26.00 29.25 32.50 FREQUENCY (MHz) Figure 18. Single-Tone FFT of Channel A Digitizing fIN = 140 MHz @ −9 dBFS While Channel B Digitizes fIN = 140 MHz @ −9 dBFS 0 –10 MAGNITUDE (dB) –50 –90 –100 4 5 –50 –60 –70 2 6 –80 5 –90 –100 4 3 –100 –110 05154-025 –110 –120 –130 0 3.25 6.50 –120 –130 9.75 13.00 16.25 19.50 22.75 26.00 29.25 32.50 FREQUENCY (MHz) 0 Figure 16. Single-Tone FFT of Channel A Digitizing fIN = 110 MHz @ −9 dBFS While Channel B Digitizes fIN = 110 M z @ −9 dBFS 1 –20 –30 –40 –50 –60 –70 2 –80 3 –90 6 4 5 –100 05154-026 –110 –120 –130 0 3.25 6.50 3.25 6.50 9.75 13.00 16.25 19.50 22.75 26.00 29.25 32.50 FREQUENCY (MHz) Figure 19. Single-Tone FFT of Channel B Digitizing fIN = 140 MHz @ −9 dBFS While Channel A Digitizes fIN = 140 MHz @ −9dBFS 0 –10 MAGNITUDE (dB) 1 05154-022 MAGNITUDE (dB) 0 –10 9.75 13.00 16.25 19.50 22.75 26.00 29.25 32.50 FREQUENCY (MHz) Figure 17. Single-Tone FFT of Channel B Digitizing fIN = 110 MHz @ −9 dBFS While Channel A Digitizes fIN = 110 MHz @ −9 dBFS Rev. 0 | Page 10 of 20 AD15252 THEORY OF OPERATION The AD15252 consists of two high performance ADC channels. The dual ADC paths are independent, except for a shared internal band gap reference source, VREF. Each path consists of a differential front end amplification circuit followed by a sample-and-hold amplifier and multistage pipeline ADC. High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given full-scale input frequency (fINPUT) due only to aperture jitter (tJ) can be calculated by The output-staging block aligns the data, carries out the error correction, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. In the equation, the rms aperture jitter, tJ, represents the rootsum square of all jitter sources, which includes the clock input, analog input signal, and ADC aperture jitter specification. ANALOG INPUT Each analog input is fully differential, allowing sampling of differential input signals. The differential input signals are accoupled and terminated in 100 Ω input impedances. The fullscale differential signal input range is 296 mV p-p. VOLTAGE REFERENCE The internal voltage reference of the ADC is pin strapped to a fixed value of 0.5 V. A 10 μF capacitor should be used between REFT and REFB. CLOCK INPUT AND CONSIDERATIONS Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, can be sensitive to clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. SNR Degradation = 20 × log 10 (1/2 × p × f INPUT × tJ) Undersampling applications are particularly sensitive to jitter. For optimal performance, especially in cases where aperture jitter can affect the dynamic range of the AD15252, it is important to minimize input clock jitter. The clock input circuitry should use stable references, for example, using analog power and ground planes to generate the valid high and low digital levels for the AD15252 clock input. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. POWER DISSIPATION AND STANDBY MODE The AD15252 provides separate clock inputs for each channel. The optimum performance is achieved with the clocks operated at the same frequency and phase. Clocking the channels asynchronously can significantly degrade performance. In some applications, it is desirable to skew the clock timing of adjacent channels. The AD15252’s separate clock inputs allow clock timing skew (typically ±1 ns) between the channels without significant performance degradation. The AD15252 contains two internal clock duty cycle stabilizers (DCS), one for each converter, which retime the nonsampling edge, providing an internal clock with a nominal 50% duty cycle. Input clock rates of over 40 MHz can use the DCS so that a wide range of input clock duty cycles can be accommodated. Maintaining a 50% duty cycle clock is particularly important in high speed applications, when proper track-and-hold times for the converter are required to maintain high performance. The duty cycle stabilizer uses a delay-locked loop to create the nonsampling edge. As a result, any change to the sampling frequency requires approximately 2 μs to 3 μs to allow the DLL to acquire and settle to the new rate. The power dissipated by the AD15252 is proportional to its sampling rates. The digital (DRVDD) power dissipation is determined primarily by the strength of the digital drivers and the load on each output bit. The digital drive current can be calculated by IDRVDD = VDRVDD × CLOAD × fCLOCK × N where: N is the number of bits changing. CLOAD is the average load on the digital pins that changed. The analog circuitry is optimally biased so that each speed grade provides excellent performance while affording reduced power consumption. Each speed grade dissipates a baseline power at low sample rates that increase with clock frequency. Either channel of the AD15252 can be placed into standby mode independently by asserting the PDWN_A or PDWN_B pins. The minimum standby power is achieved when both channels are placed into full power-down mode using PDWN_A = PDWN_B = high. Under this condition, the internal references are powered down. When either or both of the channel paths are enabled after a power-down, the wake-up time is directly related to the recharging of the REFT and REFB decoupling capacitors and to the duration of the power-down. Typically, it takes approximately 5 ms to restore full operation with fully discharged 10 μF decoupling capacitors on REFT and REFB. Rev. 0 | Page 11 of 20 AD15252 A single channel can be powered down for moderate power savings. The powered-down channel shuts down internal circuits, but both the reference buffers and shared reference remain powered. Because the buffer and voltage reference remain powered, the wake-up time is reduced to several clock cycles. The data format can be selected for either offset binary or twos complement. This is discussed later in the Data Format section. TIMING The AD15252 provides latched data outputs with a pipeline delay of seven clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of the clock signal. Refer to Figure 20 for a detailed timing diagram. When using only one channel of the AD15252, the clock for the disabled channel should also be disabled, or distortion occurs in the channel in use. The length of the output data lines and the loads placed on them should be minimized to reduce transients within the AD15252. These transients can detract from the converter’s dynamic performance. DIGITAL OUTPUTS The AD15252 output drivers can be configured to interface with 2.5 V or 3.3 V logic families by matching DRVDD to the digital supply of the interfaced logic. The output drivers are sized to provide sufficient output current to drive a wide variety of logic families. However, large drive currents tend to cause current glitches on the supplies, which can affect converter performance. Applications requiring the ADC to drive large capacitive loads or large fan-outs can require external buffers or latches. A–1 A1 A0 The lowest typical conversion rate of the AD15252 is 1 MSPS. At clock rates below 1 MSPS, dynamic performance can degrade. DATA FORMAT The AD15252 data output format can be configured for either twos complement or offset binary. This is controlled by the data format select pin (DFS). Connecting DFS to AGND produces offset binary output data. Conversely, connecting DFS to AVDD formats the output data as twos complement. A7 A3 A4 B–1 B1 B0 ANALOG INPUT ADC A A8 A2 A6 A5 B8 B2 ANALOG INPUT ADC B B7 B3 B4 B6 B5 CLK_A = CLK_B = MUX_SELECT A–7 tODF B–7 A–6 B–6 A–5 B–5 A–4 B–4 A–3 B–3 A–2 B–2 A–1 B–1 A0 B0 A1 D0_A –D11_A 05154-002 B–8 tODR Figure 20. Example of Multiplexed Data Format Using the Channel A Output and the Same Clock Tied to CLK_A, CLK_B, and MUX_SELECT Rev. 0 | Page 12 of 20 AD15252 Figure 21. AD15252 Evaluation Board Top Silk 05154-029 05154-027 PCB AND EVALUATION BOARD Figure 22. AD15252 Evaluation Board Top Paste 05154-030 05154-028 Figure 23. AD15252 Evaluation Board Top Mask Figure 24. AD15252 Evaluation Board Top Signal Rev. 0 | Page 13 of 20 05154-031 05154-033 AD15252 05154-032 05154-034 Figure 27. AD15252 Evaluation Board Bottom Signal Figure 25. AD15252 Evaluation Board Power Plane Figure 28. AD15252 Evaluation Board Bottom Mask Figure 26. AD15252 Evaluation Board Ground Plane Rev. 0 | Page 14 of 20 05154-035 AD15252 Figure 29. AD15252 Evaluation Board Bottom Paste Rev. 0 | Page 15 of 20 1 2 3 4 +VCC AGND AVDD AGND 05154-036 AGND R4 DNI J2 Z = 50Ω O AGND R1 DNI 6 T4 1 + SEC SEC 1 4 3 TC1-1-13M PRI 6 T1 C28 10μF L1 2 DGND + C7 10μF DIGITAL +2.5V DGND 1 +VDD 4 3 TC1-1-13M PRI +VDD DGND DRVDD DGND J1 Z = 50Ω O Z5.531.3425.0 J5 Z5.531.3425.0 1 2 3 4 TC1-1-13M 3 4 TC1-1-13M 3 4 PRI SEC R8 0Ω R7 0Ω AGND R97 DNI R10 0Ω R9 0Ω AGND R96 DNI C29 0.1μF AGND AGND 1 PRI 6 T2 1 6 T3 2 VIN+A AGND L2 VIN+B VIN–A R11 100Ω + VIN–B R12 100Ω C30 10μF 1 +VCC AGND AGND DUTAVDD LSB1_A LSB0_A LSB1_B LSB0_B C24 0.1μF VIN+B VIN–B OEB_B DUTCLK_B PDWN_B DFS C23 0.1μF VIN+A VIN–A C4 10μF E2 D7 D8 F5 H4 H1 H2 H3 E1 E4 G4 F4 E3 D2 C3 10μF A1 A2 A3 D1 D4 B4 C4 OEB_A CLK_A PDWN_A C26 0.1μF C1 0.1μF L3 2 REFB DNC DNC DNC DNC VINB VINB VCM_B REFT OEB_B CLK_B PDWN_B DFS AGND C8 0.1μF DUTAVDD + C13 10μF REF_RTN VINA VINA VCM_A VREF AGND AGND + 1 AVDD C9 10μF DUTAVDD C31 0.1μF OEB_A DUTCLK_A PDWN_A AGND + C10 10μF ANALOG +3.3V C1 C2 C3 F1 F2 F3 E6 D6 U1 AD15252 AGND DGND D11_B D10_B D09_B D08_B D07_B D06_B D05_B D04_B D03_B D02_B D01_B D00_B OTR_B D11_A D10_A D09_A D08_A D07_A D06_A D05_A D04_A D03_A D02_A D01_A D00_A OTR_A C27 0.1μF + 1 + C15 10μF E7 F8 F7 G8 F6 H8 G7 H7 G6 H6 G5 H5 E8 C5 A5 B5 A6 B6 A7 B7 A8 C6 B8 C7 C8 A4 D11_B D10_B D09_B D08_B D07_B D06_B D05_B D04_B D03_B D02_B D01_B D00_B OTR_B D11_A D10_A D09_A D08_A D07_A D06_A D05_A D04_A D03_A D02_A D01_A D00_A OTR_A LSB_B MSB_B LSB_A MSB_A DGND C20 0.1μF DUTDRVDD DUTDVDD L4 2 DGND DRVDD C2 10μF AVDD AVDD AVDD AVDD AVDD AVDD DRVDD DRVDD AGND AGND AGND AGND AGND AGND AGND DRGND DRGND Rev. 0 | Page 16 of 20 SEC Figure 30. AD15252 Evaluation Board Schematic: Analog Front End ADC B1 B2 B3 D3 G1 G2 G3 D5 E5 J6 JP1 DFS PDWN_B OEB_B OEB_A DGND JP2 JP4 OEB_B JP3 OEB_A JP5 DFS PDWN_B R2 5.1kΩ ANALOG +3.3V R3 5.1kΩ ANALOG +3.3V R5 5.1kΩ ANALOG +3.3V R6 5.1kΩ ANALOG +3.3V PDWN_A R81 5.1kΩ ANALOG +3.3V DGND E11 E12 AGND DGND DGND E10 E8 DGND DGND DRVDD E9 E7 AGND E6 E4 E2 +VCC AGND E5 E3 AGND AGND E1 PDWN_A JP9 JP10 AGND +VDD AVDD AGND SHUNT ON = GND OFF = +3.3V AD15252 AD15252 1 19 DATACLK_A OTR_A D06_A D07_A D08_A D09_A D10_A D11_A R13 150Ω R14 150Ω R20 150Ω R19 150Ω R18 150Ω R17 150Ω R16 150Ω R15 150Ω 2 3 4 5 6 7 8 9 10 OE1 OE2 VCC IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 GND O0 O1 O2 O3 O4 O5 O6 O7 LSB1_A D00_A D01_A D02_A D03_A D04_A D05_A R28 DNI R27 DNI R26 150Ω R25 150Ω R24 150Ω R23 150Ω R22 150Ω R21 150Ω C16 0.1μF DGND 18 17 16 15 14 13 12 11 U3 LSB1_AX 1 19 VCC OE1 OE2 2 3 4 5 6 7 8 9 10 O0 O1 O2 O3 O4 O5 O6 O7 IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 GND R45 22.1Ω R46 22.1Ω R52 22.1Ω R51 22.1Ω R50 22.1Ω R49 22.1Ω R48 22.1Ω R47 22.1Ω DIGITAL C17 +2.5V 0.1μF 20 R60 22.1Ω R59 22.1Ω DGND R58 22.1Ω R57 22.1Ω R56 22.1Ω R55 22.1Ω R54 22.1Ω R53 22.1Ω 74VHC541MTC LSB0_AX LSB0_A 20 18 17 16 15 14 13 12 11 DATACLK_A2 OTR_A2 D06_A2 D07_A2 D08_A2 D09_A2 D10_A2 D11_A2 LSB0_A2 LSB1_A2 D00_A2 D01_A2 TP5 D02_A2 TSW-140-08-S-D-RA 79 77 75 73 71 69 67 65 63 61 59 57 55 53 51 49 47 45 43 41 D03_A2 J7:C D04_A2 DIGITAL +2.5V 1 19 D05_B D06_B D07_B D08_B D09_B D10_B D11_B OTR_B R36 150Ω R35 150Ω R34 150Ω R33 150Ω R32 150Ω R31 150Ω R30 150Ω R29 150Ω 2 3 4 5 6 7 8 9 10 OE1 OE2 VCC IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 GND O0 O1 O2 O3 O4 O5 O6 O7 D00_B D01_B D02_B D03_B D04_B LSB0_B DATACLK_B R42 DNI R41 150Ω R40 150Ω R39 150Ω R38 150Ω U5 R37 150Ω R43 DNI R44 0Ω LSB1_AX 18 17 16 15 14 13 12 11 C22 0.1μF DGND 74VHC541MTC LSB0_AX LSB1_B 20 1 19 2 3 4 5 6 7 8 9 10 DGND OE1 OE2 VCC IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 GND O0 O1 O2 O3 O4 O5 O6 O7 DIGITAL C25 +2.5V 0.1μF 20 DGND 18 17 16 15 14 13 12 11 R68 22.1Ω R67 22.1Ω R66 22.1Ω R65 22.1Ω R64 22.1Ω R63 22.1Ω R62 22.1Ω R61 22.1Ω R74 22.1Ω R73 22.1Ω R72 22.1Ω R71 22.1Ω R70 22.1Ω R69 22.1Ω R75 22.1Ω R76 22.1Ω DATACLK_B2 OTR_B2 D06_B2 D07_B2 D08_B2 D09_B2 D10_B2 D11_B2 TSW-140-08-S-D-RA 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 TSW-140-08-S-D-RA 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 DGND DATACLK_B2 DGND D11_B2 D10_B2 D09_B2 D08_B2 D07_B2 D06_B2 D05_B2 D04_B2 D03_B2 D02_B2 D01_B2 D00_B2 LSB1_B2 LSB0_B2 OTR_B2 DGND LSB0_B2 J7:A J7:B DGND LSB1_B2 D00_B2 D01_B2 TP6 D02_B2 D03_B2 LSB1_AX LSB0_AX R77 0Ω R78 0Ω D04_B2 D05_B2 DGND LSB1_BX 74VHC541MTC LSB0_BX R79 0Ω R80 0Ω DGND Figure 31. AD15252 Evaluation Board Schematic: Digital Outputs Rev. 0 | Page 17 of 20 J7:D DGND D05_A2 74VHC541MTC U4 TSW-140-08-S-D-RA 80 78 76 74 72 70 68 66 64 62 60 58 56 54 52 50 48 46 44 42 DGND DATACLK_A2 DGND D11_A2 D10_A2 D09_A2 D08_A2 D07_A2 D06_A2 D05_A2 D04_A2 D03_A2 D02_A2 D01_A2 D00_A2 LSB1_A2 LSB0_A2 OTR_A2 DGND 05154-037 DIGITAL +2.5V U2 AD15252 5 U6:C 6 U6:D 8 9 74VHC04MTC 74VHC04MTC AGND ANALOG +3.3V C11 0.1μF CLK_A 3 AGND R83 49.9Ω C14 0.1μF JP8 AGND XTAL A = ENABLE B = DISABLE A B R98 100kΩ AGND 1 7 C21 0.1μF 8 74VHC04MTC DATACLK_A DELAY A = 1 DELAY B = 2 DELAY AGND 14 AGND Y1 14 74VHC04MTC DUTCLK_A 1 U6:A VCC 2 GND R85 0Ω AGND R92 DNI DUTCLK_A 74VHC04MTC 74VHC04MTC 7 R82 DNI U6:F 13 12 TP8 AGND VF140SHHL-65MHz DATACLK_A ANALOG +3.3V C12 0.1μF ANALOG +3.3V C19 0.1μF DATACLK_B AGND TP9 AGND J4 C6 0.1μF R84 49.9Ω R100 1kΩ R82 0Ω 14 1 VCC GND R99 1kΩ 7 R89 0Ω R88 0Ω U7:A 2 13 U7:F 12 R87 DNI 74VHC04MTC 74VHC04MTC DUTCLK_B R91 DNI AGND AGND AGND CLK_B 3 U7:B 4 74VHC04MTC U7:E 11 10 JP7 R95 TP10 DNI A B DUTCLK_B 74VHC04MTC DATACLK_B DELAY A = 1 DELAY B = 2 DELAY 5 U7:C 6 74VHC04MTC U7:D 9 8 74VHC04MTC AGND Figure 32. AD15252 Evaluation Board Schematic: Encode Rev. 0 | Page 18 of 20 05154-038 ANALOG +3.3V U6:E 11 10 ANALOG +3.3V C18 0.1μF R90 100kΩ R94 0Ω C5 0.1μF J3 U6:B 4 TP7 JP6 R93 A 22.1Ω B AD15252 OUTLINE DIMENSIONS 8.10 8.00 SQ 7.90 8 7 6 5 4 3 2 1 A BALL A1 CORNER TOP VIEW B C 5.60 BSC SQ D 0.80 BSC E F G H BOTTOM VIEW 1.70 1.55 1.35 DETAIL A 1.31 1.21 1.10 DETAIL A 0.34 NOM 0.25 MIN 0.55 0.50 0.45 BALL DIAMETER SEATING PLANE COPLANARITY 0.12 COMPLIANT TO JEDEC STANDARDS MO-205-BA Figure 33. 64-Lead Chip Scale Package Ball Grid Array [CSP_BGA] (BC-64-1) Dimensions shown in millimeters ORDERING GUIDE Model AD15252BBC AD15252/PCB Temperature Range −40°C to +85°C Package Description 64-Lead Chip Scale Package Ball Grid Array (CSP_BGA) Evaluation Board Rev. 0 | Page 19 of 20 Package Option BC-64-1 AD15252 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05154–0–8/05(0) Rev. 0 | Page 20 of 20