AD AD8504

FEATURES
Supply current: 1 μA maximum/amplifier
Offset voltage: 3 mV maximum
Single-supply or dual-supply operation
Rail-to-rail input and output
No phase reversal
Unity gain stable
PIN CONFIGURATIONS
OUT A 1
V+
8
–IN A 2
AD8502 7 OUT B
TOP VIEW
+IN A 3 (Not to Scale) 6 –IN B
V– 4
+IN B
5
06323-001
Preliminary Technical Data
1μ Micropower Precision CMOS
Operational Amplifier
AD8502/AD8504
Figure 1. 8-Lead SOT23
APPLICATIONS
GENERAL DESCRIPTION
The AD850x family are low power, precision CMOS op amps
featuring a maximum supply current of 1 μA. The AD850x family
has a maximum offset voltage of 3 mV and a typical input bias
current of 1 pA, and it operates rail-to-rail on both the input
and output. The AD850x family can operate from a singlesupply voltage of +1.8 V to +5.5 V or a dual-supply voltage of
±0.9 V to ±2.75 V.
OUT A
1
14 OUT D
IN A
2
13 –IN D
+IN A
3
AD8504
V+
4
TOP VIEW
(Not to Scale)
+IN B
5
10 +IN C
–IN B
6
9
–IN C
OUT B
7
8
OUT C
12 +IN D
11 V–
06323-02
Portable equipment
Remote sensors
Low power filters
Threshold detectors
Current sensing
Figure 2. 14-Lead TSSOP (RU-14)
With its low power consumption, low input bias current, and
rail-to-rail input and output, the AD850x family is ideally suited
for a variety of battery-powered portable applications. Potential
applications include bedside monitors, pulse monitors, glucose
meters, smoke and fire detectors, vibration monitors, and
backup battery sensors.
The ability to swing rail-to-rail at both the input and output
helps maximize dynamic range and signal-to-noise ratio in
systems that operate at very low voltages. The low offset voltage
allows the AD850x family to be used in systems with high gain
without having excessively large output offset errors, and it
provides high accuracy without the need for system calibration.
The AD850x family is fully specified over the industrial
temperature range (−40°C to +85°C) and is operational over the
extended industrial temperature range (−40°C to +125°C). The
AD8502 is available in a 8-lead, SOT23 surface-mount package.
The AD8504 is available in 14-lead TSSOP surface-mount
package.
Rev. PrB
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
AD8502/AD8504
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
Thermal Resistance .......................................................................5
Applications....................................................................................... 1
ESD Caution...................................................................................5
General Description ......................................................................... 1
Typical Performance Characteristics ........ Error! Bookmark not
defined.
Pin Configuration............................................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Outline Dimensions .................... Error! Bookmark not defined.
Ordering Guide ....................... Error! Bookmark not defined.
Electrical Characteristics............................................................. 3
Absolute Maximum Ratings............................................................ 5
REVISION HISTORY
Rev. PrB | Page 2 of 6
Preliminary Technical Data
AD8502/AD8504
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
@ VS = +5 V, VCM = VS/2, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
Offset Voltage Drift
Input Voltage Range
Input Bias Current
Symbol
Conditions
VOS
∆VOS/∆T
0 V < VCM < 5 V
−40°C < TA < +85°C
Min
Typ
Max
Unit
0.5
3
10
+5.3
10
100
600
5
50
100
mV
μV/°C
V
pA
pA
pA
pA
pA
pA
dB
dB
dB
dB
pF
pF
−0.3
IB
1
−40°C < TA < +85°C
−40°C < TA < +125°C
Input Offset Current
IOS
Common-Mode Rejection Ratio
CMRR
Large Signal Voltage Gain
AVO
Input Capacitance
CDIFF
CCM
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Short-Circuit Current
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Phase Margin
NOISE PERFORMANCE
Peak-to-Peak Noise
Voltage Noise Density
Current Noise Density
VOH
VOL
0.5
−40°C < TA < +85°C
−40°C < TA < +125°C
0 V < VCM < 5 V
−40°C < TA < +85°C
0.1 V < VOUT < 4.9 V
0.1 V < VOUT < 4.9 V; −40°C < TA < +85°C
2
4.5
RLOAD = 100 kΩ to GND
4.970
V
RLOAD = 10 kΩ to GND
4.900
V
RLOAD = 100 kΩ to VS
5
mV
RLOAD = 10 kΩ to VS
20
mV
ISC
VOUT = GND
PSRR
1.8 V < VS < 5 V
−40°C < TA < +85°C
VO = VS/2
−40°C < TA < +85°C
−40°C < TA < +125°C
ISY
SR
GBP
ØO
en
in
75
65
98
80
0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
Rev. PrB | Page 3 of 6
mA
90
70
1
1.5
2
dB
dB
μA
μA
μA
0.004
7
60
V/μs
kHz
Degrees
6
190
0.1
μV p-p
nV/√Hz
pA/√Hz
AD8502/AD8504
Preliminary Technical Data
@ VS = +1.8 V, VCM = VS/2, TA = 25°C, unless otherwise noted.
Table 2.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
Offset Voltage Drift
Input Voltage Range
Input Bias Current
Symbol
Conditions
VOS
∆VOS/∆T
0 V < VCM < 1.8 V
−40°C < TA < +85°C
Min
Typ
Max
Unit
0.5
3.5
3
12
+2.1
10
100
600
5
50
100
−40°C < TA < +85°C
−40°C < TA < +125°C
0 V < VCM < 1.8 V
60
mV
μV/°C
V
pA
pA
pA
pA
pA
pA
dB
−40°C < TA < +85°C
55
dB
0.1 V < VOUT < 1.7 V
88
dB
0.1 V < VOUT < 1.7 V; −40°C < TA < +85°C
70
−0.3
IB
1
−40°C < TA < +85°C
−40°C < TA < +125°C
Input Offset Current
Common-Mode Rejection Ratio
IOS
CMRR
Large Signal Voltage Gain
AVO
Input Capacitance
CDIFF
CCM
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Short-Circuit Current
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Phase Margin
NOISE PERFORMANCE
Peak-to-Peak Noise
Voltage Noise Density
Current Noise Density
VOH
VOL
0.5
dB
pF
pF
2
4.5
RLOAD = 100 kΩ to GND
1.790
V
RLOAD = 10 kΩ to GND
1.760
V
RLOAD = 100 kΩ to VS
5
mV
RLOAD = 10 kΩ to VS
20
mV
ISC
PSRR
ISY
mA
1.8 V < VS < 5 V
−40°C < TA < +85°C
VO = VS/2
−40°C < TA < +85°C
−40°C < TA < +125°C
SR
GBP
ØO
en
in
0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
Rev. PrB | Page 4 of 6
90
70
1
1.5
2
dB
dB
μA
μA
μA
0.004
V/μs
kHz
Degrees
6
190
0.1
μV p-p
nV/√Hz
pA/√Hz
Preliminary Technical Data
AD8502/AD8504
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 3.
Parameter
Supply Voltage
Input Voltage
Differential Input Voltage
Output Short-Circuit Duration to GND
Storage Temperature Range
Lead Temperature (Soldering, 60 sec)
Operating Temperature Range
Junction Temperature Range
Rating
6V
VSS − 0.4 V to VDD + 0.4 V
±6 V
Indefinite
−65°C to +150°C
300°C
−40°C to +125°C
−65°C to +150°C
Absolute maximum ratings apply at 25°C, unless otherwise
noted.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 4. Thermal Characteristics
Package Type
8-lead SOT23 (RJ-8)
14-lead TSSOP (RU-14)
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V
readily accumulate on the human body and test equipment and can discharge without
detection. Although this product features proprietary ESD protection circuitry,
permanent damage may occur on devices subjected to high energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
2.90 BSC
8
7
6
5
1
2
3
4
1.60 BSC
2.80 BSC
PIN 1
INDICATOR
0.65 BSC
*0.90
1.95
BSC
0.87
0.84
*1.00 MAX
0.10 MAX
0.38
0.22
SEATING
PLANE
0.20
0.08
8°
4°
0°
*COMPLIANT TO JEDEC STANDARDS MO-193-BA WITH
THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.
Figure 2. 8-Lead Thin Small Outline Transistor Package [TSOT]
(UJ-8)
Dimensions shown in millimeters
Rev. PrB | Page 5 of 6
0.60
0.45
0.30
θJA
376
180
θJC
126
35
Unit
°C/W
°C/W
AD8502/AD8504
Preliminary Technical Data
5.10
5.00
4.90
14
8
4.50
4.40
4.30
1
7
PIN 1
1.05
1.00
0.80
0.65
BSC
1.20
MAX
0.15
0.05
0.30
0.19
0.20
0.09
SEATING
COPLANARITY
PLANE
0.10
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 3. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
Rev. PrB | Page 6 of 6
0.75
0.60
0.45
PR06323-0-9/06(PrB)
6.40
BSC