ONSEMI M74VHC1G132DFT2G

MC74VHC1G132
2−Input NAND
Schmitt−Trigger
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MARKING
DIAGRAMS
5
5
1
SC−88A/SOT−353/SC−70
DF SUFFIX
CASE 419A
M
The MC74VHC1G132 is a single gate CMOS Schmitt NAND
trigger fabricated with silicon gate CMOS technology. It achieves high
speed operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The MC74VHC1G132 input structure provides protection when
voltages up to 7.0 V are applied, regardless of the supply voltage. This
allows the MC74VHC1G132 to be used to interface 5.0 V circuits to
3.0 V circuits.
The MC74VHC1G132 can be used to enhance noise immunity or to
square up slowly changing waveforms.
1
Features
•
•
•
•
•
•
•
VD M G
G
5
High Speed: tPD = 3.6 ns (Typ) at VCC = 5.0 V
Low Power Dissipation: ICC = 1.0 mA (Max) at TA = 25°C
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Pin and Function Compatible with Other Standard Logic Families
Chip Complexity: FETs = 68; Equivalent Gates = 16
Pb−Free Packages are Available
IN B
1
IN A
2
5
VD AYW G
G
5
1
TSOP−5/SOT−23/SC−59
DT SUFFIX
CASE 483
1
VD
= Device Code
M
= Date Code*
A
= Assembly Location
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may
vary depending upon manufacturing location.
VCC
PIN ASSIGNMENT
GND
1
4
3
OUT Y
IN B
2
IN A
3
GND
4
OUT Y
5
VCC
Figure 1. Pinout (Top View)
FUNCTION TABLE
Inputs
IN A
IN B
&
OUT Y
Figure 2. Logic Symbol
Output
A
B
Y
L
L
H
H
L
H
L
H
H
H
H
L
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 2005
August, 2005 − Rev. 17
1
Publication Order Number:
MC74VHC1G132/D
MC74VHC1G132
MAXIMUM RATINGS
Symbol
Parameter
VCC
DC Supply Voltage
VIN
DC Input Voltage
VOUT
DC Output Voltage
IIK
DC Input Diode Current
IOK
DC Output Diode Current
IOUT
DC Output Sink Current
ICC
DC Supply Current per Supply Pin
TSTG
Storage Temperature Range
TL
Lead Temperature, 1 mm from Case for 10 Seconds
TJ
Junction Temperature Under Bias
qJA
Thermal Resistance
PD
Power Dissipation in Still Air at 85°C
MSL
Moisture Sensitivity
FR
Flammability Rating
VESD
Latchup Performance
Unit
V
−0.5 to +7.0
V
*0.5 to VCC )0.5
V
−20
mA
$20
mA
$12.5
mA
$25
mA
*65 to )150
°C
260
°C
)150
°C
SC70−5/SC−88A (Note 1)
TSOP−5
350
230
°C/W
SC70−5/SC−88A
TSOP−5
150
200
mW
Level 1
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
u2000
u200
N/A
V
Above VCC and Below GND at 125°C (Note 5)
$500
mA
ESD Withstand Voltage
ILATCHUP
Value
*0.5 to )7.0
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2−ounce copper trace with no air flow.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Min
Max
Unit
VCC
DC Supply Voltage
2.0
5.5
V
VIN
DC Input Voltage
0.0
5.5
V
DC Output Voltage
0.0
VCC
V
Operating Temperature Range
VCC = 3.3 V ± 0.3 V
VCC = 5.0 V ± 0.5 V
Time, Hours
Time, Years
80
1,032,200
117.8
90
419,300
47.9
100
178,700
20.4
110
79,600
9.4
120
37,000
4.2
130
17,800
2.0
140
8,900
1.0
)125
°C
−
−
No Limit
No Limit
ns/V
TJ = 80° C
Junction
Temperature °C
*55
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
TJ = 110° C
Device Junction Temperature versus
Time to 0.1% Bond Failures
TJ = 120° C
NORMALIZED FAILURE RATE
Input Rise and Fall Time
TJ = 130° C
TA
tr , tf
TJ = 90° C
VOUT
Parameter
TJ = 100° C
Symbol
1
1
10
100
1000
TIME, YEARS
Figure 3. Failure Rate vs. Time Junction Temperature
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2
MC74VHC1G132
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Conditions
TA ≤ 85°C
TA = 25°C
−55 ≤ TA ≤ 125°C
VCC
(V)
Min
Typ
Max
Min
Max
Min
Max
Unit
VT+
Positive Threshold
Voltage
3.0
4.5
5.5
1.50
2.35
2.80
1.88
2.66
3.21
2.25
3.10
3.70
1.50
2.35
2.80
2.25
3.10
3.70
1.50
2.35
2.80
2.25
3.10
3.70
V
VT−
Negative Threshold
Voltage
3.0
4.5
5.5
0.65
1.10
1.45
1.03
1.62
2.02
1.40
2.10
2.60
0.65
1.10
1.45
1.40
2.10
2.60
0.65
1.10
1.45
1.40
2.10
2.60
V
VH
Hysteresis Voltage
3.0
4.5
5.5
0.30
0.40
0.50
0.85
1.05
1.20
1.60
2.00
2.25
0.30
0.40
0.50
1.60
2.00
2.25
0.30
0.40
0.50
1.60
2.00
2.25
V
VIN = VCC or GND
2.0
1.9
2.0
1.9
1.9
VIN = VIH or VIL
IOH = −50 mA
3.0
4.5
2.9
4.4
3.0
4.5
2.9
4.4
2.9
4.5
IOH = −4 mA
IOH = −8 mA
3.0
4.5
2.58
3.94
2.48
3.80
2.34
3.66
VIN = VIH or VIL
IOL = 50 mA
2.0
3.0
4.5
IOL = 4 mA
IOL = 8 mA
VOH
VOL
Minimum High−Level
Output Voltage
IOH = −50mA
Maximum Low−Level
Output Voltage
0.0
0.0
0.0
V
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
V
IIN
Maximum Input
Leakage Current
VIN = 5.5 V or GND
0 to
5.5
±0.1
±1.0
±1.0
mA
ICC
Maximum Quiescent
Supply Current
VIN = VCC or GND
5.5
1.0
20
40
mA
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AC ELECTRICAL CHARACTERISTICS Cload = 50 pF, Input tr/tf = 3.0 ns
TA ≤ 85°C
TA = 25°C
Symbol
tPLH,
tPHL
CIN
Parameter
Maximum
Propagation Delay,
A or B to Y
Min
Test Conditions
−55 ≤ TA ≤ 125°C
Typ
Max
Min
Max
Min
Max
Unit
ns
VCC = 3.3 ± 0.3 V
CL = 15 pF
CL = 50 pF
4.6
6.1
11.9
15.4
1.0
1.0
14.0
17.5
1.0
1.0
16.1
19.6
VCC = 5.0 ± 0.5 V
CL = 15 pF
CL = 50 pF
3.6
4.3
7.7
9.7
1.0
1.0
9.0
11.0
1.0
1.0
10.3
12.3
5.5
10
Maximum Input
Capacitance
10
10
pF
Typical @ 25°C, VCC = 5.0 V
CPD
11
Power Dissipation Capacitance (Note 6)
pF
6. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no−load dynamic
power consumption; PD = CPD VCC2 fin + ICC VCC.
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3
MC74VHC1G132
TEST POINT
VCC
A or B
OUTPUT
50%
DEVICE
UNDER
TEST
GND
tPLH
Y
tPHL
CL*
50% VCC
*Includes all probe and jig capacitance
Figure 4. Switching Waveforms
Figure 5. Test Circuit
DEVICE ORDERING INFORMATION
Package Type
Tape and Reel Size†
MC74VHC1G132DFT1
SC70−5/SC−88A/SOT−353
178 mm (7 in)
3000 Units / Tape & Reel
M74VHC1G132DFT1G
SC70−5/SC−88A/SOT−353
(Pb−Free)
178 mm (7 in)
3000 Units / Tape & Reel
MC74VHC1G132DFT2
SC70−5/SC−88A/SOT−353
178 mm (7 in)
3000 Units / Tape & Reel
M74VHC1G132DFT2G
SC70−5/SC−88A/SOT−353
(Pb−Free)
178 mm (7 in)
3000 Units / Tape & Reel
MC74VHC1G132DTT1
SOT23−5/TSOP−5SC59−5
178 mm (7 in)
3000 Units / Tape & Reel
M74VHC1G132DTT1G
SOT23−5/TSOP−5SC59−5
(Pb−Free)
178 mm (7 in)
3000 Units / Tape & Reel
Device Order Number
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
MC74VHC1G132
PACKAGE DIMENSIONS
SC−88A / SOT−353 / SC70
CASE 419A−02
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
A
G
5
4
−B−
S
1
2
DIM
A
B
C
D
G
H
J
K
N
S
3
D 5 PL
0.2 (0.008)
M
B
M
N
INCHES
MIN
MAX
0.071
0.087
0.045
0.053
0.031
0.043
0.004
0.012
0.026 BSC
−−−
0.004
0.004
0.010
0.004
0.012
0.008 REF
0.079
0.087
J
C
K
H
SOLDERING FOOTPRINT*
0.50
0.0197
0.65
0.025
0.65
0.025
0.40
0.0157
1.9
0.0748
SCALE 20:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
mm Ǔ
ǒinches
MILLIMETERS
MIN
MAX
1.80
2.20
1.15
1.35
0.80
1.10
0.10
0.30
0.65 BSC
−−−
0.10
0.10
0.25
0.10
0.30
0.20 REF
2.00
2.20
MC74VHC1G132
PACKAGE DIMENSIONS
TSOP−5 / SOT23−5 / SC59−5
DT SUFFIX
CASE 483−02
ISSUE D
D
S
5
4
1
2
3
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. A AND B DIMENSIONS DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
B
L
G
A
DIM
A
B
C
D
G
H
J
K
L
M
S
J
C
0.05 (0.002)
H
M
K
MILLIMETERS
MIN
MAX
2.90
3.10
1.30
1.70
0.90
1.10
0.25
0.50
0.85
1.05
0.013
0.100
0.10
0.26
0.20
0.60
1.25
1.55
0_
10 _
2.50
3.00
INCHES
MIN
MAX
0.1142 0.1220
0.0512 0.0669
0.0354 0.0433
0.0098 0.0197
0.0335 0.0413
0.0005 0.0040
0.0040 0.0102
0.0079 0.0236
0.0493 0.0610
0_
10 _
0.0985 0.1181
SOLDERING FOOTPRINT*
0.95
0.037
1.9
0.074
2.4
0.094
1.0
0.039
0.7
0.028
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MC74VHC1G132/D