LC03−6R2 Low Capacitance Surface Mount TVS for High−Speed Data Interfaces The LC03−6 transient voltage suppressor is designed to protect equipment attached to high speed communication lines from ESD, EFT, and lighting. Features: • • • • • • http://onsemi.com SO−8 LOW CAPACITANCE VOLTAGE SUPPRESSOR 2 kW PEAK POWER 6 VOLTS SO−8 Package Peak Power − 2000 Watts 8 x 20 S ITU K.20 IPP = 40 A (5/310 s) Bellcore 1089 (Intra−Building) 100 A (2/10 s) ESD Rating: IEC 61000−4−2 (ESD) 15 kV (air) 8 kV (contact) IEC 61000−4−4 (EFT) 40 A (5/50 ns) IEC 61000−4−5 (lighting) 95 A (8/20 s) UL Flammability Rating of 94V−0 PIN CONFIGURATION AND SCHEMATIC Typical Applications: • High Speed Communication Line Protection 1 8 2 7 3 6 4 5 MAXIMUM RATINGS Rating Symbol Value Unit Peak Power Dissipation 8 x 20 S @ TA = 25°C (Note 1) Ppk 2000 W Peak Pulse Current (8 x 20 S Waveform) IPP 100 TJ, Tstg −55 to +150 °C TL 260 °C Junction and Storage Temperature Range Lead Solder Temperature − Maximum 10 Seconds Duration 8 A 1 SO−8 CASE 751 PLASTIC MARKING DIAGRAM 1. Non−repetitive current pulse 8 x 20 S exponential decay waveform LC036 LYWW LC036= Device Code L = Location Code Y = Year WW = Work Week ORDERING INFORMATION Device LC03−6R2 Package Shipping† SO−8 2500/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2004 January, 2004 − Rev. 3 1 Publication Order Number: LC03−6R2/D LC03−6R2 ELECTRICAL CHARACTERISTICS Characteristic Symbol Min Typ Max Unit VBR 6.8 − − V Reverse Leakage Current @ VRWN = 5.0 Volts IR N/A − 20 A Maximum Clamping Voltage @ IPP = 50 A, 8 x 20 S VC N/A − 15 V Maximum Clamping Voltage @ IPP = 100 A, 8 x 20 S VC N/A − 20 V Between I/O Pins and Ground @ VR = 0 Volts, 1.0 MHz Capacitance − 16 25 pF Between I/O Pins @ VR = 0 Volts, 1.0 MHz Capacitance − 8.0 12 pF Reverse Breakdown Voltage @ It = 1.0 mA TYPICAL CHARACTERISTICS 16 IR, REVERSE LEAKAGE (A) VZ, REVERSE VOLTAGE (V) 10 8 6 4 2 0 −80 −60 −40 −20 0 20 40 60 80 100 120 140 T, TEMPERATURE (°C) 14 12 10 8 6 4 2 0 −80 −60 −40 −20 Figure 1. Reverse Voltage versus Temperature PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 s 80 70 60 HALF VALUE IRSM/2 @ 20 s 50 40 30 tP 20 60 80 100 120 140 18 16 8 x 20 s Waveform 14 12 10 8 6 4 2 10 0 40 20 PEAK VALUE IRSM @ 8 s tr 90 20 Figure 2. Reverse Leakage versus Temperature VC, CLAMPING VOLTAGE (V) % OF PEAK PULSE CURRENT 100 0 T, TEMPERATURE (°C) 0 0 20 40 60 80 0 10 20 30 40 50 60 70 80 90 100 110 IPP, PEAK PULSE CURRENT (A) t, TIME (s) Figure 3. 8 × 20 s Pulse Waveform Figure 4. Clamping Voltage versus Peak Pulse Current http://onsemi.com 2 LC03−6R2 APPLICATIONS INFORMATION The LC03−6 ON Semiconductor’s device is a TVS Diode array designed to protect sensitive electronics such as communications systems, computers, and computer peripherals against damage due to transient over−voltage conditions caused by lightning, electrostatic discharge (ESD), and electrical fast transients (EFT). Because of its relative low capacitance (<25 pf), it can be used in high speed I/O data lines such as USB 1.1 ports. The integrated design of the LC03−6 device offers high surge rating, low capacitance steering diodes, and a TVS diode integrated in a single package (SO−8). In addition, this device offers compliance to Bellcore 1089 requirements (intra−building). If differential protection is required by some particular applications, then the configuration for differential protection is made as shown in the Figure 6: LC03−6 Device’s Configurations Options T1/E1 Linecard Protection (Intra−Building) LC03−6 Line 1 In Line 2 Out Line 2 Out The Figure 7 shows a typical schematic for a T1/E1 line card protection circuit. The LC03−6 device is connected between Tip & Ring on the transmit and receive line pairs. it provides protection to metallic and common mode lightning surges per Bellcore 1089 intra−building (For further information, see Bellcore 1089 standard). A metallic voltage is defined as a difference of potential between the T and R terminals of a telecommunications pair. Currents caused by lightning, in the absence of protector operation and with balanced terminal equipment and telecommunications loop, cause Tip and Ring conductors to attain the same potential hence do not produce metallic transients. Common mode surges are suppressed by the isolation of the transformer. LC03−6 Line 2 In N/C Figure 6. Configuration for Differential Protection (Line−to−Line) The LC03−6 device is able to protect two high speed data lines against transient over−voltage conditions by driving them to a fixed reference point for clamping purposes. Depending in the application’s requirements, the LC03−6 device can be configured for protection in either differential mode (Line−to−Line) or common mode (Line−to−ground). The Figure 5 shows the connection for Differential mode (Line−to−Line) and Common mode (Line−to−Ground) protection. The inputs and outputs of the I/O data lines are connected at terminals 1 to 8, and 4 to 5 while the terminals 2, 3, 6 and 7 are connected to ground; for better performance, it is recommended to minimize parasitic inductances by using ground planes and minimizing the PCB trace lengths for the ground return connections. Line 1 Out N/C N/C Line 2 In Protection of Two High−speed I/O Data Lines Line 1 In N/C Line 1 Out Figure 5. Configuration for Differential and Common Mode Protection http://onsemi.com 3 LC03−6R2 PTC R1 RTIP R3 LC03−6 R2 RRING T1 PTC T1/E1 TRANSCEIVER R4 PTC TTIP LC03−6 R5 TRING T2 PTC Figure 7. Typical T1 Line Card Protection ESD Protection in USB 1.1 Port Applications transient condition which reduces significantly the performance of the ESD protection circuit. The LC03−6 device provides a unique TVS Diode array designed to protect two I/O data lines (single USB port) against damage due to ESD conditions or transient voltage conditions. Because of its low capacitance, it can be used in high speed I/O data lines such as USB 1.1 components. In addition to its low capacitance characteristics, the LC03−6 device from ON Semiconductor complies with the most common industrial standards for ESD, EFT and surge protection: IEC61000−4−2, IEC61000−4−4, IEC61000−4−5. As we know, a USB port is composed of four lines. The lines D+ & D− are used for bi−directional data transmission, and the remaining two lines are reserved for bus voltage and ground. Since USB is a hot plugging and unplugging system, all its four lines have the risk to receive ESD conditions in the real field of the application. Typical ESD protection techniques are commonly formed by the combination of different discrete semiconductor products which make this technique obsolete and non−efficient because the interconnections of the discrete devices increase the parasitic inductance effects during a http://onsemi.com 4 LC03−6R2 PACKAGE DIMENSIONS SO−8 CASE 751−07 ISSUE AA NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDAARD IS 751−07 −X− A 8 5 0.25 (0.010) S B 1 M Y M 4 K −Y− G C N X 45 SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M S http://onsemi.com 5 J DIM A B C D G H J K M N S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0 8 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 8 0.010 0.020 0.228 0.244 LC03−6R2 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 http://onsemi.com 6 For additional information, please contact your local Sales Representative. LC03−6R2/D