NUP4201MR6 Low Capacitance TSOP−6 Diode−TVS Array for High Speed Data Lines Protection http://onsemi.com The NUP4201MR6 transient voltage suppressor is designed to protect high speed data lines from ESD, EFT, and lighting. Features: • Low Capacitance (3 pF Maximum Between I/O Lines) • ESD Rating of Class 3B (Exceeding 8 kV) per Human Body model and Class C (Exceeding 400 V) per Machine Model • Protection for the Following IEC Standards: • IEC 61000−4−2 (ESD) 15 kV (air) 8 kV (contact) IEC 61000−4−4 (EFT) 40 A (5/50 ns) IEC 61000−4−5 (lighting) 23 A (8/20 s) UL Flammability Rating of 94 V−0 PIN CONFIGURATION AND SCHEMATIC Typical Applications: • • • • TSOP−6 LOW CAPACITANCE DIODE TVS ARRAY 500 WATTS PEAK POWER 6 VOLTS High Speed Communication Line Protection USB 1.1 and 2.0 Power and Data Line Protection Digital Video Interface (DVI) Monitors and Flat Panel Displays I/O 1 6 I/O VN 2 5 VP I/O 3 4 I/O MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Symbol Value Unit Peak Power Dissipation 8 x 20 S @ TA = 25°C (Note 1) Ppk 500 W Operating Junction Temperature Range TJ −40 to +125 °C Storage Temperature Range Tstg −55 to +150 °C Lead Solder Temperature − Maximum (10 Seconds) TL 235 °C ESD 16000 400 20000 20000 V Human Body Model (HBM) Machine Model (MM) IEC 61000−4−2 Air (ESD) IEC 61000−4−2 Contact (ESD) 6 1 TSOP−6 CASE 318G PLASTIC MARKING DIAGRAM 1. Non−repetitive current pulse per Figure 1 (Pin 5 to Pin 2) 63M 63 = Specific Device Code M = Date Code ORDERING INFORMATION Device NUP4201MR6T1 Semiconductor Components Industries, LLC, 2003 August, 2003 − Rev. 0 1 Package Shipping TSOP−6 3000/Tape & Reel Publication Order Number: NUP4201MR6/D NUP4201MR6 ELECTRICAL CHARACTERISTICS (TJ=25°C unless otherwise specified) Parameter Symbol Reverse Working Voltage Conditions VRWM Breakdown Voltage Min Typ (Note 2) VBR IT=1 mA, (Note 3) Max Unit 5.0 V 6.0 V Reverse Leakage Current IR VRWM = 5 V 5.0 A Clamping Voltage VC IPP = 5 A (Note 4) 12.5 V Clamping Voltage VC IPP = 8 A (Note 4) 20 V Maximum Peak Pulse Current IPP 8x20 s Waveform 25 A Junction Capacitance CJ VR = 0 V, f=1 MHz between I/O Pins and GND 3.0 5.0 pF Junction Capacitance CJ VR = 0 V, f=1 MHz between I/O Pins 1.5 3.0 pF 2. TVS devices are normally selected according to the working peak reverse voltage (VRWM), which should be equal or greater than the DC or continuous peak operating voltage level. 3. VBR is measured at pulse test current IT. 4. Non−repetitive current pulse per Figure 1 (Pin 5 to Pin 2) TYPICAL PERFORMANCE CURVES 100 100 90 90 % OF PEAK PULSE CURRENT PEAK POWER DISSIPATION (%) (TJ = 25°C unless otherwise noted) 80 70 60 50 40 30 20 10 0 0 25 50 75 100 125 150 175 PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 s 80 70 60 HALF VALUE IRSM/2 @ 20 s 50 40 30 tP 20 10 0 200 PEAK VALUE IRSM @ 8 s tr 0 20 TA, AMBIENT TEMPERATURE (°C) 20 4.5 18 CLAMPING VOLTAGE (V) JUNCTION CAPACITANCE (pF) 5.0 4.0 3.5 I/O−Ground 2.5 2.0 I/O lines 1.5 1.0 80 16 14 12 10 8 6 4 2 0.5 0.0 60 Figure 2. 8 × 20 s Pulse Waveform Figure 1. Pulse Derating Curve 3.0 40 t, TIME (s) 0 1 2 3 4 0 5 0 10 20 30 40 50 PEAK PULSE CURRENT (A) VBR, REVERSE VOLTAGE (V) Figure 4. Clamping Voltage vs. Peak Pulse Current (8 x 20 s Waveform) Figure 3. Junction Capacitance vs Reverse Voltage http://onsemi.com 2 NUP4201MR6 PACKAGE DIMENSIONS TSOP−6 CASE 318G−02 ISSUE J NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. A L 6 S 1 5 4 2 3 B D G M J C 0.05 (0.002) H K http://onsemi.com 3 MILLIMETERS DIM MIN MAX A 2.90 3.10 B 1.30 1.70 C 0.90 1.10 D 0.25 0.50 G 0.85 1.05 H 0.013 0.100 J 0.10 0.26 K 0.20 0.60 L 1.25 1.55 M 0_ 10 _ S 2.50 3.00 INCHES MIN MAX 0.1142 0.1220 0.0512 0.0669 0.0354 0.0433 0.0098 0.0197 0.0335 0.0413 0.0005 0.0040 0.0040 0.0102 0.0079 0.0236 0.0493 0.0610 0_ 10 _ 0.0985 0.1181 NUP4201MR6 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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